SRAM_CTRL/MAIN Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: `ed1c41cd0f`

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.501m	1.226ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.160s	54.319us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.080s	46.565us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	4.980s	1.443ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.140s	24.475us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	8.670s	1.463ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.080s	46.565us	20	20	100.00
		sram_ctrl_csr_aliasing	1.140s	24.475us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	9.010m	36.956ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.369m	71.774ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	32.159m	34.920ms	48	50	96.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	10.984m	42.184ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	58.047m	622.636ms	48	50	96.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	23.432m	56.212ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.348m	135.430ms	50	50	100.00
V2	executable	sram_ctrl_executable	23.400m	23.995ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.143m	3.848ms	50	50	100.00
		sram_ctrl_partial_access_b2b	13.128m	99.178ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.937m	2.720ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.997m	3.134ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	22.280m	25.998ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	8.620s	4.812ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.491h	428.622ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	1.080s	21.797us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.730s	120.794us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.730s	120.794us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.160s	54.319us	5	5	100.00
		sram_ctrl_csr_rw	1.080s	46.565us	20	20	100.00
		sram_ctrl_csr_aliasing	1.140s	24.475us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.250s	71.325us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.160s	54.319us	5	5	100.00
		sram_ctrl_csr_rw	1.080s	46.565us	20	20	100.00
		sram_ctrl_csr_aliasing	1.140s	24.475us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.250s	71.325us	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.846m	29.288ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	6.060s	735.865us	5	5	100.00
		sram_ctrl_tl_intg_err	4.340s	508.451us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	6.060s	735.865us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.340s	508.451us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	22.280m	25.998ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.080s	46.565us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	23.400m	23.995ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	23.400m	23.995ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	23.400m	23.995ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.348m	135.430ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.846m	29.288ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	1.501m	1.226ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.501m	1.226ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.501m	1.226ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	23.400m	23.995ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	6.060s	735.865us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.348m	135.430ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	6.060s	735.865us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	6.060s	735.865us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.501m	1.226ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	6.060s	735.865us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.748m	8.050ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1033	1040	99.33

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	11	68.75
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 15.sram_ctrl_stress_all.54169212131316968074499721215346134024996862077355744853899341916137572772902
    Line 118, in log /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 1441563979049 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xcefeaca5
  UVM_INFO @ 1441563979049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sram_ctrl_multiple_keys has 2 failures.
  - 22.sram_ctrl_multiple_keys.21920011164120424624439087453970504470801180656145131751458764128400692925019
    Line 101, in log /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/22.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 94083223340 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x5e9a602d
  UVM_INFO @ 94083223340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.sram_ctrl_multiple_keys.69280499231767837867577118891391617901517775584043560714546008477258168832024
    Line 87, in log /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/43.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 16673127059 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xd0b20e53
  UVM_INFO @ 16673127059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test sram_ctrl_bijection has 2 failures.
  - 27.sram_ctrl_bijection.53443418160115014630761665275323349686871525524830751144295337837147127693717
    Line 83, in log /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/27.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.sram_ctrl_bijection.115642476869754438797526796510190225155531765207033673702654272781327342054880
    Line 83, in log /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/36.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 12.sram_ctrl_regwen.20609242226602430680236674547264549473233559996988417370085783355963966169429
    Line 122, in log /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/12.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 118654601028 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xca708245
  UVM_INFO @ 118654601028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 23.sram_ctrl_executable.40280713364881518987109777441437499475240179145506268464919723560538513206236
    Line 93, in log /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/23.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 48773291178 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x9d9a2927
  UVM_INFO @ 48773291178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/MAIN Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: ed1c41cd0f

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `ed1c41cd0f`