SRAM_CTRL/MAIN Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: `372a6306e0`

Branch: os_regression_2024_09_03

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.836m	2.043ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.080s	85.126us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.090s	13.749us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.500s	1.445ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.150s	51.452us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	10.730s	4.931ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.090s	13.749us	20	20	100.00
		sram_ctrl_csr_aliasing	1.150s	51.452us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.375m	173.008ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.845m	19.571ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	35.429m	117.844ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.793m	4.847ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	52.986m	1.000s	48	50	96.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	23.326m	64.927ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	6.623m	305.163ms	50	50	100.00
V2	executable	sram_ctrl_executable	21.541m	10.804ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	1.719m	892.375us	50	50	100.00
		sram_ctrl_partial_access_b2b	12.748m	27.242ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.927m	8.469ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.758m	1.563ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	22.374m	20.172ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	10.300s	6.676ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.945h	1.897s	48	50	96.00
V2	alert_test	sram_ctrl_alert_test	1.070s	48.024us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.880s	131.677us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.880s	131.677us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.080s	85.126us	5	5	100.00
		sram_ctrl_csr_rw	1.090s	13.749us	20	20	100.00
		sram_ctrl_csr_aliasing	1.150s	51.452us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.270s	25.979us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.080s	85.126us	5	5	100.00
		sram_ctrl_csr_rw	1.090s	13.749us	20	20	100.00
		sram_ctrl_csr_aliasing	1.150s	51.452us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.270s	25.979us	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.692m	28.268ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	5.010s	923.137us	5	5	100.00
		sram_ctrl_tl_intg_err	5.520s	1.125ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	5.010s	923.137us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	5.520s	1.125ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	22.374m	20.172ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.090s	13.749us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	21.541m	10.804ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	21.541m	10.804ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	21.541m	10.804ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	6.623m	305.163ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.692m	28.268ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	1.836m	2.043ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.836m	2.043ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.836m	2.043ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	21.541m	10.804ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	5.010s	923.137us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	6.623m	305.163ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	5.010s	923.137us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	5.010s	923.137us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.836m	2.043ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	5.010s	923.137us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.171m	4.879ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1033	1040	99.33

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	12	75.00
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_executable has 1 failures.
  - 16.sram_ctrl_executable.104654530213265068104694688314217662942719893953752512905458291250957024995568
    Line 93, in log /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/16.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 38967124991 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x9121bf4c
  UVM_INFO @ 38967124991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sram_ctrl_stress_all has 1 failures.
  - 49.sram_ctrl_stress_all.111666008198594987241511199983172101211083421282857999606095263866971289940023
    Line 103, in log /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 86800860333 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xe5914939
  UVM_INFO @ 86800860333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test sram_ctrl_bijection has 2 failures.
  - 20.sram_ctrl_bijection.75974898527917640192176799064660156804172817293321490986760918801220356218808
    Line 83, in log /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/20.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.sram_ctrl_bijection.59827628742684410175745430742206550062471049285926719913228410008709896404173
    Line 83, in log /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/30.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:867) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 23.sram_ctrl_stress_all_with_rand_reset.28322291203550580280950577489667983617748547542515688878056225715350428594513
    Line 152, in log /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6225712535 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6225712535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 30.sram_ctrl_stress_all.59274755459970331903876864563921138100965299011614665616879527217215130405344
    Line 101, in log /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 6880301328991 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x4255596a
  UVM_INFO @ 6880301328991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 33.sram_ctrl_regwen.26680007926212394669500621387806722065742996359877802412757213093081593027970
    Line 107, in log /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/33.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 117468886161 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x54b0a586
  UVM_INFO @ 117468886161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/MAIN Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: 372a6306e0

Branch: os_regression_2024_09_03

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `372a6306e0`