SRAM_CTRL/MAIN Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: `af2d1709f9`

Branch: os_regression_2024_09_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.808m	2.615ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.060s	19.310us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.100s	51.729us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.210s	446.140us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.180s	23.803us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	9.440s	4.899ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.100s	51.729us	20	20	100.00
		sram_ctrl_csr_aliasing	1.180s	23.803us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	7.416m	86.151ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.879m	10.454ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	34.640m	29.339ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	8.290m	20.640ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	55.965m	304.911ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	21.631m	64.556ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	4.016m	133.988ms	50	50	100.00
V2	executable	sram_ctrl_executable	24.269m	29.809ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	1.327m	4.027ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.204m	15.805ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.809m	12.662ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.899m	820.439us	50	50	100.00
V2	regwen	sram_ctrl_regwen	22.645m	60.624ms	48	50	96.00
V2	ram_cfg	sram_ctrl_ram_cfg	7.560s	3.048ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.722h	296.041ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	1.080s	20.610us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	7.090s	301.327us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	7.090s	301.327us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.060s	19.310us	5	5	100.00
		sram_ctrl_csr_rw	1.100s	51.729us	20	20	100.00
		sram_ctrl_csr_aliasing	1.180s	23.803us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.240s	86.141us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.060s	19.310us	5	5	100.00
		sram_ctrl_csr_rw	1.100s	51.729us	20	20	100.00
		sram_ctrl_csr_aliasing	1.180s	23.803us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.240s	86.141us	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.581m	14.403ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	6.230s	838.559us	5	5	100.00
		sram_ctrl_tl_intg_err	4.010s	237.518us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	6.230s	838.559us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.010s	237.518us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	22.645m	60.624ms	48	50	96.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.100s	51.729us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	24.269m	29.809ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	24.269m	29.809ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	24.269m	29.809ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	4.016m	133.988ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.581m	14.403ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	1.808m	2.615ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.808m	2.615ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.808m	2.615ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	24.269m	29.809ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	6.230s	838.559us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	4.016m	133.988ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	6.230s	838.559us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	6.230s	838.559us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.808m	2.615ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	6.230s	838.559us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.276m	15.660ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1034	1040	99.42

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	11	68.75
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.94	99.19	94.27	99.72	100.00	96.03	99.12	97.26

Failure Buckets

UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test sram_ctrl_regwen has 2 failures.
  - 10.sram_ctrl_regwen.31566988021849538021423366227979614882250928919765248196301637479344811437047
    Line 111, in log /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 106069256200 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xe2320b37
  UVM_INFO @ 106069256200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.sram_ctrl_regwen.93080138283493372292380721218379088863610304015592185595593051382883763530436
    Line 92, in log /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 43450740412 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xb6553e1f
  UVM_INFO @ 43450740412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sram_ctrl_stress_all has 1 failures.
  - 27.sram_ctrl_stress_all.6326389513784182147883126634258850579984096827273728499335946454680556990876
    Line 171, in log /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 2100491232424 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xf6e43e51
  UVM_INFO @ 2100491232424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 12.sram_ctrl_multiple_keys.61309213134900016844821939786857409248939158594907050280490441005586293451145
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 71590130172 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x50c5b0ba
  UVM_INFO @ 71590130172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 15.sram_ctrl_executable.47163685219206001112678294350778513509708772965966946741177320912990357229416
    Line 87, in log /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 16633056359 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xa8039009
  UVM_INFO @ 16633056359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test sram_ctrl_bijection has 1 failures.
  - 34.sram_ctrl_bijection.109351628072785778016517273665191726175832206243171508858388568568851488907466
    Line 83, in log /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/MAIN Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: af2d1709f9

Branch: os_regression_2024_09_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `af2d1709f9`