SRAM_CTRL/RET Simulation Results

Wednesday May 24 2023 07:09:34 UTC

GitHub Revision: `26b0ee226`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 844256362

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.291m	515.390us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.670s	52.290us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.710s	43.799us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.130s	969.298us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.720s	55.318us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.230s	248.437us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.710s	43.799us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	55.318us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	12.740s	9.428ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.420s	175.115us	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	44.304m	88.283ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	8.134m	21.103ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.341m	6.090ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	38.698m	19.491ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	17.850s	1.060ms	50	50	100.00
V2	executable	sram_ctrl_executable	35.276m	68.381ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.530m	4.419ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.119m	24.612ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.808m	139.652us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.753m	166.438us	50	50	100.00
V2	regwen	sram_ctrl_regwen	33.057m	20.061ms	48	50	96.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.350s	41.224us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.845h	349.304ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	0.710s	25.961us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.450s	1.957ms	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.450s	1.957ms	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.670s	52.290us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	43.799us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	55.318us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	89.893us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.670s	52.290us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	43.799us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	55.318us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	89.893us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	15.490s	1.082ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.570s	1.750ms	5	5	100.00
		sram_ctrl_tl_intg_err	3.080s	607.249us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.570s	1.750ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.080s	607.249us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	33.057m	20.061ms	48	50	96.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.710s	43.799us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	35.276m	68.381ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	35.276m	68.381ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	35.276m	68.381ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	17.850s	1.060ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	15.490s	1.082ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.291m	515.390us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.291m	515.390us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	35.276m	68.381ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.570s	1.750ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	17.850s	1.060ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.570s	1.750ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.570s	1.750ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.291m	515.390us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.570s	1.750ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.232h	3.019ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1035	1040	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	12	75.00
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.26	99.16	93.54	100.00	70.00	97.41	99.70	100.00

Failure Buckets

UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 3 failures:

Test sram_ctrl_stress_all has 1 failures.

10.sram_ctrl_stress_all.550772556
Line 254, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 59804557502 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x53658b82
  UVM_INFO @ 59804557502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test sram_ctrl_regwen has 2 failures.

12.sram_ctrl_regwen.2207263283
Line 249, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_regwen/latest/run.log

  UVM_FATAL @ 42097434312 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x8f5ea37
  UVM_INFO @ 42097434312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.sram_ctrl_regwen.2947447850
Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/27.sram_ctrl_regwen/latest/run.log

  UVM_FATAL @ 147510091042 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xaad6e6a7
  UVM_INFO @ 147510091042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 3.sram_ctrl_multiple_keys.670338025
    Line 251, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 46459516299 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xe06d861
  UVM_INFO @ 46459516299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 9.sram_ctrl_executable.4183163539
    Line 241, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 10491082714 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xd61ae03b
  UVM_INFO @ 10491082714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```