SRAM_CTRL/RET Simulation Results

Sunday May 28 2023 07:05:15 UTC

GitHub Revision: c06cc3921

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2869101736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.443m	779.511us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.700s	49.317us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.730s	13.463us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.970s	145.698us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.680s	177.156us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.700s	136.476us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.730s	13.463us	20	20	100.00
		sram_ctrl_csr_aliasing	0.680s	177.156us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	11.610s	4.639ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.600s	439.345us	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	37.577m	22.161ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.643m	16.806ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.291m	9.694ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	41.863m	4.559ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	16.580s	2.430ms	50	50	100.00
V2	executable	sram_ctrl_executable	35.205m	7.937ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.364m	2.564ms	50	50	100.00
		sram_ctrl_partial_access_b2b	8.594m	106.500ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.541m	138.322us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	3.002m	158.679us	50	50	100.00
V2	regwen	sram_ctrl_regwen	32.173m	81.235ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.180s	369.270us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.900h	61.327ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.720s	36.843us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.270s	755.403us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.270s	755.403us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.700s	49.317us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	13.463us	20	20	100.00
		sram_ctrl_csr_aliasing	0.680s	177.156us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	82.156us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.700s	49.317us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	13.463us	20	20	100.00
		sram_ctrl_csr_aliasing	0.680s	177.156us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	82.156us	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	10.830s	1.508ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	4.020s	2.531ms	5	5	100.00
		sram_ctrl_tl_intg_err	2.400s	224.769us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	4.020s	2.531ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.400s	224.769us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	32.173m	81.235ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.730s	13.463us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	35.205m	7.937ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	35.205m	7.937ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	35.205m	7.937ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	16.580s	2.430ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	10.830s	1.508ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.443m	779.511us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.443m	779.511us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	35.205m	7.937ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	4.020s	2.531ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	16.580s	2.430ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	4.020s	2.531ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	4.020s	2.531ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.443m	779.511us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	4.020s	2.531ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.872h	4.662ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1039	1040	99.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	15	93.75
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.26	99.16	93.54	100.00	70.00	97.41	99.70	100.00

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
  • Test sram_ctrl_executable has 1 failures.

    • 8.sram_ctrl_executable.986521005
      Line 251, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_executable/latest/run.log

        UVM_FATAL @ 48158343479 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x5814e5e1
        UVM_INFO @ 48158343479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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