SRAM_CTRL/RET Simulation Results

Monday May 29 2023 07:02:33 UTC

GitHub Revision: 877a77116

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88555427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.129m	652.209us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.660s	18.569us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.700s	23.758us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.880s	146.789us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.670s	18.840us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.480s	33.957us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.700s	23.758us	20	20	100.00
		sram_ctrl_csr_aliasing	0.670s	18.840us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	11.000s	1.181ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.560s	610.437us	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	29.199m	36.458ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	5.854m	14.931ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.421m	11.266ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	33.709m	4.408ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	23.390s	3.281ms	50	50	100.00
V2	executable	sram_ctrl_executable	34.117m	38.588ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.337m	851.211us	50	50	100.00
		sram_ctrl_partial_access_b2b	9.174m	44.335ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.157m	2.111ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.683m	326.044us	50	50	100.00
V2	regwen	sram_ctrl_regwen	33.695m	90.536ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.710s	111.802us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.704h	29.568ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.710s	40.454us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.320s	124.918us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.320s	124.918us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.660s	18.569us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	23.758us	20	20	100.00
		sram_ctrl_csr_aliasing	0.670s	18.840us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	37.947us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.660s	18.569us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	23.758us	20	20	100.00
		sram_ctrl_csr_aliasing	0.670s	18.840us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	37.947us	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	10.720s	1.729ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.890s	497.299us	5	5	100.00
		sram_ctrl_tl_intg_err	2.800s	2.000ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.890s	497.299us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.800s	2.000ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	33.695m	90.536ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.700s	23.758us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	34.117m	38.588ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	34.117m	38.588ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	34.117m	38.588ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	23.390s	3.281ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	10.720s	1.729ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.129m	652.209us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.129m	652.209us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	34.117m	38.588ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.890s	497.299us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	23.390s	3.281ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.890s	497.299us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.890s	497.299us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.129m	652.209us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.890s	497.299us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.531h	2.509ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1040	1040	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	16	100.00
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.26	99.16	93.54	100.00	70.00	97.41	99.70	100.00

Past Results

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