SRAM_CTRL/RET Simulation Results

Wednesday January 10 2024 20:03:22 UTC

GitHub Revision: `cf38c1d296`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 55803132295021657086212552594002090640066687299415498461130788370399872772386

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.735m	651.808us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.680s	54.565us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.690s	12.137us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.170s	575.350us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.730s	29.822us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.730s	35.027us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.690s	12.137us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	29.822us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	10.550s	3.424ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.610s	634.707us	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	29.602m	238.705ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.526m	11.388ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.577m	62.189ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	25.684m	14.561ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	14.260s	562.983us	39	50	78.00
V2	executable	sram_ctrl_executable	28.612m	76.470ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.790m	1.595ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.941m	92.078ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.837m	140.777us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.019m	300.079us	50	50	100.00
V2	regwen	sram_ctrl_regwen	25.122m	75.163ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.290s	33.506us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.511h	166.898ms	42	50	84.00
V2	alert_test	sram_ctrl_alert_test	0.680s	24.108us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.930s	2.071ms	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.930s	2.071ms	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.680s	54.565us	5	5	100.00
		sram_ctrl_csr_rw	0.690s	12.137us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	29.822us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.750s	25.188us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.680s	54.565us	5	5	100.00
		sram_ctrl_csr_rw	0.690s	12.137us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	29.822us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.750s	25.188us	20	20	100.00
V2		TOTAL			721	740	97.43
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	10.250s	2.132ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.160s	550.684us	5	5	100.00
		sram_ctrl_tl_intg_err	2.370s	260.797us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.160s	550.684us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.370s	260.797us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	25.122m	75.163ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.690s	12.137us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	28.612m	76.470ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	28.612m	76.470ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	28.612m	76.470ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	14.260s	562.983us	39	50	78.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	10.250s	2.132ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.735m	651.808us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.735m	651.808us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	28.612m	76.470ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.160s	550.684us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	14.260s	562.983us	39	50	78.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.160s	550.684us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.160s	550.684us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.735m	651.808us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.160s	550.684us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.824h	2.275ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1021	1040	98.17

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.65	100.00	98.13	100.00	100.00	99.71	99.70	100.00

Failure Buckets

UVM_ERROR (sram_ctrl_scoreboard.sv:369) [scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= * (* [*] vs * [*])

has 19 failures:

Test sram_ctrl_lc_escalation has 11 failures.

0.sram_ctrl_lc_escalation.61534896001974947068408889517544406009830174950342835285898402419270996685851
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 984902560 ps: (sram_ctrl_scoreboard.sv:369) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 984902560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.sram_ctrl_lc_escalation.105262194619726033123818023908949401453211833121305567221813925355763429925960
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 614296421 ps: (sram_ctrl_scoreboard.sv:369) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 614296421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

Test sram_ctrl_stress_all has 8 failures.

2.sram_ctrl_stress_all.102007992416156154200446923078721805931429004581439101156318410909399636412861
Line 272, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 2970035835 ps: (sram_ctrl_scoreboard.sv:369) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 2970035835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.sram_ctrl_stress_all.62866270500486038644158425391108070710837771951303251248926241644803963891588
Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 12597753298 ps: (sram_ctrl_scoreboard.sv:369) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 12597753298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.