SRAM_CTRL/RET Simulation Results

Sunday January 14 2024 20:02:50 UTC

GitHub Revision: `5f48fbc0e7`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 17974844803940076144755676589184454804069451770040436570888369542024131598097

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.870m	3.401ms	49	50	98.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.660s	84.645us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.760s	21.583us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.950s	201.361us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.700s	144.142us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.020s	49.716us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.760s	21.583us	20	20	100.00
		sram_ctrl_csr_aliasing	0.700s	144.142us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	11.230s	5.454ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.990s	181.524us	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	39.938m	105.925ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.485m	4.657ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.216m	15.173ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	38.054m	4.450ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	15.740s	632.782us	43	50	86.00
V2	executable	sram_ctrl_executable	34.023m	6.378ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.954m	6.599ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.103m	106.114ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.884m	503.495us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.644m	163.549us	50	50	100.00
V2	regwen	sram_ctrl_regwen	32.257m	135.907ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.210s	40.435us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.869h	322.327ms	43	50	86.00
V2	alert_test	sram_ctrl_alert_test	0.710s	22.493us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.510s	133.131us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.510s	133.131us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.660s	84.645us	5	5	100.00
		sram_ctrl_csr_rw	0.760s	21.583us	20	20	100.00
		sram_ctrl_csr_aliasing	0.700s	144.142us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	27.453us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.660s	84.645us	5	5	100.00
		sram_ctrl_csr_rw	0.760s	21.583us	20	20	100.00
		sram_ctrl_csr_aliasing	0.700s	144.142us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	27.453us	20	20	100.00
V2		TOTAL			725	740	97.97
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	10.580s	2.682ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.600s	556.521us	5	5	100.00
		sram_ctrl_tl_intg_err	2.770s	445.193us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.600s	556.521us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.770s	445.193us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	32.257m	135.907ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.760s	21.583us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	34.023m	6.378ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	34.023m	6.378ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	34.023m	6.378ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	15.740s	632.782us	43	50	86.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	10.580s	2.682ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.870m	3.401ms	49	50	98.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.870m	3.401ms	49	50	98.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	34.023m	6.378ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.600s	556.521us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	15.740s	632.782us	43	50	86.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.600s	556.521us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.600s	556.521us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.870m	3.401ms	49	50	98.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.600s	556.521us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.766h	4.376ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1024	1040	98.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.65	100.00	98.13	100.00	100.00	99.71	99.70	100.00

Failure Buckets

UVM_ERROR (sram_ctrl_scoreboard.sv:369) [scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= * (* [*] vs * [*]) has 14 failures:

Test sram_ctrl_lc_escalation has 7 failures.

3.sram_ctrl_lc_escalation.42909010568146065284589991630477715428226857604565152998120284877010869419046
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 930388379 ps: (sram_ctrl_scoreboard.sv:369) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 930388379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.sram_ctrl_lc_escalation.54415353012526224043216339245481326144518087626467690669161741668806507066903
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 225992729 ps: (sram_ctrl_scoreboard.sv:369) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 225992729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test sram_ctrl_stress_all has 7 failures.

13.sram_ctrl_stress_all.26127834392711038625048003465625607529755104395278518309814303167156997317464
Line 419, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 8987302763 ps: (sram_ctrl_scoreboard.sv:369) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 8987302763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.sram_ctrl_stress_all.98111672613241822175529051752676395156759911479234839417988420839801827548984
Line 291, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 4700906237 ps: (sram_ctrl_scoreboard.sv:369) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 4700906237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 5.sram_ctrl_regwen.43410260240631596662415449735396247462551853357218458347999567645607689622693
    Line 286, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 60837307370 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x6a0568fe
  UVM_INFO @ 60837307370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_smoke has 1 failures.
  - 32.sram_ctrl_smoke.43725919265700013855356396925817541139173195733373849384049201071113567434715
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/32.sram_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 10255356495 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xb4f9fc38
  UVM_INFO @ 10255356495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```