SRAM_CTRL/RET Simulation Results

Wednesday January 17 2024 20:02:30 UTC

GitHub Revision: `4d88b9516c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 3635458896929517279689574864899235923834879224879080668186365324190153451241

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.529m	550.809us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.690s	21.463us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.720s	24.591us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.120s	151.822us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.710s	20.604us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.950s	73.250us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.720s	24.591us	20	20	100.00
		sram_ctrl_csr_aliasing	0.710s	20.604us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	10.740s	2.817ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.620s	181.324us	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	30.582m	5.887ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.272m	4.552ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.528m	27.108ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	38.574m	5.909ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	20.800s	809.173us	40	50	80.00
V2	executable	sram_ctrl_executable	37.532m	20.284ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.272m	3.363ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.920m	391.602ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.941m	535.448us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.376m	1.484ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	38.693m	20.326ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.400s	116.969us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.756h	71.754ms	45	50	90.00
V2	alert_test	sram_ctrl_alert_test	0.710s	41.759us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.880s	153.270us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.880s	153.270us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.690s	21.463us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	24.591us	20	20	100.00
		sram_ctrl_csr_aliasing	0.710s	20.604us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.790s	22.487us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.690s	21.463us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	24.591us	20	20	100.00
		sram_ctrl_csr_aliasing	0.710s	20.604us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.790s	22.487us	20	20	100.00
V2		TOTAL			725	740	97.97
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	17.390s	694.247us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.240s	1.065ms	5	5	100.00
		sram_ctrl_tl_intg_err	3.160s	580.187us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.240s	1.065ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.160s	580.187us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	38.693m	20.326ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.720s	24.591us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	37.532m	20.284ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	37.532m	20.284ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	37.532m	20.284ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	20.800s	809.173us	40	50	80.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	17.390s	694.247us	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.529m	550.809us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.529m	550.809us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	37.532m	20.284ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.240s	1.065ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	20.800s	809.173us	40	50	80.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.240s	1.065ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.240s	1.065ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.529m	550.809us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.240s	1.065ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.733h	2.732ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1025	1040	98.56

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.65	100.00	98.13	100.00	100.00	99.71	99.70	100.00

Failure Buckets

UVM_ERROR (sram_ctrl_scoreboard.sv:369) [scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= * (* [*] vs * [*]) has 13 failures:

Test sram_ctrl_lc_escalation has 10 failures.

5.sram_ctrl_lc_escalation.92739731715597553649500155160186539002119513029713834692472791962636232054757
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 606240727 ps: (sram_ctrl_scoreboard.sv:369) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 606240727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.sram_ctrl_lc_escalation.15255949942019279998957689697303521074214757809330419498897146711987192468889
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 423995807 ps: (sram_ctrl_scoreboard.sv:369) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 423995807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test sram_ctrl_stress_all has 3 failures.

36.sram_ctrl_stress_all.80440287002067023511061725455381629530020438541894845669525800413556221479865
Line 516, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 10507216448 ps: (sram_ctrl_scoreboard.sv:369) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 10507216448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.sram_ctrl_stress_all.34345851022976763653248387216957797559216435312102820418759324219878175814129
Line 438, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 8545456194 ps: (sram_ctrl_scoreboard.sv:369) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 8545456194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 35.sram_ctrl_stress_all.35105438596581227980893722143567845749842953811775674154431972932989692191505
    Line 295, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 105656849127 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x405206eb
  UVM_INFO @ 105656849127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 43.sram_ctrl_stress_all.30360816650156146289097598431536118785407142590134783380372680526036440788308
    Line 282, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 30669646056 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xa80be85
  UVM_INFO @ 30669646056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```