SRAM_CTRL/RET Simulation Results

Sunday January 21 2024 20:02:56 UTC

GitHub Revision: `796f9fb805`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 82526748448873323296379810788667205332667151893362240729689214265893867671108

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.893m	526.982us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.740s	14.694us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.710s	12.646us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.200s	242.683us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.770s	70.649us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.480s	51.337us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.710s	12.646us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	70.649us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	10.430s	1.331ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.630s	589.028us	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	29.686m	38.906ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.614m	8.168ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.330m	9.253ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	36.732m	20.966ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	13.970s	1.845ms	43	50	86.00
V2	executable	sram_ctrl_executable	29.930m	18.716ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.594m	3.102ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.226m	26.010ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.715m	583.529us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	3.010m	309.841us	50	50	100.00
V2	regwen	sram_ctrl_regwen	36.116m	19.957ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.790s	54.936us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.749h	14.150ms	43	50	86.00
V2	alert_test	sram_ctrl_alert_test	0.710s	89.063us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.640s	983.735us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.640s	983.735us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.740s	14.694us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	12.646us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	70.649us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	120.453us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.740s	14.694us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	12.646us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	70.649us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	120.453us	20	20	100.00
V2		TOTAL			724	740	97.84
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	5.640s	207.538us	0	20	0.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.260s	495.371us	5	5	100.00
		sram_ctrl_tl_intg_err	2.510s	275.640us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.260s	495.371us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.510s	275.640us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	36.116m	19.957ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.710s	12.646us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	29.930m	18.716ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	29.930m	18.716ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	29.930m	18.716ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	13.970s	1.845ms	43	50	86.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	5.640s	207.538us	0	20	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.893m	526.982us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.893m	526.982us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	29.930m	18.716ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.260s	495.371us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	13.970s	1.845ms	43	50	86.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.260s	495.371us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.260s	495.371us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.893m	526.982us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.260s	495.371us	5	5	100.00
V2S		TOTAL			25	45	55.56
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.290h	5.441ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1004	1040	96.54

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	12	75.00
V2S	3	3	2	66.67
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.50	100.00	98.18	100.00	100.00	99.71	99.70	98.89

Failure Buckets

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'success' while register 'sram_ctrl_regs_reg_block.scr_key_rotated' is being accessed has 20 failures:

Test sram_ctrl_passthru_mem_tl_intg_err has 20 failures.

0.sram_ctrl_passthru_mem_tl_intg_err.52898178913973971305775801506375771283317307220697326926353519722248464469607
Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @  13120288 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'success' while register 'sram_ctrl_regs_reg_block.scr_key_rotated' is being accessed
  UVM_INFO @  31381289 ps: (cip_base_vseq__tl_errors.svh:378) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Running run_passthru_mem_tl_intg_err_vseq 2/20
  UVM_INFO @  31454208 ps: (cip_base_vseq__tl_errors.svh:442) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Backdoor inject intg fault to sram_ctrl_prim_reg_block addr 0x1a7eb000
  UVM_INFO @  31454208 ps: (sram_ctrl_common_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Backdoor change mem (addr 0x1a7eb000) value 0xd7fcab13 by flipping bits 4000020100
  UVM_WARNING @  31714633 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'success' while register 'sram_ctrl_regs_reg_block.scr_key_rotated' is being accessed

1.sram_ctrl_passthru_mem_tl_intg_err.12400650182465063689143460109643330122744889454292322314329832474245167223111
Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @  47202310 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'success' while register 'sram_ctrl_regs_reg_block.scr_key_rotated' is being accessed
  UVM_ERROR @  47722310 ps: (sram_ctrl_scoreboard.sv:560) [uvm_test_top.env.scoreboard] Check failed mirrored_value == item.d_data (6 [0x6] vs 5 [0x5]) reg name: sram_ctrl_regs_reg_block.scr_key_rotated
  UVM_INFO @  47722310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 18 more failures.

UVM_ERROR (sram_ctrl_scoreboard.sv:371) [scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= * (* [*] vs * [*]) has 13 failures:

Test sram_ctrl_lc_escalation has 7 failures.

1.sram_ctrl_lc_escalation.9176318960430249990670428866187838515434279872305788035953307563435669526579
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 253221880 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 253221880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.sram_ctrl_lc_escalation.40267183947509253106671765416990743920859550083720642564301179423282124392935
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 260850772 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 260850772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test sram_ctrl_stress_all has 6 failures.

1.sram_ctrl_stress_all.44069545731657110375902241586589757988284392958479507818560041439116912592233
Line 297, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 3644035162 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 3644035162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.sram_ctrl_stress_all.40663496288978937822330312132169988910134903966431357598487093066067342005618
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 329199482 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 329199482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 30.sram_ctrl_regwen.24575365042622270923113952463657921368077522128332142654417801101587119894438
    Line 288, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/30.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 103785375068 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x7a678b8e
  UVM_INFO @ 103785375068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sram_ctrl_stress_all has 1 failures.
  - 34.sram_ctrl_stress_all.65747832770482245427567471497298068970182315328314105910951804193409740548722
    Line 320, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 154416272931 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x70a476c3
  UVM_INFO @ 154416272931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 20.sram_ctrl_multiple_keys.39561069630745930185954847993560126747709954136478113383872394982593891185469
    Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/20.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 27254757918 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xa99954ec
  UVM_INFO @ 27254757918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```