SRAM_CTRL/RET Simulation Results

Wednesday January 24 2024 20:02:24 UTC

GitHub Revision: `17d5a97c3b`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 111545506019531132515166311410934274348263845011639206515682989027305484635840

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.071m	676.468us	49	50	98.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.690s	43.083us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.740s	15.590us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.280s	198.545us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.730s	20.431us	4	5	80.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.540s	33.300us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.740s	15.590us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	20.431us	4	5	80.00
V1	mem_walk	sram_ctrl_mem_walk	11.390s	5.457ms	49	50	98.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.800s	307.476us	49	50	98.00
V1		TOTAL			201	205	98.05
V2	multiple_keys	sram_ctrl_multiple_keys	37.752m	14.012ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.449m	7.861ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.422m	5.482ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	38.618m	13.540ms	49	50	98.00
V2	lc_escalation	sram_ctrl_lc_escalation	14.630s	546.466us	34	50	68.00
V2	executable	sram_ctrl_executable	33.846m	33.395ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.242m	731.394us	50	50	100.00
		sram_ctrl_partial_access_b2b	10.817m	9.380ms	49	50	98.00
V2	max_throughput	sram_ctrl_max_throughput	2.421m	536.763us	48	50	96.00
		sram_ctrl_throughput_w_partial_write	2.701m	1.625ms	49	50	98.00
V2	regwen	sram_ctrl_regwen	41.212m	54.045ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.180s	28.909us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.284h	162.292ms	41	50	82.00
V2	alert_test	sram_ctrl_alert_test	0.740s	12.317us	49	50	98.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.910s	146.894us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.910s	146.894us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.690s	43.083us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	15.590us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	20.431us	4	5	80.00
		sram_ctrl_same_csr_outstanding	0.850s	51.585us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.690s	43.083us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	15.590us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	20.431us	4	5	80.00
		sram_ctrl_same_csr_outstanding	0.850s	51.585us	20	20	100.00
V2		TOTAL			707	740	95.54
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	5.250s	401.365us	0	20	0.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.060s	645.363us	5	5	100.00
		sram_ctrl_tl_intg_err	3.950s	4.213ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.060s	645.363us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.950s	4.213ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	41.212m	54.045ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.740s	15.590us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	33.846m	33.395ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	33.846m	33.395ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	33.846m	33.395ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	14.630s	546.466us	34	50	68.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	5.250s	401.365us	0	20	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.071m	676.468us	49	50	98.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.071m	676.468us	49	50	98.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	33.846m	33.395ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.060s	645.363us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	14.630s	546.466us	34	50	68.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.060s	645.363us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.060s	645.363us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.071m	676.468us	49	50	98.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.060s	645.363us	5	5	100.00
V2S		TOTAL			25	45	55.56
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.828h	7.162ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			982	1040	94.42

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	4	50.00
V2	16	16	7	43.75
V2S	3	3	2	66.67
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.50	100.00	98.18	100.00	100.00	99.71	99.70	98.89

Failure Buckets

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'success' while register 'sram_ctrl_regs_reg_block.scr_key_rotated' is being accessed has 20 failures:

Test sram_ctrl_passthru_mem_tl_intg_err has 20 failures.

0.sram_ctrl_passthru_mem_tl_intg_err.42643922531409505540780763555709535912146928143156720574683836432079351431602
Line 271, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @  49195836 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'success' while register 'sram_ctrl_regs_reg_block.scr_key_rotated' is being accessed
  UVM_INFO @  49326270 ps: (cip_base_vseq__tl_errors.svh:442) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Backdoor inject intg fault to sram_ctrl_prim_reg_block addr 0x2ae200c
  UVM_INFO @  49326270 ps: (sram_ctrl_common_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Backdoor change mem (addr 0x2ae200c) value 0xf779d6e8 by flipping bits 4000040040
  UVM_INFO @ 123151914 ps: (cip_base_vseq__tl_errors.svh:378) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Running run_passthru_mem_tl_intg_err_vseq 2/20
  UVM_INFO @ 123412782 ps: (cip_base_vseq__tl_errors.svh:442) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Backdoor inject intg fault to sram_ctrl_prim_reg_block addr 0x2ae2000

1.sram_ctrl_passthru_mem_tl_intg_err.65908788696789287764505822835463642477537657605555655437461947193174645273302
Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 161127316 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'success' while register 'sram_ctrl_regs_reg_block.scr_key_rotated' is being accessed
  UVM_INFO @ 385984234 ps: (cip_base_vseq__tl_errors.svh:378) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Running run_passthru_mem_tl_intg_err_vseq 2/10
  UVM_INFO @ 386269948 ps: (cip_base_vseq__tl_errors.svh:442) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Backdoor inject intg fault to sram_ctrl_prim_reg_block addr 0x6970d004
  UVM_INFO @ 386269948 ps: (sram_ctrl_common_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Backdoor change mem (addr 0x6970d004) value 0xd74a7cb7 by flipping bits 4800000200
  UVM_WARNING @ 386698519 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'success' while register 'sram_ctrl_regs_reg_block.scr_key_rotated' is being accessed

... and 18 more failures.

UVM_ERROR (sram_ctrl_scoreboard.sv:371) [scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= * (* [*] vs * [*]) has 20 failures:

Test sram_ctrl_lc_escalation has 14 failures.

2.sram_ctrl_lc_escalation.67898025434681170712168506807263633675967477222939693654263424914471264851822
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 1657155390 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 1657155390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.sram_ctrl_lc_escalation.110298029577848549232966359781912634513482779037839182470197642891859008016726
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 493393426 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 493393426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

Test sram_ctrl_stress_all has 6 failures.

13.sram_ctrl_stress_all.79003127303423043674427547550232489622289648673076880827227882608274282480180
Line 344, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 4070579916 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 4070579916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.sram_ctrl_stress_all.96467500905626997870549615286511599265102701835534357572021260980901361017106
Line 372, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 5762661708 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 5762661708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Job sram_ctrl_ret-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 5 failures:
- Test sram_ctrl_bijection has 1 failures.
  - 4.sram_ctrl_bijection.21648229241586821611890866931897885899027772407327931314651718817498063230577
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_bijection/latest/run.log
```
  Job ID: smart:fab4806f-c71f-4d11-9c14-028ca99c5940
```
- Test sram_ctrl_mem_walk has 1 failures.
  - 13.sram_ctrl_mem_walk.54581591564927062118859900553141939714726410424709718567724930318576720582666
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_mem_walk/latest/run.log
```
  Job ID: smart:72b5cfba-73a8-4f73-92cd-a29d66661530
```
- Test sram_ctrl_access_during_key_req has 1 failures.
  - 24.sram_ctrl_access_during_key_req.78742741440926146419079650050190205634369425210605153272665322357498263063153
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_access_during_key_req/latest/run.log
```
  Job ID: smart:ad2a7be4-3e73-456b-8860-6a11b8b42eed
```
- Test sram_ctrl_mem_partial_access has 1 failures.
  - 28.sram_ctrl_mem_partial_access.44780998208830178497487572392567681837927579276365172835671598101662349357134
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/28.sram_ctrl_mem_partial_access/latest/run.log
```
  Job ID: smart:23a19c6c-41da-4d33-b89e-865c3e0386cc
```
- Test sram_ctrl_smoke has 1 failures.
  - 43.sram_ctrl_smoke.115490762066316616407088676336701458827742445325225628504045248823160530373472
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/43.sram_ctrl_smoke/latest/run.log
```
  Job ID: smart:975c22d7-4353-44a0-a4d1-be5875d7d35b
```
Job sram_ctrl_ret-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 3 failures:
- Test sram_ctrl_lc_escalation has 1 failures.
  - 8.sram_ctrl_lc_escalation.18094561875668260428140893744865969502043417255636747055798327090495826349788
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_lc_escalation/latest/run.log
```
  Job ID: smart:5cd3cfce-7a32-454a-b062-c587e0c62ca4
```
- Test sram_ctrl_multiple_keys has 1 failures.
  - 27.sram_ctrl_multiple_keys.77581179773122618682543267305920876925720727742043004424260169331492525905505
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/27.sram_ctrl_multiple_keys/latest/run.log
```
  Job ID: smart:3ed7372c-3d28-4cc4-b378-a943ef7cbd0a
```
- Test sram_ctrl_throughput_w_partial_write has 1 failures.
  - 45.sram_ctrl_throughput_w_partial_write.14764432173887853234456101440885087462467468443234977571042412701194859477964
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/45.sram_ctrl_throughput_w_partial_write/latest/run.log
```
  Job ID: smart:ef35449c-b0f9-4162-b95a-79d542a8cad8
```
Job sram_ctrl_ret-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 3 failures:
- Test sram_ctrl_max_throughput has 2 failures.
  - 19.sram_ctrl_max_throughput.112094242232790195894078859208104308468556354013878582416453355822529922718646
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_max_throughput/latest/run.log
```
  Job ID: smart:bbba8d51-25de-46bd-94e4-355924e8129f
```
  - 40.sram_ctrl_max_throughput.107414662493253533558420248704233105390675647538112271202782461512709503694097
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/40.sram_ctrl_max_throughput/latest/run.log
```
  Job ID: smart:46b8f5e2-00d4-4cf9-9b6c-755999d3bfa5
```
- Test sram_ctrl_stress_all has 1 failures.
  - 30.sram_ctrl_stress_all.15148919942277217571027250727908664370568491198167504087944161553318989533096
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_all/latest/run.log
```
  Job ID: smart:bff7581c-3710-46c0-8c3e-d08de4c523c4
```
UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_stress_all has 2 failures.
  - 0.sram_ctrl_stress_all.893783068718690772090838285992342630841126750032248821924660492859779786851
    Line 336, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 220577197006 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x4856bff9
  UVM_INFO @ 220577197006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.sram_ctrl_stress_all.81545265048400377302850584121886919879952024118281500562042181737854527548168
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 11182897616 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x6dfb9ed6
  UVM_INFO @ 11182897616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job sram_ctrl_ret-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 2 failures:
- Test sram_ctrl_alert_test has 1 failures.
  - 1.sram_ctrl_alert_test.74330051506676915075176992702808326726096567796463336903433963553751864841147
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_alert_test/latest/run.log
```
  Job ID: smart:a9623bd4-4f21-46cb-9cbb-e5ef5e803aa0
```
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 7.sram_ctrl_stress_all_with_rand_reset.37678046401398593676709457113724222790494218535071528150650449618542511797306
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:504a11e4-a60b-4f29-93bf-64c60ab871b5
```
Job sram_ctrl_ret-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 2 failures:
- Test sram_ctrl_partial_access_b2b has 1 failures.
  - 22.sram_ctrl_partial_access_b2b.97072152112788543016612777097909597957828946950103124254838072900638660740220
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_partial_access_b2b/latest/run.log
```
  Job ID: smart:83a1d6a7-074f-40aa-ab10-d1afd933881d
```
- Test sram_ctrl_lc_escalation has 1 failures.
  - 39.sram_ctrl_lc_escalation.114202765015091720443135593099535802663028500236021612111820558816288863191941
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/39.sram_ctrl_lc_escalation/latest/run.log
```
  Job ID: smart:21b7ee77-7fcb-40b3-9dc5-31e8f3cc88b1
```
Job sram_ctrl_ret-sim-vcs_run_cover_reg_top killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:
- Test sram_ctrl_csr_aliasing has 1 failures.
  - 0.sram_ctrl_csr_aliasing.71230069659488384537537878734290534391978309618446374910499920949411290355339
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_aliasing/latest/run.log
```
  Job ID: smart:6fd4b174-0f4b-4ab3-b6b7-e7f6e0618f7b
```