4ddd81322f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | sram_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| sram_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | mem_walk | sram_ctrl_mem_walk | 0 | 50 | 0.00 | ||
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 0 | 50 | 0.00 | ||
| V1 | TOTAL | 0 | 205 | 0.00 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 0 | 50 | 0.00 | ||
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 0 | 50 | 0.00 | ||
| V2 | bijection | sram_ctrl_bijection | 0 | 50 | 0.00 | ||
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 0 | 50 | 0.00 | ||
| V2 | lc_escalation | sram_ctrl_lc_escalation | 0 | 50 | 0.00 | ||
| V2 | executable | sram_ctrl_executable | 0 | 50 | 0.00 | ||
| V2 | partial_access | sram_ctrl_partial_access | 0 | 50 | 0.00 | ||
| sram_ctrl_partial_access_b2b | 0 | 50 | 0.00 | ||||
| V2 | max_throughput | sram_ctrl_max_throughput | 0 | 50 | 0.00 | ||
| sram_ctrl_throughput_w_partial_write | 0 | 50 | 0.00 | ||||
| V2 | regwen | sram_ctrl_regwen | 0 | 50 | 0.00 | ||
| V2 | ram_cfg | sram_ctrl_ram_cfg | 0 | 50 | 0.00 | ||
| V2 | stress_all | sram_ctrl_stress_all | 0 | 50 | 0.00 | ||
| V2 | alert_test | sram_ctrl_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| sram_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| sram_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| sram_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| sram_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| sram_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| sram_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 740 | 0.00 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | tl_intg_err | sram_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| sram_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | prim_count_check | sram_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 0 | 50 | 0.00 | ||
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 0 | 50 | 0.00 | ||
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 0 | 50 | 0.00 | ||
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 0 | 50 | 0.00 | ||
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 0 | 50 | 0.00 | ||
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 0 | 50 | 0.00 | ||
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 0 | 50 | 0.00 | ||
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | TOTAL | 0 | 45 | 0.00 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 1040 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 0 | 0.00 |
| V2 | 16 | 16 | 0 | 0.00 |
| V2S | 3 | 3 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 1042 failures:
0.sram_ctrl_smoke.51794002057558988746630221853649933309435464780433179904759606742417951072097
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_smoke/latest/run.log
1.sram_ctrl_smoke.46220071541944104422863188694970777900458644103359353109979903711511406881677
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_smoke/latest/run.log
... and 48 more failures.
0.sram_ctrl_multiple_keys.2354503629999116999914444192541002681018689416962001693362984702596207190389
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_multiple_keys/latest/run.log
1.sram_ctrl_multiple_keys.46047393655234291143639383290647191352753516884629660953727797810757643963816
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_multiple_keys/latest/run.log
... and 48 more failures.
0.sram_ctrl_bijection.32208087534773920398481084411201277354395056564283438451541023121622562646767
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_bijection/latest/run.log
1.sram_ctrl_bijection.35098388750478337147596074969489307089942344620271080890160186984626606169162
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_bijection/latest/run.log
... and 48 more failures.
0.sram_ctrl_stress_pipeline.26974587565387663882021288634367224971510297425557730101217006641092184211601
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_pipeline/latest/run.log
1.sram_ctrl_stress_pipeline.70161396955224350846500785375318616229534538754578924819083377474644525689403
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_pipeline/latest/run.log
... and 48 more failures.
0.sram_ctrl_partial_access.14779433504674267584368819367195245329642156705239190439990804182474620079412
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access/latest/run.log
1.sram_ctrl_partial_access.67068933538998399356897611403425607678251691760837378034842379134879721660196
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_partial_access/latest/run.log
... and 48 more failures.
Test default has 1 failures.
Test cover_reg_top has 1 failures.