SRAM_CTRL/RET Simulation Results

Sunday February 04 2024 20:02:57 UTC

GitHub Revision: `0dd29ab736`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 76373007482531906509957308269646114477602578576554530782790132514100107307713

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	3.020m	2.861ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.680s	18.824us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.730s	39.724us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.220s	466.023us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.750s	55.155us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.770s	311.804us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.730s	39.724us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	55.155us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	11.430s	3.274ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.910s	804.398us	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	30.313m	97.044ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.648m	26.566ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.378m	5.690ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	33.617m	22.639ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	17.500s	571.410us	46	50	92.00
V2	executable	sram_ctrl_executable	42.908m	28.151ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.752m	3.350ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.867m	263.739ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.783m	528.373us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.925m	593.377us	50	50	100.00
V2	regwen	sram_ctrl_regwen	34.114m	40.912ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.250s	56.962us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.692h	199.331ms	46	50	92.00
V2	alert_test	sram_ctrl_alert_test	0.760s	13.123us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.110s	482.187us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.110s	482.187us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.680s	18.824us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	39.724us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	55.155us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	21.929us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.680s	18.824us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	39.724us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	55.155us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	21.929us	20	20	100.00
V2		TOTAL			731	740	98.78
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.550s	630.866us	0	20	0.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.310s	1.562ms	5	5	100.00
		sram_ctrl_tl_intg_err	2.990s	4.272ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.310s	1.562ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.990s	4.272ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	34.114m	40.912ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.730s	39.724us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	42.908m	28.151ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	42.908m	28.151ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	42.908m	28.151ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	17.500s	571.410us	46	50	92.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.550s	630.866us	0	20	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	3.020m	2.861ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	3.020m	2.861ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	42.908m	28.151ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.310s	1.562ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	17.500s	571.410us	46	50	92.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.310s	1.562ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.310s	1.562ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	3.020m	2.861ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.310s	1.562ms	5	5	100.00
V2S		TOTAL			25	45	55.56
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.348h	9.245ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1011	1040	97.21

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	2	66.67
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.50	100.00	98.18	100.00	100.00	99.71	99.70	98.89

Failure Buckets

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'success' while register 'sram_ctrl_regs_reg_block.scr_key_rotated' is being accessed

has 20 failures:

Test sram_ctrl_passthru_mem_tl_intg_err has 20 failures.

0.sram_ctrl_passthru_mem_tl_intg_err.5044973205680882572732958492578077408921686357106566497639419636072181642557
Line 271, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @  41320459 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'success' while register 'sram_ctrl_regs_reg_block.scr_key_rotated' is being accessed
  UVM_INFO @  41331570 ps: (cip_base_vseq__tl_errors.svh:442) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Backdoor inject intg fault to sram_ctrl_prim_reg_block addr 0x4c0c9008
  UVM_INFO @  41331570 ps: (sram_ctrl_common_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Backdoor change mem (addr 0x4c0c9008) value 0x27ec66fb by flipping bits 810010000
  UVM_INFO @  41364903 ps: (dv_base_reg.sv:316) [sram_ctrl_regs_reg_block.ctrl_regwen] lock_lockable_flds 1376273040 val
  UVM_INFO @  41431569 ps: (dv_base_reg.sv:316) [sram_ctrl_regs_reg_block.exec_regwen] lock_lockable_flds  298353359 val

1.sram_ctrl_passthru_mem_tl_intg_err.83061068546088054256678753465676462214432102215598569042772798140215748965486
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @  51736021 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'success' while register 'sram_ctrl_regs_reg_block.scr_key_rotated' is being accessed
  UVM_INFO @  52194358 ps: (dv_base_reg.sv:316) [sram_ctrl_regs_reg_block.ctrl_regwen] lock_lockable_flds  168047481 val
  UVM_INFO @  53527702 ps: (dv_base_reg.sv:316) [sram_ctrl_regs_reg_block.exec_regwen] lock_lockable_flds          1 val
  UVM_INFO @  54569377 ps: (dv_base_reg.sv:316) [sram_ctrl_regs_reg_block.ctrl_regwen] lock_lockable_flds          1 val
  UVM_INFO @ 139070053 ps: (cip_base_vseq__tl_errors.svh:378) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Running run_passthru_mem_tl_intg_err_vseq 2/10

... and 18 more failures.

UVM_ERROR (sram_ctrl_scoreboard.sv:371) [scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= * (* [*] vs * [*])

has 8 failures:

Test sram_ctrl_stress_all has 4 failures.

11.sram_ctrl_stress_all.88399799282843121019775400716683890682577428481955934842413839677411358893131
Line 406, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 7243377161 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 7243377161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.sram_ctrl_stress_all.29232703340454737129405333280460961253646639570880327272637987183459797693522
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 2868101415 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 2868101415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test sram_ctrl_lc_escalation has 4 failures.

28.sram_ctrl_lc_escalation.35932699231279713344045765668686907154562819757296674001736493295672868928682
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/28.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @  88460411 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @  88460411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.sram_ctrl_lc_escalation.59739618744783408965222929973476588861331119558521338136104990593574059169329
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/33.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @  32366536 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @  32366536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 28.sram_ctrl_regwen.98316547296947759368977828699690200712675322881227455371245353634896353301838
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/28.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 14582388337 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xe012a76c
  UVM_INFO @ 14582388337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```