SRAM_CTRL/RET Simulation Results

Wednesday February 07 2024 20:02:46 UTC

GitHub Revision: `5c87d18988`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 42540109002295994234923032062842839138270099951232798724643629525632267455156

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.579m	747.863us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.680s	21.716us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.720s	15.927us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.230s	620.716us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.750s	50.465us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.300s	57.570us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.720s	15.927us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	50.465us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	10.610s	2.619ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.870s	533.591us	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	29.900m	24.191ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.825m	4.246ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.433m	10.831ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	28.227m	18.043ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	19.620s	10.154ms	46	50	92.00
V2	executable	sram_ctrl_executable	28.369m	3.385ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	3.049m	7.580ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.235m	114.226ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.217m	533.508us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.926m	157.442us	50	50	100.00
V2	regwen	sram_ctrl_regwen	31.608m	29.998ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.750s	50.358us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.829h	177.637ms	46	50	92.00
V2	alert_test	sram_ctrl_alert_test	0.720s	23.574us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.060s	180.253us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.060s	180.253us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.680s	21.716us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	15.927us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	50.465us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	40.380us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.680s	21.716us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	15.927us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	50.465us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	40.380us	20	20	100.00
V2		TOTAL			730	740	98.65
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	5.870s	1.834ms	0	20	0.00
V2S	tl_intg_err	sram_ctrl_sec_cm	4.080s	620.264us	5	5	100.00
		sram_ctrl_tl_intg_err	3.700s	2.229ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	4.080s	620.264us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.700s	2.229ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	31.608m	29.998ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.720s	15.927us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	28.369m	3.385ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	28.369m	3.385ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	28.369m	3.385ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	19.620s	10.154ms	46	50	92.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	5.870s	1.834ms	0	20	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.579m	747.863us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.579m	747.863us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	28.369m	3.385ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	4.080s	620.264us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	19.620s	10.154ms	46	50	92.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	4.080s	620.264us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	4.080s	620.264us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.579m	747.863us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	4.080s	620.264us	5	5	100.00
V2S		TOTAL			25	45	55.56
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.852h	1.831ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1010	1040	97.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	12	75.00
V2S	3	3	2	66.67
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.47	100.00	98.18	100.00	100.00	99.71	99.70	98.70

Failure Buckets

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'success' while register 'sram_ctrl_regs_reg_block.scr_key_rotated' is being accessed has 20 failures:

Test sram_ctrl_passthru_mem_tl_intg_err has 20 failures.

0.sram_ctrl_passthru_mem_tl_intg_err.71468932978677100616804867921207299742630495562964794694231412040858504293986
Line 275, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @  36408715 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'success' while register 'sram_ctrl_regs_reg_block.scr_key_rotated' is being accessed
  UVM_INFO @  36512880 ps: (dv_base_reg.sv:316) [sram_ctrl_regs_reg_block.exec_regwen] lock_lockable_flds          0 val
  UVM_INFO @  36554546 ps: (dv_base_reg.sv:316) [sram_ctrl_regs_reg_block.ctrl_regwen] lock_lockable_flds          0 val
  UVM_ERROR @  36700377 ps: (sram_ctrl_scoreboard.sv:560) [uvm_test_top.env.scoreboard] Check failed mirrored_value == item.d_data (6 [0x6] vs 5 [0x5]) reg name: sram_ctrl_regs_reg_block.scr_key_rotated
  UVM_INFO @  36700377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

1.sram_ctrl_passthru_mem_tl_intg_err.113365815516475447027385185142880564426063288378302302620293948734624645279913
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 102526170 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'success' while register 'sram_ctrl_regs_reg_block.scr_key_rotated' is being accessed
  UVM_INFO @ 103071624 ps: (dv_base_reg.sv:316) [sram_ctrl_regs_reg_block.ctrl_regwen] lock_lockable_flds 3708593291 val
  UVM_INFO @ 103344351 ps: (dv_base_reg.sv:316) [sram_ctrl_regs_reg_block.exec_regwen] lock_lockable_flds          0 val
  UVM_INFO @ 104435259 ps: (dv_base_reg.sv:316) [sram_ctrl_regs_reg_block.ctrl_regwen] lock_lockable_flds          1 val
  UVM_INFO @ 251435112 ps: (cip_base_vseq__tl_errors.svh:378) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Running run_passthru_mem_tl_intg_err_vseq 2/20

... and 18 more failures.

UVM_ERROR (sram_ctrl_scoreboard.sv:371) [scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= * (* [*] vs * [*]) has 8 failures:

Test sram_ctrl_lc_escalation has 4 failures.

6.sram_ctrl_lc_escalation.38977074675015180708863507698918229751395878054138447689700723458936418220575
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 555757162 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 555757162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.sram_ctrl_lc_escalation.8164751198828466262872544344984159283117239195338896680635139390282417003673
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 792378090 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 792378090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test sram_ctrl_stress_all has 4 failures.

13.sram_ctrl_stress_all.13998286133414538538284230953558561197931307680294345486769936942718618201307
Line 272, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 565981741 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 565981741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.sram_ctrl_stress_all.70228103795380776906632050726038622642394716284943286098975707126928410999993
Line 509, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 10579859526 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 10579859526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 2.sram_ctrl_executable.54955698420308333467076348164450958561196492217273883637348415599396310674532
    Line 292, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 114468064863 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x499ca951
  UVM_INFO @ 114468064863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 9.sram_ctrl_regwen.34033626820781223392340190962973300553598908504371421224048546042882549993790
    Line 283, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 43800180778 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xcc36b50a
  UVM_INFO @ 43800180778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```