93b7cb99d8
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | sram_ctrl_smoke | 0 | 50 | 0.00 | ||
V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
V1 | csr_rw | sram_ctrl_csr_rw | 0 | 20 | 0.00 | ||
V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 0 | 5 | 0.00 | ||
V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||
V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 0 | 20 | 0.00 | ||
sram_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
V1 | mem_walk | sram_ctrl_mem_walk | 0 | 50 | 0.00 | ||
V1 | mem_partial_access | sram_ctrl_mem_partial_access | 0 | 50 | 0.00 | ||
V1 | TOTAL | 0 | 205 | 0.00 | |||
V2 | multiple_keys | sram_ctrl_multiple_keys | 0 | 50 | 0.00 | ||
V2 | stress_pipeline | sram_ctrl_stress_pipeline | 0 | 50 | 0.00 | ||
V2 | bijection | sram_ctrl_bijection | 0 | 50 | 0.00 | ||
V2 | access_during_key_req | sram_ctrl_access_during_key_req | 0 | 50 | 0.00 | ||
V2 | lc_escalation | sram_ctrl_lc_escalation | 0 | 50 | 0.00 | ||
V2 | executable | sram_ctrl_executable | 0 | 50 | 0.00 | ||
V2 | partial_access | sram_ctrl_partial_access | 0 | 50 | 0.00 | ||
sram_ctrl_partial_access_b2b | 0 | 50 | 0.00 | ||||
V2 | max_throughput | sram_ctrl_max_throughput | 0 | 50 | 0.00 | ||
sram_ctrl_throughput_w_partial_write | 0 | 50 | 0.00 | ||||
V2 | regwen | sram_ctrl_regwen | 0 | 50 | 0.00 | ||
V2 | ram_cfg | sram_ctrl_ram_cfg | 0 | 50 | 0.00 | ||
V2 | stress_all | sram_ctrl_stress_all | 0 | 50 | 0.00 | ||
V2 | alert_test | sram_ctrl_alert_test | 0 | 50 | 0.00 | ||
V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 0 | 20 | 0.00 | ||
V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 0 | 20 | 0.00 | ||
V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
sram_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
sram_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
sram_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
sram_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
sram_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
sram_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
V2 | TOTAL | 0 | 740 | 0.00 | |||
V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 0 | 20 | 0.00 | ||
V2S | tl_intg_err | sram_ctrl_sec_cm | 0 | 5 | 0.00 | ||
sram_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||||
V2S | prim_count_check | sram_ctrl_sec_cm | 0 | 5 | 0.00 | ||
V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||
V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 0 | 50 | 0.00 | ||
V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 0 | 20 | 0.00 | ||
V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 0 | 50 | 0.00 | ||
V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 0 | 50 | 0.00 | ||
V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 0 | 50 | 0.00 | ||
V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 0 | 50 | 0.00 | ||
V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 0 | 20 | 0.00 | ||
V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 0 | 50 | 0.00 | ||
V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 0 | 50 | 0.00 | ||
V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 0 | 50 | 0.00 | ||
V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 0 | 5 | 0.00 | ||
V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 0 | 50 | 0.00 | ||
V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 0 | 5 | 0.00 | ||
V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 0 | 5 | 0.00 | ||
V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 0 | 50 | 0.00 | ||
V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 0 | 5 | 0.00 | ||
V2S | TOTAL | 0 | 45 | 0.00 | |||
V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
V3 | TOTAL | 0 | 50 | 0.00 | |||
TOTAL | 0 | 1040 | 0.00 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 0 | 0.00 |
V2 | 16 | 16 | 0 | 0.00 |
V2S | 3 | 3 | 0 | 0.00 |
V3 | 1 | 1 | 0 | 0.00 |
Job killed most likely because its dependent job failed.
has 1042 failures:
0.sram_ctrl_smoke.58018736703620524715006725517184715884760093531632531466142751960337791253410
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_smoke/latest/run.log
1.sram_ctrl_smoke.26122751678773233494619034986624965244530931502796767474392056407423879604232
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_smoke/latest/run.log
... and 48 more failures.
0.sram_ctrl_multiple_keys.12298996687951285966772977060259170772116104998676081189107795536612991517071
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_multiple_keys/latest/run.log
1.sram_ctrl_multiple_keys.37933787349437141751532345187073233440435842862363131155331043828047961266886
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_multiple_keys/latest/run.log
... and 48 more failures.
0.sram_ctrl_bijection.74185799524526043237854861951547092946908358276351897778431175751509172918475
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_bijection/latest/run.log
1.sram_ctrl_bijection.69250276796839650822985321616328630939945635326795712678735339608101433617302
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_bijection/latest/run.log
... and 48 more failures.
0.sram_ctrl_stress_pipeline.105994003652925791189896787681300567757297247214491762912898900280430891577675
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_pipeline/latest/run.log
1.sram_ctrl_stress_pipeline.2409251072972711394868177505239661237062233690100224359189685663256790869394
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_pipeline/latest/run.log
... and 48 more failures.
0.sram_ctrl_partial_access.12863479066345013977474977823503256349647856900941821336019841788054683557201
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access/latest/run.log
1.sram_ctrl_partial_access.26615748817702069688716025425024156568280725461373590575657479596640668480840
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_partial_access/latest/run.log
... and 48 more failures.
Job sram_ctrl_ret-sim-vcs_build_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 1 failures:
default
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/build.log
Job ID: smart:ca5bc602-ce14-40a0-9c3b-ad60f1ca690a
Job sram_ctrl_ret-sim-vcs_build_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 1 failures:
cover_reg_top
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/build.log
Job ID: smart:a32c98ce-9405-429d-a7a5-9088ce229269