SRAM_CTRL/RET Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: `8faf04697a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.496m	143.433us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.720s	40.621us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.770s	84.274us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.280s	184.192us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.770s	61.782us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.880s	36.454us	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.770s	84.274us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	61.782us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	10.880s	4.412ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.290s	150.113us	50	50	100.00
V1		TOTAL			185	205	90.24
V2	multiple_keys	sram_ctrl_multiple_keys	30.816m	16.036ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.209m	16.900ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.570m	1.955ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	34.071m	39.036ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	16.370s	603.842us	38	50	76.00
V2	executable	sram_ctrl_executable	29.418m	6.261ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.863m	782.059us	50	50	100.00
		sram_ctrl_partial_access_b2b	11.895m	102.992ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.775m	352.157us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.793m	929.681us	50	50	100.00
V2	regwen	sram_ctrl_regwen	24.186m	10.973ms	48	50	96.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.250s	32.092us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.245h	62.305ms	46	50	92.00
V2	alert_test	sram_ctrl_alert_test	0.740s	19.353us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.490s	446.668us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.490s	446.668us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.720s	40.621us	5	5	100.00
		sram_ctrl_csr_rw	0.770s	84.274us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	61.782us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.850s	26.801us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.720s	40.621us	5	5	100.00
		sram_ctrl_csr_rw	0.770s	84.274us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	61.782us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.850s	26.801us	20	20	100.00
V2		TOTAL			722	740	97.57
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	5.670s	428.119us	0	20	0.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.840s	1.627ms	5	5	100.00
		sram_ctrl_tl_intg_err	2.720s	2.611ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.840s	1.627ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.720s	2.611ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	24.186m	10.973ms	48	50	96.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.770s	84.274us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	29.418m	6.261ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	29.418m	6.261ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	29.418m	6.261ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	16.370s	603.842us	38	50	76.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	5.670s	428.119us	0	20	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.496m	143.433us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.496m	143.433us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	29.418m	6.261ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.840s	1.627ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	16.370s	603.842us	38	50	76.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.840s	1.627ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.840s	1.627ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.496m	143.433us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.840s	1.627ms	5	5	100.00
V2S		TOTAL			25	45	55.56
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.037m	747.151us	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			932	1040	89.62

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	13	81.25
V2S	3	3	2	66.67
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.26	100.00	97.48	100.00	100.00	99.14	99.70	98.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:756) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 50 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 50 failures.
  - 0.sram_ctrl_stress_all_with_rand_reset.41633658821248502857438167479238720327813921723463004420116330175920156150853
    Line 281, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3143942339 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 3143942339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.sram_ctrl_stress_all_with_rand_reset.31869798077373038298650696176307128128179551567214979164608908148696792627865
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 462584019 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 462584019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 48 more failures.

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'success' while register 'sram_ctrl_regs_reg_block.scr_key_rotated' is being accessed has 20 failures:

Test sram_ctrl_passthru_mem_tl_intg_err has 20 failures.

0.sram_ctrl_passthru_mem_tl_intg_err.27261794906920406311690135375596449800278900144823072883125700756462727501931
Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @  49023113 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'success' while register 'sram_ctrl_regs_reg_block.scr_key_rotated' is being accessed
  UVM_INFO @  49240503 ps: (dv_base_reg.sv:316) [sram_ctrl_regs_reg_block.exec_regwen] lock_lockable_flds 3590051911 val
  UVM_INFO @  49762239 ps: (dv_base_reg.sv:316) [sram_ctrl_regs_reg_block.ctrl_regwen] lock_lockable_flds          1 val
  UVM_INFO @  49849195 ps: (dv_base_reg.sv:316) [sram_ctrl_regs_reg_block.exec_regwen] lock_lockable_flds          1 val
  UVM_INFO @ 140674737 ps: (cip_base_vseq__tl_errors.svh:378) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Running run_passthru_mem_tl_intg_err_vseq 2/10

1.sram_ctrl_passthru_mem_tl_intg_err.94609296217354998147825609013084515823959312128136308499579043829748082159729
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @  51005319 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'success' while register 'sram_ctrl_regs_reg_block.scr_key_rotated' is being accessed
  UVM_INFO @  51421989 ps: (dv_base_reg.sv:316) [sram_ctrl_regs_reg_block.ctrl_regwen] lock_lockable_flds 3286667535 val
  UVM_INFO @  53088669 ps: (dv_base_reg.sv:316) [sram_ctrl_regs_reg_block.exec_regwen] lock_lockable_flds          0 val
  UVM_INFO @  54213678 ps: (dv_base_reg.sv:316) [sram_ctrl_regs_reg_block.ctrl_regwen] lock_lockable_flds          1 val
  UVM_INFO @ 120130872 ps: (cip_base_vseq__tl_errors.svh:378) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Running run_passthru_mem_tl_intg_err_vseq 2/10

... and 18 more failures.

UVM_ERROR (sram_ctrl_scoreboard.sv:371) [scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= * (* [*] vs * [*]) has 16 failures:

Test sram_ctrl_lc_escalation has 12 failures.

2.sram_ctrl_lc_escalation.61132848534121030653653000990650618853541941626123809494279255707349755016627
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 391721268 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 391721268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.sram_ctrl_lc_escalation.40189307006827824369361840732483486102929712779596995150862140077117649637698
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 1588404001 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 1588404001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

Test sram_ctrl_stress_all has 4 failures.

14.sram_ctrl_stress_all.50656648921685027439195613028338308418132998661582768447058841009710823796141
Line 414, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 24724726848 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 24724726848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.sram_ctrl_stress_all.93100895983888079093668969604649793269943327883372416007902794378401010732288
Line 272, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 287208937 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 287208937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 9 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 9 failures.
  - 1.sram_ctrl_csr_mem_rw_with_rand_reset.31464084072621465871804746115949881940391709662267606398976184603843291517248
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 169077623 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @ 169077623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.sram_ctrl_csr_mem_rw_with_rand_reset.4186461246489640555702889045784781843218076559400014194961010131932554480378
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 166117209 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @ 166117209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 4 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 4 failures.
  - 2.sram_ctrl_csr_mem_rw_with_rand_reset.50463708269534063781106194330500201923364216239110478886132444132389375038413
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  23965647 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  23965647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.sram_ctrl_csr_mem_rw_with_rand_reset.91405867080367759028684632342809353813325351380618519983914566295564645572839
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  91660373 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (12 [0xc] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  91660373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: * has 3 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 3 failures.
  - 0.sram_ctrl_csr_mem_rw_with_rand_reset.68909153750410067740709657186551108663194387419990416220516687366552134379413
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  24943352 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: 0x0
  UVM_INFO @  24943352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.sram_ctrl_csr_mem_rw_with_rand_reset.112748855186969967044132854083657374483918801926878797521911607138132233556163
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  26530328 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: 0x0
  UVM_INFO @  26530328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 2 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 5.sram_ctrl_csr_mem_rw_with_rand_reset.38288176509758297509752113975464611087154047601797887062110448357927909061185
    Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  24948394 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  24948394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.sram_ctrl_csr_mem_rw_with_rand_reset.73030403777778944425033153673719021031795999175574793709421670390455206636646
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  50979013 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  50979013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: * has 2 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 6.sram_ctrl_csr_mem_rw_with_rand_reset.95319100538601545349096101423799482519605636863257585106340811501390513722979
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  24706793 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
  UVM_INFO @  24706793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.sram_ctrl_csr_mem_rw_with_rand_reset.8346901075651039594382504655343260083008501400016485864773969351227779535299
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 242818718 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
  UVM_INFO @ 242818718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_regwen has 2 failures.
  - 27.sram_ctrl_regwen.85104157389936891403011291625373118014275800611474849774528880553996762007491
    Line 290, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/27.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 44690363108 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x898e4de2
  UVM_INFO @ 44690363108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.sram_ctrl_regwen.7084360908040083318172833724202233532429132263458216908698708301882601798264
    Line 286, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/39.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 34049953698 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x1403ef84
  UVM_INFO @ 34049953698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```