39f3866b56| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 2.279m | 641.433us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0.730s | 20.544us | 5 | 5 | 100.00 |
| V1 | csr_rw | sram_ctrl_csr_rw | 0.730s | 31.316us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 2.250s | 455.993us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0.750s | 22.947us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 2.030s | 46.117us | 15 | 20 | 75.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 0.730s | 31.316us | 20 | 20 | 100.00 |
| sram_ctrl_csr_aliasing | 0.750s | 22.947us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | sram_ctrl_mem_walk | 12.750s | 8.877ms | 50 | 50 | 100.00 |
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 6.110s | 695.623us | 50 | 50 | 100.00 |
| V1 | TOTAL | 200 | 205 | 97.56 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 28.175m | 35.121ms | 50 | 50 | 100.00 |
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 7.113m | 17.996ms | 50 | 50 | 100.00 |
| V2 | bijection | sram_ctrl_bijection | 1.645m | 75.817ms | 50 | 50 | 100.00 |
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 33.520m | 18.934ms | 50 | 50 | 100.00 |
| V2 | lc_escalation | sram_ctrl_lc_escalation | 10.280s | 1.796ms | 50 | 50 | 100.00 |
| V2 | executable | sram_ctrl_executable | 31.096m | 7.697ms | 50 | 50 | 100.00 |
| V2 | partial_access | sram_ctrl_partial_access | 2.760m | 225.673us | 50 | 50 | 100.00 |
| sram_ctrl_partial_access_b2b | 9.432m | 59.381ms | 50 | 50 | 100.00 | ||
| V2 | max_throughput | sram_ctrl_max_throughput | 2.382m | 272.700us | 50 | 50 | 100.00 |
| sram_ctrl_throughput_w_partial_write | 2.643m | 157.648us | 50 | 50 | 100.00 | ||
| V2 | regwen | sram_ctrl_regwen | 31.512m | 16.219ms | 50 | 50 | 100.00 |
| V2 | ram_cfg | sram_ctrl_ram_cfg | 0.870s | 78.550us | 50 | 50 | 100.00 |
| V2 | stress_all | sram_ctrl_stress_all | 1.540h | 15.803ms | 44 | 50 | 88.00 |
| V2 | alert_test | sram_ctrl_alert_test | 0.750s | 16.521us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 4.840s | 149.052us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 4.840s | 149.052us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0.730s | 20.544us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.730s | 31.316us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.750s | 22.947us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.860s | 60.058us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0.730s | 20.544us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.730s | 31.316us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.750s | 22.947us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.860s | 60.058us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 734 | 740 | 99.19 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 3.960s | 2.855ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | sram_ctrl_sec_cm | 3.130s | 234.584us | 5 | 5 | 100.00 |
| sram_ctrl_tl_intg_err | 2.460s | 202.559us | 20 | 20 | 100.00 | ||
| V2S | prim_count_check | sram_ctrl_sec_cm | 3.130s | 234.584us | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 2.460s | 202.559us | 20 | 20 | 100.00 |
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 31.512m | 16.219ms | 50 | 50 | 100.00 |
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 0.730s | 31.316us | 20 | 20 | 100.00 |
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 31.096m | 7.697ms | 50 | 50 | 100.00 |
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 31.096m | 7.697ms | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 31.096m | 7.697ms | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 10.280s | 1.796ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 3.960s | 2.855ms | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_readback | sram_ctrl_smoke | 2.279m | 641.433us | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 2.279m | 641.433us | 50 | 50 | 100.00 |
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 2.279m | 641.433us | 50 | 50 | 100.00 |
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 31.096m | 7.697ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 3.130s | 234.584us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 10.280s | 1.796ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 3.130s | 234.584us | 5 | 5 | 100.00 |
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 3.130s | 234.584us | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 2.279m | 641.433us | 50 | 50 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 3.130s | 234.584us | 5 | 5 | 100.00 |
| V2S | TOTAL | 45 | 45 | 100.00 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 13.913m | 5.616ms | 39 | 50 | 78.00 |
| V3 | TOTAL | 39 | 50 | 78.00 | |||
| TOTAL | 1018 | 1040 | 97.88 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 16 | 16 | 15 | 93.75 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.93 | 99.16 | 94.27 | 99.72 | 100.00 | 95.95 | 99.12 | 97.26 |
UVM_ERROR (cip_base_vseq.sv:836) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:
7.sram_ctrl_stress_all_with_rand_reset.32421493047884200889791108681496270230965940653204693060349640401226620450382
Line 491, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7779439218 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7779439218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.sram_ctrl_stress_all_with_rand_reset.105122127467421647147427950791432528339828747835077865042359877045387069328735
Line 432, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 13579313566 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 13579313566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 6 failures:
6.sram_ctrl_stress_all.66852401848169833271428809378065013870112066163347502591709338179449016191887
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all/latest/run.log
Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
UVM_ERROR @ 88542165 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
UVM_INFO @ 88542165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.sram_ctrl_stress_all.62888515033866234519028370916779186649323575082035368319885261925526232906155
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all/latest/run.log
Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
UVM_ERROR @ 15585086 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
UVM_INFO @ 15585086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: * has 1 failures:
0.sram_ctrl_csr_mem_rw_with_rand_reset.98828592654290887584555656691416978349536502788110138237621877018347433642025
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 87736606 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: 0x0
UVM_INFO @ 87736606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:
1.sram_ctrl_csr_mem_rw_with_rand_reset.44037993946212924740259104935519295283892814992506775727866686615551384123909
Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 112872798 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (4 [0x4] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
UVM_INFO @ 112872798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
8.sram_ctrl_csr_mem_rw_with_rand_reset.25287185072307651480445829033560719171899311548423064341131934674220370143881
Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 67864637 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
UVM_INFO @ 67864637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
9.sram_ctrl_csr_mem_rw_with_rand_reset.85746505592626583076548130528194689716725485183121521824101663763813693982060
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 46117035 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (6 [0x6] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
UVM_INFO @ 46117035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: * has 1 failures:
18.sram_ctrl_csr_mem_rw_with_rand_reset.68675772712975859652525691939854929816282334928612769549218789012790595458798
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 47522469 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
UVM_INFO @ 47522469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:755) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
41.sram_ctrl_stress_all_with_rand_reset.53953180102337509978958851586371984075636646024032990061427509819423080840922
Line 272, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8878456 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 8878456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---