SRAM_CTRL/RET Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: fdfa12db04

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.447m 10.211ms 49 50 98.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.720s 15.135us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.730s 25.844us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.090s 238.896us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.760s 112.685us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.350s 317.177us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.730s 25.844us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 112.685us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 11.760s 574.733us 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 6.040s 168.491us 50 50 100.00
V1 TOTAL 204 205 99.51
V2 multiple_keys sram_ctrl_multiple_keys 28.503m 14.535ms 48 50 96.00
V2 stress_pipeline sram_ctrl_stress_pipeline 6.490m 3.983ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.442m 18.378ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 32.538m 16.321ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 9.180s 1.438ms 50 50 100.00
V2 executable sram_ctrl_executable 32.296m 4.517ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.496m 1.570ms 50 50 100.00
sram_ctrl_partial_access_b2b 9.503m 24.595ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.369m 135.528us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.501m 927.693us 50 50 100.00
V2 regwen sram_ctrl_regwen 30.515m 19.232ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 0.850s 27.431us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 1.722h 48.403ms 47 50 94.00
V2 alert_test sram_ctrl_alert_test 0.720s 19.137us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.010s 496.257us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.010s 496.257us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.720s 15.135us 5 5 100.00
sram_ctrl_csr_rw 0.730s 25.844us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 112.685us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.940s 363.697us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.720s 15.135us 5 5 100.00
sram_ctrl_csr_rw 0.730s 25.844us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 112.685us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.940s 363.697us 20 20 100.00
V2 TOTAL 735 740 99.32
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 3.480s 1.745ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.230s 688.600us 5 5 100.00
sram_ctrl_tl_intg_err 2.500s 645.732us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.230s 688.600us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.500s 645.732us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 30.515m 19.232ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.730s 25.844us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 32.296m 4.517ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 32.296m 4.517ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 32.296m 4.517ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 9.180s 1.438ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 3.480s 1.745ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.447m 10.211ms 49 50 98.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.447m 10.211ms 49 50 98.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.447m 10.211ms 49 50 98.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 32.296m 4.517ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.230s 688.600us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 9.180s 1.438ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.230s 688.600us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.230s 688.600us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.447m 10.211ms 49 50 98.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.230s 688.600us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 12.637m 1.400ms 47 50 94.00
V3 TOTAL 47 50 94.00
TOTAL 1031 1040 99.13

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 16 14 87.50
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44

Failure Buckets

Past Results