SRAM_CTRL/RET Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: `e9b7e615a7`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.679m	282.607us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.690s	22.722us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.750s	16.123us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.050s	463.072us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.790s	22.020us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.500s	43.546us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.750s	16.123us	20	20	100.00
		sram_ctrl_csr_aliasing	0.790s	22.020us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	12.700s	3.445ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.200s	1.337ms	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	30.469m	121.885ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.268m	19.343ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.543m	37.601ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	37.633m	3.638ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	12.540s	11.241ms	50	50	100.00
V2	executable	sram_ctrl_executable	33.109m	20.089ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.886m	774.473us	50	50	100.00
		sram_ctrl_partial_access_b2b	9.489m	91.200ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.640m	284.485us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.493m	153.739us	50	50	100.00
V2	regwen	sram_ctrl_regwen	31.873m	25.845ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.820s	129.748us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.812h	286.670ms	48	50	96.00
V2	alert_test	sram_ctrl_alert_test	0.710s	13.014us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.830s	465.960us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.830s	465.960us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.690s	22.722us	5	5	100.00
		sram_ctrl_csr_rw	0.750s	16.123us	20	20	100.00
		sram_ctrl_csr_aliasing	0.790s	22.020us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.880s	17.698us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.690s	22.722us	5	5	100.00
		sram_ctrl_csr_rw	0.750s	16.123us	20	20	100.00
		sram_ctrl_csr_aliasing	0.790s	22.020us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.880s	17.698us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.720s	651.843us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.260s	261.780us	5	5	100.00
		sram_ctrl_tl_intg_err	2.480s	686.471us	19	20	95.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.260s	261.780us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.480s	686.471us	19	20	95.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	31.873m	25.845ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.750s	16.123us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	33.109m	20.089ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	33.109m	20.089ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	33.109m	20.089ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	12.540s	11.241ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.720s	651.843us	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.679m	282.607us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.679m	282.607us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.679m	282.607us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	33.109m	20.089ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.260s	261.780us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	12.540s	11.241ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.260s	261.780us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.260s	261.780us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.679m	282.607us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.260s	261.780us	5	5	100.00
V2S		TOTAL			44	45	97.78
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	11.893m	6.713ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			1025	1040	98.56

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	13	81.25
V2S	3	3	2	66.67
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 9 failures.
  - 5.sram_ctrl_stress_all_with_rand_reset.19952668150239408948341771799547994418671376122598471489758978725715994693153
    Line 340, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2555349366 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2555349366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.sram_ctrl_stress_all_with_rand_reset.42513082150049539338581442245801851154418431791051345547391262274110708730612
    Line 311, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3090859896 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3090859896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 2 failures:

Test sram_ctrl_stress_all has 2 failures.

5.sram_ctrl_stress_all.36746997869802705155490495816487411691919219629511784863694178179808604365891
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  28074870 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  28074870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.sram_ctrl_stress_all.74224905869646798174851464815430470972939342150393270423447557576544585031602
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 103200797 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 103200797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
- Test sram_ctrl_tl_intg_err has 1 failures.
  - 0.sram_ctrl_tl_intg_err.32415415740812651597880508819475929632485191374008209485565048018698135507886
    Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_tl_intg_err/latest/run.log
```
  UVM_ERROR @  35663706 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @  35663706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 0.sram_ctrl_csr_mem_rw_with_rand_reset.30302188692805091026722382061555350192513772498341229226135065819599824698995
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 111933927 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @ 111933927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:264) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 8.sram_ctrl_multiple_keys.21322610935891557704919792623509538087983666380873123482243073495132097289734
    Line 282, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 40763218807 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xf14faaf5
  UVM_INFO @ 40763218807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:264) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 19.sram_ctrl_executable.61515741250784688028886583222480910816853136614681983208079026378738351957413
    Line 332, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 186124013242 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xf19e554e
  UVM_INFO @ 186124013242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```