SRAM_CTRL/RET Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: 625f353e9c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.812m 2.563ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.700s 57.221us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.770s 25.008us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.030s 636.227us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.770s 196.701us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.700s 130.128us 18 20 90.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.770s 25.008us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 196.701us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 13.320s 2.636ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 6.400s 882.691us 50 50 100.00
V1 TOTAL 203 205 99.02
V2 multiple_keys sram_ctrl_multiple_keys 28.930m 22.434ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 6.930m 4.199ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.466m 11.072ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 30.264m 10.963ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 10.800s 8.015ms 50 50 100.00
V2 executable sram_ctrl_executable 31.340m 75.248ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 1.853m 1.122ms 50 50 100.00
sram_ctrl_partial_access_b2b 10.176m 23.848ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.752m 136.389us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.803m 149.104us 50 50 100.00
V2 regwen sram_ctrl_regwen 34.032m 21.089ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 0.850s 30.424us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 1.907h 33.461ms 46 50 92.00
V2 alert_test sram_ctrl_alert_test 0.710s 49.346us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.650s 2.383ms 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.650s 2.383ms 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.700s 57.221us 5 5 100.00
sram_ctrl_csr_rw 0.770s 25.008us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 196.701us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.830s 54.211us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.700s 57.221us 5 5 100.00
sram_ctrl_csr_rw 0.770s 25.008us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 196.701us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.830s 54.211us 20 20 100.00
V2 TOTAL 736 740 99.46
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 4.110s 4.221ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.570s 411.263us 5 5 100.00
sram_ctrl_tl_intg_err 2.630s 327.466us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.570s 411.263us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.630s 327.466us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 34.032m 21.089ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.770s 25.008us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 31.340m 75.248ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 31.340m 75.248ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 31.340m 75.248ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 10.800s 8.015ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 4.110s 4.221ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.812m 2.563ms 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.812m 2.563ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.812m 2.563ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 31.340m 75.248ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.570s 411.263us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 10.800s 8.015ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.570s 411.263us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.570s 411.263us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.812m 2.563ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.570s 411.263us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 11.565m 11.457ms 42 50 84.00
V3 TOTAL 42 50 84.00
TOTAL 1026 1040 98.65

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 16 15 93.75
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44

Failure Buckets

Past Results