SRAM_CTRL/RET Simulation Results

Friday August 02 2024 23:02:48 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75989420798843487383163268541581889763599806834398027919895759109584083292465

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.797m 2.880ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.690s 20.295us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.690s 19.662us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.320s 184.489us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.760s 61.015us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 33.300s 10.001ms 17 20 85.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.690s 19.662us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 61.015us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 12.170s 2.635ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 6.330s 1.600ms 50 50 100.00
V1 TOTAL 202 205 98.54
V2 multiple_keys sram_ctrl_multiple_keys 27.484m 44.613ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 6.666m 4.226ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.480m 19.263ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 31.095m 3.132ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 10.100s 3.291ms 50 50 100.00
V2 executable sram_ctrl_executable 28.058m 52.241ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.602m 687.105us 50 50 100.00
sram_ctrl_partial_access_b2b 8.968m 41.650ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.696m 146.768us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.825m 376.060us 50 50 100.00
V2 regwen sram_ctrl_regwen 34.347m 23.996ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 0.870s 31.262us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 1.839h 261.312ms 47 50 94.00
V2 alert_test sram_ctrl_alert_test 0.690s 32.300us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.580s 521.004us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.580s 521.004us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.690s 20.295us 5 5 100.00
sram_ctrl_csr_rw 0.690s 19.662us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 61.015us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.850s 77.205us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.690s 20.295us 5 5 100.00
sram_ctrl_csr_rw 0.690s 19.662us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 61.015us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.850s 77.205us 20 20 100.00
V2 TOTAL 737 740 99.59
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 3.510s 1.541ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.560s 517.084us 5 5 100.00
sram_ctrl_tl_intg_err 2.490s 2.904ms 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.560s 517.084us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.490s 2.904ms 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 34.347m 23.996ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.690s 19.662us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 28.058m 52.241ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 28.058m 52.241ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 28.058m 52.241ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 10.100s 3.291ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 3.510s 1.541ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.797m 2.880ms 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.797m 2.880ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.797m 2.880ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 28.058m 52.241ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.560s 517.084us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 10.100s 3.291ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.560s 517.084us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.560s 517.084us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.797m 2.880ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.560s 517.084us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 16.349m 4.768ms 38 50 76.00
V3 TOTAL 38 50 76.00
TOTAL 1022 1040 98.27

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 16 15 93.75
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44

Failure Buckets

Past Results