SRAM_CTRL/RET Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.475m	599.857us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.700s	17.472us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.720s	12.878us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.160s	180.204us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.780s	101.798us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.180s	70.315us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.720s	12.878us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	101.798us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	12.060s	2.369ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.410s	681.791us	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	32.422m	76.838ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.629m	15.273ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.413m	32.899ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	28.617m	9.366ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	10.820s	17.344ms	50	50	100.00
V2	executable	sram_ctrl_executable	42.466m	18.060ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.718m	2.567ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.591m	96.695ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.694m	280.007us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.845m	622.122us	50	50	100.00
V2	regwen	sram_ctrl_regwen	33.012m	12.908ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.880s	56.214us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.089h	176.550ms	45	50	90.00
V2	alert_test	sram_ctrl_alert_test	0.700s	18.961us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.640s	496.846us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.640s	496.846us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.700s	17.472us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	12.878us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	101.798us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	86.157us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.700s	17.472us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	12.878us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	101.798us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	86.157us	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.720s	6.155ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.520s	562.196us	5	5	100.00
		sram_ctrl_tl_intg_err	2.640s	266.819us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.520s	562.196us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.640s	266.819us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	33.012m	12.908ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.720s	12.878us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	42.466m	18.060ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	42.466m	18.060ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	42.466m	18.060ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	10.820s	17.344ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.720s	6.155ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.475m	599.857us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.475m	599.857us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.475m	599.857us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	42.466m	18.060ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.520s	562.196us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	10.820s	17.344ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.520s	562.196us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.520s	562.196us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.475m	599.857us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.520s	562.196us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	12.136m	1.761ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			1027	1040	98.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 6 failures.
  - 2.sram_ctrl_stress_all_with_rand_reset.41537519514968572469497886032287052126247971951657223603948379906700232672643
    Line 475, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2328774978 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2328774978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.sram_ctrl_stress_all_with_rand_reset.10637227753874898519546340095914706190690525240038039399960129699404705900303
    Line 328, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1521488467 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1521488467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 3 failures:

Test sram_ctrl_stress_all has 3 failures.

2.sram_ctrl_stress_all.76438412308716111582166041764222348138592959864093016514921565130250885812736
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  17246919 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  17246919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.sram_ctrl_stress_all.57726766343310426001998088710194437846553525531012168003090908511817751403813
Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 234470111 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 234470111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 10.sram_ctrl_csr_mem_rw_with_rand_reset.9788411657080180905247507242903098495594994355260129573089940856083907154384
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 109949096 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
  UVM_INFO @ 109949096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:264) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 22.sram_ctrl_executable.105883666126163640611999518763959617328195655216106710455314567499299766618698
    Line 286, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 50962591900 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x647b6a5b
  UVM_INFO @ 50962591900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:264) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 47.sram_ctrl_stress_all.75370862628124005669217036372077179064015598590954902111514177718847731453895
    Line 327, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 200628052493 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xad9927a9
  UVM_INFO @ 200628052493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(rdata_o))' has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 48.sram_ctrl_stress_all.42372074724246091611705306999289547213768372956538535336302882527188413307564
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_all/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @  66748031 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  66748031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```