SRAM_CTRL/RET Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: f1535c5540

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.149m 667.261us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.690s 16.958us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.730s 20.897us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.230s 714.111us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.740s 17.199us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.280s 132.514us 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.730s 20.897us 20 20 100.00
sram_ctrl_csr_aliasing 0.740s 17.199us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 11.990s 2.615ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 6.060s 357.917us 50 50 100.00
V1 TOTAL 204 205 99.51
V2 multiple_keys sram_ctrl_multiple_keys 28.404m 8.634ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.155m 4.339ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.571m 30.023ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 31.912m 22.907ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 9.830s 4.951ms 50 50 100.00
V2 executable sram_ctrl_executable 32.300m 17.968ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.558m 883.027us 50 50 100.00
sram_ctrl_partial_access_b2b 10.093m 50.762ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.566m 139.853us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.611m 386.618us 50 50 100.00
V2 regwen sram_ctrl_regwen 37.182m 86.839ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 0.910s 66.592us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.007h 921.810ms 46 50 92.00
V2 alert_test sram_ctrl_alert_test 0.720s 30.619us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.080s 149.930us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.080s 149.930us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.690s 16.958us 5 5 100.00
sram_ctrl_csr_rw 0.730s 20.897us 20 20 100.00
sram_ctrl_csr_aliasing 0.740s 17.199us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.790s 44.173us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.690s 16.958us 5 5 100.00
sram_ctrl_csr_rw 0.730s 20.897us 20 20 100.00
sram_ctrl_csr_aliasing 0.740s 17.199us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.790s 44.173us 20 20 100.00
V2 TOTAL 736 740 99.46
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 3.550s 862.959us 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.680s 1.815ms 5 5 100.00
sram_ctrl_tl_intg_err 3.510s 677.905us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.680s 1.815ms 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 3.510s 677.905us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 37.182m 86.839ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.730s 20.897us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 32.300m 17.968ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 32.300m 17.968ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 32.300m 17.968ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 9.830s 4.951ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 3.550s 862.959us 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.149m 667.261us 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.149m 667.261us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.149m 667.261us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 32.300m 17.968ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.680s 1.815ms 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 9.830s 4.951ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.680s 1.815ms 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.680s 1.815ms 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.149m 667.261us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.680s 1.815ms 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 13.254m 10.246ms 39 50 78.00
V3 TOTAL 39 50 78.00
TOTAL 1024 1040 98.46

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 16 15 93.75
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44

Failure Buckets

Past Results