SRAM_CTRL/RET Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: `e45ccd274a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.598m	3.096ms	49	50	98.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.690s	14.239us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.770s	16.674us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.220s	174.656us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.720s	69.267us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.510s	46.599us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.770s	16.674us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	69.267us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	12.110s	3.156ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.330s	3.269ms	50	50	100.00
V1		TOTAL			202	205	98.54
V2	multiple_keys	sram_ctrl_multiple_keys	36.238m	47.764ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.966m	4.369ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.417m	5.676ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	28.058m	19.690ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	11.510s	1.916ms	50	50	100.00
V2	executable	sram_ctrl_executable	28.540m	94.610ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.522m	768.347us	50	50	100.00
		sram_ctrl_partial_access_b2b	9.574m	322.646ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.389m	325.703us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.337m	1.231ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	32.839m	314.478ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.860s	33.487us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.626h	64.978ms	46	50	92.00
V2	alert_test	sram_ctrl_alert_test	0.720s	26.905us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.740s	136.068us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.740s	136.068us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.690s	14.239us	5	5	100.00
		sram_ctrl_csr_rw	0.770s	16.674us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	69.267us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	39.961us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.690s	14.239us	5	5	100.00
		sram_ctrl_csr_rw	0.770s	16.674us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	69.267us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	39.961us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.740s	1.697ms	19	20	95.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.960s	1.867ms	5	5	100.00
		sram_ctrl_tl_intg_err	2.480s	332.667us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.960s	1.867ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.480s	332.667us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	32.839m	314.478ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.770s	16.674us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	28.540m	94.610ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	28.540m	94.610ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	28.540m	94.610ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	11.510s	1.916ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.740s	1.697ms	19	20	95.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.598m	3.096ms	49	50	98.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.598m	3.096ms	49	50	98.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.598m	3.096ms	49	50	98.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	28.540m	94.610ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.960s	1.867ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	11.510s	1.916ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.960s	1.867ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.960s	1.867ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.598m	3.096ms	49	50	98.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.960s	1.867ms	5	5	100.00
V2S		TOTAL			44	45	97.78
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	17.173m	2.404ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			1026	1040	98.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	6	75.00
V2	16	16	15	93.75
V2S	3	3	2	66.67
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 6 failures.
  - 10.sram_ctrl_stress_all_with_rand_reset.79460239575052338771657452777883377027589854313371116145979302823020891939636
    Line 308, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1377778103 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1377778103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.sram_ctrl_stress_all_with_rand_reset.40428877066054089952651834972696413592441343260970093396887944183755062499276
    Line 348, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5182057297 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5182057297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 3 failures:

Test sram_ctrl_stress_all has 3 failures.

1.sram_ctrl_stress_all.15139282355065385938551223087051002357849872120899734644523941921560709505731
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  54538891 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  54538891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.sram_ctrl_stress_all.29117184126248430706342531530670145000998707851375879513730971860758973360326
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 300881567 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 300881567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 2 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 6.sram_ctrl_csr_mem_rw_with_rand_reset.111370841782745271278470494347585533077686547908753100252049863460899014727368
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  23735768 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  23735768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.sram_ctrl_csr_mem_rw_with_rand_reset.114923479766426984943972463645121412435322042528388854151893104555571481267790
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  42244574 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (13 [0xd] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  42244574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
- Test sram_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 11.sram_ctrl_passthru_mem_tl_intg_err.66782944075155167320522312256457097357623924426819095223373866905216345023906
    Line 374, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_ERROR @ 1135731389 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 1135731389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_smoke has 1 failures.
  - 39.sram_ctrl_smoke.24415648557694009136829792208576384494215691109511506364748723647526678665323
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/39.sram_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 10494063155 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x67722b6b
  UVM_INFO @ 10494063155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 41.sram_ctrl_stress_all.43545749718887275891779755115533786199641981088918681368717627945153384160276
    Line 284, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 49066713790 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x88ca4749
  UVM_INFO @ 49066713790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```