SRAM_CTRL/RET Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: `34b8fc33e3`

Branch: earlgrey_1_0_0_2024_08_20_RC0

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.601m	1.997ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.760s	22.819us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.920s	24.373us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.150s	226.429us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.710s	14.418us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.940s	68.842us	16	20	80.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.920s	24.373us	20	20	100.00
		sram_ctrl_csr_aliasing	0.710s	14.418us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	17.300s	2.609ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	8.800s	528.791us	50	50	100.00
V1		TOTAL			201	205	98.05
V2	multiple_keys	sram_ctrl_multiple_keys	27.770m	28.799ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.998m	53.938ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.960m	33.661ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	23.903m	5.105ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	18.650s	1.552ms	50	50	100.00
V2	executable	sram_ctrl_executable	25.628m	32.970ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	1.970m	977.261us	49	50	98.00
		sram_ctrl_partial_access_b2b	10.507m	19.236ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.824m	401.889us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.928m	616.141us	50	50	100.00
V2	regwen	sram_ctrl_regwen	26.814m	17.276ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.280s	37.310us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.230h	121.539ms	48	50	96.00
V2	alert_test	sram_ctrl_alert_test	1.050s	14.755us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.580s	1.909ms	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.580s	1.909ms	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.760s	22.819us	5	5	100.00
		sram_ctrl_csr_rw	0.920s	24.373us	20	20	100.00
		sram_ctrl_csr_aliasing	0.710s	14.418us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.990s	33.206us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.760s	22.819us	5	5	100.00
		sram_ctrl_csr_rw	0.920s	24.373us	20	20	100.00
		sram_ctrl_csr_aliasing	0.710s	14.418us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.990s	33.206us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.570s	1.655ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	5.320s	370.154us	5	5	100.00
		sram_ctrl_tl_intg_err	2.910s	1.284ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	5.320s	370.154us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.910s	1.284ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	26.814m	17.276ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.920s	24.373us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	25.628m	32.970ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	25.628m	32.970ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	25.628m	32.970ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	18.650s	1.552ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.570s	1.655ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	1.601m	1.997ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.601m	1.997ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.601m	1.997ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	25.628m	32.970ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	5.320s	370.154us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	18.650s	1.552ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	5.320s	370.154us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	5.320s	370.154us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.601m	1.997ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	5.320s	370.154us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	15.049m	1.274ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			1025	1040	98.56

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	12	75.00
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 5 failures.
  - 14.sram_ctrl_stress_all_with_rand_reset.57335975206832577063437358615248043909666384982345984701099812522380486478448
    Line 263, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2316217681 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2316217681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.sram_ctrl_stress_all_with_rand_reset.64355230384612236579585763648513030580654477048510278262551050967371995769018
    Line 136, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 739741783 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 739741783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 24.sram_ctrl_stress_all_with_rand_reset.12005398106390236038572829911330389559141093430007624857768322609336959910122
    Line 104, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11537050817 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x1465d822
  UVM_INFO @ 11537050817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sram_ctrl_executable has 1 failures.
  - 44.sram_ctrl_executable.58059943906664628172398519767471847252407422977772198895917119499295260214107
    Line 111, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_ret-sim-vcs/44.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 66811099874 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x281c8c59
  UVM_INFO @ 66811099874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sram_ctrl_stress_all has 1 failures.
  - 48.sram_ctrl_stress_all.107056964123626707332133291508847238409977423717065905840681145379173895392242
    Line 93, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 17291857021 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xf0aa4cd2
  UVM_INFO @ 17291857021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 14.sram_ctrl_multiple_keys.82440539770580971301302554909902221578129431196150103773295740095595537187349
    Line 87, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_ret-sim-vcs/14.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 10491944426 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xc48aca35
  UVM_INFO @ 10491944426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sram_ctrl_stress_all has 1 failures.
  - 23.sram_ctrl_stress_all.59953749138064534871671567300229339549346044651286693341562877867623823674205
    Line 114, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 179100199904 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xf9d551e4
  UVM_INFO @ 179100199904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 2.sram_ctrl_csr_mem_rw_with_rand_reset.84074632221674289119383293037905662377860447185223578337830980478534078704012
    Line 87, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 107199320 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (12 [0xc] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @ 107199320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 4.sram_ctrl_csr_mem_rw_with_rand_reset.74866118393616620995644226773333496111181616191496299637900889734306261100836
    Line 93, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 121338178 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: 0x0
  UVM_INFO @ 121338178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_seed_valid reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 7.sram_ctrl_csr_mem_rw_with_rand_reset.780582341941663354263679579154610641228186525148855024258171731484193807838
    Line 93, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 146746248 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_seed_valid reset value: 0x0
  UVM_INFO @ 146746248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 17.sram_ctrl_csr_mem_rw_with_rand_reset.12276881854047282248993085480950553161974672074995990650128972743622240421305
    Line 93, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 161778660 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @ 161778660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_partial_access has 1 failures.
  - 19.sram_ctrl_partial_access.98452232396378189555074331384169483406206808193038521773594305220873550817296
    Line 87, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_ret-sim-vcs/19.sram_ctrl_partial_access/latest/run.log
```
  UVM_FATAL @ 10353573787 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xa713e46d
  UVM_INFO @ 10353573787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/RET Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: 34b8fc33e3

Branch: earlgrey_1_0_0_2024_08_20_RC0

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `34b8fc33e3`