SRAM_CTRL/RET Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: 0825c81be0

Branch: os_regression_2024_08_22

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.265m	2.632ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.630s	44.132us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.630s	13.098us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.010s	180.502us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.710s	292.139us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.540s	153.309us	17	20	85.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.630s	13.098us	20	20	100.00
		sram_ctrl_csr_aliasing	0.710s	292.139us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	11.150s	2.608ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.600s	351.269us	50	50	100.00
V1		TOTAL			202	205	98.54
V2	multiple_keys	sram_ctrl_multiple_keys	17.429m	97.269ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.132m	4.239ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.386m	54.047ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	17.861m	93.522ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	10.180s	1.161ms	50	50	100.00
V2	executable	sram_ctrl_executable	18.248m	38.830ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.207m	2.691ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.503m	111.866ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.171m	758.013us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.220m	980.735us	50	50	100.00
V2	regwen	sram_ctrl_regwen	24.061m	112.832ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.770s	280.591us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	59.188m	326.879ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.650s	17.856us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.200s	233.970us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.200s	233.970us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.630s	44.132us	5	5	100.00
		sram_ctrl_csr_rw	0.630s	13.098us	20	20	100.00
		sram_ctrl_csr_aliasing	0.710s	292.139us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.750s	181.887us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.630s	44.132us	5	5	100.00
		sram_ctrl_csr_rw	0.630s	13.098us	20	20	100.00
		sram_ctrl_csr_aliasing	0.710s	292.139us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.750s	181.887us	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	8.090s	2.093ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.950s	645.853us	5	5	100.00
		sram_ctrl_tl_intg_err	2.350s	355.337us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.950s	645.853us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.350s	355.337us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	24.061m	112.832ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.630s	13.098us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	18.248m	38.830ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	18.248m	38.830ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	18.248m	38.830ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	10.180s	1.161ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	8.090s	2.093ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	1.265m	2.632ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.265m	2.632ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.265m	2.632ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	18.248m	38.830ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.950s	645.853us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	10.180s	1.161ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.950s	645.853us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.950s	645.853us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.265m	2.632ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.950s	645.853us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	9.430m	8.382ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			1028	1040	98.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	16	100.00
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 9 failures.

    • 9.sram_ctrl_stress_all_with_rand_reset.45901934637810285521345138460007567432006186534865862527877042113573395249436
      Line 94, in log /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5278473392 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5278473392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 10.sram_ctrl_stress_all_with_rand_reset.18516523684110980336487994876340901303852685721898250544918890704549464849293
      Line 276, in log /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3400121030 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3400121030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 7 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 2 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 2 failures.

    • 2.sram_ctrl_csr_mem_rw_with_rand_reset.11538550895243465078801882671503321532120453938734636988425956407975892058327
      Line 87, in log /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 150593644 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
        UVM_INFO @ 150593644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 17.sram_ctrl_csr_mem_rw_with_rand_reset.19631354493596670266984450844099934549341985114392000249733262411005671991733
      Line 87, in log /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  94759507 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
        UVM_INFO @  94759507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 15.sram_ctrl_csr_mem_rw_with_rand_reset.77325493643180469705474637065180107896990114916374235877573293311911348175225
      Line 87, in log /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  99062077 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (5 [0x5] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
        UVM_INFO @  99062077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.22_14.24.59
• 2024.08.20_08.07.46
• 2024.08.19_08.21.09
• 2024.08.18_08.47.38
• 2024.08.17_07.28.33
• 2024.08.16_08.46.36
• 2024.08.15_05.43.58