SRAM_CTRL/RET Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: `e733a8ef8a`

Branch: os_regression_2024_08_24

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.449m	2.588ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.100s	106.756us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.040s	15.418us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.730s	538.839us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.060s	14.867us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.230s	51.446us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.040s	15.418us	20	20	100.00
		sram_ctrl_csr_aliasing	1.060s	14.867us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	17.720s	2.719ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	10.820s	3.823ms	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	35.105m	33.295ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	10.735m	4.285ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.919m	4.926ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	39.531m	22.637ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	17.110s	944.335us	50	50	100.00
V2	executable	sram_ctrl_executable	32.885m	23.139ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.381m	448.997us	50	50	100.00
		sram_ctrl_partial_access_b2b	16.076m	24.514ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.064m	144.211us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.994m	582.788us	50	50	100.00
V2	regwen	sram_ctrl_regwen	28.382m	135.048ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.490s	84.933us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.889h	158.474ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.140s	14.376us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.240s	124.187us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.240s	124.187us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.100s	106.756us	5	5	100.00
		sram_ctrl_csr_rw	1.040s	15.418us	20	20	100.00
		sram_ctrl_csr_aliasing	1.060s	14.867us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.240s	58.553us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.100s	106.756us	5	5	100.00
		sram_ctrl_csr_rw	1.040s	15.418us	20	20	100.00
		sram_ctrl_csr_aliasing	1.060s	14.867us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.240s	58.553us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	6.500s	1.913ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	4.430s	440.894us	5	5	100.00
		sram_ctrl_tl_intg_err	4.360s	719.781us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	4.430s	440.894us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.360s	719.781us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	28.382m	135.048ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.040s	15.418us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	32.885m	23.139ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	32.885m	23.139ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	32.885m	23.139ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	17.110s	944.335us	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	6.500s	1.913ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.449m	2.588ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.449m	2.588ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.449m	2.588ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	32.885m	23.139ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	4.430s	440.894us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	17.110s	944.335us	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	4.430s	440.894us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	4.430s	440.894us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.449m	2.588ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	4.430s	440.894us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	21.216m	9.134ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			1030	1040	99.04

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 6 failures.
  - 6.sram_ctrl_stress_all_with_rand_reset.81858724045543407071803988366593431001095410699934601390590802569027317947406
    Line 92, in log /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 585886836 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 585886836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.sram_ctrl_stress_all_with_rand_reset.71154680402549097549310365186207835343204279698275416268736783940730962290764
    Line 278, in log /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2424501279 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2424501279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 3.sram_ctrl_csr_mem_rw_with_rand_reset.21487505420286813391158402024894486577598810759833243751029550465227719132801
    Line 93, in log /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 331895432 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (14 [0xe] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @ 331895432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_seed_valid reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 7.sram_ctrl_csr_mem_rw_with_rand_reset.21552604533407798522204234686192146196491427661195113925184926044030039049066
    Line 87, in log /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  91987061 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_seed_valid reset value: 0x0
  UVM_INFO @  91987061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 21.sram_ctrl_regwen.36407992106637866682611284499215868257376172659045338669845740873971926805023
    Line 101, in log /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/21.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 24876523170 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xf051751f
  UVM_INFO @ 24876523170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 30.sram_ctrl_multiple_keys.84943207037901347061124023332281696554209281461136932231000159551186357215720
    Line 93, in log /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/30.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 42504509656 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x28ab4d21
  UVM_INFO @ 42504509656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/RET Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: e733a8ef8a

Branch: os_regression_2024_08_24

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e733a8ef8a`