SRAM_CTRL/RET Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: `4674f625b3`

Branch: os_regression_2024_08_26

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.802m	655.882us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.180s	128.989us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.030s	54.710us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.870s	244.188us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.030s	20.316us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.760s	141.774us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.030s	54.710us	20	20	100.00
		sram_ctrl_csr_aliasing	1.030s	20.316us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	16.460s	565.995us	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	8.880s	196.762us	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	28.100m	37.685ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.753m	16.036ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.974m	13.885ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	23.680m	3.967ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	16.910s	2.810ms	50	50	100.00
V2	executable	sram_ctrl_executable	26.988m	63.096ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.803m	659.544us	50	50	100.00
		sram_ctrl_partial_access_b2b	12.081m	53.378ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.861m	153.196us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.008m	1.626ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	26.486m	20.120ms	48	50	96.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.440s	74.036us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.470h	296.834ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.060s	24.758us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	7.840s	713.857us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	7.840s	713.857us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.180s	128.989us	5	5	100.00
		sram_ctrl_csr_rw	1.030s	54.710us	20	20	100.00
		sram_ctrl_csr_aliasing	1.030s	20.316us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.170s	88.012us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.180s	128.989us	5	5	100.00
		sram_ctrl_csr_rw	1.030s	54.710us	20	20	100.00
		sram_ctrl_csr_aliasing	1.030s	20.316us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.170s	88.012us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	6.030s	2.769ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	5.410s	597.467us	5	5	100.00
		sram_ctrl_tl_intg_err	4.770s	538.446us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	5.410s	597.467us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.770s	538.446us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	26.486m	20.120ms	48	50	96.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.030s	54.710us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	26.988m	63.096ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	26.988m	63.096ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	26.988m	63.096ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	16.910s	2.810ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	6.030s	2.769ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	1.802m	655.882us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.802m	655.882us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.802m	655.882us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	26.988m	63.096ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	5.410s	597.467us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	16.910s	2.810ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	5.410s	597.467us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	5.410s	597.467us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.802m	655.882us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	5.410s	597.467us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	18.101m	12.789ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			1027	1040	98.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	15	93.75
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 9 failures.
  - 17.sram_ctrl_stress_all_with_rand_reset.40249506588712167005711089266916360721432511194376337518375776809381713125828
    Line 220, in log /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1289584000 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1289584000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.sram_ctrl_stress_all_with_rand_reset.25371075542853775980465851005589698251407574262040053197011660842130673840170
    Line 219, in log /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5726522277 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5726522277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_regwen has 2 failures.
  - 31.sram_ctrl_regwen.104495670293444712355240371656435364802407952113569236066160104049557792284129
    Line 88, in log /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/31.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 10295516049 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xd493d8e9
  UVM_INFO @ 10295516049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.sram_ctrl_regwen.53209546535341828940519690158001450209135604713872297564104995867315450828070
    Line 105, in log /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/46.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 60202814774 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xe16d34eb
  UVM_INFO @ 60202814774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 16.sram_ctrl_csr_mem_rw_with_rand_reset.114822119077145475769379059956392591240948324777673482658985907428356361485104
    Line 87, in log /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  90682033 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (3 [0x3] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  90682033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_seed_valid reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 17.sram_ctrl_csr_mem_rw_with_rand_reset.64726338214048445137720616218717815972967136373985976038805891455414856207992
    Line 93, in log /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 161355437 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_seed_valid reset value: 0x0
  UVM_INFO @ 161355437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/RET Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: 4674f625b3

Branch: os_regression_2024_08_26

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `4674f625b3`