SRAM_CTRL/RET Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: `a861deb3de`

Branch: os_regression_2024_08_28

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.966m	292.545us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.120s	47.836us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.040s	17.674us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.670s	1.269ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.980s	40.485us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.950s	92.074us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.040s	17.674us	20	20	100.00
		sram_ctrl_csr_aliasing	0.980s	40.485us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	17.300s	1.425ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	8.730s	197.720us	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	29.140m	24.845ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	8.293m	8.060ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.913m	6.938ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	25.092m	3.921ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	13.650s	956.432us	50	50	100.00
V2	executable	sram_ctrl_executable	32.358m	23.358ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.613m	2.925ms	50	50	100.00
		sram_ctrl_partial_access_b2b	12.971m	47.491ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.841m	140.110us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.773m	293.719us	50	50	100.00
V2	regwen	sram_ctrl_regwen	29.392m	28.170ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.640s	164.272us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.216h	55.603ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	1.110s	14.222us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.220s	264.238us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.220s	264.238us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.120s	47.836us	5	5	100.00
		sram_ctrl_csr_rw	1.040s	17.674us	20	20	100.00
		sram_ctrl_csr_aliasing	0.980s	40.485us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.250s	37.380us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.120s	47.836us	5	5	100.00
		sram_ctrl_csr_rw	1.040s	17.674us	20	20	100.00
		sram_ctrl_csr_aliasing	0.980s	40.485us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.250s	37.380us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	7.650s	6.645ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	6.090s	328.822us	5	5	100.00
		sram_ctrl_tl_intg_err	4.980s	2.540ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	6.090s	328.822us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.980s	2.540ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	29.392m	28.170ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.040s	17.674us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	32.358m	23.358ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	32.358m	23.358ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	32.358m	23.358ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	13.650s	956.432us	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	7.650s	6.645ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	1.966m	292.545us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.966m	292.545us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.966m	292.545us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	32.358m	23.358ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	6.090s	328.822us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	13.650s	956.432us	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	6.090s	328.822us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	6.090s	328.822us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.966m	292.545us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	6.090s	328.822us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	12.663m	2.291ms	38	50	76.00
V3		TOTAL			38	50	76.00
		TOTAL			1024	1040	98.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 10 failures.
  - 0.sram_ctrl_stress_all_with_rand_reset.100101537060163153634872154843428183816374575657541676321807501258592219940316
    Line 293, in log /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5174456937 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5174456937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.sram_ctrl_stress_all_with_rand_reset.53669049277731490884592614809368587009928614350923604713373930267911494928897
    Line 363, in log /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2084524060 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2084524060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 1.sram_ctrl_multiple_keys.34530505363502793019097079661143169697017007889330359665900118785844973540714
    Line 97, in log /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/1.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 37641206515 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x1ce246a9
  UVM_INFO @ 37641206515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sram_ctrl_stress_all has 1 failures.
  - 14.sram_ctrl_stress_all.115230775143821250977722072432288118757346719148084217504256047785263053255313
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 10250886106 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xea172b16
  UVM_INFO @ 10250886106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 30.sram_ctrl_stress_all_with_rand_reset.60383873818713448830795484032492413534062803941064208734268054829190837005109
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 14613720753 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x66268713
  UVM_INFO @ 14613720753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 4.sram_ctrl_csr_mem_rw_with_rand_reset.112256838740506740935682410296129380828533940919590681753069325504150500936117
    Line 87, in log /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 100197904 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: 0x0
  UVM_INFO @ 100197904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 19.sram_ctrl_csr_mem_rw_with_rand_reset.2745478157556354367391184495889107694631280347807046296240438908004853666934
    Line 87, in log /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  23284149 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  23284149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:771) [sram_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 35.sram_ctrl_stress_all_with_rand_reset.21839312181241922340247796819269766162717408757215520918935327023748332333589
    Line 437, in log /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1353166360 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1353166360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/RET Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: a861deb3de

Branch: os_regression_2024_08_28

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `a861deb3de`