SRAM_CTRL/RET Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: `ed1c41cd0f`

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.233m	2.639ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.130s	56.932us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.030s	23.518us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.560s	375.108us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.100s	35.506us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.790s	138.271us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.030s	23.518us	20	20	100.00
		sram_ctrl_csr_aliasing	1.100s	35.506us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	18.550s	1.359ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	9.140s	174.442us	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	30.345m	188.693ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	8.329m	4.152ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.837m	3.364ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	25.626m	17.170ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	18.680s	7.586ms	50	50	100.00
V2	executable	sram_ctrl_executable	33.842m	61.282ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.255m	645.336us	50	50	100.00
		sram_ctrl_partial_access_b2b	12.233m	201.201ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.070m	526.092us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.062m	583.570us	50	50	100.00
V2	regwen	sram_ctrl_regwen	28.473m	67.979ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.300s	31.278us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.258h	92.278ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	1.100s	26.096us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	7.550s	144.062us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	7.550s	144.062us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.130s	56.932us	5	5	100.00
		sram_ctrl_csr_rw	1.030s	23.518us	20	20	100.00
		sram_ctrl_csr_aliasing	1.100s	35.506us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.340s	156.877us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.130s	56.932us	5	5	100.00
		sram_ctrl_csr_rw	1.030s	23.518us	20	20	100.00
		sram_ctrl_csr_aliasing	1.100s	35.506us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.340s	156.877us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	6.280s	2.778ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	4.640s	262.681us	5	5	100.00
		sram_ctrl_tl_intg_err	4.190s	480.471us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	4.640s	262.681us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.190s	480.471us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	28.473m	67.979ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.030s	23.518us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	33.842m	61.282ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	33.842m	61.282ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	33.842m	61.282ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	18.680s	7.586ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	6.280s	2.778ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.233m	2.639ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.233m	2.639ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.233m	2.639ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	33.842m	61.282ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	4.640s	262.681us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	18.680s	7.586ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	4.640s	262.681us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	4.640s	262.681us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.233m	2.639ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	4.640s	262.681us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	15.446m	1.662ms	42	50	84.00
V3		TOTAL			42	50	84.00
		TOTAL			1027	1040	98.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	12	75.00
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.93	99.16	94.27	99.72	100.00	95.95	99.12	97.26

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 8 failures.
  - 1.sram_ctrl_stress_all_with_rand_reset.64385580837299946851184274390069665703197776612688325833953785387441395563129
    Line 131, in log /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2209241261 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2209241261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.sram_ctrl_stress_all_with_rand_reset.13938202870885679452422207432091731326319907231851482205467107815426312597475
    Line 174, in log /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2439769276 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2439769276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 7.sram_ctrl_stress_all.105053128018029665024343029136822168982902770752844683817834292074577417406507
    Line 93, in log /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 23271761592 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x201e31bc
  UVM_INFO @ 23271761592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sram_ctrl_executable has 1 failures.
  - 38.sram_ctrl_executable.54082033544990900303224305968789928044625509909698999930742392612340272627524
    Line 91, in log /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/38.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 45397941868 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xbeb149d
  UVM_INFO @ 45397941868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 3.sram_ctrl_csr_mem_rw_with_rand_reset.114134527652326535022106001832561480581185905209320725197723718299021384368099
    Line 87, in log /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  26090486 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (7 [0x7] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  26090486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 31.sram_ctrl_regwen.68046523559327317930272323983780008967792306501253797628454952817170819995666
    Line 104, in log /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/31.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 67204076907 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x2379011b
  UVM_INFO @ 67204076907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 36.sram_ctrl_multiple_keys.52251239818470502507979822351370347125983868712692198768792451812689984432126
    Line 107, in log /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/36.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 101177168438 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x94ccb573
  UVM_INFO @ 101177168438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/RET Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: ed1c41cd0f

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `ed1c41cd0f`