SRAM_CTRL/RET Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: `372a6306e0`

Branch: os_regression_2024_09_03

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.913m	5.774ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.060s	25.455us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.000s	36.247us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.460s	170.264us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.110s	18.820us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.490s	44.263us	17	20	85.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.000s	36.247us	20	20	100.00
		sram_ctrl_csr_aliasing	1.110s	18.820us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	18.010s	2.744ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	8.550s	676.152us	50	50	100.00
V1		TOTAL			202	205	98.54
V2	multiple_keys	sram_ctrl_multiple_keys	31.066m	3.783ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.136m	3.496ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	2.375m	99.465ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	21.456m	17.685ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	18.310s	3.225ms	50	50	100.00
V2	executable	sram_ctrl_executable	28.197m	123.526ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.891m	455.000us	50	50	100.00
		sram_ctrl_partial_access_b2b	12.926m	176.550ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.983m	144.939us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.777m	617.986us	50	50	100.00
V2	regwen	sram_ctrl_regwen	21.557m	16.003ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.310s	215.049us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.637h	347.386ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	1.060s	110.933us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	8.210s	1.212ms	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	8.210s	1.212ms	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.060s	25.455us	5	5	100.00
		sram_ctrl_csr_rw	1.000s	36.247us	20	20	100.00
		sram_ctrl_csr_aliasing	1.110s	18.820us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.240s	26.164us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.060s	25.455us	5	5	100.00
		sram_ctrl_csr_rw	1.000s	36.247us	20	20	100.00
		sram_ctrl_csr_aliasing	1.110s	18.820us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.240s	26.164us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	6.090s	530.284us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	6.280s	417.065us	5	5	100.00
		sram_ctrl_tl_intg_err	4.060s	208.116us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	6.280s	417.065us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.060s	208.116us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	21.557m	16.003ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.000s	36.247us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	28.197m	123.526ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	28.197m	123.526ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	28.197m	123.526ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	18.310s	3.225ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	6.090s	530.284us	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	1.913m	5.774ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.913m	5.774ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.913m	5.774ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	28.197m	123.526ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	6.280s	417.065us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	18.310s	3.225ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	6.280s	417.065us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	6.280s	417.065us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.913m	5.774ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	6.280s	417.065us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	11.730m	2.678ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			1029	1040	98.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 6 failures.
  - 7.sram_ctrl_stress_all_with_rand_reset.109094666304950113107433997245369236825128575055062755553829857030307358943864
    Line 306, in log /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1862253386 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1862253386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.sram_ctrl_stress_all_with_rand_reset.29408058712966936443328523018504587560519647835505018855920748007243644454456
    Line 92, in log /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4620528224 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4620528224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 2 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 3.sram_ctrl_csr_mem_rw_with_rand_reset.88438343558748831462912169439756069304285799536972336741985370195211288463292
    Line 87, in log /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  91738378 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (11 [0xb] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  91738378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.sram_ctrl_csr_mem_rw_with_rand_reset.92291995200830689632208499365076154378651599562720988407623951985999136665969
    Line 87, in log /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  51301128 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  51301128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 11.sram_ctrl_csr_mem_rw_with_rand_reset.62028358774242490747234018633100327759151969747798632339567978626785105799051
    Line 87, in log /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  23875050 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  23875050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 34.sram_ctrl_stress_all.43246220917375861459221082356649113270993300157889937700448532991738566125420
    Line 157, in log /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 183504520149 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x170b632
  UVM_INFO @ 183504520149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 38.sram_ctrl_regwen.21975553172673537151944730599654576225547172386994182034626489376322553072300
    Line 88, in log /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/38.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 10224136641 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x35410921
  UVM_INFO @ 10224136641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/RET Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: 372a6306e0

Branch: os_regression_2024_09_03

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `372a6306e0`