SRAM_CTRL/RET Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: `af2d1709f9`

Branch: os_regression_2024_09_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.072m	4.863ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.060s	14.015us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.060s	14.196us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.620s	47.671us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.210s	45.900us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.350s	205.531us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.060s	14.196us	20	20	100.00
		sram_ctrl_csr_aliasing	1.210s	45.900us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	18.430s	2.615ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	8.860s	1.149ms	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	32.191m	34.358ms	47	50	94.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	8.762m	19.159ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.708m	14.449ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	22.736m	15.223ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	17.660s	910.652us	50	50	100.00
V2	executable	sram_ctrl_executable	30.037m	77.695ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.587m	378.300us	50	50	100.00
		sram_ctrl_partial_access_b2b	14.499m	103.141ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.008m	136.870us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.096m	305.189us	50	50	100.00
V2	regwen	sram_ctrl_regwen	27.507m	104.089ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.340s	103.364us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.337h	78.546ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.100s	22.181us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	7.880s	138.282us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	7.880s	138.282us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.060s	14.015us	5	5	100.00
		sram_ctrl_csr_rw	1.060s	14.196us	20	20	100.00
		sram_ctrl_csr_aliasing	1.210s	45.900us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.210s	71.274us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.060s	14.015us	5	5	100.00
		sram_ctrl_csr_rw	1.060s	14.196us	20	20	100.00
		sram_ctrl_csr_aliasing	1.210s	45.900us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.210s	71.274us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	8.130s	753.017us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	5.210s	288.113us	5	5	100.00
		sram_ctrl_tl_intg_err	4.450s	584.840us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	5.210s	288.113us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.450s	584.840us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	27.507m	104.089ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.060s	14.196us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	30.037m	77.695ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	30.037m	77.695ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	30.037m	77.695ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	17.660s	910.652us	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	8.130s	753.017us	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.072m	4.863ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.072m	4.863ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.072m	4.863ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	30.037m	77.695ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	5.210s	288.113us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	17.660s	910.652us	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	5.210s	288.113us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	5.210s	288.113us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.072m	4.863ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	5.210s	288.113us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	14.501m	13.918ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			1026	1040	98.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	15	93.75
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 9 failures.
  - 1.sram_ctrl_stress_all_with_rand_reset.28427146654414576850110607962487390338428709052750114945576600653459041849603
    Line 183, in log /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 967889484 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 967889484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.sram_ctrl_stress_all_with_rand_reset.46087667609847664148801674669219007838263978568821045130169366501430270884913
    Line 152, in log /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 890667886 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 890667886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test sram_ctrl_multiple_keys has 3 failures.
  - 3.sram_ctrl_multiple_keys.75510134186109002990364363692540715874639496295570093823790414915440057877279
    Line 101, in log /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 41888134844 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x5c38baba
  UVM_INFO @ 41888134844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.sram_ctrl_multiple_keys.107251312768167176048953883253762702792825171001660203684237055535877978734126
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 11732407800 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x7f17e58c
  UVM_INFO @ 11732407800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 0.sram_ctrl_csr_mem_rw_with_rand_reset.101236813477469620219221061893039650851618930673404253500605099695032114669332
    Line 87, in log /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  45468453 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  45468453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 6.sram_ctrl_csr_mem_rw_with_rand_reset.32412255011245757402360524314166697084756447272592339300881499654267640361422
    Line 93, in log /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 205531180 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (14 [0xe] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @ 205531180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/RET Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: af2d1709f9

Branch: os_regression_2024_09_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `af2d1709f9`