| T369 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.260719302 |
|
|
Feb 07 04:33:48 PM PST 24 |
Feb 07 04:38:09 PM PST 24 |
2638435899 ps |
| T32 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3782109121 |
|
|
Feb 07 04:38:58 PM PST 24 |
Feb 07 04:43:01 PM PST 24 |
5536008056 ps |
| T370 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.2895908266 |
|
|
Feb 07 05:02:50 PM PST 24 |
Feb 07 05:11:34 PM PST 24 |
4199540966 ps |
| T371 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.719042868 |
|
|
Feb 07 05:02:56 PM PST 24 |
Feb 07 05:16:05 PM PST 24 |
9511855250 ps |
| T887 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.640955342 |
|
|
Feb 07 04:51:40 PM PST 24 |
Feb 07 05:18:39 PM PST 24 |
22291556201 ps |
| T888 |
/workspace/coverage/default/3.chip_tap_straps_prod.3904560744 |
|
|
Feb 07 04:56:44 PM PST 24 |
Feb 07 05:00:01 PM PST 24 |
2685610704 ps |
| T753 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.3367866677 |
|
|
Feb 07 04:58:31 PM PST 24 |
Feb 07 05:09:56 PM PST 24 |
5674137224 ps |
| T755 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.2528687314 |
|
|
Feb 07 05:04:17 PM PST 24 |
Feb 07 05:15:29 PM PST 24 |
6044201920 ps |
| T344 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.715743079 |
|
|
Feb 07 04:42:04 PM PST 24 |
Feb 07 05:36:50 PM PST 24 |
11997500830 ps |
| T889 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2336295612 |
|
|
Feb 07 04:57:01 PM PST 24 |
Feb 07 05:07:33 PM PST 24 |
6070628608 ps |
| T131 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.4114600963 |
|
|
Feb 07 04:34:19 PM PST 24 |
Feb 07 05:37:06 PM PST 24 |
16747584564 ps |
| T103 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.4010814592 |
|
|
Feb 07 04:43:32 PM PST 24 |
Feb 07 04:56:46 PM PST 24 |
4022210872 ps |
| T890 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.1578167583 |
|
|
Feb 07 04:59:14 PM PST 24 |
Feb 07 05:27:29 PM PST 24 |
9253357093 ps |
| T104 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.395979731 |
|
|
Feb 07 04:51:57 PM PST 24 |
Feb 07 05:01:39 PM PST 24 |
4000343772 ps |
| T891 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2352076389 |
|
|
Feb 07 04:35:08 PM PST 24 |
Feb 07 04:43:01 PM PST 24 |
4640111140 ps |
| T892 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.337517821 |
|
|
Feb 07 04:38:01 PM PST 24 |
Feb 07 04:43:29 PM PST 24 |
3099143332 ps |
| T893 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2197776790 |
|
|
Feb 07 04:49:45 PM PST 24 |
Feb 07 05:13:13 PM PST 24 |
12450995724 ps |
| T46 |
/workspace/coverage/default/0.chip_tap_straps_testunlock0.2530812410 |
|
|
Feb 07 04:35:47 PM PST 24 |
Feb 07 04:39:13 PM PST 24 |
2860795720 ps |
| T403 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.2031418819 |
|
|
Feb 07 04:33:28 PM PST 24 |
Feb 07 04:39:08 PM PST 24 |
2778813472 ps |
| T122 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.318234285 |
|
|
Feb 07 04:49:30 PM PST 24 |
Feb 07 04:59:27 PM PST 24 |
8153054320 ps |
| T109 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.607241453 |
|
|
Feb 07 04:50:51 PM PST 24 |
Feb 07 04:59:59 PM PST 24 |
3224439560 ps |
| T217 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3546170423 |
|
|
Feb 07 04:32:08 PM PST 24 |
Feb 07 04:49:37 PM PST 24 |
5442500348 ps |
| T894 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1348445759 |
|
|
Feb 07 04:39:26 PM PST 24 |
Feb 07 05:00:13 PM PST 24 |
12961814184 ps |
| T895 |
/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.116487499 |
|
|
Feb 07 04:40:12 PM PST 24 |
Feb 07 04:43:29 PM PST 24 |
2218472056 ps |
| T250 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.193153263 |
|
|
Feb 07 04:34:18 PM PST 24 |
Feb 07 04:43:32 PM PST 24 |
3386831832 ps |
| T132 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3281723411 |
|
|
Feb 07 04:50:29 PM PST 24 |
Feb 07 05:48:26 PM PST 24 |
17212139992 ps |
| T351 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.3852162548 |
|
|
Feb 07 04:32:17 PM PST 24 |
Feb 07 04:36:08 PM PST 24 |
2502906058 ps |
| T756 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3099208915 |
|
|
Feb 07 05:07:02 PM PST 24 |
Feb 07 05:14:26 PM PST 24 |
4422103864 ps |
| T178 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.3657876254 |
|
|
Feb 07 04:37:54 PM PST 24 |
Feb 07 04:42:38 PM PST 24 |
2782367237 ps |
| T117 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4112813289 |
|
|
Feb 07 04:51:56 PM PST 24 |
Feb 07 05:01:03 PM PST 24 |
5221439152 ps |
| T896 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1218704026 |
|
|
Feb 07 04:55:28 PM PST 24 |
Feb 07 05:01:38 PM PST 24 |
5450056032 ps |
| T897 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3444679251 |
|
|
Feb 07 04:52:53 PM PST 24 |
Feb 07 05:03:14 PM PST 24 |
3933274450 ps |
| T162 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2422081564 |
|
|
Feb 07 04:34:56 PM PST 24 |
Feb 07 04:44:36 PM PST 24 |
4756207786 ps |
| T291 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1022252013 |
|
|
Feb 07 04:51:58 PM PST 24 |
Feb 07 04:55:38 PM PST 24 |
1871192916 ps |
| T292 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4090062049 |
|
|
Feb 07 04:52:48 PM PST 24 |
Feb 07 05:04:47 PM PST 24 |
4050246448 ps |
| T293 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.631812879 |
|
|
Feb 07 04:34:07 PM PST 24 |
Feb 07 05:26:41 PM PST 24 |
20388618152 ps |
| T173 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.243116271 |
|
|
Feb 07 04:48:10 PM PST 24 |
Feb 07 05:02:31 PM PST 24 |
7535013323 ps |
| T268 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3451054713 |
|
|
Feb 07 04:33:43 PM PST 24 |
Feb 07 04:53:09 PM PST 24 |
5825229600 ps |
| T251 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2749680723 |
|
|
Feb 07 04:34:53 PM PST 24 |
Feb 07 04:45:43 PM PST 24 |
7252418698 ps |
| T276 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3300019177 |
|
|
Feb 07 05:03:49 PM PST 24 |
Feb 07 05:10:41 PM PST 24 |
3732719252 ps |
| T277 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.1119314749 |
|
|
Feb 07 05:01:56 PM PST 24 |
Feb 07 05:10:42 PM PST 24 |
4057556724 ps |
| T216 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2337171753 |
|
|
Feb 07 04:32:27 PM PST 24 |
Feb 07 04:49:02 PM PST 24 |
4912868022 ps |
| T278 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3807882198 |
|
|
Feb 07 04:42:27 PM PST 24 |
Feb 07 04:51:47 PM PST 24 |
18878285064 ps |
| T110 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.649086994 |
|
|
Feb 07 04:34:35 PM PST 24 |
Feb 07 04:44:11 PM PST 24 |
2590111268 ps |
| T73 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4179494629 |
|
|
Feb 07 04:53:14 PM PST 24 |
Feb 07 05:22:53 PM PST 24 |
22807008250 ps |
| T749 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1081541639 |
|
|
Feb 07 04:58:27 PM PST 24 |
Feb 07 05:07:21 PM PST 24 |
3512028806 ps |
| T898 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3618705780 |
|
|
Feb 07 04:58:06 PM PST 24 |
Feb 07 06:03:11 PM PST 24 |
23299530864 ps |
| T899 |
/workspace/coverage/default/1.rom_raw_unlock.2165063015 |
|
|
Feb 07 04:49:27 PM PST 24 |
Feb 07 05:28:53 PM PST 24 |
14719355375 ps |
| T900 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.3441556443 |
|
|
Feb 07 04:38:47 PM PST 24 |
Feb 07 04:44:59 PM PST 24 |
3959428536 ps |
| T901 |
/workspace/coverage/default/1.chip_sw_uart_smoketest.1451914025 |
|
|
Feb 07 04:46:45 PM PST 24 |
Feb 07 04:51:20 PM PST 24 |
2926690172 ps |
| T285 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2155550154 |
|
|
Feb 07 04:42:27 PM PST 24 |
Feb 07 04:52:59 PM PST 24 |
4066425912 ps |
| T902 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3855331987 |
|
|
Feb 07 04:37:31 PM PST 24 |
Feb 07 04:42:35 PM PST 24 |
4803554082 ps |
| T690 |
/workspace/coverage/default/1.chip_sw_power_idle_load.868451360 |
|
|
Feb 07 04:45:37 PM PST 24 |
Feb 07 04:57:09 PM PST 24 |
3538386550 ps |
| T139 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.772496348 |
|
|
Feb 07 04:48:55 PM PST 24 |
Feb 07 04:51:01 PM PST 24 |
2436075407 ps |
| T903 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.2279472957 |
|
|
Feb 07 04:54:40 PM PST 24 |
Feb 07 05:00:14 PM PST 24 |
2952648280 ps |
| T904 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.3254880774 |
|
|
Feb 07 04:46:35 PM PST 24 |
Feb 07 04:51:32 PM PST 24 |
2950778700 ps |
| T766 |
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1686025757 |
|
|
Feb 07 04:58:00 PM PST 24 |
Feb 07 05:05:31 PM PST 24 |
3640965888 ps |
| T252 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.1556584701 |
|
|
Feb 07 05:04:23 PM PST 24 |
Feb 07 05:14:36 PM PST 24 |
4740689758 ps |
| T279 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.545962943 |
|
|
Feb 07 04:39:38 PM PST 24 |
Feb 07 04:43:59 PM PST 24 |
3031357670 ps |
| T260 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.4242960332 |
|
|
Feb 07 04:43:30 PM PST 24 |
Feb 07 04:47:47 PM PST 24 |
2849112616 ps |
| T905 |
/workspace/coverage/default/0.chip_sw_kmac_smoketest.4023558415 |
|
|
Feb 07 04:37:55 PM PST 24 |
Feb 07 04:43:51 PM PST 24 |
2779771460 ps |
| T218 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.30476117 |
|
|
Feb 07 04:48:33 PM PST 24 |
Feb 07 05:03:56 PM PST 24 |
5752923092 ps |
| T906 |
/workspace/coverage/default/0.chip_sw_example_concurrency.2890107178 |
|
|
Feb 07 04:32:59 PM PST 24 |
Feb 07 04:36:10 PM PST 24 |
2030150356 ps |
| T343 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2336177089 |
|
|
Feb 07 04:33:35 PM PST 24 |
Feb 07 05:04:46 PM PST 24 |
7762697094 ps |
| T907 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.577120583 |
|
|
Feb 07 04:47:57 PM PST 24 |
Feb 07 04:58:44 PM PST 24 |
5241051608 ps |
| T136 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.298674793 |
|
|
Feb 07 04:49:35 PM PST 24 |
Feb 07 05:20:43 PM PST 24 |
13307749060 ps |
| T908 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.208026449 |
|
|
Feb 07 04:34:13 PM PST 24 |
Feb 07 04:49:29 PM PST 24 |
6332884640 ps |
| T909 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3038367105 |
|
|
Feb 07 04:39:06 PM PST 24 |
Feb 07 05:01:05 PM PST 24 |
10087220547 ps |
| T697 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3465877385 |
|
|
Feb 07 04:40:38 PM PST 24 |
Feb 07 05:12:11 PM PST 24 |
9126736520 ps |
| T910 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1434094088 |
|
|
Feb 07 04:34:12 PM PST 24 |
Feb 07 04:40:02 PM PST 24 |
5133067210 ps |
| T911 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1421685071 |
|
|
Feb 07 04:37:13 PM PST 24 |
Feb 07 04:46:54 PM PST 24 |
3904713224 ps |
| T74 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.766774631 |
|
|
Feb 07 04:44:13 PM PST 24 |
Feb 07 04:52:35 PM PST 24 |
7478624904 ps |
| T912 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1545205624 |
|
|
Feb 07 04:34:30 PM PST 24 |
Feb 07 04:47:08 PM PST 24 |
4772596440 ps |
| T263 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.444891207 |
|
|
Feb 07 04:50:30 PM PST 24 |
Feb 07 04:55:00 PM PST 24 |
3524006444 ps |
| T913 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.2741564329 |
|
|
Feb 07 04:33:11 PM PST 24 |
Feb 07 04:54:17 PM PST 24 |
6005469116 ps |
| T795 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.2164141385 |
|
|
Feb 07 04:59:45 PM PST 24 |
Feb 07 05:12:50 PM PST 24 |
6127227748 ps |
| T914 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3333550094 |
|
|
Feb 07 04:40:30 PM PST 24 |
Feb 07 04:49:20 PM PST 24 |
6588712400 ps |
| T720 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2641015138 |
|
|
Feb 07 04:53:50 PM PST 24 |
Feb 07 05:02:23 PM PST 24 |
3704287282 ps |
| T75 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3880753437 |
|
|
Feb 07 04:34:33 PM PST 24 |
Feb 07 04:43:51 PM PST 24 |
7213070328 ps |
| T915 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.189882900 |
|
|
Feb 07 04:40:25 PM PST 24 |
Feb 07 05:13:26 PM PST 24 |
8537705559 ps |
| T916 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3041840003 |
|
|
Feb 07 04:38:46 PM PST 24 |
Feb 07 04:55:20 PM PST 24 |
5913430152 ps |
| T668 |
/workspace/coverage/default/2.chip_jtag_csr_rw.962095107 |
|
|
Feb 07 04:45:33 PM PST 24 |
Feb 07 05:09:03 PM PST 24 |
10111709312 ps |
| T53 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3387360865 |
|
|
Feb 07 04:39:37 PM PST 24 |
Feb 07 05:01:30 PM PST 24 |
11337447192 ps |
| T917 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.652654231 |
|
|
Feb 07 04:39:50 PM PST 24 |
Feb 07 05:00:41 PM PST 24 |
10389269132 ps |
| T785 |
/workspace/coverage/default/93.chip_sw_all_escalation_resets.4275414199 |
|
|
Feb 07 05:05:28 PM PST 24 |
Feb 07 05:12:08 PM PST 24 |
4887588088 ps |
| T918 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2164681955 |
|
|
Feb 07 04:40:45 PM PST 24 |
Feb 07 04:53:50 PM PST 24 |
5008050128 ps |
| T919 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.880511021 |
|
|
Feb 07 04:51:48 PM PST 24 |
Feb 07 04:56:46 PM PST 24 |
3027257972 ps |
| T716 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.3586529071 |
|
|
Feb 07 05:00:20 PM PST 24 |
Feb 07 05:12:07 PM PST 24 |
5820616904 ps |
| T186 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2208020802 |
|
|
Feb 07 04:34:49 PM PST 24 |
Feb 07 05:39:08 PM PST 24 |
13735522296 ps |
| T745 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.2558065777 |
|
|
Feb 07 05:04:15 PM PST 24 |
Feb 07 05:15:05 PM PST 24 |
5440965936 ps |
| T920 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.4106017836 |
|
|
Feb 07 04:40:27 PM PST 24 |
Feb 07 04:43:45 PM PST 24 |
2583409387 ps |
| T921 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.1621584615 |
|
|
Feb 07 04:43:47 PM PST 24 |
Feb 07 05:05:07 PM PST 24 |
10974906680 ps |
| T922 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1723802421 |
|
|
Feb 07 04:44:19 PM PST 24 |
Feb 07 04:51:17 PM PST 24 |
3144467124 ps |
| T923 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.812766784 |
|
|
Feb 07 04:31:55 PM PST 24 |
Feb 07 04:34:42 PM PST 24 |
2556194168 ps |
| T44 |
/workspace/coverage/default/1.chip_tap_straps_rma.2591973296 |
|
|
Feb 07 04:44:04 PM PST 24 |
Feb 07 04:48:30 PM PST 24 |
3569078041 ps |
| T924 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.3243390157 |
|
|
Feb 07 04:35:31 PM PST 24 |
Feb 07 04:42:25 PM PST 24 |
2914925180 ps |
| T925 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2138412096 |
|
|
Feb 07 05:03:04 PM PST 24 |
Feb 07 05:09:47 PM PST 24 |
6827763377 ps |
| T758 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2091814838 |
|
|
Feb 07 05:01:40 PM PST 24 |
Feb 07 05:08:44 PM PST 24 |
3848107384 ps |
| T699 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.768024319 |
|
|
Feb 07 04:41:15 PM PST 24 |
Feb 07 05:36:49 PM PST 24 |
20262660830 ps |
| T754 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.4099316004 |
|
|
Feb 07 05:04:00 PM PST 24 |
Feb 07 05:09:20 PM PST 24 |
3661424856 ps |
| T926 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3664655971 |
|
|
Feb 07 04:49:23 PM PST 24 |
Feb 07 04:54:41 PM PST 24 |
4338737900 ps |
| T927 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.914436598 |
|
|
Feb 07 04:43:26 PM PST 24 |
Feb 07 04:52:17 PM PST 24 |
4093392416 ps |
| T928 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2469404371 |
|
|
Feb 07 04:45:39 PM PST 24 |
Feb 07 05:04:31 PM PST 24 |
5504903008 ps |
| T89 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3272208613 |
|
|
Feb 07 04:53:28 PM PST 24 |
Feb 07 06:03:45 PM PST 24 |
24223916199 ps |
| T111 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.1013573894 |
|
|
Feb 07 04:42:11 PM PST 24 |
Feb 07 05:13:55 PM PST 24 |
7013298380 ps |
| T264 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1065886192 |
|
|
Feb 07 04:36:09 PM PST 24 |
Feb 07 04:48:40 PM PST 24 |
4291602352 ps |
| T797 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.709344628 |
|
|
Feb 07 04:58:16 PM PST 24 |
Feb 07 05:04:33 PM PST 24 |
3901274412 ps |
| T163 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3529801735 |
|
|
Feb 07 04:36:14 PM PST 24 |
Feb 07 04:40:13 PM PST 24 |
3061752110 ps |
| T303 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.981341947 |
|
|
Feb 07 04:42:47 PM PST 24 |
Feb 07 05:24:51 PM PST 24 |
10597629906 ps |
| T304 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1183216611 |
|
|
Feb 07 04:48:15 PM PST 24 |
Feb 07 07:54:53 PM PST 24 |
59218680679 ps |
| T305 |
/workspace/coverage/default/1.rom_e2e_smoke.760175987 |
|
|
Feb 07 04:45:56 PM PST 24 |
Feb 07 05:22:59 PM PST 24 |
8495274496 ps |
| T306 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.279903149 |
|
|
Feb 07 05:00:56 PM PST 24 |
Feb 07 05:09:27 PM PST 24 |
5134801248 ps |
| T307 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.2703914838 |
|
|
Feb 07 05:02:34 PM PST 24 |
Feb 07 05:12:06 PM PST 24 |
4707817664 ps |
| T308 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.221974546 |
|
|
Feb 07 04:38:55 PM PST 24 |
Feb 07 05:04:27 PM PST 24 |
7146591075 ps |
| T14 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.4012152809 |
|
|
Feb 07 04:32:18 PM PST 24 |
Feb 07 04:40:05 PM PST 24 |
4930035930 ps |
| T309 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.3970784457 |
|
|
Feb 07 05:01:41 PM PST 24 |
Feb 07 05:16:04 PM PST 24 |
5718043520 ps |
| T286 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1793202453 |
|
|
Feb 07 04:53:34 PM PST 24 |
Feb 07 05:06:32 PM PST 24 |
4486107484 ps |
| T153 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3267150307 |
|
|
Feb 07 04:32:58 PM PST 24 |
Feb 07 04:35:12 PM PST 24 |
3668241761 ps |
| T174 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2885754385 |
|
|
Feb 07 04:39:12 PM PST 24 |
Feb 07 04:47:54 PM PST 24 |
4358047256 ps |
| T373 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.3236574589 |
|
|
Feb 07 04:40:49 PM PST 24 |
Feb 07 05:17:50 PM PST 24 |
24980225436 ps |
| T374 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1724114048 |
|
|
Feb 07 04:35:16 PM PST 24 |
Feb 07 04:44:13 PM PST 24 |
5758521132 ps |
| T352 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2097272906 |
|
|
Feb 07 04:39:35 PM PST 24 |
Feb 07 04:46:00 PM PST 24 |
3020239930 ps |
| T375 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.541566434 |
|
|
Feb 07 04:36:53 PM PST 24 |
Feb 07 04:42:29 PM PST 24 |
4024463770 ps |
| T929 |
/workspace/coverage/default/1.chip_sw_example_flash.2898331148 |
|
|
Feb 07 04:40:11 PM PST 24 |
Feb 07 04:45:17 PM PST 24 |
2795636564 ps |
| T930 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2074115685 |
|
|
Feb 07 05:01:01 PM PST 24 |
Feb 07 05:35:21 PM PST 24 |
12389145118 ps |
| T931 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3184346441 |
|
|
Feb 07 04:42:08 PM PST 24 |
Feb 07 04:47:00 PM PST 24 |
2438308736 ps |
| T932 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1160332916 |
|
|
Feb 07 04:34:52 PM PST 24 |
Feb 07 04:42:19 PM PST 24 |
3627456120 ps |
| T933 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3739433824 |
|
|
Feb 07 04:53:36 PM PST 24 |
Feb 07 04:57:50 PM PST 24 |
2564080493 ps |
| T714 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3569121935 |
|
|
Feb 07 05:06:10 PM PST 24 |
Feb 07 05:12:56 PM PST 24 |
4020385764 ps |
| T746 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.4134692170 |
|
|
Feb 07 04:47:32 PM PST 24 |
Feb 07 05:00:01 PM PST 24 |
5003402600 ps |
| T934 |
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3453524449 |
|
|
Feb 07 04:55:45 PM PST 24 |
Feb 07 05:10:17 PM PST 24 |
5456119762 ps |
| T267 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.72646735 |
|
|
Feb 07 04:33:35 PM PST 24 |
Feb 07 04:44:45 PM PST 24 |
4257041040 ps |
| T735 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.4075033843 |
|
|
Feb 07 05:02:54 PM PST 24 |
Feb 07 05:13:51 PM PST 24 |
5900813672 ps |
| T346 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.1602009165 |
|
|
Feb 07 04:59:27 PM PST 24 |
Feb 07 05:30:40 PM PST 24 |
8861317872 ps |
| T935 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.428566783 |
|
|
Feb 07 04:57:45 PM PST 24 |
Feb 07 05:15:45 PM PST 24 |
6182858972 ps |
| T710 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.2568227654 |
|
|
Feb 07 05:04:35 PM PST 24 |
Feb 07 05:13:41 PM PST 24 |
5736297368 ps |
| T702 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.1576566800 |
|
|
Feb 07 05:01:25 PM PST 24 |
Feb 07 05:13:07 PM PST 24 |
4394865336 ps |
| T315 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.1588993973 |
|
|
Feb 07 05:04:38 PM PST 24 |
Feb 07 05:16:14 PM PST 24 |
4805849960 ps |
| T740 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1318408479 |
|
|
Feb 07 05:02:36 PM PST 24 |
Feb 07 05:08:25 PM PST 24 |
3752862868 ps |
| T717 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2126100285 |
|
|
Feb 07 05:08:09 PM PST 24 |
Feb 07 05:18:03 PM PST 24 |
5322333370 ps |
| T936 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.330973905 |
|
|
Feb 07 04:56:07 PM PST 24 |
Feb 07 05:14:04 PM PST 24 |
11213628847 ps |
| T937 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2539828040 |
|
|
Feb 07 04:51:30 PM PST 24 |
Feb 07 04:56:44 PM PST 24 |
3218075640 ps |
| T693 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.203029073 |
|
|
Feb 07 04:33:38 PM PST 24 |
Feb 07 04:49:28 PM PST 24 |
4672475214 ps |
| T938 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.274997684 |
|
|
Feb 07 04:33:15 PM PST 24 |
Feb 07 05:10:21 PM PST 24 |
12750578818 ps |
| T652 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.2989608902 |
|
|
Feb 07 04:51:04 PM PST 24 |
Feb 07 04:57:07 PM PST 24 |
3027509623 ps |
| T939 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.821579379 |
|
|
Feb 07 04:59:52 PM PST 24 |
Feb 07 05:36:09 PM PST 24 |
14287853180 ps |
| T704 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.4251935586 |
|
|
Feb 07 05:03:22 PM PST 24 |
Feb 07 05:13:28 PM PST 24 |
4649152066 ps |
| T350 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1859346888 |
|
|
Feb 07 04:45:07 PM PST 24 |
Feb 07 04:50:37 PM PST 24 |
2275106432 ps |
| T940 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.267573821 |
|
|
Feb 07 04:51:20 PM PST 24 |
Feb 07 04:57:08 PM PST 24 |
3647404153 ps |
| T941 |
/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.816634734 |
|
|
Feb 07 04:51:13 PM PST 24 |
Feb 07 04:54:23 PM PST 24 |
2485444900 ps |
| T750 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.731773634 |
|
|
Feb 07 05:00:18 PM PST 24 |
Feb 07 05:06:36 PM PST 24 |
3877285888 ps |
| T942 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1427195800 |
|
|
Feb 07 04:32:35 PM PST 24 |
Feb 07 04:47:10 PM PST 24 |
8204352466 ps |
| T90 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3447239628 |
|
|
Feb 07 04:40:12 PM PST 24 |
Feb 07 05:42:22 PM PST 24 |
19025610242 ps |
| T943 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2150507971 |
|
|
Feb 07 04:58:52 PM PST 24 |
Feb 07 05:01:55 PM PST 24 |
2509031100 ps |
| T944 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.2796191670 |
|
|
Feb 07 04:33:00 PM PST 24 |
Feb 07 08:05:33 PM PST 24 |
64741757504 ps |
| T945 |
/workspace/coverage/default/0.chip_sw_aes_smoketest.1884757961 |
|
|
Feb 07 04:39:50 PM PST 24 |
Feb 07 04:43:56 PM PST 24 |
2828183842 ps |
| T791 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3637751116 |
|
|
Feb 07 05:02:58 PM PST 24 |
Feb 07 05:08:58 PM PST 24 |
3543370618 ps |
| T323 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2864398725 |
|
|
Feb 07 05:05:09 PM PST 24 |
Feb 07 05:11:14 PM PST 24 |
3793672848 ps |
| T332 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.1585488651 |
|
|
Feb 07 04:59:22 PM PST 24 |
Feb 07 05:09:11 PM PST 24 |
4776051088 ps |
| T333 |
/workspace/coverage/default/1.chip_sw_flash_crash_alert.2251405591 |
|
|
Feb 07 04:45:01 PM PST 24 |
Feb 07 04:57:14 PM PST 24 |
5195877954 ps |
| T334 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3530100041 |
|
|
Feb 07 04:37:22 PM PST 24 |
Feb 07 04:55:23 PM PST 24 |
7957179976 ps |
| T335 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3076252615 |
|
|
Feb 07 04:41:57 PM PST 24 |
Feb 07 05:07:19 PM PST 24 |
6959190624 ps |
| T336 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.152075156 |
|
|
Feb 07 04:36:50 PM PST 24 |
Feb 07 05:08:19 PM PST 24 |
9598783098 ps |
| T337 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2568974209 |
|
|
Feb 07 04:59:39 PM PST 24 |
Feb 07 05:07:56 PM PST 24 |
4062634248 ps |
| T338 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1375801040 |
|
|
Feb 07 04:43:10 PM PST 24 |
Feb 07 04:56:31 PM PST 24 |
4692996304 ps |
| T946 |
/workspace/coverage/default/2.chip_sw_hmac_enc.1410007771 |
|
|
Feb 07 04:51:46 PM PST 24 |
Feb 07 04:56:37 PM PST 24 |
3071607182 ps |
| T947 |
/workspace/coverage/default/0.chip_sw_example_flash.974262319 |
|
|
Feb 07 04:33:02 PM PST 24 |
Feb 07 04:37:07 PM PST 24 |
2585280964 ps |
| T730 |
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.276425287 |
|
|
Feb 07 05:05:37 PM PST 24 |
Feb 07 05:13:38 PM PST 24 |
3839442046 ps |
| T792 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2441596051 |
|
|
Feb 07 05:01:55 PM PST 24 |
Feb 07 05:09:20 PM PST 24 |
4052431704 ps |
| T948 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access.3970830373 |
|
|
Feb 07 04:48:30 PM PST 24 |
Feb 07 05:05:31 PM PST 24 |
5386740596 ps |
| T164 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.590704810 |
|
|
Feb 07 04:36:29 PM PST 24 |
Feb 07 04:41:39 PM PST 24 |
2535405102 ps |
| T949 |
/workspace/coverage/default/2.chip_tap_straps_dev.1973661014 |
|
|
Feb 07 04:52:35 PM PST 24 |
Feb 07 05:16:49 PM PST 24 |
14671894148 ps |
| T123 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.280193929 |
|
|
Feb 07 04:33:42 PM PST 24 |
Feb 07 04:41:00 PM PST 24 |
6985659368 ps |
| T345 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2211248691 |
|
|
Feb 07 04:42:01 PM PST 24 |
Feb 07 05:31:42 PM PST 24 |
12405797752 ps |
| T261 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.1717266324 |
|
|
Feb 07 04:34:16 PM PST 24 |
Feb 07 04:38:13 PM PST 24 |
3514450500 ps |
| T950 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3117749996 |
|
|
Feb 07 04:39:40 PM PST 24 |
Feb 07 04:55:16 PM PST 24 |
9977698545 ps |
| T793 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1042009904 |
|
|
Feb 07 04:59:42 PM PST 24 |
Feb 07 05:08:41 PM PST 24 |
3948487980 ps |
| T719 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1142976852 |
|
|
Feb 07 05:02:52 PM PST 24 |
Feb 07 05:10:34 PM PST 24 |
3773970652 ps |
| T951 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1854805875 |
|
|
Feb 07 04:35:29 PM PST 24 |
Feb 07 04:46:49 PM PST 24 |
4209868856 ps |
| T647 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4122285972 |
|
|
Feb 07 04:46:49 PM PST 24 |
Feb 07 05:46:53 PM PST 24 |
24809578654 ps |
| T952 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2043544584 |
|
|
Feb 07 04:49:35 PM PST 24 |
Feb 07 04:58:08 PM PST 24 |
4863126090 ps |
| T953 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2557298338 |
|
|
Feb 07 04:32:53 PM PST 24 |
Feb 07 04:38:28 PM PST 24 |
3716973059 ps |
| T954 |
/workspace/coverage/default/2.rom_e2e_shutdown_output.2399876215 |
|
|
Feb 07 04:58:38 PM PST 24 |
Feb 07 05:47:51 PM PST 24 |
29063947520 ps |
| T247 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.1550476805 |
|
|
Feb 07 04:51:57 PM PST 24 |
Feb 07 04:55:49 PM PST 24 |
2714210419 ps |
| T254 |
/workspace/coverage/default/1.chip_sw_alert_handler_escalation.1972593058 |
|
|
Feb 07 04:41:15 PM PST 24 |
Feb 07 04:53:05 PM PST 24 |
4665780564 ps |
| T723 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.4166491184 |
|
|
Feb 07 05:04:33 PM PST 24 |
Feb 07 05:11:28 PM PST 24 |
3033797700 ps |
| T955 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.703658972 |
|
|
Feb 07 04:34:23 PM PST 24 |
Feb 07 04:55:55 PM PST 24 |
23048387954 ps |
| T96 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2223226494 |
|
|
Feb 07 04:51:27 PM PST 24 |
Feb 07 05:00:06 PM PST 24 |
4169420171 ps |
| T167 |
/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.3514878867 |
|
|
Feb 07 04:41:02 PM PST 24 |
Feb 07 04:49:52 PM PST 24 |
5582151064 ps |
| T956 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.216115057 |
|
|
Feb 07 04:35:00 PM PST 24 |
Feb 07 05:07:42 PM PST 24 |
13053933496 ps |
| T165 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2813224709 |
|
|
Feb 07 04:53:02 PM PST 24 |
Feb 07 05:09:41 PM PST 24 |
9164713082 ps |
| T769 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.1379455401 |
|
|
Feb 07 05:04:28 PM PST 24 |
Feb 07 05:13:40 PM PST 24 |
4756335742 ps |
| T957 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4212627735 |
|
|
Feb 07 04:39:07 PM PST 24 |
Feb 07 05:33:34 PM PST 24 |
32509915930 ps |
| T958 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3850300242 |
|
|
Feb 07 04:49:57 PM PST 24 |
Feb 07 05:12:11 PM PST 24 |
6005591874 ps |
| T706 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.3758866729 |
|
|
Feb 07 04:59:18 PM PST 24 |
Feb 07 05:13:57 PM PST 24 |
5572345332 ps |
| T237 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.3135909942 |
|
|
Feb 07 04:33:55 PM PST 24 |
Feb 07 04:42:57 PM PST 24 |
4156337724 ps |
| T192 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3755926534 |
|
|
Feb 07 04:38:15 PM PST 24 |
Feb 07 06:24:06 PM PST 24 |
133164016430 ps |
| T669 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2710875567 |
|
|
Feb 07 05:03:20 PM PST 24 |
Feb 07 05:10:49 PM PST 24 |
3973132026 ps |
| T959 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.4080171729 |
|
|
Feb 07 04:36:14 PM PST 24 |
Feb 07 04:40:48 PM PST 24 |
2752117400 ps |
| T960 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.4265722416 |
|
|
Feb 07 04:34:18 PM PST 24 |
Feb 07 04:57:29 PM PST 24 |
7541482300 ps |
| T961 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1295912099 |
|
|
Feb 07 04:50:59 PM PST 24 |
Feb 07 04:56:13 PM PST 24 |
3166929294 ps |
| T670 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.102848887 |
|
|
Feb 07 04:59:44 PM PST 24 |
Feb 07 05:06:53 PM PST 24 |
3952464382 ps |
| T781 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2830991466 |
|
|
Feb 07 04:59:40 PM PST 24 |
Feb 07 05:08:00 PM PST 24 |
3408688288 ps |
| T962 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.1764788717 |
|
|
Feb 07 04:53:20 PM PST 24 |
Feb 07 05:07:40 PM PST 24 |
4977095912 ps |
| T963 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1605599140 |
|
|
Feb 07 04:33:01 PM PST 24 |
Feb 07 05:23:13 PM PST 24 |
13505995490 ps |
| T204 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.3901774711 |
|
|
Feb 07 04:42:19 PM PST 24 |
Feb 07 04:58:46 PM PST 24 |
5984354512 ps |
| T11 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2675597273 |
|
|
Feb 07 04:45:12 PM PST 24 |
Feb 07 04:53:20 PM PST 24 |
5227472446 ps |
| T203 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.3958107752 |
|
|
Feb 07 04:44:47 PM PST 24 |
Feb 07 04:58:15 PM PST 24 |
4857835404 ps |
| T394 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.334006333 |
|
|
Feb 07 04:41:12 PM PST 24 |
Feb 07 05:06:37 PM PST 24 |
6749691744 ps |
| T395 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.167343515 |
|
|
Feb 07 04:47:19 PM PST 24 |
Feb 07 05:19:26 PM PST 24 |
10979674936 ps |
| T396 |
/workspace/coverage/default/0.chip_tap_straps_rma.3055633483 |
|
|
Feb 07 04:32:57 PM PST 24 |
Feb 07 04:37:30 PM PST 24 |
3859984152 ps |
| T397 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.625655855 |
|
|
Feb 07 04:38:07 PM PST 24 |
Feb 07 04:42:20 PM PST 24 |
3141051176 ps |
| T398 |
/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3015010229 |
|
|
Feb 07 04:33:35 PM PST 24 |
Feb 07 05:05:05 PM PST 24 |
9103857556 ps |
| T399 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1882657112 |
|
|
Feb 07 04:40:29 PM PST 24 |
Feb 07 05:27:04 PM PST 24 |
11772467030 ps |
| T400 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.1465122696 |
|
|
Feb 07 04:32:12 PM PST 24 |
Feb 07 04:35:51 PM PST 24 |
2260597500 ps |
| T964 |
/workspace/coverage/default/1.chip_sw_aes_entropy.1546393220 |
|
|
Feb 07 04:40:24 PM PST 24 |
Feb 07 04:44:59 PM PST 24 |
2456796728 ps |
| T965 |
/workspace/coverage/default/2.rom_keymgr_functest.475637238 |
|
|
Feb 07 04:57:27 PM PST 24 |
Feb 07 05:08:19 PM PST 24 |
5270898076 ps |
| T240 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.454668378 |
|
|
Feb 07 05:03:42 PM PST 24 |
Feb 07 05:12:33 PM PST 24 |
4740290128 ps |
| T966 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1072981553 |
|
|
Feb 07 04:35:29 PM PST 24 |
Feb 07 04:41:26 PM PST 24 |
2981157905 ps |
| T967 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.791505042 |
|
|
Feb 07 04:54:04 PM PST 24 |
Feb 07 04:58:07 PM PST 24 |
2713253595 ps |
| T968 |
/workspace/coverage/default/0.chip_sw_flash_crash_alert.184283733 |
|
|
Feb 07 04:36:24 PM PST 24 |
Feb 07 04:50:40 PM PST 24 |
5704694530 ps |
| T718 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3491954617 |
|
|
Feb 07 05:02:40 PM PST 24 |
Feb 07 05:10:04 PM PST 24 |
3356466630 ps |
| T969 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.829668066 |
|
|
Feb 07 05:03:11 PM PST 24 |
Feb 07 05:13:57 PM PST 24 |
5795662360 ps |
| T705 |
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1060027171 |
|
|
Feb 07 05:05:26 PM PST 24 |
Feb 07 05:12:47 PM PST 24 |
3941312512 ps |
| T692 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.3065516573 |
|
|
Feb 07 05:04:16 PM PST 24 |
Feb 07 05:12:40 PM PST 24 |
4775534916 ps |
| T970 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3387883482 |
|
|
Feb 07 04:32:40 PM PST 24 |
Feb 07 04:54:04 PM PST 24 |
8757015200 ps |
| T721 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2100288418 |
|
|
Feb 07 05:01:22 PM PST 24 |
Feb 07 05:11:07 PM PST 24 |
4148019568 ps |
| T134 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.1278940540 |
|
|
Feb 07 04:54:24 PM PST 24 |
Feb 07 05:04:01 PM PST 24 |
3002498072 ps |
| T971 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.2655265455 |
|
|
Feb 07 04:41:24 PM PST 24 |
Feb 07 05:17:49 PM PST 24 |
8670077108 ps |
| T972 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2384674615 |
|
|
Feb 07 04:33:35 PM PST 24 |
Feb 07 05:21:01 PM PST 24 |
22251674464 ps |
| T349 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2313510751 |
|
|
Feb 07 04:36:12 PM PST 24 |
Feb 07 04:38:35 PM PST 24 |
2828638900 ps |
| T973 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.669929859 |
|
|
Feb 07 04:32:19 PM PST 24 |
Feb 07 04:38:55 PM PST 24 |
3245918784 ps |
| T974 |
/workspace/coverage/default/0.chip_sw_power_idle_load.4186011647 |
|
|
Feb 07 04:37:54 PM PST 24 |
Feb 07 04:50:46 PM PST 24 |
4601729932 ps |
| T748 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.2571077177 |
|
|
Feb 07 05:04:18 PM PST 24 |
Feb 07 05:16:27 PM PST 24 |
6103354052 ps |
| T287 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.3265523587 |
|
|
Feb 07 04:57:46 PM PST 24 |
Feb 07 05:11:41 PM PST 24 |
6052777630 ps |
| T975 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2379284414 |
|
|
Feb 07 04:48:32 PM PST 24 |
Feb 07 04:56:07 PM PST 24 |
4067148406 ps |
| T147 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.3913662022 |
|
|
Feb 07 04:55:15 PM PST 24 |
Feb 07 05:02:05 PM PST 24 |
4425127956 ps |
| T976 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.2793410991 |
|
|
Feb 07 04:42:22 PM PST 24 |
Feb 07 05:18:57 PM PST 24 |
24322314450 ps |
| T15 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3810081621 |
|
|
Feb 07 04:34:38 PM PST 24 |
Feb 07 05:04:10 PM PST 24 |
19156388888 ps |
| T977 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3265529525 |
|
|
Feb 07 04:42:17 PM PST 24 |
Feb 07 04:49:08 PM PST 24 |
4863726430 ps |
| T978 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2267036981 |
|
|
Feb 07 04:37:32 PM PST 24 |
Feb 07 04:50:09 PM PST 24 |
5601658250 ps |
| T979 |
/workspace/coverage/default/0.chip_sw_coremark.4031565771 |
|
|
Feb 07 04:34:47 PM PST 24 |
Feb 07 07:19:12 PM PST 24 |
50243049196 ps |
| T21 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.697825557 |
|
|
Feb 07 04:44:53 PM PST 24 |
Feb 07 05:18:46 PM PST 24 |
21225297380 ps |
| T200 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1735778846 |
|
|
Feb 07 04:38:34 PM PST 24 |
Feb 07 05:10:42 PM PST 24 |
12417419872 ps |
| T709 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.2896628383 |
|
|
Feb 07 04:38:36 PM PST 24 |
Feb 07 04:49:50 PM PST 24 |
6332227000 ps |
| T980 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1709882829 |
|
|
Feb 07 04:45:08 PM PST 24 |
Feb 07 04:49:23 PM PST 24 |
3349104373 ps |
| T288 |
/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.4075176199 |
|
|
Feb 07 04:49:57 PM PST 24 |
Feb 07 04:56:33 PM PST 24 |
2798417074 ps |
| T981 |
/workspace/coverage/default/0.chip_sw_example_rom.3953472916 |
|
|
Feb 07 04:31:22 PM PST 24 |
Feb 07 04:33:10 PM PST 24 |
2275477564 ps |
| T982 |
/workspace/coverage/default/1.chip_sw_kmac_idle.2031731420 |
|
|
Feb 07 04:41:56 PM PST 24 |
Feb 07 04:45:28 PM PST 24 |
2765669000 ps |
| T255 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2519564442 |
|
|
Feb 07 05:04:01 PM PST 24 |
Feb 07 05:10:09 PM PST 24 |
3816567178 ps |