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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.37 95.45 94.67 95.51 95.45 97.57 99.58


Total test records in report: 2875
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T2508 /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.2750288224 Feb 07 04:20:20 PM PST 24 Feb 07 04:26:56 PM PST 24 11959506094 ps
T2509 /workspace/coverage/cover_reg_top/51.xbar_stress_all.1193517422 Feb 07 04:18:06 PM PST 24 Feb 07 04:24:35 PM PST 24 4389814825 ps
T2510 /workspace/coverage/cover_reg_top/98.xbar_access_same_device.3420771747 Feb 07 04:24:55 PM PST 24 Feb 07 04:26:24 PM PST 24 2085007110 ps
T2511 /workspace/coverage/cover_reg_top/85.xbar_stress_all.1048021051 Feb 07 04:22:59 PM PST 24 Feb 07 04:25:06 PM PST 24 3733813020 ps
T2512 /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.1623933943 Feb 07 04:22:59 PM PST 24 Feb 07 05:03:26 PM PST 24 130500258164 ps
T2513 /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.4159648525 Feb 07 04:12:26 PM PST 24 Feb 07 04:12:46 PM PST 24 122050886 ps
T2514 /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.960857556 Feb 07 04:18:44 PM PST 24 Feb 07 04:19:23 PM PST 24 322292587 ps
T2515 /workspace/coverage/cover_reg_top/61.xbar_same_source.3239710785 Feb 07 04:19:17 PM PST 24 Feb 07 04:19:41 PM PST 24 746502187 ps
T2516 /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.1495798720 Feb 07 04:13:48 PM PST 24 Feb 07 04:17:08 PM PST 24 11786148176 ps
T2517 /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.2860992853 Feb 07 04:20:01 PM PST 24 Feb 07 04:35:54 PM PST 24 85546058408 ps
T2518 /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.2367872175 Feb 07 04:21:15 PM PST 24 Feb 07 04:21:25 PM PST 24 46312639 ps
T2519 /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.943434612 Feb 07 04:24:27 PM PST 24 Feb 07 04:26:12 PM PST 24 3124196495 ps
T2520 /workspace/coverage/cover_reg_top/61.xbar_random.3941224102 Feb 07 04:20:22 PM PST 24 Feb 07 04:21:02 PM PST 24 456502941 ps
T2521 /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.1289164496 Feb 07 04:16:26 PM PST 24 Feb 07 04:17:08 PM PST 24 401862864 ps
T2522 /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.1021032733 Feb 07 04:11:51 PM PST 24 Feb 07 04:20:28 PM PST 24 9188718666 ps
T2523 /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.167418515 Feb 07 04:18:30 PM PST 24 Feb 07 04:27:52 PM PST 24 30292636644 ps
T2524 /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.849437184 Feb 07 04:17:20 PM PST 24 Feb 07 04:28:31 PM PST 24 40967827923 ps
T2525 /workspace/coverage/cover_reg_top/91.xbar_random.2503447924 Feb 07 04:23:43 PM PST 24 Feb 07 04:25:03 PM PST 24 2072970818 ps
T2526 /workspace/coverage/cover_reg_top/34.xbar_smoke.1599328700 Feb 07 04:15:09 PM PST 24 Feb 07 04:15:17 PM PST 24 51546768 ps
T2527 /workspace/coverage/cover_reg_top/96.xbar_smoke.3782583865 Feb 07 04:24:28 PM PST 24 Feb 07 04:24:37 PM PST 24 164506980 ps
T2528 /workspace/coverage/cover_reg_top/6.xbar_smoke.4247521286 Feb 07 04:11:48 PM PST 24 Feb 07 04:11:57 PM PST 24 203838884 ps
T2529 /workspace/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.4215166633 Feb 07 04:11:50 PM PST 24 Feb 07 04:17:39 PM PST 24 10586718545 ps
T2530 /workspace/coverage/cover_reg_top/82.xbar_access_same_device.3194809416 Feb 07 04:22:16 PM PST 24 Feb 07 04:24:07 PM PST 24 1404250260 ps
T712 /workspace/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.1744638989 Feb 07 04:11:50 PM PST 24 Feb 07 04:17:34 PM PST 24 10319550361 ps
T2531 /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.920236202 Feb 07 04:19:33 PM PST 24 Feb 07 04:19:51 PM PST 24 46308431 ps
T682 /workspace/coverage/cover_reg_top/4.chip_tl_errors.933870054 Feb 07 04:11:45 PM PST 24 Feb 07 04:18:31 PM PST 24 4476836560 ps
T2532 /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3616139516 Feb 07 04:12:15 PM PST 24 Feb 07 04:12:45 PM PST 24 282807594 ps
T2533 /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.734484876 Feb 07 04:19:40 PM PST 24 Feb 07 04:19:48 PM PST 24 42191410 ps
T2534 /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.1032667516 Feb 07 04:15:11 PM PST 24 Feb 07 04:15:23 PM PST 24 202009382 ps
T2535 /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.3482131059 Feb 07 04:11:54 PM PST 24 Feb 07 04:25:48 PM PST 24 53636415097 ps
T2536 /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.3162328433 Feb 07 04:20:14 PM PST 24 Feb 07 04:20:45 PM PST 24 71892424 ps
T2537 /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.391979981 Feb 07 04:15:10 PM PST 24 Feb 07 04:15:17 PM PST 24 48581771 ps
T2538 /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.1075957021 Feb 07 04:21:50 PM PST 24 Feb 07 04:32:15 PM PST 24 56097293503 ps
T2539 /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.3496728031 Feb 07 04:23:31 PM PST 24 Feb 07 04:36:44 PM PST 24 42186545441 ps
T2540 /workspace/coverage/cover_reg_top/28.xbar_smoke.4108830600 Feb 07 04:14:18 PM PST 24 Feb 07 04:14:24 PM PST 24 48166642 ps
T2541 /workspace/coverage/cover_reg_top/48.xbar_access_same_device.3634469813 Feb 07 04:17:22 PM PST 24 Feb 07 04:18:30 PM PST 24 1338397861 ps
T2542 /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.4021746935 Feb 07 04:18:54 PM PST 24 Feb 07 04:20:11 PM PST 24 4717360486 ps
T2543 /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.3655173542 Feb 07 04:24:53 PM PST 24 Feb 07 04:31:05 PM PST 24 9374610075 ps
T2544 /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.4075445654 Feb 07 04:12:20 PM PST 24 Feb 07 04:13:14 PM PST 24 550884225 ps
T2545 /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.3396547768 Feb 07 04:19:32 PM PST 24 Feb 07 04:21:02 PM PST 24 5236019467 ps
T2546 /workspace/coverage/cover_reg_top/27.xbar_access_same_device.2762247334 Feb 07 04:14:13 PM PST 24 Feb 07 04:14:51 PM PST 24 408199612 ps
T2547 /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.1317750985 Feb 07 04:15:36 PM PST 24 Feb 07 04:17:07 PM PST 24 5260672001 ps
T2548 /workspace/coverage/cover_reg_top/14.xbar_same_source.2772637913 Feb 07 04:12:22 PM PST 24 Feb 07 04:13:25 PM PST 24 2082592082 ps
T2549 /workspace/coverage/cover_reg_top/54.xbar_same_source.1146578194 Feb 07 04:18:35 PM PST 24 Feb 07 04:18:46 PM PST 24 116956582 ps
T2550 /workspace/coverage/cover_reg_top/41.xbar_smoke.1452557593 Feb 07 04:16:27 PM PST 24 Feb 07 04:16:35 PM PST 24 48342725 ps
T2551 /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.3886532996 Feb 07 04:13:38 PM PST 24 Feb 07 04:14:13 PM PST 24 877537010 ps
T2552 /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.2354483867 Feb 07 04:13:02 PM PST 24 Feb 07 04:30:40 PM PST 24 97816735178 ps
T2553 /workspace/coverage/cover_reg_top/13.chip_tl_errors.1883577516 Feb 07 04:12:33 PM PST 24 Feb 07 04:17:01 PM PST 24 4019891276 ps
T2554 /workspace/coverage/cover_reg_top/20.xbar_random.2857543964 Feb 07 04:13:26 PM PST 24 Feb 07 04:13:33 PM PST 24 42977007 ps
T2555 /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.1011111256 Feb 07 04:11:47 PM PST 24 Feb 07 04:11:54 PM PST 24 40465588 ps
T2556 /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.3900563088 Feb 07 04:11:47 PM PST 24 Feb 07 04:15:09 PM PST 24 17221749479 ps
T2557 /workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.2110089209 Feb 07 04:12:35 PM PST 24 Feb 07 04:18:24 PM PST 24 8059037608 ps
T2558 /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.1773393812 Feb 07 04:19:23 PM PST 24 Feb 07 04:40:09 PM PST 24 65592859421 ps
T2559 /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.4212355313 Feb 07 04:12:06 PM PST 24 Feb 07 04:12:22 PM PST 24 347224497 ps
T2560 /workspace/coverage/cover_reg_top/40.xbar_stress_all.4097041700 Feb 07 04:16:22 PM PST 24 Feb 07 04:30:06 PM PST 24 20407803985 ps
T2561 /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.2523455100 Feb 07 04:14:39 PM PST 24 Feb 07 04:17:38 PM PST 24 1464136156 ps
T2562 /workspace/coverage/cover_reg_top/74.xbar_smoke.3413266388 Feb 07 04:21:04 PM PST 24 Feb 07 04:21:10 PM PST 24 44061106 ps
T2563 /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.925344936 Feb 07 04:19:02 PM PST 24 Feb 07 04:26:52 PM PST 24 1067524013 ps
T2564 /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.2707620855 Feb 07 04:17:14 PM PST 24 Feb 07 04:18:23 PM PST 24 3824051308 ps
T2565 /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.4168740509 Feb 07 04:20:14 PM PST 24 Feb 07 04:34:54 PM PST 24 46616261189 ps
T2566 /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.4224964459 Feb 07 04:21:13 PM PST 24 Feb 07 05:01:28 PM PST 24 119978148426 ps
T2567 /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.462212585 Feb 07 04:23:36 PM PST 24 Feb 07 04:23:59 PM PST 24 196291562 ps
T2568 /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.600483369 Feb 07 04:22:19 PM PST 24 Feb 07 04:31:39 PM PST 24 5215711110 ps
T2569 /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.2451077462 Feb 07 04:21:59 PM PST 24 Feb 07 04:29:59 PM PST 24 10948994312 ps
T2570 /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.2569803638 Feb 07 04:22:35 PM PST 24 Feb 07 04:30:01 PM PST 24 23494067529 ps
T2571 /workspace/coverage/cover_reg_top/74.xbar_error_random.1930989247 Feb 07 04:21:11 PM PST 24 Feb 07 04:21:20 PM PST 24 177715125 ps
T2572 /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.872257613 Feb 07 04:15:19 PM PST 24 Feb 07 04:36:23 PM PST 24 73917689499 ps
T2573 /workspace/coverage/cover_reg_top/0.xbar_access_same_device.2128353890 Feb 07 04:11:32 PM PST 24 Feb 07 04:14:05 PM PST 24 3325232213 ps
T2574 /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.2000191354 Feb 07 04:17:32 PM PST 24 Feb 07 04:20:22 PM PST 24 1837379025 ps
T2575 /workspace/coverage/cover_reg_top/80.xbar_error_random.45801157 Feb 07 04:22:05 PM PST 24 Feb 07 04:22:48 PM PST 24 465294943 ps
T2576 /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.3749212017 Feb 07 04:23:46 PM PST 24 Feb 07 04:26:59 PM PST 24 877033102 ps
T2577 /workspace/coverage/cover_reg_top/63.xbar_same_source.1949462436 Feb 07 04:19:41 PM PST 24 Feb 07 04:20:16 PM PST 24 470410828 ps
T2578 /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.1374603279 Feb 07 04:23:54 PM PST 24 Feb 07 04:25:44 PM PST 24 10686595909 ps
T2579 /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.3195194767 Feb 07 04:17:58 PM PST 24 Feb 07 04:18:26 PM PST 24 619522791 ps
T2580 /workspace/coverage/cover_reg_top/24.xbar_random.3940508552 Feb 07 04:13:49 PM PST 24 Feb 07 04:14:04 PM PST 24 290259030 ps
T2581 /workspace/coverage/cover_reg_top/76.xbar_same_source.1317287005 Feb 07 04:21:23 PM PST 24 Feb 07 04:21:34 PM PST 24 46513114 ps
T2582 /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.935311879 Feb 07 04:21:13 PM PST 24 Feb 07 04:21:24 PM PST 24 63516179 ps
T2583 /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.1452864370 Feb 07 04:17:39 PM PST 24 Feb 07 04:18:10 PM PST 24 156590294 ps
T2584 /workspace/coverage/cover_reg_top/24.xbar_access_same_device.2619262133 Feb 07 04:13:49 PM PST 24 Feb 07 04:15:09 PM PST 24 1782519454 ps
T2585 /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.981300541 Feb 07 04:25:06 PM PST 24 Feb 07 04:30:59 PM PST 24 1910000405 ps
T2586 /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.392582151 Feb 07 04:22:58 PM PST 24 Feb 07 04:24:45 PM PST 24 6236253438 ps
T2587 /workspace/coverage/cover_reg_top/46.xbar_random.2487900833 Feb 07 04:17:08 PM PST 24 Feb 07 04:17:33 PM PST 24 642863146 ps
T2588 /workspace/coverage/cover_reg_top/72.xbar_random.1371378476 Feb 07 04:20:46 PM PST 24 Feb 07 04:21:55 PM PST 24 2107200594 ps
T2589 /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.3096679205 Feb 07 04:15:38 PM PST 24 Feb 07 04:15:45 PM PST 24 28229205 ps
T2590 /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.535214024 Feb 07 04:16:20 PM PST 24 Feb 07 04:19:58 PM PST 24 3926507174 ps
T2591 /workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.1858196848 Feb 07 04:11:37 PM PST 24 Feb 07 04:17:16 PM PST 24 7782446440 ps
T2592 /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.4175069247 Feb 07 04:20:56 PM PST 24 Feb 07 04:26:28 PM PST 24 799589958 ps
T2593 /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.1901271669 Feb 07 04:19:11 PM PST 24 Feb 07 04:21:21 PM PST 24 6700687946 ps
T713 /workspace/coverage/cover_reg_top/19.chip_tl_errors.3119012549 Feb 07 04:13:10 PM PST 24 Feb 07 04:16:20 PM PST 24 2976771352 ps
T2594 /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.2196630736 Feb 07 04:16:44 PM PST 24 Feb 07 04:18:28 PM PST 24 6031080649 ps
T2595 /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.1068247937 Feb 07 04:11:43 PM PST 24 Feb 07 04:12:07 PM PST 24 272357507 ps
T2596 /workspace/coverage/cover_reg_top/9.xbar_same_source.1390887655 Feb 07 04:12:11 PM PST 24 Feb 07 04:12:20 PM PST 24 186290392 ps
T2597 /workspace/coverage/cover_reg_top/16.xbar_random.1215030242 Feb 07 04:12:28 PM PST 24 Feb 07 04:13:56 PM PST 24 2161162634 ps
T2598 /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.1885520055 Feb 07 04:24:11 PM PST 24 Feb 07 04:27:36 PM PST 24 11177846756 ps
T2599 /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.2406478412 Feb 07 04:21:14 PM PST 24 Feb 07 04:22:48 PM PST 24 9114010346 ps
T2600 /workspace/coverage/cover_reg_top/46.xbar_access_same_device.864619780 Feb 07 04:17:14 PM PST 24 Feb 07 04:18:22 PM PST 24 1580574807 ps
T2601 /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.2105474051 Feb 07 04:15:46 PM PST 24 Feb 07 04:17:27 PM PST 24 5749350135 ps
T2602 /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.3432392236 Feb 07 04:24:07 PM PST 24 Feb 07 04:24:32 PM PST 24 550004813 ps
T588 /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.3814504882 Feb 07 04:21:33 PM PST 24 Feb 07 04:22:45 PM PST 24 1056513399 ps
T2603 /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.985549781 Feb 07 04:15:06 PM PST 24 Feb 07 04:18:28 PM PST 24 5206184172 ps
T2604 /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.1081881579 Feb 07 04:18:57 PM PST 24 Feb 07 04:19:05 PM PST 24 54957658 ps
T2605 /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.880543106 Feb 07 04:16:36 PM PST 24 Feb 07 04:18:13 PM PST 24 3196428636 ps
T2606 /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.3812765965 Feb 07 04:20:00 PM PST 24 Feb 07 04:21:20 PM PST 24 6926963603 ps
T2607 /workspace/coverage/cover_reg_top/56.xbar_access_same_device.2235632760 Feb 07 04:18:40 PM PST 24 Feb 07 04:19:24 PM PST 24 883941919 ps
T2608 /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.2527794042 Feb 07 04:24:40 PM PST 24 Feb 07 04:28:33 PM PST 24 6369070242 ps
T2609 /workspace/coverage/cover_reg_top/1.xbar_same_source.3231173628 Feb 07 04:11:45 PM PST 24 Feb 07 04:12:33 PM PST 24 1681647058 ps
T2610 /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.2919503217 Feb 07 04:13:11 PM PST 24 Feb 07 04:39:01 PM PST 24 14794275732 ps
T2611 /workspace/coverage/cover_reg_top/12.xbar_same_source.1903084973 Feb 07 04:12:27 PM PST 24 Feb 07 04:13:02 PM PST 24 417767163 ps
T2612 /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.1711645462 Feb 07 04:19:50 PM PST 24 Feb 07 04:22:13 PM PST 24 806199148 ps
T2613 /workspace/coverage/cover_reg_top/69.xbar_stress_all.2241539871 Feb 07 04:20:36 PM PST 24 Feb 07 04:27:36 PM PST 24 5156182528 ps
T2614 /workspace/coverage/cover_reg_top/0.xbar_random.3743773195 Feb 07 04:11:25 PM PST 24 Feb 07 04:11:36 PM PST 24 89654269 ps
T2615 /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.4288436553 Feb 07 04:18:50 PM PST 24 Feb 07 04:22:25 PM PST 24 569813211 ps
T2616 /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.1138312836 Feb 07 04:19:57 PM PST 24 Feb 07 04:20:05 PM PST 24 55344990 ps
T2617 /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.4144543220 Feb 07 04:13:47 PM PST 24 Feb 07 04:29:34 PM PST 24 85071752370 ps
T2618 /workspace/coverage/cover_reg_top/26.xbar_smoke.1734743131 Feb 07 04:13:56 PM PST 24 Feb 07 04:14:04 PM PST 24 136057192 ps
T2619 /workspace/coverage/cover_reg_top/88.xbar_random.2938385153 Feb 07 04:23:35 PM PST 24 Feb 07 04:25:02 PM PST 24 2464433150 ps
T2620 /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.2777404564 Feb 07 04:13:36 PM PST 24 Feb 07 04:24:51 PM PST 24 35806793441 ps
T2621 /workspace/coverage/cover_reg_top/42.xbar_random.777288551 Feb 07 04:16:28 PM PST 24 Feb 07 04:16:58 PM PST 24 805853293 ps
T2622 /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.726938268 Feb 07 04:21:12 PM PST 24 Feb 07 04:21:39 PM PST 24 644462508 ps
T2623 /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.1208596760 Feb 07 04:11:39 PM PST 24 Feb 07 04:12:01 PM PST 24 458106778 ps
T2624 /workspace/coverage/cover_reg_top/19.chip_csr_rw.1667149406 Feb 07 04:13:13 PM PST 24 Feb 07 04:17:49 PM PST 24 3903793655 ps
T2625 /workspace/coverage/cover_reg_top/19.xbar_same_source.3509286440 Feb 07 04:13:10 PM PST 24 Feb 07 04:13:43 PM PST 24 388457482 ps
T2626 /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.3340016879 Feb 07 04:12:27 PM PST 24 Feb 07 04:13:53 PM PST 24 4626285569 ps
T2627 /workspace/coverage/cover_reg_top/63.xbar_stress_all.7850043 Feb 07 04:19:37 PM PST 24 Feb 07 04:23:22 PM PST 24 2344346836 ps
T2628 /workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.3106950202 Feb 07 04:12:20 PM PST 24 Feb 07 04:17:41 PM PST 24 6487282348 ps
T2629 /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.77887392 Feb 07 04:16:53 PM PST 24 Feb 07 04:18:13 PM PST 24 7397927269 ps
T2630 /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.2454279006 Feb 07 04:14:16 PM PST 24 Feb 07 04:14:56 PM PST 24 317851394 ps
T2631 /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.3333450173 Feb 07 04:19:16 PM PST 24 Feb 07 04:19:33 PM PST 24 150968077 ps
T2632 /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.2967708830 Feb 07 04:20:41 PM PST 24 Feb 07 04:21:04 PM PST 24 218860494 ps
T678 /workspace/coverage/cover_reg_top/29.chip_tl_errors.221264843 Feb 07 04:14:23 PM PST 24 Feb 07 04:18:58 PM PST 24 3810597800 ps
T2633 /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.3752500072 Feb 07 04:20:34 PM PST 24 Feb 07 04:21:23 PM PST 24 4191544613 ps
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