| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.37 | 95.45 | 94.67 | 95.51 | 95.45 | 97.57 | 99.58 |
| T2752 | /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.150782893 | Feb 07 04:18:57 PM PST 24 | Feb 07 04:20:26 PM PST 24 | 8141641522 ps | ||
| T2753 | /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.1970646241 | Feb 07 04:21:54 PM PST 24 | Feb 07 04:22:00 PM PST 24 | 51625338 ps | ||
| T2754 | /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.711360199 | Feb 07 04:15:11 PM PST 24 | Feb 07 04:19:51 PM PST 24 | 24566803185 ps | ||
| T2755 | /workspace/coverage/cover_reg_top/81.xbar_random.1761369968 | Feb 07 04:22:09 PM PST 24 | Feb 07 04:22:45 PM PST 24 | 387293124 ps | ||
| T2756 | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.428899679 | Feb 07 04:23:59 PM PST 24 | Feb 07 04:27:23 PM PST 24 | 880443373 ps | ||
| T2757 | /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.2683255863 | Feb 07 04:23:48 PM PST 24 | Feb 07 04:23:54 PM PST 24 | 39759475 ps | ||
| T2758 | /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.234311540 | Feb 07 04:23:39 PM PST 24 | Feb 07 04:35:44 PM PST 24 | 40436428155 ps | ||
| T2759 | /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.3503830330 | Feb 07 04:22:03 PM PST 24 | Feb 07 04:39:24 PM PST 24 | 53403845444 ps | ||
| T2760 | /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.1809005039 | Feb 07 04:14:31 PM PST 24 | Feb 07 04:29:07 PM PST 24 | 79354751145 ps | ||
| T2761 | /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.1971275868 | Feb 07 04:24:13 PM PST 24 | Feb 07 04:43:47 PM PST 24 | 68007274992 ps | ||
| T2762 | /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.3712145803 | Feb 07 04:12:39 PM PST 24 | Feb 07 04:13:38 PM PST 24 | 1327572868 ps | ||
| T2763 | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.2313635051 | Feb 07 04:19:51 PM PST 24 | Feb 07 04:19:59 PM PST 24 | 52816673 ps | ||
| T2764 | /workspace/coverage/cover_reg_top/79.xbar_access_same_device.3628104654 | Feb 07 04:21:52 PM PST 24 | Feb 07 04:22:12 PM PST 24 | 259329320 ps | ||
| T2765 | /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.2272378522 | Feb 07 04:18:33 PM PST 24 | Feb 07 04:20:55 PM PST 24 | 7914424656 ps | ||
| T2766 | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.1715262337 | Feb 07 04:11:50 PM PST 24 | Feb 07 04:12:48 PM PST 24 | 185309928 ps | ||
| T2767 | /workspace/coverage/cover_reg_top/25.xbar_smoke.701287971 | Feb 07 04:13:57 PM PST 24 | Feb 07 04:14:07 PM PST 24 | 200538663 ps | ||
| T2768 | /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.353144998 | Feb 07 04:20:54 PM PST 24 | Feb 07 04:21:32 PM PST 24 | 386743746 ps | ||
| T2769 | /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.2744249799 | Feb 07 04:23:36 PM PST 24 | Feb 07 04:23:52 PM PST 24 | 120775846 ps | ||
| T2770 | /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.4216209469 | Feb 07 04:12:10 PM PST 24 | Feb 07 04:13:39 PM PST 24 | 8449458983 ps | ||
| T2771 | /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.1215970859 | Feb 07 04:16:18 PM PST 24 | Feb 07 04:18:00 PM PST 24 | 9543430452 ps | ||
| T2772 | /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.2577478573 | Feb 07 04:21:36 PM PST 24 | Feb 07 04:21:51 PM PST 24 | 232897724 ps | ||
| T2773 | /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.1226518603 | Feb 07 04:23:35 PM PST 24 | Feb 07 04:24:08 PM PST 24 | 338236670 ps | ||
| T2774 | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.496664871 | Feb 07 04:18:15 PM PST 24 | Feb 07 04:29:25 PM PST 24 | 6612995063 ps | ||
| T2775 | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.2858684974 | Feb 07 04:24:11 PM PST 24 | Feb 07 04:30:01 PM PST 24 | 3509313902 ps | ||
| T2776 | /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.123109564 | Feb 07 04:17:15 PM PST 24 | Feb 07 04:18:20 PM PST 24 | 3952605899 ps | ||
| T2777 | /workspace/coverage/cover_reg_top/37.xbar_access_same_device.3437789276 | Feb 07 04:15:52 PM PST 24 | Feb 07 04:16:08 PM PST 24 | 265603462 ps | ||
| T2778 | /workspace/coverage/cover_reg_top/96.xbar_same_source.2911183350 | Feb 07 04:24:27 PM PST 24 | Feb 07 04:24:57 PM PST 24 | 380635833 ps | ||
| T2779 | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.2143319271 | Feb 07 04:23:38 PM PST 24 | Feb 07 04:32:37 PM PST 24 | 8622255286 ps | ||
| T2780 | /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.316446559 | Feb 07 04:22:35 PM PST 24 | Feb 07 04:50:00 PM PST 24 | 92512705364 ps | ||
| T2781 | /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.1675269368 | Feb 07 04:24:21 PM PST 24 | Feb 07 04:25:00 PM PST 24 | 970356495 ps | ||
| T2782 | /workspace/coverage/cover_reg_top/20.xbar_access_same_device.1073925285 | Feb 07 04:13:20 PM PST 24 | Feb 07 04:14:47 PM PST 24 | 2361365868 ps | ||
| T2783 | /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.3420731244 | Feb 07 04:14:14 PM PST 24 | Feb 07 04:15:42 PM PST 24 | 8177709622 ps | ||
| T2784 | /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.3624089513 | Feb 07 04:20:51 PM PST 24 | Feb 07 04:39:54 PM PST 24 | 62171360811 ps | ||
| T2785 | /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.3902044798 | Feb 07 04:11:47 PM PST 24 | Feb 07 04:50:36 PM PST 24 | 142088914239 ps | ||
| T2786 | /workspace/coverage/cover_reg_top/31.xbar_smoke.362034386 | Feb 07 04:14:45 PM PST 24 | Feb 07 04:14:54 PM PST 24 | 218347937 ps | ||
| T2787 | /workspace/coverage/cover_reg_top/51.xbar_same_source.1552434060 | Feb 07 04:18:03 PM PST 24 | Feb 07 04:18:22 PM PST 24 | 222754383 ps | ||
| T2788 | /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.932848576 | Feb 07 04:17:57 PM PST 24 | Feb 07 04:56:56 PM PST 24 | 123162965658 ps | ||
| T2789 | /workspace/coverage/cover_reg_top/56.xbar_smoke.2870558028 | Feb 07 04:18:42 PM PST 24 | Feb 07 04:18:49 PM PST 24 | 52996535 ps | ||
| T2790 | /workspace/coverage/cover_reg_top/73.xbar_smoke.348473311 | Feb 07 04:20:53 PM PST 24 | Feb 07 04:20:59 PM PST 24 | 49740745 ps | ||
| T2791 | /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.1079982698 | Feb 07 04:22:58 PM PST 24 | Feb 07 04:23:22 PM PST 24 | 191782298 ps | ||
| T2792 | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.2240804084 | Feb 07 04:12:22 PM PST 24 | Feb 07 04:13:30 PM PST 24 | 940398443 ps | ||
| T2793 | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.1892042523 | Feb 07 04:15:47 PM PST 24 | Feb 07 04:23:12 PM PST 24 | 4037407147 ps | ||
| T2794 | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.3668441302 | Feb 07 04:11:39 PM PST 24 | Feb 07 04:12:20 PM PST 24 | 737036261 ps | ||
| T2795 | /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.2423587790 | Feb 07 04:15:06 PM PST 24 | Feb 07 04:15:12 PM PST 24 | 36237198 ps | ||
| T2796 | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.2087036141 | Feb 07 04:17:07 PM PST 24 | Feb 07 04:18:39 PM PST 24 | 2520679049 ps | ||
| T2797 | /workspace/coverage/cover_reg_top/39.xbar_error_random.2410416499 | Feb 07 04:16:08 PM PST 24 | Feb 07 04:16:27 PM PST 24 | 211419865 ps | ||
| T2798 | /workspace/coverage/cover_reg_top/57.xbar_random.1114241055 | Feb 07 04:19:07 PM PST 24 | Feb 07 04:19:15 PM PST 24 | 82046239 ps | ||
| T2799 | /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.2167562561 | Feb 07 04:14:24 PM PST 24 | Feb 07 04:14:51 PM PST 24 | 231129151 ps | ||
| T2800 | /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.592982140 | Feb 07 04:13:12 PM PST 24 | Feb 07 04:18:30 PM PST 24 | 18065943318 ps | ||
| T2801 | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.4154758061 | Feb 07 04:11:39 PM PST 24 | Feb 07 04:18:59 PM PST 24 | 15590140547 ps | ||
| T2802 | /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.2460887717 | Feb 07 04:23:26 PM PST 24 | Feb 07 04:23:34 PM PST 24 | 48483490 ps | ||
| T2803 | /workspace/coverage/cover_reg_top/90.xbar_smoke.1326478794 | Feb 07 04:23:39 PM PST 24 | Feb 07 04:23:49 PM PST 24 | 218695499 ps | ||
| T2804 | /workspace/coverage/cover_reg_top/93.xbar_random.3137600754 | Feb 07 04:23:54 PM PST 24 | Feb 07 04:24:34 PM PST 24 | 1161649440 ps | ||
| T2805 | /workspace/coverage/cover_reg_top/53.xbar_access_same_device.1252337862 | Feb 07 04:18:15 PM PST 24 | Feb 07 04:19:03 PM PST 24 | 1094177030 ps | ||
| T2806 | /workspace/coverage/cover_reg_top/85.xbar_error_random.3998511129 | Feb 07 04:22:56 PM PST 24 | Feb 07 04:24:17 PM PST 24 | 2012267974 ps | ||
| T2807 | /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.4079989292 | Feb 07 04:15:11 PM PST 24 | Feb 07 04:15:31 PM PST 24 | 148590692 ps | ||
| T2808 | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.958347637 | Feb 07 04:12:03 PM PST 24 | Feb 07 04:24:09 PM PST 24 | 14152437266 ps | ||
| T2809 | /workspace/coverage/cover_reg_top/1.xbar_smoke.1945876820 | Feb 07 04:11:30 PM PST 24 | Feb 07 04:11:38 PM PST 24 | 135053226 ps | ||
| T2810 | /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.4042086391 | Feb 07 04:22:18 PM PST 24 | Feb 07 04:22:34 PM PST 24 | 129633240 ps | ||
| T2811 | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.4108098967 | Feb 07 04:12:26 PM PST 24 | Feb 07 04:24:18 PM PST 24 | 62117266454 ps | ||
| T2812 | /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.3722238459 | Feb 07 04:11:38 PM PST 24 | Feb 07 04:39:59 PM PST 24 | 15338732130 ps | ||
| T2813 | /workspace/coverage/cover_reg_top/55.xbar_random.3992287067 | Feb 07 04:18:32 PM PST 24 | Feb 07 04:19:00 PM PST 24 | 720553189 ps | ||
| T2814 | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.3015151079 | Feb 07 04:19:17 PM PST 24 | Feb 07 04:19:56 PM PST 24 | 491906135 ps | ||
| T2815 | /workspace/coverage/cover_reg_top/8.xbar_stress_all.2061466204 | Feb 07 04:12:09 PM PST 24 | Feb 07 04:16:03 PM PST 24 | 6790636303 ps | ||
| T2816 | /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.3768713644 | Feb 07 04:17:38 PM PST 24 | Feb 07 04:18:03 PM PST 24 | 216707689 ps | ||
| T2817 | /workspace/coverage/cover_reg_top/5.xbar_random.1956194413 | Feb 07 04:11:47 PM PST 24 | Feb 07 04:11:57 PM PST 24 | 90785242 ps | ||
| T2818 | /workspace/coverage/cover_reg_top/76.xbar_error_random.170119947 | Feb 07 04:21:27 PM PST 24 | Feb 07 04:22:10 PM PST 24 | 1254461900 ps | ||
| T2819 | /workspace/coverage/cover_reg_top/30.xbar_smoke.975507591 | Feb 07 04:14:31 PM PST 24 | Feb 07 04:14:40 PM PST 24 | 45637009 ps | ||
| T2820 | /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.4261614241 | Feb 07 04:22:46 PM PST 24 | Feb 07 04:23:50 PM PST 24 | 5738371104 ps | ||
| T2821 | /workspace/coverage/cover_reg_top/46.xbar_smoke.481906561 | Feb 07 04:17:10 PM PST 24 | Feb 07 04:17:19 PM PST 24 | 169273065 ps | ||
| T2822 | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.3962318314 | Feb 07 04:17:39 PM PST 24 | Feb 07 04:22:12 PM PST 24 | 7468077888 ps | ||
| T2823 | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.2604780849 | Feb 07 04:19:06 PM PST 24 | Feb 07 04:19:53 PM PST 24 | 1761462027 ps | ||
| T2824 | /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.4241262280 | Feb 07 04:18:39 PM PST 24 | Feb 07 04:19:24 PM PST 24 | 1061101301 ps | ||
| T679 | /workspace/coverage/cover_reg_top/1.chip_tl_errors.4257135119 | Feb 07 04:11:32 PM PST 24 | Feb 07 04:14:47 PM PST 24 | 3554533767 ps | ||
| T2825 | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.1532424816 | Feb 07 04:25:03 PM PST 24 | Feb 07 04:25:44 PM PST 24 | 329615465 ps | ||
| T2826 | /workspace/coverage/cover_reg_top/72.xbar_error_random.1306986883 | Feb 07 04:20:58 PM PST 24 | Feb 07 04:21:09 PM PST 24 | 98212225 ps | ||
| T2827 | /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.280310961 | Feb 07 04:23:11 PM PST 24 | Feb 07 04:24:13 PM PST 24 | 1297265775 ps | ||
| T2828 | /workspace/coverage/cover_reg_top/91.xbar_same_source.3869960175 | Feb 07 04:23:45 PM PST 24 | Feb 07 04:24:03 PM PST 24 | 553439839 ps | ||
| T2829 | /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.1187200900 | Feb 07 04:24:56 PM PST 24 | Feb 07 04:26:35 PM PST 24 | 8805338966 ps | ||
| T2830 | /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.1150395132 | Feb 07 04:15:54 PM PST 24 | Feb 07 04:16:07 PM PST 24 | 94372834 ps | ||
| T2831 | /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.2380378045 | Feb 07 04:11:46 PM PST 24 | Feb 07 04:39:30 PM PST 24 | 95008745411 ps | ||
| T2832 | /workspace/coverage/cover_reg_top/81.xbar_access_same_device.1095392107 | Feb 07 04:22:08 PM PST 24 | Feb 07 04:22:44 PM PST 24 | 890142562 ps | ||
| T2833 | /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.2992078832 | Feb 07 04:22:33 PM PST 24 | Feb 07 04:24:07 PM PST 24 | 5445690002 ps | ||
| T2834 | /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.1301132070 | Feb 07 04:22:19 PM PST 24 | Feb 07 04:22:35 PM PST 24 | 141608905 ps | ||
| T2835 | /workspace/coverage/cover_reg_top/33.xbar_smoke.2470650051 | Feb 07 04:15:06 PM PST 24 | Feb 07 04:15:13 PM PST 24 | 41377434 ps | ||
| T2836 | /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.1838617959 | Feb 07 04:19:07 PM PST 24 | Feb 07 04:19:26 PM PST 24 | 390098073 ps | ||
| T2837 | /workspace/coverage/cover_reg_top/27.xbar_random.3394874202 | Feb 07 04:14:18 PM PST 24 | Feb 07 04:15:15 PM PST 24 | 1783159067 ps | ||
| T2838 | /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.970996075 | Feb 07 04:15:56 PM PST 24 | Feb 07 04:18:05 PM PST 24 | 6897603203 ps | ||
| T2839 | /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.3816808891 | Feb 07 04:21:36 PM PST 24 | Feb 07 04:38:05 PM PST 24 | 53496882120 ps | ||
| T2840 | /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.3066458161 | Feb 07 04:22:47 PM PST 24 | Feb 07 04:24:28 PM PST 24 | 5375629209 ps | ||
| T2841 | /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.2337866719 | Feb 07 04:12:06 PM PST 24 | Feb 07 04:31:58 PM PST 24 | 69767443692 ps | ||
| T2842 | /workspace/coverage/cover_reg_top/62.xbar_same_source.1181098409 | Feb 07 04:19:31 PM PST 24 | Feb 07 04:20:10 PM PST 24 | 1240953240 ps | ||
| T2843 | /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.494046087 | Feb 07 04:24:07 PM PST 24 | Feb 07 04:25:40 PM PST 24 | 5575433522 ps | ||
| T2844 | /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.2107031946 | Feb 07 04:20:20 PM PST 24 | Feb 07 04:29:46 PM PST 24 | 34003175984 ps | ||
| T2845 | /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.497797550 | Feb 07 04:21:22 PM PST 24 | Feb 07 04:37:20 PM PST 24 | 49033031141 ps | ||
| T2846 | /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.125809825 | Feb 07 04:12:11 PM PST 24 | Feb 07 04:12:41 PM PST 24 | 259855001 ps | ||
| T2847 | /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.2745739341 | Feb 07 04:12:33 PM PST 24 | Feb 07 04:13:00 PM PST 24 | 222281330 ps | ||
| T2848 | /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.288823488 | Feb 07 04:14:14 PM PST 24 | Feb 07 04:19:14 PM PST 24 | 26511407456 ps | ||
| T2849 | /workspace/coverage/cover_reg_top/48.xbar_random.2639501050 | Feb 07 04:17:23 PM PST 24 | Feb 07 04:17:50 PM PST 24 | 772255425 ps | ||
| T2850 | /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.4126624710 | Feb 07 04:15:12 PM PST 24 | Feb 07 04:15:42 PM PST 24 | 328610017 ps | ||
| T2851 | /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.1911856979 | Feb 07 04:11:49 PM PST 24 | Feb 07 04:28:18 PM PST 24 | 97632228045 ps | ||
| T2852 | /workspace/coverage/cover_reg_top/2.xbar_error_random.2892419487 | Feb 07 04:11:44 PM PST 24 | Feb 07 04:12:39 PM PST 24 | 1599026139 ps | ||
| T2853 | /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.3245232870 | Feb 07 04:19:18 PM PST 24 | Feb 07 04:30:03 PM PST 24 | 55765363926 ps | ||
| T2854 | /workspace/coverage/cover_reg_top/98.xbar_stress_all.3994099826 | Feb 07 04:24:59 PM PST 24 | Feb 07 04:27:17 PM PST 24 | 3583090938 ps | ||
| T2855 | /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.17102055 | Feb 07 04:14:52 PM PST 24 | Feb 07 04:15:45 PM PST 24 | 1272278018 ps | ||
| T2856 | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.3636477604 | Feb 07 04:17:52 PM PST 24 | Feb 07 04:18:12 PM PST 24 | 382581306 ps | ||
| T2857 | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.764959589 | Feb 07 04:23:38 PM PST 24 | Feb 07 04:24:27 PM PST 24 | 521708954 ps | ||
| T2858 | /workspace/coverage/cover_reg_top/71.xbar_error_random.4058561853 | Feb 07 04:20:44 PM PST 24 | Feb 07 04:21:10 PM PST 24 | 674166137 ps | ||
| T2859 | /workspace/coverage/cover_reg_top/94.xbar_error_random.3950144146 | Feb 07 04:24:17 PM PST 24 | Feb 07 04:25:40 PM PST 24 | 2449916297 ps | ||
| T2860 | /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.3559656598 | Feb 07 04:13:14 PM PST 24 | Feb 07 04:31:16 PM PST 24 | 105033012346 ps | ||
| T2861 | /workspace/coverage/cover_reg_top/85.xbar_access_same_device.2774191575 | Feb 07 04:23:02 PM PST 24 | Feb 07 04:24:38 PM PST 24 | 2537674035 ps | ||
| T2862 | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.3559270457 | Feb 07 04:20:40 PM PST 24 | Feb 07 04:21:21 PM PST 24 | 1055737430 ps | ||
| T2863 | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.1075635539 | Feb 07 04:23:16 PM PST 24 | Feb 07 04:23:32 PM PST 24 | 40253840 ps | ||
| T2864 | /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.2063134924 | Feb 07 04:18:29 PM PST 24 | Feb 07 04:18:36 PM PST 24 | 40432804 ps | ||
| T2865 | /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.2031098238 | Feb 07 04:21:14 PM PST 24 | Feb 07 04:36:43 PM PST 24 | 51042938855 ps | ||
| T2866 | /workspace/coverage/cover_reg_top/28.xbar_access_same_device.14100955 | Feb 07 04:14:24 PM PST 24 | Feb 07 04:16:39 PM PST 24 | 3373395328 ps | ||
| T2867 | /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.2988420741 | Feb 07 04:19:36 PM PST 24 | Feb 07 04:20:31 PM PST 24 | 1246728345 ps | ||
| T2868 | /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.1199371424 | Feb 07 04:20:59 PM PST 24 | Feb 07 04:35:06 PM PST 24 | 77973989909 ps | ||
| T2869 | /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.3097208637 | Feb 07 04:11:56 PM PST 24 | Feb 07 04:29:50 PM PST 24 | 105836046923 ps | ||
| T2870 | /workspace/coverage/cover_reg_top/2.xbar_same_source.1873948998 | Feb 07 04:12:01 PM PST 24 | Feb 07 04:13:13 PM PST 24 | 2478195841 ps | ||
| T2871 | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.4114419889 | Feb 07 04:21:30 PM PST 24 | Feb 07 04:22:27 PM PST 24 | 219174818 ps | ||
| T2872 | /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.2435173935 | Feb 07 04:12:49 PM PST 24 | Feb 07 04:13:27 PM PST 24 | 469044403 ps | ||
| T2873 | /workspace/coverage/cover_reg_top/83.xbar_smoke.1775295301 | Feb 07 04:22:14 PM PST 24 | Feb 07 04:22:23 PM PST 24 | 169992605 ps | ||
| T2874 | /workspace/coverage/cover_reg_top/33.xbar_error_random.709473432 | Feb 07 04:15:07 PM PST 24 | Feb 07 04:15:51 PM PST 24 | 581826006 ps | ||
| T2875 | /workspace/coverage/cover_reg_top/49.xbar_random.2967394405 | Feb 07 04:17:36 PM PST 24 | Feb 07 04:18:13 PM PST 24 | 861292380 ps |
| Test location | /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.3456443508 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 28701524385 ps |
| CPU time | 4184.3 seconds |
| Started | Feb 07 04:12:03 PM PST 24 |
| Finished | Feb 07 05:21:48 PM PST 24 |
| Peak memory | 580216 kb |
| Host | smart-ad638e1f-a346-4b8f-99ea-425848634979 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456443508 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 10.chip_same_csr_outstanding.3456443508 |
| Directory | /workspace/10.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all.186448094 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 2467846687 ps |
| CPU time | 228.95 seconds |
| Started | Feb 07 04:16:40 PM PST 24 |
| Finished | Feb 07 04:20:29 PM PST 24 |
| Peak memory | 556664 kb |
| Host | smart-964fbd5f-4f40-403f-b0ae-6039c4c94bc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186448094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.186448094 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2760087121 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5534617264 ps |
| CPU time | 321.31 seconds |
| Started | Feb 07 04:11:23 PM PST 24 |
| Finished | Feb 07 04:16:45 PM PST 24 |
| Peak memory | 633084 kb |
| Host | smart-1d695b6a-8cd1-4861-b8f3-14abd280036c |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760087121 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 9.chip_padctrl_attributes.2760087121 |
| Directory | /workspace/9.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.1173622708 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 160030378535 ps |
| CPU time | 3150.12 seconds |
| Started | Feb 07 04:13:39 PM PST 24 |
| Finished | Feb 07 05:06:10 PM PST 24 |
| Peak memory | 556800 kb |
| Host | smart-505bddb3-a815-442d-8509-807209fb5da7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173622708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_ device_slow_rsp.1173622708 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/81.chip_sw_all_escalation_resets.2289401076 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 5468908880 ps |
| CPU time | 595.44 seconds |
| Started | Feb 07 05:03:57 PM PST 24 |
| Finished | Feb 07 05:13:53 PM PST 24 |
| Peak memory | 633864 kb |
| Host | smart-23694ea8-adcc-45ef-bfe4-d94e12d3a6cc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2289401076 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.2289401076 |
| Directory | /workspace/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.2329164370 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 145104104508 ps |
| CPU time | 2692.06 seconds |
| Started | Feb 07 04:23:47 PM PST 24 |
| Finished | Feb 07 05:08:39 PM PST 24 |
| Peak memory | 556576 kb |
| Host | smart-694fc149-3d5c-4af6-a9c7-fc9d33a55faa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329164370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_ device_slow_rsp.2329164370 |
| Directory | /workspace/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.218418411 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 112304091783 ps |
| CPU time | 2300.97 seconds |
| Started | Feb 07 04:25:08 PM PST 24 |
| Finished | Feb 07 05:03:34 PM PST 24 |
| Peak memory | 556592 kb |
| Host | smart-de848bf9-bece-4f30-95f0-114f0689fdaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218418411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_d evice_slow_rsp.218418411 |
| Directory | /workspace/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_0.981368724 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 6057875890 ps |
| CPU time | 1311.84 seconds |
| Started | Feb 07 04:53:56 PM PST 24 |
| Finished | Feb 07 05:15:49 PM PST 24 |
| Peak memory | 601048 kb |
| Host | smart-5fcf7789-1899-4798-8169-df922a0e1ef4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981368724 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_plic_all_irqs_0.981368724 |
| Directory | /workspace/2.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.3830652745 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 11788091798 ps |
| CPU time | 384.02 seconds |
| Started | Feb 07 04:12:37 PM PST 24 |
| Finished | Feb 07 04:19:02 PM PST 24 |
| Peak memory | 556904 kb |
| Host | smart-5bce8819-dcf2-4ed2-ad24-8cdd88fa3304 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830652745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.3830652745 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.4096415303 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 31459910375 ps |
| CPU time | 2419.25 seconds |
| Started | Feb 07 04:39:16 PM PST 24 |
| Finished | Feb 07 05:19:36 PM PST 24 |
| Peak memory | 606960 kb |
| Host | smart-2508d0d1-1cd9-43d7-a485-ab38cb461a5c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4096415303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testun locks.4096415303 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1406908671 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 3813622648 ps |
| CPU time | 364.85 seconds |
| Started | Feb 07 04:32:34 PM PST 24 |
| Finished | Feb 07 04:38:40 PM PST 24 |
| Peak memory | 600960 kb |
| Host | smart-810ef20c-49c3-42eb-9647-4aa94c14cf8a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406 908671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.1406908671 |
| Directory | /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.815834211 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 4169430216 ps |
| CPU time | 363.17 seconds |
| Started | Feb 07 04:37:17 PM PST 24 |
| Finished | Feb 07 04:43:21 PM PST 24 |
| Peak memory | 601380 kb |
| Host | smart-3282181a-9367-4d12-be95-e0b68721c714 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81 5834211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.815834211 |
| Directory | /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.3188497465 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 112824523764 ps |
| CPU time | 2173.38 seconds |
| Started | Feb 07 04:19:17 PM PST 24 |
| Finished | Feb 07 04:55:31 PM PST 24 |
| Peak memory | 556848 kb |
| Host | smart-e9c95f50-fd03-4795-9ee2-35553bfdb6ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188497465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_ device_slow_rsp.3188497465 |
| Directory | /workspace/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3529801735 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 3061752110 ps |
| CPU time | 238.59 seconds |
| Started | Feb 07 04:36:14 PM PST 24 |
| Finished | Feb 07 04:40:13 PM PST 24 |
| Peak memory | 599156 kb |
| Host | smart-6ade5df0-eeaf-4e08-9881-ea24d97ac97e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3529801735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.3529801735 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.4197743158 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 100200329647 ps |
| CPU time | 1800.25 seconds |
| Started | Feb 07 04:19:07 PM PST 24 |
| Finished | Feb 07 04:49:09 PM PST 24 |
| Peak memory | 556576 kb |
| Host | smart-5b7c0bce-5009-4742-8093-333be1ed7404 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197743158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_ device_slow_rsp.4197743158 |
| Directory | /workspace/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_20.3958107752 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 4857835404 ps |
| CPU time | 807.09 seconds |
| Started | Feb 07 04:44:47 PM PST 24 |
| Finished | Feb 07 04:58:15 PM PST 24 |
| Peak memory | 600688 kb |
| Host | smart-e7a20216-1ed9-4887-9f3b-0614f1b92e8b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958107752 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_20.3958107752 |
| Directory | /workspace/1.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.3568095306 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 117561237201 ps |
| CPU time | 2228.39 seconds |
| Started | Feb 07 04:21:38 PM PST 24 |
| Finished | Feb 07 04:58:49 PM PST 24 |
| Peak memory | 555832 kb |
| Host | smart-67ed4e2c-9096-43a7-b096-0531bcff94e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568095306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_ device_slow_rsp.3568095306 |
| Directory | /workspace/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_csr_rw.851706112 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 20688953915 ps |
| CPU time | 2357.04 seconds |
| Started | Feb 07 04:36:54 PM PST 24 |
| Finished | Feb 07 05:16:12 PM PST 24 |
| Peak memory | 593156 kb |
| Host | smart-210fdc15-580c-4911-b8c0-77f22628ae86 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851706112 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.ch ip_jtag_csr_rw.851706112 |
| Directory | /workspace/1.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_tl_errors.2518557783 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 4026068962 ps |
| CPU time | 275.91 seconds |
| Started | Feb 07 04:12:01 PM PST 24 |
| Finished | Feb 07 04:16:37 PM PST 24 |
| Peak memory | 580304 kb |
| Host | smart-e0f100a9-51c7-498a-a47d-b90d508c5788 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518557783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.2518557783 |
| Directory | /workspace/3.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.222208046 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 21810353580 ps |
| CPU time | 1430.63 seconds |
| Started | Feb 07 04:46:00 PM PST 24 |
| Finished | Feb 07 05:09:52 PM PST 24 |
| Peak memory | 601808 kb |
| Host | smart-f3422f7b-3019-4c9c-8195-414061a51023 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 222208046 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.222208046 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1578369704 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 103246356495 ps |
| CPU time | 1813.28 seconds |
| Started | Feb 07 04:11:42 PM PST 24 |
| Finished | Feb 07 04:41:56 PM PST 24 |
| Peak memory | 556820 kb |
| Host | smart-0ffdde29-37e0-4148-be69-db4147c1fe07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578369704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_d evice_slow_rsp.1578369704 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all.1245162775 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 3374106257 ps |
| CPU time | 283.9 seconds |
| Started | Feb 07 04:11:51 PM PST 24 |
| Finished | Feb 07 04:16:35 PM PST 24 |
| Peak memory | 556880 kb |
| Host | smart-fafb992e-4085-4a2e-9e39-54ea9de899f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245162775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.1245162775 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/83.chip_sw_all_escalation_resets.1083344786 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4775442752 ps |
| CPU time | 516.97 seconds |
| Started | Feb 07 05:04:07 PM PST 24 |
| Finished | Feb 07 05:12:45 PM PST 24 |
| Peak memory | 635228 kb |
| Host | smart-10b3dff4-630e-4767-b10b-7ac63f5e9498 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1083344786 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.1083344786 |
| Directory | /workspace/83.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_boot_mode.649086994 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 2590111268 ps |
| CPU time | 575.42 seconds |
| Started | Feb 07 04:34:35 PM PST 24 |
| Finished | Feb 07 04:44:11 PM PST 24 |
| Peak memory | 600692 kb |
| Host | smart-8219906a-bc10-4158-a3cd-35deac918f76 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649086994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_b oot_mode.649086994 |
| Directory | /workspace/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_10.4035493611 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 3515074544 ps |
| CPU time | 715.07 seconds |
| Started | Feb 07 04:43:49 PM PST 24 |
| Finished | Feb 07 04:55:47 PM PST 24 |
| Peak memory | 600672 kb |
| Host | smart-47a36d47-13bb-4a6e-a689-47e548ddbc3e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035493611 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_10.4035493611 |
| Directory | /workspace/1.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.4052992083 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 94089288452 ps |
| CPU time | 1748.58 seconds |
| Started | Feb 07 04:21:21 PM PST 24 |
| Finished | Feb 07 04:50:32 PM PST 24 |
| Peak memory | 555720 kb |
| Host | smart-d4f9a8d9-c4da-482e-800a-3c0d4a70b503 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052992083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_ device_slow_rsp.4052992083 |
| Directory | /workspace/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_csr_rw.2638438601 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 19971997158 ps |
| CPU time | 2726.71 seconds |
| Started | Feb 07 04:27:10 PM PST 24 |
| Finished | Feb 07 05:12:38 PM PST 24 |
| Peak memory | 593068 kb |
| Host | smart-7202b2dd-fddc-44d5-b348-61a74b8b2ae7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638438601 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_jtag_csr_rw.2638438601 |
| Directory | /workspace/0.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.1766525595 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 6892476055 ps |
| CPU time | 1015.98 seconds |
| Started | Feb 07 04:22:12 PM PST 24 |
| Finished | Feb 07 04:39:09 PM PST 24 |
| Peak memory | 558568 kb |
| Host | smart-eae44ae9-9cb8-46e1-8a28-8714291b5d3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766525595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all _with_rand_reset.1766525595 |
| Directory | /workspace/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2206961865 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 4943305062 ps |
| CPU time | 546.36 seconds |
| Started | Feb 07 04:35:35 PM PST 24 |
| Finished | Feb 07 04:44:42 PM PST 24 |
| Peak memory | 600644 kb |
| Host | smart-38ce160a-7326-4824-a9ff-81c11f73a404 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22069618 65 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2206961865 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.596636245 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 71668981036 ps |
| CPU time | 794.14 seconds |
| Started | Feb 07 04:12:24 PM PST 24 |
| Finished | Feb 07 04:25:42 PM PST 24 |
| Peak memory | 555376 kb |
| Host | smart-2a2cdb15-9e8d-448f-b9c7-682097f5cf93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596636245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.596636245 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.462096618 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 59430157036 ps |
| CPU time | 10739.6 seconds |
| Started | Feb 07 04:38:13 PM PST 24 |
| Finished | Feb 07 07:37:15 PM PST 24 |
| Peak memory | 614272 kb |
| Host | smart-aca05e20-d6ec-430c-b7d4-0f62d8e3c004 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=462096618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.462096618 |
| Directory | /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2572393311 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 6276068720 ps |
| CPU time | 1023.85 seconds |
| Started | Feb 07 04:36:15 PM PST 24 |
| Finished | Feb 07 04:53:19 PM PST 24 |
| Peak memory | 601240 kb |
| Host | smart-f887ccd9-8474-4da8-9518-c3bf08aa794b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25723933 11 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.2572393311 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3387360865 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 11337447192 ps |
| CPU time | 1312.33 seconds |
| Started | Feb 07 04:39:37 PM PST 24 |
| Finished | Feb 07 05:01:30 PM PST 24 |
| Peak memory | 602672 kb |
| Host | smart-a285f903-d840-4ec8-9cf0-39a9a2f7269f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387360865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.3387360865 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3215746065 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3141328459 ps |
| CPU time | 241.13 seconds |
| Started | Feb 07 04:37:27 PM PST 24 |
| Finished | Feb 07 04:41:29 PM PST 24 |
| Peak memory | 600688 kb |
| Host | smart-9a9826db-f11e-48ec-ae77-554510bf1123 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215 746065 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.3215746065 |
| Directory | /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.4010163059 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 44582641475 ps |
| CPU time | 5051.16 seconds |
| Started | Feb 07 04:31:45 PM PST 24 |
| Finished | Feb 07 05:55:57 PM PST 24 |
| Peak memory | 615336 kb |
| Host | smart-9b3c3341-68d8-4fb5-b9b0-2afa4cd00b28 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4010163059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.4010163059 |
| Directory | /workspace/0.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.615653621 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 6127283488 ps |
| CPU time | 575.18 seconds |
| Started | Feb 07 04:37:08 PM PST 24 |
| Finished | Feb 07 04:46:44 PM PST 24 |
| Peak memory | 600956 kb |
| Host | smart-dc6bce53-4ff0-4bf1-b766-6fc966622ebf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 615653621 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.615653621 |
| Directory | /workspace/0.chip_sw_otp_ctrl_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.539121416 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 6545633464 ps |
| CPU time | 1522.05 seconds |
| Started | Feb 07 04:50:11 PM PST 24 |
| Finished | Feb 07 05:15:34 PM PST 24 |
| Peak memory | 601900 kb |
| Host | smart-59f30b7b-e856-473b-8c6d-5e1e24145c6a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539121416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_toggle.539121416 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/cover_reg_top/25.chip_tl_errors.1332501082 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 3564463648 ps |
| CPU time | 273.03 seconds |
| Started | Feb 07 04:13:56 PM PST 24 |
| Finished | Feb 07 04:18:30 PM PST 24 |
| Peak memory | 580276 kb |
| Host | smart-8bdcb788-87c9-4fcf-8c92-8b333b288572 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332501082 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.1332501082 |
| Directory | /workspace/25.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2208020802 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 13735522296 ps |
| CPU time | 3858.34 seconds |
| Started | Feb 07 04:34:49 PM PST 24 |
| Finished | Feb 07 05:39:08 PM PST 24 |
| Peak memory | 601672 kb |
| Host | smart-40dff683-2339-49b3-868b-cb80141e22f8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22080 20802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.2208020802 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2461677065 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 4619778951 ps |
| CPU time | 584.98 seconds |
| Started | Feb 07 04:11:40 PM PST 24 |
| Finished | Feb 07 04:21:25 PM PST 24 |
| Peak memory | 559436 kb |
| Host | smart-6be40224-50fd-4110-8dbb-1974dc69e8a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461677065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_ with_rand_reset.2461677065 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_retention.2373467753 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4497713294 ps |
| CPU time | 319.21 seconds |
| Started | Feb 07 04:33:41 PM PST 24 |
| Finished | Feb 07 04:39:02 PM PST 24 |
| Peak memory | 602296 kb |
| Host | smart-9d180f26-cea8-45de-8955-039f14008125 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373467753 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.2373467753 |
| Directory | /workspace/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_testunlock0.2951785623 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 8700234526 ps |
| CPU time | 448.59 seconds |
| Started | Feb 07 04:56:59 PM PST 24 |
| Finished | Feb 07 05:04:29 PM PST 24 |
| Peak memory | 610344 kb |
| Host | smart-55a80468-38f8-4016-b699-a20da0ec7d16 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2951785623 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.2951785623 |
| Directory | /workspace/4.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/65.chip_sw_all_escalation_resets.1556584701 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 4740689758 ps |
| CPU time | 611.37 seconds |
| Started | Feb 07 05:04:23 PM PST 24 |
| Finished | Feb 07 05:14:36 PM PST 24 |
| Peak memory | 636224 kb |
| Host | smart-221ceb87-82a0-49a7-9388-e1460aeac1f9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1556584701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.1556584701 |
| Directory | /workspace/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2864398725 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 3793672848 ps |
| CPU time | 361.04 seconds |
| Started | Feb 07 05:05:09 PM PST 24 |
| Finished | Feb 07 05:11:14 PM PST 24 |
| Peak memory | 633888 kb |
| Host | smart-4016b9c3-a897-4cfe-b170-727d4561e938 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864398725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2864398725 |
| Directory | /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all.903852922 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 20817049418 ps |
| CPU time | 889.65 seconds |
| Started | Feb 07 04:21:22 PM PST 24 |
| Finished | Feb 07 04:36:13 PM PST 24 |
| Peak memory | 558296 kb |
| Host | smart-e3901823-e81a-42bf-a85a-f08b820c1d7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903852922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.903852922 |
| Directory | /workspace/76.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1791660051 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 5412943785 ps |
| CPU time | 757.81 seconds |
| Started | Feb 07 04:46:19 PM PST 24 |
| Finished | Feb 07 04:58:57 PM PST 24 |
| Peak memory | 599768 kb |
| Host | smart-900ce011-8a3b-4200-9f33-8b32d0fd8b8e |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791660051 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1791660051 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/30.chip_sw_all_escalation_resets.1478970420 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 6236634332 ps |
| CPU time | 722.16 seconds |
| Started | Feb 07 05:01:47 PM PST 24 |
| Finished | Feb 07 05:13:49 PM PST 24 |
| Peak memory | 635196 kb |
| Host | smart-8d1fb01c-75f9-429f-9e09-7fa15ebe68c8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1478970420 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.1478970420 |
| Directory | /workspace/30.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/38.chip_sw_all_escalation_resets.3593668663 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 4590695514 ps |
| CPU time | 694.62 seconds |
| Started | Feb 07 05:01:28 PM PST 24 |
| Finished | Feb 07 05:13:04 PM PST 24 |
| Peak memory | 636636 kb |
| Host | smart-0c9c5197-097a-4b18-9116-a7d8b9832490 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3593668663 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.3593668663 |
| Directory | /workspace/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/92.chip_sw_all_escalation_resets.1588993973 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 4805849960 ps |
| CPU time | 695.09 seconds |
| Started | Feb 07 05:04:38 PM PST 24 |
| Finished | Feb 07 05:16:14 PM PST 24 |
| Peak memory | 634852 kb |
| Host | smart-80efd610-4c91-4cfe-9839-0d34cb619531 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1588993973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.1588993973 |
| Directory | /workspace/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/21.chip_tl_errors.2809889036 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 3568001383 ps |
| CPU time | 259.69 seconds |
| Started | Feb 07 04:13:27 PM PST 24 |
| Finished | Feb 07 04:17:48 PM PST 24 |
| Peak memory | 580364 kb |
| Host | smart-91b70ba8-d4ec-47ea-96bf-727c6379b742 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809889036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.2809889036 |
| Directory | /workspace/21.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3267150307 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 3668241761 ps |
| CPU time | 133.55 seconds |
| Started | Feb 07 04:32:58 PM PST 24 |
| Finished | Feb 07 04:35:12 PM PST 24 |
| Peak memory | 602736 kb |
| Host | smart-ddaba45b-3ee3-4f1e-9d66-3470e09183d7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3267150307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.3267150307 |
| Directory | /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.1949049893 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 8839829041 ps |
| CPU time | 1176 seconds |
| Started | Feb 07 04:23:54 PM PST 24 |
| Finished | Feb 07 04:43:31 PM PST 24 |
| Peak memory | 575756 kb |
| Host | smart-45daeeef-43fc-4d14-ab11-71e32b1c3686 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949049893 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_al l_with_reset_error.1949049893 |
| Directory | /workspace/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_data_integrity_escalation.3518415827 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 5692574468 ps |
| CPU time | 749.39 seconds |
| Started | Feb 07 04:39:12 PM PST 24 |
| Finished | Feb 07 04:51:42 PM PST 24 |
| Peak memory | 601972 kb |
| Host | smart-1f08bc15-c833-4250-bec0-14e653f8f70c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3518415827 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.3518415827 |
| Directory | /workspace/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.4251165855 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3131219233 ps |
| CPU time | 299.14 seconds |
| Started | Feb 07 04:53:00 PM PST 24 |
| Finished | Feb 07 04:57:59 PM PST 24 |
| Peak memory | 599356 kb |
| Host | smart-8aa15826-d9ac-483e-9a00-e18bf7cf0345 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251 165855 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.4251165855 |
| Directory | /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_auto_mode.72646735 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 4257041040 ps |
| CPU time | 665.85 seconds |
| Started | Feb 07 04:33:35 PM PST 24 |
| Finished | Feb 07 04:44:45 PM PST 24 |
| Peak memory | 599364 kb |
| Host | smart-2257e437-4d82-43c8-90ee-9a7500649329 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72646735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_au to_mode.72646735 |
| Directory | /workspace/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_entropy.2031418819 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 2778813472 ps |
| CPU time | 339.28 seconds |
| Started | Feb 07 04:33:28 PM PST 24 |
| Finished | Feb 07 04:39:08 PM PST 24 |
| Peak memory | 599072 kb |
| Host | smart-367f8f11-5237-4cee-bebc-0a05a1824a92 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031418819 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_entropy.2031418819 |
| Directory | /workspace/0.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2813224709 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 9164713082 ps |
| CPU time | 998.67 seconds |
| Started | Feb 07 04:53:02 PM PST 24 |
| Finished | Feb 07 05:09:41 PM PST 24 |
| Peak memory | 601320 kb |
| Host | smart-7e8174d2-cb8a-4674-ac8b-a869ecfd09fa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813224709 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.2813224709 |
| Directory | /workspace/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_0.4217667185 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 6086314680 ps |
| CPU time | 1492.56 seconds |
| Started | Feb 07 04:35:05 PM PST 24 |
| Finished | Feb 07 04:59:59 PM PST 24 |
| Peak memory | 599632 kb |
| Host | smart-475777b0-18d2-4a11-8e28-ad3fae5590e4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217667185 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_0.4217667185 |
| Directory | /workspace/0.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1124562656 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 5810985655 ps |
| CPU time | 325.18 seconds |
| Started | Feb 07 04:11:40 PM PST 24 |
| Finished | Feb 07 04:17:06 PM PST 24 |
| Peak memory | 641500 kb |
| Host | smart-52a75602-00ff-4090-8060-8b55519c4ee4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124562656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_r eset.1124562656 |
| Directory | /workspace/1.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1824283371 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 5642609224 ps |
| CPU time | 1108.54 seconds |
| Started | Feb 07 04:56:10 PM PST 24 |
| Finished | Feb 07 05:14:40 PM PST 24 |
| Peak memory | 602820 kb |
| Host | smart-1a4bce08-66a0-4c68-ac2f-79eafe492c03 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824283371 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.1824283371 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.1662756582 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 10002850388 ps |
| CPU time | 694.26 seconds |
| Started | Feb 07 04:12:28 PM PST 24 |
| Finished | Feb 07 04:24:03 PM PST 24 |
| Peak memory | 559240 kb |
| Host | smart-219de5d5-cc10-4b87-b52a-ab7ad9dd87df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662756582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all _with_rand_reset.1662756582 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_wake.1604651441 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4428249196 ps |
| CPU time | 322.7 seconds |
| Started | Feb 07 04:47:20 PM PST 24 |
| Finished | Feb 07 04:52:43 PM PST 24 |
| Peak memory | 601688 kb |
| Host | smart-640210bf-d066-46d0-9728-5ad1e5027526 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604651441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.1604651441 |
| Directory | /workspace/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_tl_errors.2107094941 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 3745480420 ps |
| CPU time | 279.64 seconds |
| Started | Feb 07 04:12:31 PM PST 24 |
| Finished | Feb 07 04:17:11 PM PST 24 |
| Peak memory | 580344 kb |
| Host | smart-8ebf92b1-9b21-4041-88bd-d56549b7e21c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107094941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.2107094941 |
| Directory | /workspace/15.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.rom_raw_unlock.226110904 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 14616724599 ps |
| CPU time | 2008.56 seconds |
| Started | Feb 07 04:37:16 PM PST 24 |
| Finished | Feb 07 05:10:45 PM PST 24 |
| Peak memory | 607056 kb |
| Host | smart-fb767876-dcef-459e-8e39-ad7c2bfa0af6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:fake_rsa_test_key_0:ot_flash_binary,rom_with_fake_keys:0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226110904 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.226110904 |
| Directory | /workspace/0.rom_raw_unlock/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.1503279616 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 7454962450 ps |
| CPU time | 379.51 seconds |
| Started | Feb 07 04:12:04 PM PST 24 |
| Finished | Feb 07 04:18:24 PM PST 24 |
| Peak memory | 629244 kb |
| Host | smart-d46249d3-b2f8-451e-9eb6-90f4090b4800 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503279616 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 9.chip_csr_mem_rw_with_rand_reset.1503279616 |
| Directory | /workspace/9.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.1010005614 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 10058943814 ps |
| CPU time | 955.22 seconds |
| Started | Feb 07 04:12:05 PM PST 24 |
| Finished | Feb 07 04:28:01 PM PST 24 |
| Peak memory | 575768 kb |
| Host | smart-2aa3499b-be49-4111-af7e-44fc0acba069 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010005614 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all _with_reset_error.1010005614 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_20.2315330242 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 3913342928 ps |
| CPU time | 717.63 seconds |
| Started | Feb 07 04:34:27 PM PST 24 |
| Finished | Feb 07 04:46:26 PM PST 24 |
| Peak memory | 599216 kb |
| Host | smart-2c31e00e-d602-49ef-bd9d-2aa27a220397 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315330242 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_20.2315330242 |
| Directory | /workspace/0.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio.229111946 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 3622292400 ps |
| CPU time | 452.43 seconds |
| Started | Feb 07 04:48:31 PM PST 24 |
| Finished | Feb 07 04:56:05 PM PST 24 |
| Peak memory | 599760 kb |
| Host | smart-d5d845a7-eae0-4d37-8a43-a895b55d386d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229111946 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.chip_sw_gpio.229111946 |
| Directory | /workspace/2.chip_sw_gpio/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.3054312156 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 28530611200 ps |
| CPU time | 3611.29 seconds |
| Started | Feb 07 04:12:03 PM PST 24 |
| Finished | Feb 07 05:12:15 PM PST 24 |
| Peak memory | 580304 kb |
| Host | smart-15632cfb-5316-4127-9cfc-32c216d09b9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054312156 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.chip_same_csr_outstanding.3054312156 |
| Directory | /workspace/9.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.1390823279 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 587705974 ps |
| CPU time | 175.32 seconds |
| Started | Feb 07 04:12:50 PM PST 24 |
| Finished | Feb 07 04:15:48 PM PST 24 |
| Peak memory | 559208 kb |
| Host | smart-fbb05565-5ba9-4e32-a611-9b3d6f9f510b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390823279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_al l_with_reset_error.1390823279 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.3689760211 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 11741086602 ps |
| CPU time | 546.26 seconds |
| Started | Feb 07 04:18:34 PM PST 24 |
| Finished | Feb 07 04:27:41 PM PST 24 |
| Peak memory | 559420 kb |
| Host | smart-1039365c-1fe8-495a-a0e7-f2856f287a1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689760211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_al l_with_reset_error.3689760211 |
| Directory | /workspace/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pincfg.944565295 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 31331492648 ps |
| CPU time | 6261.52 seconds |
| Started | Feb 07 04:32:06 PM PST 24 |
| Finished | Feb 07 06:16:28 PM PST 24 |
| Peak memory | 600656 kb |
| Host | smart-5b4fee06-71c2-40e1-8d1a-cb946d92fef9 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=944565295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.944565295 |
| Directory | /workspace/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_wake.4012152809 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4930035930 ps |
| CPU time | 466.39 seconds |
| Started | Feb 07 04:32:18 PM PST 24 |
| Finished | Feb 07 04:40:05 PM PST 24 |
| Peak memory | 601688 kb |
| Host | smart-39bcd6b2-e14b-4b81-a30f-9d5625c4f9ec |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012152809 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.4012152809 |
| Directory | /workspace/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_wake.387901403 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 2805434564 ps |
| CPU time | 227.43 seconds |
| Started | Feb 07 04:37:54 PM PST 24 |
| Finished | Feb 07 04:41:42 PM PST 24 |
| Peak memory | 599608 kb |
| Host | smart-93cc3e7b-f051-4ed0-9f84-4af3c0b73ccd |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387901403 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.387901403 |
| Directory | /workspace/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_tl_errors.806311511 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 3856255654 ps |
| CPU time | 219.88 seconds |
| Started | Feb 07 04:12:38 PM PST 24 |
| Finished | Feb 07 04:16:23 PM PST 24 |
| Peak memory | 580352 kb |
| Host | smart-e36bd336-fb80-48a6-8fdd-63cdac5e922d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806311511 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.806311511 |
| Directory | /workspace/14.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_test.999491635 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3493245732 ps |
| CPU time | 366.15 seconds |
| Started | Feb 07 04:33:32 PM PST 24 |
| Finished | Feb 07 04:39:39 PM PST 24 |
| Peak memory | 600784 kb |
| Host | smart-55cc856d-e8af-4659-ac59-cef8b61c0a0c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999491635 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_alert_test.999491635 |
| Directory | /workspace/0.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init.1817903545 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 22509988940 ps |
| CPU time | 2431.41 seconds |
| Started | Feb 07 04:37:52 PM PST 24 |
| Finished | Feb 07 05:18:24 PM PST 24 |
| Peak memory | 602656 kb |
| Host | smart-9eddcb6b-e12e-4b93-b4d0-ca5aa0ada65c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817903545 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.1817903545 |
| Directory | /workspace/1.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1352157576 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 6048591600 ps |
| CPU time | 808.65 seconds |
| Started | Feb 07 04:41:49 PM PST 24 |
| Finished | Feb 07 04:55:19 PM PST 24 |
| Peak memory | 601284 kb |
| Host | smart-eb13376e-5f10-4d46-921a-179b7b51e48c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13521575 76 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.1352157576 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3257069132 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 4805452088 ps |
| CPU time | 532.88 seconds |
| Started | Feb 07 04:51:58 PM PST 24 |
| Finished | Feb 07 05:00:53 PM PST 24 |
| Peak memory | 601288 kb |
| Host | smart-5e061803-9680-420d-8dbe-03ae93019d7c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32570691 32 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.3257069132 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.606487482 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 5118757684 ps |
| CPU time | 608.34 seconds |
| Started | Feb 07 04:57:40 PM PST 24 |
| Finished | Feb 07 05:07:49 PM PST 24 |
| Peak memory | 601220 kb |
| Host | smart-e3a017b6-e5e2-4fdc-b39c-5e66265426a9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60648748 2 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.606487482 |
| Directory | /workspace/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through.4140132068 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 7442004855 ps |
| CPU time | 764.52 seconds |
| Started | Feb 07 04:32:37 PM PST 24 |
| Finished | Feb 07 04:45:22 PM PST 24 |
| Peak memory | 618364 kb |
| Host | smart-b0f39374-476d-437f-af5c-44a50da0cc16 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140132068 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.4140132068 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2362771419 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 4690034778 ps |
| CPU time | 1005.96 seconds |
| Started | Feb 07 04:48:41 PM PST 24 |
| Finished | Feb 07 05:05:30 PM PST 24 |
| Peak memory | 600904 kb |
| Host | smart-d05a8aed-e693-455b-b054-cae4fa0c9a16 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2362771419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.2362771419 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.106941489 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 2639858009 ps |
| CPU time | 119.26 seconds |
| Started | Feb 07 04:39:06 PM PST 24 |
| Finished | Feb 07 04:41:06 PM PST 24 |
| Peak memory | 601304 kb |
| Host | smart-9faae748-6492-452a-b264-c263886a6890 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106941489 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.106941489 |
| Directory | /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_20.755106757 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 4687499814 ps |
| CPU time | 802.57 seconds |
| Started | Feb 07 04:53:35 PM PST 24 |
| Finished | Feb 07 05:06:59 PM PST 24 |
| Peak memory | 600896 kb |
| Host | smart-72a81902-5209-477c-92e6-9e9f6986eb46 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755106757 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_20.755106757 |
| Directory | /workspace/2.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/71.chip_sw_all_escalation_resets.1839297239 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 5780041212 ps |
| CPU time | 832.15 seconds |
| Started | Feb 07 05:05:14 PM PST 24 |
| Finished | Feb 07 05:19:08 PM PST 24 |
| Peak memory | 635160 kb |
| Host | smart-417fb1db-f5d4-4993-baf0-61a96fe8df1d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1839297239 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.1839297239 |
| Directory | /workspace/71.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/28.chip_tl_errors.2181568230 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 3033503907 ps |
| CPU time | 248.8 seconds |
| Started | Feb 07 04:14:13 PM PST 24 |
| Finished | Feb 07 04:18:23 PM PST 24 |
| Peak memory | 580328 kb |
| Host | smart-60b95597-8e1e-491a-966b-b10b62ae4db8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181568230 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.2181568230 |
| Directory | /workspace/28.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.3173246088 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 10556555820 ps |
| CPU time | 587.36 seconds |
| Started | Feb 07 04:22:23 PM PST 24 |
| Finished | Feb 07 04:32:11 PM PST 24 |
| Peak memory | 559344 kb |
| Host | smart-f6fa55db-3fdb-4fa4-b001-b6aba8fe454d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173246088 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_al l_with_reset_error.3173246088 |
| Directory | /workspace/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_0.3901774711 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 5984354512 ps |
| CPU time | 986.82 seconds |
| Started | Feb 07 04:42:19 PM PST 24 |
| Finished | Feb 07 04:58:46 PM PST 24 |
| Peak memory | 601024 kb |
| Host | smart-869edd9e-4466-4931-88b9-4035a9d7b3a1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901774711 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_0.3901774711 |
| Directory | /workspace/1.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.3852162548 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 2502906058 ps |
| CPU time | 229.45 seconds |
| Started | Feb 07 04:32:17 PM PST 24 |
| Finished | Feb 07 04:36:08 PM PST 24 |
| Peak memory | 601980 kb |
| Host | smart-831e51d0-a4b0-46b1-9e01-caab7683454a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852162548 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.3852162548 |
| Directory | /workspace/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.274997684 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 12750578818 ps |
| CPU time | 2224.78 seconds |
| Started | Feb 07 04:33:15 PM PST 24 |
| Finished | Feb 07 05:10:21 PM PST 24 |
| Peak memory | 613636 kb |
| Host | smart-b6c6be72-1f3a-44a6-8e95-620d13a5cde1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274997684 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.274997684 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx.4024021342 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 5950108468 ps |
| CPU time | 1117.83 seconds |
| Started | Feb 07 04:47:35 PM PST 24 |
| Finished | Feb 07 05:06:13 PM PST 24 |
| Peak memory | 603120 kb |
| Host | smart-088eb81d-562d-4dc1-b8bd-a86987d79041 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024021342 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.4024021342 |
| Directory | /workspace/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4225300657 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 18509975898 ps |
| CPU time | 555.97 seconds |
| Started | Feb 07 04:33:54 PM PST 24 |
| Finished | Feb 07 04:43:11 PM PST 24 |
| Peak memory | 613972 kb |
| Host | smart-44d91e52-e77a-40d2-b5e4-3ae019ac62ad |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4225300657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4225300657 |
| Directory | /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1854805875 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 4209868856 ps |
| CPU time | 678.89 seconds |
| Started | Feb 07 04:35:29 PM PST 24 |
| Finished | Feb 07 04:46:49 PM PST 24 |
| Peak memory | 594772 kb |
| Host | smart-0d86f7ea-ee1b-417c-b1a7-dbf0f62a0076 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854805875 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.1854805875 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3755926534 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 133164016430 ps |
| CPU time | 6349.29 seconds |
| Started | Feb 07 04:38:15 PM PST 24 |
| Finished | Feb 07 06:24:06 PM PST 24 |
| Peak memory | 608108 kb |
| Host | smart-589a9df5-0bcb-4bdb-9e57-58f42fbadd0b |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755926534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_dev.3755926534 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.631812879 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 20388618152 ps |
| CPU time | 3153.05 seconds |
| Started | Feb 07 04:34:07 PM PST 24 |
| Finished | Feb 07 05:26:41 PM PST 24 |
| Peak memory | 601392 kb |
| Host | smart-599fbd85-2b55-4ea4-9556-4e59bf65a296 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631812879 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.631812879 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1674823084 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 154454396 ps |
| CPU time | 81.44 seconds |
| Started | Feb 07 04:12:31 PM PST 24 |
| Finished | Feb 07 04:13:53 PM PST 24 |
| Peak memory | 556820 kb |
| Host | smart-05541d86-f869-4186-ab7f-cd895db71c2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674823084 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_al l_with_reset_error.1674823084 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.1610538105 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 862471973 ps |
| CPU time | 291.97 seconds |
| Started | Feb 07 04:15:13 PM PST 24 |
| Finished | Feb 07 04:20:05 PM PST 24 |
| Peak memory | 557720 kb |
| Host | smart-a96237dd-3b24-4127-82fd-ea95e33f6c02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610538105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all _with_rand_reset.1610538105 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.3325881870 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 4073610464 ps |
| CPU time | 394.43 seconds |
| Started | Feb 07 04:16:39 PM PST 24 |
| Finished | Feb 07 04:23:14 PM PST 24 |
| Peak memory | 559428 kb |
| Host | smart-3532a33a-b63e-436f-a69c-2056b3a68edf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325881870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_al l_with_reset_error.3325881870 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.692211080 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 6052403810 ps |
| CPU time | 286.98 seconds |
| Started | Feb 07 04:32:36 PM PST 24 |
| Finished | Feb 07 04:37:23 PM PST 24 |
| Peak memory | 605580 kb |
| Host | smart-37ae0d69-a8fb-4cb3-9c2f-932068b04ccb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =692211080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.692211080 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/9.chip_sw_all_escalation_resets.3173800964 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 4851597392 ps |
| CPU time | 599.2 seconds |
| Started | Feb 07 04:57:50 PM PST 24 |
| Finished | Feb 07 05:07:50 PM PST 24 |
| Peak memory | 635480 kb |
| Host | smart-86dc80f3-7f7f-4b15-b0a8-b65befe88fac |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3173800964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.3173800964 |
| Directory | /workspace/9.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_10.2537609475 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 3703626042 ps |
| CPU time | 541.18 seconds |
| Started | Feb 07 04:36:41 PM PST 24 |
| Finished | Feb 07 04:45:46 PM PST 24 |
| Peak memory | 599356 kb |
| Host | smart-fa25b6dd-4df0-4b98-adf2-175c27e45dbb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537609475 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_10.2537609475 |
| Directory | /workspace/0.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.56598231 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 3558721004 ps |
| CPU time | 366.07 seconds |
| Started | Feb 07 04:35:19 PM PST 24 |
| Finished | Feb 07 04:41:28 PM PST 24 |
| Peak memory | 634092 kb |
| Host | smart-4e043784-ee58-43c2-92c6-d1cab3e36c82 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56598231 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ alert_handler_lpg_sleep_mode_alerts.56598231 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.1229788019 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 5975332463 ps |
| CPU time | 357.48 seconds |
| Started | Feb 07 04:11:42 PM PST 24 |
| Finished | Feb 07 04:17:40 PM PST 24 |
| Peak memory | 641576 kb |
| Host | smart-a6cdaa0d-91bf-4db0-9258-3ac0203facef |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229788019 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_r eset.1229788019 |
| Directory | /workspace/2.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1065886192 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 4291602352 ps |
| CPU time | 750.66 seconds |
| Started | Feb 07 04:36:09 PM PST 24 |
| Finished | Feb 07 04:48:40 PM PST 24 |
| Peak memory | 617720 kb |
| Host | smart-319e61f1-3d44-442a-85de-258eeec33d4a |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065886192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1065886192 |
| Directory | /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_tl_errors.784505202 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 3409108168 ps |
| CPU time | 203.83 seconds |
| Started | Feb 07 04:11:22 PM PST 24 |
| Finished | Feb 07 04:14:47 PM PST 24 |
| Peak memory | 580368 kb |
| Host | smart-028bac3c-5b97-4073-a5b6-3738bda06c0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784505202 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.784505202 |
| Directory | /workspace/0.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_csrng.1013573894 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 7013298380 ps |
| CPU time | 1902.7 seconds |
| Started | Feb 07 04:42:11 PM PST 24 |
| Finished | Feb 07 05:13:55 PM PST 24 |
| Peak memory | 601168 kb |
| Host | smart-67852081-d2b4-41c9-b7f0-e508c7663505 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1013573894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.1013573894 |
| Directory | /workspace/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_10.1278940540 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 3002498072 ps |
| CPU time | 574.37 seconds |
| Started | Feb 07 04:54:24 PM PST 24 |
| Finished | Feb 07 05:04:01 PM PST 24 |
| Peak memory | 600640 kb |
| Host | smart-4ad6e8d0-c284-409d-907d-f0f8f5d072a2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278940540 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.1278940540 |
| Directory | /workspace/2.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/0.chip_sw_plic_sw_irq.1717266324 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 3514450500 ps |
| CPU time | 237.05 seconds |
| Started | Feb 07 04:34:16 PM PST 24 |
| Finished | Feb 07 04:38:13 PM PST 24 |
| Peak memory | 600480 kb |
| Host | smart-d9154d85-c73c-471e-bc2b-ee1ad2c7cd22 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717266324 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_plic_sw_irq.1717266324 |
| Directory | /workspace/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pattgen_ios.1433395437 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 2101804864 ps |
| CPU time | 154.15 seconds |
| Started | Feb 07 04:37:26 PM PST 24 |
| Finished | Feb 07 04:40:01 PM PST 24 |
| Peak memory | 597460 kb |
| Host | smart-33d4ce64-479e-48c6-80cc-8519274c78d0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433395437 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.1433395437 |
| Directory | /workspace/1.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.675826449 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 35414375546 ps |
| CPU time | 3521.81 seconds |
| Started | Feb 07 04:33:36 PM PST 24 |
| Finished | Feb 07 05:32:22 PM PST 24 |
| Peak memory | 604096 kb |
| Host | smart-32810a71-6b54-43c9-8896-8113b53db411 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675826449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitc h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sl eep_power_glitch_reset.675826449 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.1219116900 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 18112605986 ps |
| CPU time | 622.6 seconds |
| Started | Feb 07 04:16:45 PM PST 24 |
| Finished | Feb 07 04:27:08 PM PST 24 |
| Peak memory | 557896 kb |
| Host | smart-8c97ec42-221b-46d9-b74f-28de0229ee80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219116900 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1219116900 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.772496348 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 2436075407 ps |
| CPU time | 124.33 seconds |
| Started | Feb 07 04:48:55 PM PST 24 |
| Finished | Feb 07 04:51:01 PM PST 24 |
| Peak memory | 601196 kb |
| Host | smart-135f9e16-b6ab-46bd-b4f6-dde79cfb0fb2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772496348 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.772496348 |
| Directory | /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4122285972 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 24809578654 ps |
| CPU time | 3600.07 seconds |
| Started | Feb 07 04:46:49 PM PST 24 |
| Finished | Feb 07 05:46:53 PM PST 24 |
| Peak memory | 601028 kb |
| Host | smart-b260f5a1-ab27-4000-914e-c472740bb6a5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122285972 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.4122285972 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.3552321271 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 2867242744 ps |
| CPU time | 173.56 seconds |
| Started | Feb 07 04:53:35 PM PST 24 |
| Finished | Feb 07 04:56:29 PM PST 24 |
| Peak memory | 627588 kb |
| Host | smart-8c36abd9-7777-4551-8b9f-d91ffc9d33ea |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552321271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_lockstep_glitch.3552321271 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.3428866177 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 54339734243 ps |
| CPU time | 1048.74 seconds |
| Started | Feb 07 04:13:01 PM PST 24 |
| Finished | Feb 07 04:30:31 PM PST 24 |
| Peak memory | 555192 kb |
| Host | smart-fd6424c5-ef26-42de-a240-dbe4971135e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428866177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.3428866177 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.2527750995 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 11859561707 ps |
| CPU time | 559.71 seconds |
| Started | Feb 07 04:13:27 PM PST 24 |
| Finished | Feb 07 04:22:48 PM PST 24 |
| Peak memory | 556864 kb |
| Host | smart-8c5af152-b769-4ee3-8d2d-d08135e0f270 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527750995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all _with_rand_reset.2527750995 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_all_escalation_resets.2935582758 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 4181019304 ps |
| CPU time | 552.15 seconds |
| Started | Feb 07 04:32:46 PM PST 24 |
| Finished | Feb 07 04:41:59 PM PST 24 |
| Peak memory | 634920 kb |
| Host | smart-953584c0-fe6c-4013-b6dc-ef1d89f414c3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2935582758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.2935582758 |
| Directory | /workspace/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3691329771 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 3727061250 ps |
| CPU time | 408.63 seconds |
| Started | Feb 07 04:42:04 PM PST 24 |
| Finished | Feb 07 04:48:55 PM PST 24 |
| Peak memory | 633908 kb |
| Host | smart-1b9155ac-f6d3-4f98-9125-4df85a57cf70 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691329771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_alert_handler_lpg_sleep_mode_alerts.3691329771 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_all_escalation_resets.2896628383 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 6332227000 ps |
| CPU time | 672.88 seconds |
| Started | Feb 07 04:38:36 PM PST 24 |
| Finished | Feb 07 04:49:50 PM PST 24 |
| Peak memory | 635372 kb |
| Host | smart-9e03993e-5159-4aa7-be88-9cb97e8c0f55 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2896628383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.2896628383 |
| Directory | /workspace/1.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/10.chip_sw_all_escalation_resets.1613695144 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 4465130368 ps |
| CPU time | 706.8 seconds |
| Started | Feb 07 04:58:07 PM PST 24 |
| Finished | Feb 07 05:09:54 PM PST 24 |
| Peak memory | 635180 kb |
| Host | smart-b7055543-9960-4189-b104-1c8c96bd29fc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1613695144 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.1613695144 |
| Directory | /workspace/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1417089536 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 3402219326 ps |
| CPU time | 481.29 seconds |
| Started | Feb 07 05:00:02 PM PST 24 |
| Finished | Feb 07 05:08:05 PM PST 24 |
| Peak memory | 634032 kb |
| Host | smart-13387b90-938b-4203-bbbd-f64b2e9ffc9c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417089536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1417089536 |
| Directory | /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/11.chip_sw_all_escalation_resets.4009392561 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 5692588200 ps |
| CPU time | 565.52 seconds |
| Started | Feb 07 04:57:43 PM PST 24 |
| Finished | Feb 07 05:07:09 PM PST 24 |
| Peak memory | 635320 kb |
| Host | smart-ab1a716c-c4e2-49a1-8a41-093932f8bf20 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4009392561 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.4009392561 |
| Directory | /workspace/11.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.709344628 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 3901274412 ps |
| CPU time | 376.9 seconds |
| Started | Feb 07 04:58:16 PM PST 24 |
| Finished | Feb 07 05:04:33 PM PST 24 |
| Peak memory | 632368 kb |
| Host | smart-05891290-686f-4212-91fe-008eb6b92705 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709344628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_s w_alert_handler_lpg_sleep_mode_alerts.709344628 |
| Directory | /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2710875567 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 3973132026 ps |
| CPU time | 445.33 seconds |
| Started | Feb 07 05:03:20 PM PST 24 |
| Finished | Feb 07 05:10:49 PM PST 24 |
| Peak memory | 633808 kb |
| Host | smart-87ef4ffd-68bd-4022-ac21-a5c85fdb3749 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710875567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2710875567 |
| Directory | /workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/13.chip_sw_all_escalation_resets.3367866677 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 5674137224 ps |
| CPU time | 682.98 seconds |
| Started | Feb 07 04:58:31 PM PST 24 |
| Finished | Feb 07 05:09:56 PM PST 24 |
| Peak memory | 635488 kb |
| Host | smart-33089bfb-49cb-46c4-bd71-a25b862b7ec6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3367866677 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.3367866677 |
| Directory | /workspace/13.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1119441124 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 3657789000 ps |
| CPU time | 532.02 seconds |
| Started | Feb 07 04:58:38 PM PST 24 |
| Finished | Feb 07 05:07:30 PM PST 24 |
| Peak memory | 632600 kb |
| Host | smart-2205e6ff-7b5c-4e2a-a82a-d577eed9a5a8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119441124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1119441124 |
| Directory | /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/14.chip_sw_all_escalation_resets.4131729060 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 4604017640 ps |
| CPU time | 876.2 seconds |
| Started | Feb 07 04:58:51 PM PST 24 |
| Finished | Feb 07 05:13:28 PM PST 24 |
| Peak memory | 635196 kb |
| Host | smart-b17ab126-9fc2-4c95-8890-187cc493cffe |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4131729060 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.4131729060 |
| Directory | /workspace/14.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1081541639 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 3512028806 ps |
| CPU time | 533.27 seconds |
| Started | Feb 07 04:58:27 PM PST 24 |
| Finished | Feb 07 05:07:21 PM PST 24 |
| Peak memory | 634096 kb |
| Host | smart-a3f58fcd-45c7-4a95-bd87-38dc2297111b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081541639 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1081541639 |
| Directory | /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/15.chip_sw_all_escalation_resets.3890040683 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 5206563816 ps |
| CPU time | 592.2 seconds |
| Started | Feb 07 04:58:36 PM PST 24 |
| Finished | Feb 07 05:08:28 PM PST 24 |
| Peak memory | 635220 kb |
| Host | smart-36c859e4-c64c-4a90-876b-8b2890f4d452 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3890040683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.3890040683 |
| Directory | /workspace/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1042009904 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 3948487980 ps |
| CPU time | 537.67 seconds |
| Started | Feb 07 04:59:42 PM PST 24 |
| Finished | Feb 07 05:08:41 PM PST 24 |
| Peak memory | 632460 kb |
| Host | smart-66b32c28-38ea-4755-bb3f-4f670abb7f32 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042009904 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1042009904 |
| Directory | /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/16.chip_sw_all_escalation_resets.1380843507 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 5302861552 ps |
| CPU time | 586.52 seconds |
| Started | Feb 07 04:59:23 PM PST 24 |
| Finished | Feb 07 05:09:10 PM PST 24 |
| Peak memory | 633912 kb |
| Host | smart-898fd83f-706c-4308-86c1-7086d8816fb5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1380843507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.1380843507 |
| Directory | /workspace/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2830991466 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 3408688288 ps |
| CPU time | 498.7 seconds |
| Started | Feb 07 04:59:40 PM PST 24 |
| Finished | Feb 07 05:08:00 PM PST 24 |
| Peak memory | 633752 kb |
| Host | smart-ad55ce23-0210-4f03-af35-6be62ee00538 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830991466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2830991466 |
| Directory | /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3355726577 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 3540630140 ps |
| CPU time | 381.29 seconds |
| Started | Feb 07 04:59:13 PM PST 24 |
| Finished | Feb 07 05:05:37 PM PST 24 |
| Peak memory | 634120 kb |
| Host | smart-b4dd39ec-09d2-4871-a9d0-7d2a425a2c1a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355726577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3355726577 |
| Directory | /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.4211875645 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 3540357432 ps |
| CPU time | 328.21 seconds |
| Started | Feb 07 04:59:31 PM PST 24 |
| Finished | Feb 07 05:05:00 PM PST 24 |
| Peak memory | 633956 kb |
| Host | smart-a1d80b5f-b91c-41e1-870c-844bdf90ca6e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211875645 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4211875645 |
| Directory | /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1860267446 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 3805691232 ps |
| CPU time | 435.82 seconds |
| Started | Feb 07 04:52:19 PM PST 24 |
| Finished | Feb 07 04:59:36 PM PST 24 |
| Peak memory | 634052 kb |
| Host | smart-a8424510-0882-45c1-a646-d78d8b003703 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860267446 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_alert_handler_lpg_sleep_mode_alerts.1860267446 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/2.chip_sw_all_escalation_resets.4134692170 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 5003402600 ps |
| CPU time | 748.84 seconds |
| Started | Feb 07 04:47:32 PM PST 24 |
| Finished | Feb 07 05:00:01 PM PST 24 |
| Peak memory | 635264 kb |
| Host | smart-8a168f01-4c6e-4f38-87ed-c889c7a82975 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4134692170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.4134692170 |
| Directory | /workspace/2.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2303363442 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 3149548890 ps |
| CPU time | 374.27 seconds |
| Started | Feb 07 04:59:37 PM PST 24 |
| Finished | Feb 07 05:05:51 PM PST 24 |
| Peak memory | 632540 kb |
| Host | smart-23d3ffab-1014-4ef0-b032-5484a12ee120 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303363442 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2303363442 |
| Directory | /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/20.chip_sw_all_escalation_resets.580729250 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 4115467150 ps |
| CPU time | 583.56 seconds |
| Started | Feb 07 04:59:37 PM PST 24 |
| Finished | Feb 07 05:09:21 PM PST 24 |
| Peak memory | 635060 kb |
| Host | smart-7d7ce0b0-cf51-47f7-bc7f-5102c02b92ef |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 580729250 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.580729250 |
| Directory | /workspace/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1448545762 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 4145461416 ps |
| CPU time | 487.68 seconds |
| Started | Feb 07 04:59:09 PM PST 24 |
| Finished | Feb 07 05:07:18 PM PST 24 |
| Peak memory | 633784 kb |
| Host | smart-eef458cd-c5b0-4190-9a5f-a67257229c14 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448545762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1448545762 |
| Directory | /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/22.chip_sw_all_escalation_resets.2164141385 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 6127227748 ps |
| CPU time | 784.4 seconds |
| Started | Feb 07 04:59:45 PM PST 24 |
| Finished | Feb 07 05:12:50 PM PST 24 |
| Peak memory | 633824 kb |
| Host | smart-2ea71b92-5390-4b18-b138-10604848c127 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2164141385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.2164141385 |
| Directory | /workspace/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/23.chip_sw_all_escalation_resets.1585488651 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 4776051088 ps |
| CPU time | 588.07 seconds |
| Started | Feb 07 04:59:22 PM PST 24 |
| Finished | Feb 07 05:09:11 PM PST 24 |
| Peak memory | 635496 kb |
| Host | smart-17051a07-f939-400b-97c1-266036d26ce9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1585488651 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.1585488651 |
| Directory | /workspace/23.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/24.chip_sw_all_escalation_resets.1197538951 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 4589329520 ps |
| CPU time | 536.15 seconds |
| Started | Feb 07 04:59:58 PM PST 24 |
| Finished | Feb 07 05:08:55 PM PST 24 |
| Peak memory | 635180 kb |
| Host | smart-64930d0b-abb3-4f94-bbfa-dd4977088302 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1197538951 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.1197538951 |
| Directory | /workspace/24.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1884281246 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 3812173440 ps |
| CPU time | 430.58 seconds |
| Started | Feb 07 04:59:51 PM PST 24 |
| Finished | Feb 07 05:07:02 PM PST 24 |
| Peak memory | 633500 kb |
| Host | smart-5ce7a28c-c43c-4693-b3bd-7c6f3bd53ace |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884281246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1884281246 |
| Directory | /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/25.chip_sw_all_escalation_resets.3970784457 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 5718043520 ps |
| CPU time | 862.5 seconds |
| Started | Feb 07 05:01:41 PM PST 24 |
| Finished | Feb 07 05:16:04 PM PST 24 |
| Peak memory | 635396 kb |
| Host | smart-5daba9fc-eacd-466f-9e29-708b1dd3ecc8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3970784457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.3970784457 |
| Directory | /workspace/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1813953632 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 3625019160 ps |
| CPU time | 387.28 seconds |
| Started | Feb 07 05:00:37 PM PST 24 |
| Finished | Feb 07 05:07:05 PM PST 24 |
| Peak memory | 634132 kb |
| Host | smart-1f855573-49cf-4df8-a305-8531b6afd600 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813953632 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1813953632 |
| Directory | /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2914518766 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 2987925192 ps |
| CPU time | 368.26 seconds |
| Started | Feb 07 05:00:02 PM PST 24 |
| Finished | Feb 07 05:06:11 PM PST 24 |
| Peak memory | 632516 kb |
| Host | smart-fe4406d4-e04f-4d79-ad51-4703ff0c194f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914518766 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2914518766 |
| Directory | /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/27.chip_sw_all_escalation_resets.3061256887 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 6244557520 ps |
| CPU time | 789.66 seconds |
| Started | Feb 07 04:59:57 PM PST 24 |
| Finished | Feb 07 05:13:08 PM PST 24 |
| Peak memory | 635244 kb |
| Host | smart-b0f89462-9756-48cc-ba3c-dc674f359899 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3061256887 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.3061256887 |
| Directory | /workspace/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/28.chip_sw_all_escalation_resets.3482867069 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 4852549740 ps |
| CPU time | 628.58 seconds |
| Started | Feb 07 04:59:38 PM PST 24 |
| Finished | Feb 07 05:10:07 PM PST 24 |
| Peak memory | 635248 kb |
| Host | smart-01e27106-93ef-43ca-bfb3-4b9d301d1343 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3482867069 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.3482867069 |
| Directory | /workspace/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.946163357 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 3980185480 ps |
| CPU time | 408.66 seconds |
| Started | Feb 07 04:56:52 PM PST 24 |
| Finished | Feb 07 05:03:41 PM PST 24 |
| Peak memory | 633832 kb |
| Host | smart-9d09ce4c-8ffe-4e67-b465-f32de201e0a6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946163357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw _alert_handler_lpg_sleep_mode_alerts.946163357 |
| Directory | /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_all_escalation_resets.295822464 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 5860225400 ps |
| CPU time | 777.43 seconds |
| Started | Feb 07 04:57:27 PM PST 24 |
| Finished | Feb 07 05:10:29 PM PST 24 |
| Peak memory | 634148 kb |
| Host | smart-455a8b12-bdcc-4c85-8008-42f37fdd3c41 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 295822464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.295822464 |
| Directory | /workspace/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.102848887 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 3952464382 ps |
| CPU time | 428.19 seconds |
| Started | Feb 07 04:59:44 PM PST 24 |
| Finished | Feb 07 05:06:53 PM PST 24 |
| Peak memory | 633820 kb |
| Host | smart-2b836a0f-b3c8-44d8-99f2-46c2cc09464c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102848887 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_s w_alert_handler_lpg_sleep_mode_alerts.102848887 |
| Directory | /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/32.chip_sw_all_escalation_resets.64739088 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 5588795476 ps |
| CPU time | 775.07 seconds |
| Started | Feb 07 05:00:02 PM PST 24 |
| Finished | Feb 07 05:12:58 PM PST 24 |
| Peak memory | 635168 kb |
| Host | smart-3577ef8a-f6df-433c-8efb-13e4e0587798 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 64739088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.64739088 |
| Directory | /workspace/32.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2813024841 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 3332147194 ps |
| CPU time | 436.35 seconds |
| Started | Feb 07 05:00:33 PM PST 24 |
| Finished | Feb 07 05:07:53 PM PST 24 |
| Peak memory | 632756 kb |
| Host | smart-1fc3d11c-22df-48d9-b5e7-7b71f6164eba |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813024841 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2813024841 |
| Directory | /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2596189522 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 3975032780 ps |
| CPU time | 430.53 seconds |
| Started | Feb 07 05:02:22 PM PST 24 |
| Finished | Feb 07 05:09:43 PM PST 24 |
| Peak memory | 632584 kb |
| Host | smart-8e957dd6-732a-4a1a-850a-1e39e2888858 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596189522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2596189522 |
| Directory | /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2091814838 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 3848107384 ps |
| CPU time | 423.81 seconds |
| Started | Feb 07 05:01:40 PM PST 24 |
| Finished | Feb 07 05:08:44 PM PST 24 |
| Peak memory | 632560 kb |
| Host | smart-2930cca4-c035-41ff-800e-453657ec2152 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091814838 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2091814838 |
| Directory | /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_all_escalation_resets.2133617463 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 5921095672 ps |
| CPU time | 749.18 seconds |
| Started | Feb 07 05:00:50 PM PST 24 |
| Finished | Feb 07 05:13:20 PM PST 24 |
| Peak memory | 635384 kb |
| Host | smart-bbdb83b0-9d57-40d8-bed4-a2acf4addf64 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2133617463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.2133617463 |
| Directory | /workspace/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_all_escalation_resets.2576745271 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 5333255364 ps |
| CPU time | 710.15 seconds |
| Started | Feb 07 04:56:35 PM PST 24 |
| Finished | Feb 07 05:08:27 PM PST 24 |
| Peak memory | 634096 kb |
| Host | smart-6e1101da-e36e-44e0-9689-f8c1a806081e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2576745271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.2576745271 |
| Directory | /workspace/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/40.chip_sw_all_escalation_resets.2389503981 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 4309450700 ps |
| CPU time | 480.78 seconds |
| Started | Feb 07 05:05:28 PM PST 24 |
| Finished | Feb 07 05:13:32 PM PST 24 |
| Peak memory | 635276 kb |
| Host | smart-e4319c57-f8a3-4f0a-83fc-c5a269b8f53a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2389503981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.2389503981 |
| Directory | /workspace/40.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/43.chip_sw_all_escalation_resets.2921950751 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 5154342898 ps |
| CPU time | 646.08 seconds |
| Started | Feb 07 05:02:02 PM PST 24 |
| Finished | Feb 07 05:12:48 PM PST 24 |
| Peak memory | 635244 kb |
| Host | smart-660d699a-5c83-44ad-bf87-8b8f204e2f97 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2921950751 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.2921950751 |
| Directory | /workspace/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.4162444071 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 3131322528 ps |
| CPU time | 396.03 seconds |
| Started | Feb 07 05:01:40 PM PST 24 |
| Finished | Feb 07 05:08:17 PM PST 24 |
| Peak memory | 633724 kb |
| Host | smart-bcef8fcf-cc1c-4468-bb82-5e00f1f6db5e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162444071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4162444071 |
| Directory | /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/46.chip_sw_all_escalation_resets.1321508994 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 5522506246 ps |
| CPU time | 723.88 seconds |
| Started | Feb 07 05:01:09 PM PST 24 |
| Finished | Feb 07 05:13:14 PM PST 24 |
| Peak memory | 633924 kb |
| Host | smart-8e43329c-18c0-4f0d-a7d7-62b0984bca7b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1321508994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.1321508994 |
| Directory | /workspace/46.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1677031320 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 3157247904 ps |
| CPU time | 362.44 seconds |
| Started | Feb 07 05:02:02 PM PST 24 |
| Finished | Feb 07 05:08:06 PM PST 24 |
| Peak memory | 635188 kb |
| Host | smart-8c64b567-be85-44ba-b15b-c3e9cfc5fc6d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677031320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1677031320 |
| Directory | /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3091054623 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 4135387074 ps |
| CPU time | 382.99 seconds |
| Started | Feb 07 05:02:25 PM PST 24 |
| Finished | Feb 07 05:08:57 PM PST 24 |
| Peak memory | 632428 kb |
| Host | smart-4c4d12dc-1450-43f8-96d6-1dc31c1a33f7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091054623 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3091054623 |
| Directory | /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/53.chip_sw_all_escalation_resets.3235088814 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 4328051762 ps |
| CPU time | 682.38 seconds |
| Started | Feb 07 05:02:33 PM PST 24 |
| Finished | Feb 07 05:13:56 PM PST 24 |
| Peak memory | 634176 kb |
| Host | smart-3d29e4db-82bd-4489-8ce5-6a3dfc451690 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3235088814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.3235088814 |
| Directory | /workspace/53.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3300019177 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 3732719252 ps |
| CPU time | 410.72 seconds |
| Started | Feb 07 05:03:49 PM PST 24 |
| Finished | Feb 07 05:10:41 PM PST 24 |
| Peak memory | 634820 kb |
| Host | smart-c9aa0b78-1b16-4928-8e60-bb19d63a8080 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300019177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3300019177 |
| Directory | /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/56.chip_sw_all_escalation_resets.3700543509 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 4965395608 ps |
| CPU time | 461.8 seconds |
| Started | Feb 07 05:02:50 PM PST 24 |
| Finished | Feb 07 05:10:32 PM PST 24 |
| Peak memory | 635148 kb |
| Host | smart-f27dc165-0737-46a0-99ea-88426cd40776 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3700543509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.3700543509 |
| Directory | /workspace/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/59.chip_sw_all_escalation_resets.3306236967 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 5259475658 ps |
| CPU time | 562.78 seconds |
| Started | Feb 07 05:02:27 PM PST 24 |
| Finished | Feb 07 05:11:56 PM PST 24 |
| Peak memory | 635576 kb |
| Host | smart-8ddb75f5-4e6b-4626-8740-29b463e4bf43 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3306236967 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.3306236967 |
| Directory | /workspace/59.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.4236053412 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 3494654840 ps |
| CPU time | 474.78 seconds |
| Started | Feb 07 05:03:32 PM PST 24 |
| Finished | Feb 07 05:11:27 PM PST 24 |
| Peak memory | 633772 kb |
| Host | smart-8e10ed72-d1c0-433e-a402-c5288cf07163 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236053412 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4236053412 |
| Directory | /workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3569121935 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 4020385764 ps |
| CPU time | 405.28 seconds |
| Started | Feb 07 05:06:10 PM PST 24 |
| Finished | Feb 07 05:12:56 PM PST 24 |
| Peak memory | 632404 kb |
| Host | smart-c8642e43-293a-4ab2-9b01-cb3428872fbd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569121935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3569121935 |
| Directory | /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3857423701 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 3900460122 ps |
| CPU time | 459.28 seconds |
| Started | Feb 07 05:02:35 PM PST 24 |
| Finished | Feb 07 05:10:15 PM PST 24 |
| Peak memory | 633792 kb |
| Host | smart-f433b74f-e21c-4cf9-93e3-829417e75154 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857423701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3857423701 |
| Directory | /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/68.chip_sw_all_escalation_resets.2895908266 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 4199540966 ps |
| CPU time | 523.22 seconds |
| Started | Feb 07 05:02:50 PM PST 24 |
| Finished | Feb 07 05:11:34 PM PST 24 |
| Peak memory | 633648 kb |
| Host | smart-f4bfdfe1-8d0b-4f63-a18f-3de032d4bdbe |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2895908266 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.2895908266 |
| Directory | /workspace/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/73.chip_sw_all_escalation_resets.2528687314 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 6044201920 ps |
| CPU time | 671.51 seconds |
| Started | Feb 07 05:04:17 PM PST 24 |
| Finished | Feb 07 05:15:29 PM PST 24 |
| Peak memory | 635488 kb |
| Host | smart-b26b96fa-b349-45f7-9818-02438ea98bc8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2528687314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.2528687314 |
| Directory | /workspace/73.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2519564442 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 3816567178 ps |
| CPU time | 367.54 seconds |
| Started | Feb 07 05:04:01 PM PST 24 |
| Finished | Feb 07 05:10:09 PM PST 24 |
| Peak memory | 633836 kb |
| Host | smart-c772528b-bfa1-469b-8123-da9f620c7c73 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519564442 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2519564442 |
| Directory | /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/78.chip_sw_all_escalation_resets.688145204 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 4865204980 ps |
| CPU time | 666.13 seconds |
| Started | Feb 07 05:04:03 PM PST 24 |
| Finished | Feb 07 05:15:09 PM PST 24 |
| Peak memory | 633928 kb |
| Host | smart-fd147ea4-ac53-46db-82a6-3e541dbc204a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 688145204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.688145204 |
| Directory | /workspace/78.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.579274869 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 3258674650 ps |
| CPU time | 385.22 seconds |
| Started | Feb 07 04:57:37 PM PST 24 |
| Finished | Feb 07 05:04:02 PM PST 24 |
| Peak memory | 632480 kb |
| Host | smart-ecc69666-3e54-4fe8-b38c-e430223480b0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579274869 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw _alert_handler_lpg_sleep_mode_alerts.579274869 |
| Directory | /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.4166491184 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 3033797700 ps |
| CPU time | 413.99 seconds |
| Started | Feb 07 05:04:33 PM PST 24 |
| Finished | Feb 07 05:11:28 PM PST 24 |
| Peak memory | 632572 kb |
| Host | smart-41fd9926-30d6-451c-9526-32d3e199a193 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166491184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4166491184 |
| Directory | /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1060027171 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 3941312512 ps |
| CPU time | 439.44 seconds |
| Started | Feb 07 05:05:26 PM PST 24 |
| Finished | Feb 07 05:12:47 PM PST 24 |
| Peak memory | 632544 kb |
| Host | smart-8eaa43c6-d563-4069-8859-0c0330d6f81f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060027171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1060027171 |
| Directory | /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3099208915 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 4422103864 ps |
| CPU time | 439.05 seconds |
| Started | Feb 07 05:07:02 PM PST 24 |
| Finished | Feb 07 05:14:26 PM PST 24 |
| Peak memory | 634212 kb |
| Host | smart-8255bac7-7684-48eb-86dd-12de837eb187 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099208915 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3099208915 |
| Directory | /workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/90.chip_sw_all_escalation_resets.2344879143 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 4578844994 ps |
| CPU time | 598.73 seconds |
| Started | Feb 07 05:04:09 PM PST 24 |
| Finished | Feb 07 05:14:09 PM PST 24 |
| Peak memory | 635308 kb |
| Host | smart-649b5d61-d6fc-45f4-84ab-5acb76819d80 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2344879143 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.2344879143 |
| Directory | /workspace/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio.374999429 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 3215907360 ps |
| CPU time | 458.84 seconds |
| Started | Feb 07 04:33:40 PM PST 24 |
| Finished | Feb 07 04:41:21 PM PST 24 |
| Peak memory | 600896 kb |
| Host | smart-88e51283-d039-4100-a393-cc1b43d1b1df |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374999429 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.chip_sw_gpio.374999429 |
| Directory | /workspace/0.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1400043134 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 5405990552 ps |
| CPU time | 565.38 seconds |
| Started | Feb 07 04:35:59 PM PST 24 |
| Finished | Feb 07 04:45:25 PM PST 24 |
| Peak memory | 600724 kb |
| Host | smart-32bb8fff-02e8-4979-a526-f3b49b6e9c7e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1400043134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.1400043134 |
| Directory | /workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.4281759403 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 5650474940 ps |
| CPU time | 1008.16 seconds |
| Started | Feb 07 04:32:20 PM PST 24 |
| Finished | Feb 07 04:49:09 PM PST 24 |
| Peak memory | 602760 kb |
| Host | smart-9847b96d-8042-4d69-a7fc-c52e09f42d87 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281759403 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.4281759403 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3705671907 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 4350731240 ps |
| CPU time | 664.26 seconds |
| Started | Feb 07 04:38:33 PM PST 24 |
| Finished | Feb 07 04:49:39 PM PST 24 |
| Peak memory | 600616 kb |
| Host | smart-e84d9e62-d499-46d2-9af4-b4b1afdc6472 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705671907 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.3705671907 |
| Directory | /workspace/1.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/18.chip_sw_all_escalation_resets.2294769152 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 5596485068 ps |
| CPU time | 801.45 seconds |
| Started | Feb 07 04:59:17 PM PST 24 |
| Finished | Feb 07 05:12:41 PM PST 24 |
| Peak memory | 601816 kb |
| Host | smart-1cb42886-c5ab-4bad-9b86-a7c26d366548 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2294769152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.2294769152 |
| Directory | /workspace/18.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.715743079 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 11997500830 ps |
| CPU time | 3279.95 seconds |
| Started | Feb 07 04:42:04 PM PST 24 |
| Finished | Feb 07 05:36:50 PM PST 24 |
| Peak memory | 599592 kb |
| Host | smart-2c59bba7-9fca-494c-9e39-6fa36ad13f02 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o t_flash_binary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_dev:4,rom_with_ fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715743079 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.715743079 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init.2056457089 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 22656813867 ps |
| CPU time | 2600.96 seconds |
| Started | Feb 07 04:32:29 PM PST 24 |
| Finished | Feb 07 05:15:52 PM PST 24 |
| Peak memory | 602572 kb |
| Host | smart-cff41c64-bb72-4c10-a0f9-da89af5024af |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056457089 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.2056457089 |
| Directory | /workspace/0.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.280193929 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 6985659368 ps |
| CPU time | 436.64 seconds |
| Started | Feb 07 04:33:42 PM PST 24 |
| Finished | Feb 07 04:41:00 PM PST 24 |
| Peak memory | 601504 kb |
| Host | smart-bfbd3864-ab1c-4248-a3a7-96dab357c821 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280193929 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.280193929 |
| Directory | /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1545364768 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 8117920587 ps |
| CPU time | 834.24 seconds |
| Started | Feb 07 04:43:06 PM PST 24 |
| Finished | Feb 07 04:57:01 PM PST 24 |
| Peak memory | 603900 kb |
| Host | smart-c97f0d18-4f04-4ac1-9bb7-95da73995566 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1545364768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.1545364768 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.4039651993 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 4361626294 ps |
| CPU time | 448.23 seconds |
| Started | Feb 07 04:35:00 PM PST 24 |
| Finished | Feb 07 04:42:29 PM PST 24 |
| Peak memory | 617524 kb |
| Host | smart-dccffb01-131f-479c-92d9-ee9f27fa8e2f |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039651993 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.4039651993 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_dev.1754828042 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 10686423503 ps |
| CPU time | 1192.98 seconds |
| Started | Feb 07 04:56:10 PM PST 24 |
| Finished | Feb 07 05:16:04 PM PST 24 |
| Peak memory | 610252 kb |
| Host | smart-40e8b54a-aade-425d-9a82-a12f8b6538e6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1754828042 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.1754828042 |
| Directory | /workspace/4.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_tl_errors.4109523497 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 3772597753 ps |
| CPU time | 254.02 seconds |
| Started | Feb 07 04:12:28 PM PST 24 |
| Finished | Feb 07 04:16:43 PM PST 24 |
| Peak memory | 580272 kb |
| Host | smart-2efa989c-245a-4577-9d9b-15f17eec0666 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109523497 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.4109523497 |
| Directory | /workspace/12.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_rw.285741696 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 6029277470 ps |
| CPU time | 555.76 seconds |
| Started | Feb 07 04:12:33 PM PST 24 |
| Finished | Feb 07 04:21:49 PM PST 24 |
| Peak memory | 580288 kb |
| Host | smart-079dfc6b-8ab1-49b3-ac56-631eabf55b42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285741696 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.285741696 |
| Directory | /workspace/14.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/22.chip_tl_errors.906500546 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 3244826565 ps |
| CPU time | 180.7 seconds |
| Started | Feb 07 04:13:39 PM PST 24 |
| Finished | Feb 07 04:16:40 PM PST 24 |
| Peak memory | 580380 kb |
| Host | smart-8faeccdc-122f-4d55-a643-d2554c42507e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906500546 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.906500546 |
| Directory | /workspace/22.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/29.chip_tl_errors.221264843 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 3810597800 ps |
| CPU time | 273.84 seconds |
| Started | Feb 07 04:14:23 PM PST 24 |
| Finished | Feb 07 04:18:58 PM PST 24 |
| Peak memory | 580332 kb |
| Host | smart-11eeea05-e445-43a8-9e5a-e9acfb2597f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221264843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.221264843 |
| Directory | /workspace/29.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.1607365615 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 3579903503 ps |
| CPU time | 441.59 seconds |
| Started | Feb 07 04:17:57 PM PST 24 |
| Finished | Feb 07 04:25:20 PM PST 24 |
| Peak memory | 559412 kb |
| Host | smart-8b5385cf-8f68-4994-8aeb-a8f8826b5f30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607365615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_al l_with_reset_error.1607365615 |
| Directory | /workspace/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1573238283 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 5570503024 ps |
| CPU time | 1131.34 seconds |
| Started | Feb 07 04:35:57 PM PST 24 |
| Finished | Feb 07 04:54:49 PM PST 24 |
| Peak memory | 599580 kb |
| Host | smart-dd9d7c51-9d3b-45b6-a1a2-c1db6d775e81 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1573238283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1573238283 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1735778846 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 12417419872 ps |
| CPU time | 1925.75 seconds |
| Started | Feb 07 04:38:34 PM PST 24 |
| Finished | Feb 07 05:10:42 PM PST 24 |
| Peak memory | 601900 kb |
| Host | smart-fce4e5f0-c4c2-4e58-b475-3868d0321a38 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1735778846 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.1735778846 |
| Directory | /workspace/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3111683894 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 2577134816 ps |
| CPU time | 182.87 seconds |
| Started | Feb 07 04:38:37 PM PST 24 |
| Finished | Feb 07 04:41:41 PM PST 24 |
| Peak memory | 601780 kb |
| Host | smart-ac904a4e-32ab-49f9-8583-4ce009a45d9b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111683894 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.3111683894 |
| Directory | /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.1596909525 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 7275050560 ps |
| CPU time | 375.31 seconds |
| Started | Feb 07 04:11:43 PM PST 24 |
| Finished | Feb 07 04:17:59 PM PST 24 |
| Peak memory | 643544 kb |
| Host | smart-d5ec9420-adbb-4f5a-9a6e-09f999ce770c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596909525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_r eset.1596909525 |
| Directory | /workspace/4.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3728643814 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 5226007320 ps |
| CPU time | 469.08 seconds |
| Started | Feb 07 04:32:56 PM PST 24 |
| Finished | Feb 07 04:40:45 PM PST 24 |
| Peak memory | 600292 kb |
| Host | smart-5c83ddda-dadf-4126-ba60-ca1e709c56ed |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37 28643814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.3728643814 |
| Directory | /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2250097511 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 5217359496 ps |
| CPU time | 622.32 seconds |
| Started | Feb 07 04:33:34 PM PST 24 |
| Finished | Feb 07 04:44:02 PM PST 24 |
| Peak memory | 616152 kb |
| Host | smart-9554eb6b-3f07-4e47-b779-cbabcb7fa7b1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2250097511 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.2250097511 |
| Directory | /workspace/0.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3721733315 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 26011435509 ps |
| CPU time | 2160.72 seconds |
| Started | Feb 07 04:45:51 PM PST 24 |
| Finished | Feb 07 05:21:53 PM PST 24 |
| Peak memory | 601928 kb |
| Host | smart-04b523d6-3430-42d2-bce4-1268c0154e2c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3721733315 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.3721733315 |
| Directory | /workspace/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2317781924 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 3947752224 ps |
| CPU time | 437.71 seconds |
| Started | Feb 07 04:41:31 PM PST 24 |
| Finished | Feb 07 04:48:49 PM PST 24 |
| Peak memory | 600640 kb |
| Host | smart-66af8222-d98e-4efb-8a33-6c98283e4e1f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231778 1924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.2317781924 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_random.4014647669 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 629933034 ps |
| CPU time | 49.81 seconds |
| Started | Feb 07 04:11:26 PM PST 24 |
| Finished | Feb 07 04:12:17 PM PST 24 |
| Peak memory | 559144 kb |
| Host | smart-71bcc38a-e6b5-42a9-b4e3-0a597dc33e3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014647669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.4014647669 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.1855014889 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 125498722 ps |
| CPU time | 13.07 seconds |
| Started | Feb 07 04:13:50 PM PST 24 |
| Finished | Feb 07 04:14:03 PM PST 24 |
| Peak memory | 555356 kb |
| Host | smart-d3b8e6fe-27e3-43e8-8c75-988089a864ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855014889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_add r.1855014889 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.842588683 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 11972408140 ps |
| CPU time | 457.17 seconds |
| Started | Feb 07 04:18:36 PM PST 24 |
| Finished | Feb 07 04:26:14 PM PST 24 |
| Peak memory | 556620 kb |
| Host | smart-a5176c81-6d54-4cae-9629-073915b7154b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842588683 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.842588683 |
| Directory | /workspace/55.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.404319698 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 733869898 ps |
| CPU time | 56.39 seconds |
| Started | Feb 07 04:20:23 PM PST 24 |
| Finished | Feb 07 04:21:20 PM PST 24 |
| Peak memory | 555340 kb |
| Host | smart-0dd34f5e-88e9-4764-b251-0e979570ebd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404319698 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.404319698 |
| Directory | /workspace/58.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_tl_errors.1155357370 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 4038974935 ps |
| CPU time | 353.19 seconds |
| Started | Feb 07 04:11:49 PM PST 24 |
| Finished | Feb 07 04:17:43 PM PST 24 |
| Peak memory | 580320 kb |
| Host | smart-a5fe48a0-3eec-4c5c-8c49-e436035f612a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155357370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.1155357370 |
| Directory | /workspace/6.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.2644772425 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 2811817387 ps |
| CPU time | 249.87 seconds |
| Started | Feb 07 04:21:21 PM PST 24 |
| Finished | Feb 07 04:25:33 PM PST 24 |
| Peak memory | 556824 kb |
| Host | smart-cd4f8c46-f9a7-4c6e-b57b-64a345b5065b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644772425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.2644772425 |
| Directory | /workspace/75.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.3814504882 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 1056513399 ps |
| CPU time | 70.17 seconds |
| Started | Feb 07 04:21:33 PM PST 24 |
| Finished | Feb 07 04:22:45 PM PST 24 |
| Peak memory | 556700 kb |
| Host | smart-33d84d38-3eb5-4f0f-ac5d-a7f6033e64e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814504882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.3814504882 |
| Directory | /workspace/77.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.94549338 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 1747610215 ps |
| CPU time | 115.02 seconds |
| Started | Feb 07 04:22:20 PM PST 24 |
| Finished | Feb 07 04:24:15 PM PST 24 |
| Peak memory | 556472 kb |
| Host | smart-6c0b01bc-b116-416e-a551-145b12031b28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94549338 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.94549338 |
| Directory | /workspace/82.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1555641732 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 4719063716 ps |
| CPU time | 919.44 seconds |
| Started | Feb 07 04:34:56 PM PST 24 |
| Finished | Feb 07 04:50:17 PM PST 24 |
| Peak memory | 599724 kb |
| Host | smart-da7f8a05-9301-4357-8f11-49a8eff91437 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555641732 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.1555641732 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.203029073 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 4672475214 ps |
| CPU time | 946.73 seconds |
| Started | Feb 07 04:33:38 PM PST 24 |
| Finished | Feb 07 04:49:28 PM PST 24 |
| Peak memory | 599440 kb |
| Host | smart-40e0d2a0-fbb5-43ec-8643-741b6f88ee6c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20302 9073 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.203029073 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_idle_load.4186011647 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 4601729932 ps |
| CPU time | 770.95 seconds |
| Started | Feb 07 04:37:54 PM PST 24 |
| Finished | Feb 07 04:50:46 PM PST 24 |
| Peak memory | 601204 kb |
| Host | smart-764b6e20-a3dc-4b6e-9e10-17a652b96eca |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186011647 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.4186011647 |
| Directory | /workspace/0.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.724268213 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 17382367526 ps |
| CPU time | 3379.62 seconds |
| Started | Feb 07 04:38:02 PM PST 24 |
| Finished | Feb 07 05:34:22 PM PST 24 |
| Peak memory | 601132 kb |
| Host | smart-1736c140-2693-4cca-9271-17cb8722c863 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=180_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724268213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ csrng_edn_concurrency_reduced_freq.724268213 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.932715286 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 4302888280 ps |
| CPU time | 861.69 seconds |
| Started | Feb 07 04:33:41 PM PST 24 |
| Finished | Feb 07 04:48:05 PM PST 24 |
| Peak memory | 601224 kb |
| Host | smart-26b99192-6f07-4c33-a381-17b417cf4dda |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=932715286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.932715286 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.3121714571 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 9550564826 ps |
| CPU time | 1117.39 seconds |
| Started | Feb 07 04:11:23 PM PST 24 |
| Finished | Feb 07 04:30:01 PM PST 24 |
| Peak memory | 573572 kb |
| Host | smart-04eb8f1f-082b-4916-9732-bdc5cb7d3fba |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121714571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.3121714571 |
| Directory | /workspace/0.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.2400904824 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 4063800810 ps |
| CPU time | 232.75 seconds |
| Started | Feb 07 04:11:37 PM PST 24 |
| Finished | Feb 07 04:15:30 PM PST 24 |
| Peak memory | 639436 kb |
| Host | smart-84cb78f3-59ca-40d5-b141-1b2a61557100 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400904824 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_r eset.2400904824 |
| Directory | /workspace/0.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.1858196848 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 7782446440 ps |
| CPU time | 338.47 seconds |
| Started | Feb 07 04:11:37 PM PST 24 |
| Finished | Feb 07 04:17:16 PM PST 24 |
| Peak memory | 632540 kb |
| Host | smart-0f50bd27-59cf-43bf-893c-fd0b7ba8e3ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858196848 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.chip_csr_mem_rw_with_rand_reset.1858196848 |
| Directory | /workspace/0.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_rw.602535947 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 4741317710 ps |
| CPU time | 367.09 seconds |
| Started | Feb 07 04:11:43 PM PST 24 |
| Finished | Feb 07 04:17:50 PM PST 24 |
| Peak memory | 580236 kb |
| Host | smart-99f31fd4-6894-49ab-bceb-5133cfe591d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602535947 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.602535947 |
| Directory | /workspace/0.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1717622662 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 7077823776 ps |
| CPU time | 281.75 seconds |
| Started | Feb 07 04:11:25 PM PST 24 |
| Finished | Feb 07 04:16:07 PM PST 24 |
| Peak memory | 572108 kb |
| Host | smart-4d127584-c79d-45cc-bb09-c9ed7dbb5a51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717622662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_prim_tl_access.1717622662 |
| Directory | /workspace/0.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1949179613 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 13497241511 ps |
| CPU time | 505.65 seconds |
| Started | Feb 07 04:11:27 PM PST 24 |
| Finished | Feb 07 04:19:53 PM PST 24 |
| Peak memory | 572052 kb |
| Host | smart-2c932010-7140-476c-9e36-fad70df4ec50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949179613 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_lc_disabled.1949179613 |
| Directory | /workspace/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1531072117 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 31004752860 ps |
| CPU time | 4205.79 seconds |
| Started | Feb 07 04:11:25 PM PST 24 |
| Finished | Feb 07 05:21:33 PM PST 24 |
| Peak memory | 575256 kb |
| Host | smart-a46ba232-e47e-4448-9a01-db03001713bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531072117 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 0.chip_same_csr_outstanding.1531072117 |
| Directory | /workspace/0.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device.2128353890 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 3325232213 ps |
| CPU time | 152.06 seconds |
| Started | Feb 07 04:11:32 PM PST 24 |
| Finished | Feb 07 04:14:05 PM PST 24 |
| Peak memory | 555704 kb |
| Host | smart-032b2d8e-8368-469f-8bca-cbfa0d50d3bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128353890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device. 2128353890 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3569560493 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 40019667231 ps |
| CPU time | 692.24 seconds |
| Started | Feb 07 04:11:27 PM PST 24 |
| Finished | Feb 07 04:23:00 PM PST 24 |
| Peak memory | 555712 kb |
| Host | smart-b9ca16ad-8410-47db-b9bf-5253cc69d4b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569560493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_d evice_slow_rsp.3569560493 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1850752531 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 1032927297 ps |
| CPU time | 40.58 seconds |
| Started | Feb 07 04:11:37 PM PST 24 |
| Finished | Feb 07 04:12:18 PM PST 24 |
| Peak memory | 555320 kb |
| Host | smart-42b5983b-2f2f-4155-b37b-71f1fe1ce8dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850752531 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr .1850752531 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random.3743773195 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 89654269 ps |
| CPU time | 11.12 seconds |
| Started | Feb 07 04:11:25 PM PST 24 |
| Finished | Feb 07 04:11:36 PM PST 24 |
| Peak memory | 555596 kb |
| Host | smart-96bb649e-8ef9-4479-a977-ccbba3b1260d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743773195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.3743773195 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3627696976 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 9873935571 ps |
| CPU time | 107.41 seconds |
| Started | Feb 07 04:11:22 PM PST 24 |
| Finished | Feb 07 04:13:10 PM PST 24 |
| Peak memory | 553684 kb |
| Host | smart-45181a00-6a08-4f1b-b9df-af442b0be367 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627696976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3627696976 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.50218579 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 24062953630 ps |
| CPU time | 425.59 seconds |
| Started | Feb 07 04:11:28 PM PST 24 |
| Finished | Feb 07 04:18:34 PM PST 24 |
| Peak memory | 555652 kb |
| Host | smart-0fb4288a-7b0a-4c33-8501-522c4de2f806 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50218579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.50218579 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1806374060 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 380092933 ps |
| CPU time | 28.94 seconds |
| Started | Feb 07 04:11:20 PM PST 24 |
| Finished | Feb 07 04:11:50 PM PST 24 |
| Peak memory | 559156 kb |
| Host | smart-e276d486-983b-4fd7-b264-969bf871d246 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806374060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_dela ys.1806374060 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_same_source.1603556423 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 1244175986 ps |
| CPU time | 39.44 seconds |
| Started | Feb 07 04:11:38 PM PST 24 |
| Finished | Feb 07 04:12:18 PM PST 24 |
| Peak memory | 555132 kb |
| Host | smart-4017dbf8-6210-4c19-ae04-542c3f9a56fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603556423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.1603556423 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke.4251077495 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 48151160 ps |
| CPU time | 6.34 seconds |
| Started | Feb 07 04:11:25 PM PST 24 |
| Finished | Feb 07 04:11:31 PM PST 24 |
| Peak memory | 553556 kb |
| Host | smart-cff2bb9c-e065-422b-b131-f74d024b36fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251077495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.4251077495 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.3084713038 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 8182734089 ps |
| CPU time | 87.25 seconds |
| Started | Feb 07 04:11:25 PM PST 24 |
| Finished | Feb 07 04:12:53 PM PST 24 |
| Peak memory | 553424 kb |
| Host | smart-35aab343-5890-4708-80c0-7cf61a124384 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084713038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.3084713038 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.485208924 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 4272392975 ps |
| CPU time | 77.57 seconds |
| Started | Feb 07 04:11:19 PM PST 24 |
| Finished | Feb 07 04:12:37 PM PST 24 |
| Peak memory | 553360 kb |
| Host | smart-c63e2de3-71b1-4038-80e3-4cd76a95355c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485208924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.485208924 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3430386448 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 39649664 ps |
| CPU time | 6.07 seconds |
| Started | Feb 07 04:11:19 PM PST 24 |
| Finished | Feb 07 04:11:25 PM PST 24 |
| Peak memory | 553280 kb |
| Host | smart-1215b6eb-7ed3-4d2d-ae2a-72be2a8a65ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430386448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays .3430386448 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all.1184369289 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 950363865 ps |
| CPU time | 29.04 seconds |
| Started | Feb 07 04:11:35 PM PST 24 |
| Finished | Feb 07 04:12:04 PM PST 24 |
| Peak memory | 555624 kb |
| Host | smart-4f4e7ecc-185b-47fc-9a75-6b655e3ff356 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184369289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1184369289 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.1147037349 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 9665714632 ps |
| CPU time | 346.93 seconds |
| Started | Feb 07 04:11:36 PM PST 24 |
| Finished | Feb 07 04:17:23 PM PST 24 |
| Peak memory | 556492 kb |
| Host | smart-295d38d5-08c2-4e9b-ae4c-15e918624560 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147037349 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1147037349 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2222313598 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 946906588 ps |
| CPU time | 232.81 seconds |
| Started | Feb 07 04:11:38 PM PST 24 |
| Finished | Feb 07 04:15:31 PM PST 24 |
| Peak memory | 559284 kb |
| Host | smart-88d3eb4c-cf74-45ee-9c51-e693afe951fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222313598 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all _with_reset_error.2222313598 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2159166124 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 923728175 ps |
| CPU time | 36.96 seconds |
| Started | Feb 07 04:11:37 PM PST 24 |
| Finished | Feb 07 04:12:14 PM PST 24 |
| Peak memory | 555620 kb |
| Host | smart-ed0cc4ea-7e57-4ee8-b5b2-f9eebfe4eb28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159166124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2159166124 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3147537699 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 35923895992 ps |
| CPU time | 6276.64 seconds |
| Started | Feb 07 04:11:38 PM PST 24 |
| Finished | Feb 07 05:56:15 PM PST 24 |
| Peak memory | 580256 kb |
| Host | smart-e857af90-3dd7-499a-9cd6-36df7549839a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147537699 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.chip_csr_aliasing.3147537699 |
| Directory | /workspace/1.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1562274880 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 78319129460 ps |
| CPU time | 8675.92 seconds |
| Started | Feb 07 04:11:43 PM PST 24 |
| Finished | Feb 07 06:36:20 PM PST 24 |
| Peak memory | 579444 kb |
| Host | smart-9dc41c0a-343b-492e-ae2a-1ebf137b2e08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562274880 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.1562274880 |
| Directory | /workspace/1.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1040512041 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 5568125423 ps |
| CPU time | 245.4 seconds |
| Started | Feb 07 04:11:35 PM PST 24 |
| Finished | Feb 07 04:15:40 PM PST 24 |
| Peak memory | 614076 kb |
| Host | smart-86c908d0-8776-4f09-ac2d-1e322824b158 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040512041 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.chip_csr_mem_rw_with_rand_reset.1040512041 |
| Directory | /workspace/1.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_rw.814566002 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 5648146920 ps |
| CPU time | 540.3 seconds |
| Started | Feb 07 04:11:41 PM PST 24 |
| Finished | Feb 07 04:20:42 PM PST 24 |
| Peak memory | 580100 kb |
| Host | smart-08b0484f-0ef0-41f7-9bf0-3d58ad5d6c8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814566002 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.814566002 |
| Directory | /workspace/1.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.1123676904 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 9791382858 ps |
| CPU time | 348.52 seconds |
| Started | Feb 07 04:11:34 PM PST 24 |
| Finished | Feb 07 04:17:23 PM PST 24 |
| Peak memory | 572100 kb |
| Host | smart-8e4adbd7-59ae-4b90-9a31-cd5aacb01912 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123676904 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_prim_tl_access.1123676904 |
| Directory | /workspace/1.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.4154758061 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 15590140547 ps |
| CPU time | 440.06 seconds |
| Started | Feb 07 04:11:39 PM PST 24 |
| Finished | Feb 07 04:18:59 PM PST 24 |
| Peak memory | 573216 kb |
| Host | smart-ce683a86-b7c7-4d78-a219-4e25c0b069b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154758061 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_lc_disabled.4154758061 |
| Directory | /workspace/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.3722238459 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 15338732130 ps |
| CPU time | 1700.19 seconds |
| Started | Feb 07 04:11:38 PM PST 24 |
| Finished | Feb 07 04:39:59 PM PST 24 |
| Peak memory | 574708 kb |
| Host | smart-2bb85252-0c99-44dc-8b79-4d90b9ffe09e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722238459 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 1.chip_same_csr_outstanding.3722238459 |
| Directory | /workspace/1.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_tl_errors.4257135119 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 3554533767 ps |
| CPU time | 194.32 seconds |
| Started | Feb 07 04:11:32 PM PST 24 |
| Finished | Feb 07 04:14:47 PM PST 24 |
| Peak memory | 580168 kb |
| Host | smart-9db03676-426b-4ef1-8030-97bfc1d4747a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257135119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.4257135119 |
| Directory | /workspace/1.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device.781640146 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 2864804980 ps |
| CPU time | 109.7 seconds |
| Started | Feb 07 04:11:30 PM PST 24 |
| Finished | Feb 07 04:13:20 PM PST 24 |
| Peak memory | 555704 kb |
| Host | smart-3490dd2f-146f-438c-910d-61037ca02bf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781640146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.781640146 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.458294103 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 199393508 ps |
| CPU time | 20.65 seconds |
| Started | Feb 07 04:11:41 PM PST 24 |
| Finished | Feb 07 04:12:02 PM PST 24 |
| Peak memory | 555216 kb |
| Host | smart-0d3d30cd-2df7-4eb7-992f-f5a78c61282a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458294103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr. 458294103 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_random.4210477902 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 2298991826 ps |
| CPU time | 76.16 seconds |
| Started | Feb 07 04:11:26 PM PST 24 |
| Finished | Feb 07 04:12:42 PM PST 24 |
| Peak memory | 555400 kb |
| Host | smart-6e38418d-2d1a-4770-9da2-f7c4cad44df6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210477902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.4210477902 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random.1521939349 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 360112823 ps |
| CPU time | 33.77 seconds |
| Started | Feb 07 04:11:42 PM PST 24 |
| Finished | Feb 07 04:12:16 PM PST 24 |
| Peak memory | 555672 kb |
| Host | smart-1e9d3f37-2be4-46af-9e67-3e03bcb6a36f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521939349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.1521939349 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.3662380845 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 19086364305 ps |
| CPU time | 189.94 seconds |
| Started | Feb 07 04:11:21 PM PST 24 |
| Finished | Feb 07 04:14:32 PM PST 24 |
| Peak memory | 555428 kb |
| Host | smart-cea1c60a-6f8f-42db-bef3-adbcf13096f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662380845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3662380845 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1530484058 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 11327234928 ps |
| CPU time | 202.45 seconds |
| Started | Feb 07 04:11:41 PM PST 24 |
| Finished | Feb 07 04:15:04 PM PST 24 |
| Peak memory | 555728 kb |
| Host | smart-c8ce8cf3-c206-4360-970a-74309b313031 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530484058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.1530484058 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.1068247937 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 272357507 ps |
| CPU time | 23.55 seconds |
| Started | Feb 07 04:11:43 PM PST 24 |
| Finished | Feb 07 04:12:07 PM PST 24 |
| Peak memory | 555412 kb |
| Host | smart-9412104c-b0b2-4a85-97dd-585aec74d315 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068247937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_dela ys.1068247937 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_same_source.3231173628 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 1681647058 ps |
| CPU time | 47.98 seconds |
| Started | Feb 07 04:11:45 PM PST 24 |
| Finished | Feb 07 04:12:33 PM PST 24 |
| Peak memory | 555064 kb |
| Host | smart-1be70552-5d70-4ca7-b505-38fe21f9e78a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231173628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.3231173628 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke.1945876820 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 135053226 ps |
| CPU time | 7.33 seconds |
| Started | Feb 07 04:11:30 PM PST 24 |
| Finished | Feb 07 04:11:38 PM PST 24 |
| Peak memory | 553276 kb |
| Host | smart-f356039a-2acc-443e-875e-4e62234520ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945876820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1945876820 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.2638070035 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 8783631251 ps |
| CPU time | 99.48 seconds |
| Started | Feb 07 04:11:38 PM PST 24 |
| Finished | Feb 07 04:13:18 PM PST 24 |
| Peak memory | 553416 kb |
| Host | smart-fa69493d-eab1-41be-8969-32c0deae9503 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638070035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2638070035 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.4220100933 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 5098332261 ps |
| CPU time | 86.5 seconds |
| Started | Feb 07 04:11:29 PM PST 24 |
| Finished | Feb 07 04:12:56 PM PST 24 |
| Peak memory | 553668 kb |
| Host | smart-aabd3525-7bf3-4014-9dce-e50d172756cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220100933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.4220100933 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.4140623482 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 50597079 ps |
| CPU time | 6.49 seconds |
| Started | Feb 07 04:11:41 PM PST 24 |
| Finished | Feb 07 04:11:48 PM PST 24 |
| Peak memory | 553260 kb |
| Host | smart-da08194c-e86a-459f-8591-e48a20e87114 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140623482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays .4140623482 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all.1423061741 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 9194867517 ps |
| CPU time | 368.2 seconds |
| Started | Feb 07 04:11:44 PM PST 24 |
| Finished | Feb 07 04:17:53 PM PST 24 |
| Peak memory | 557136 kb |
| Host | smart-3d5f6f04-f5c9-46e5-9eba-ada8d10eed9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423061741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.1423061741 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.634981839 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 7574166050 ps |
| CPU time | 279.47 seconds |
| Started | Feb 07 04:11:37 PM PST 24 |
| Finished | Feb 07 04:16:17 PM PST 24 |
| Peak memory | 556592 kb |
| Host | smart-d7610524-b066-4084-a050-551a97582580 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634981839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.634981839 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.752018060 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 327760997 ps |
| CPU time | 199.16 seconds |
| Started | Feb 07 04:11:40 PM PST 24 |
| Finished | Feb 07 04:15:00 PM PST 24 |
| Peak memory | 557588 kb |
| Host | smart-b61b448e-c845-4f51-8352-911b746eab28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752018060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_w ith_rand_reset.752018060 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.1701090915 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 3702475879 ps |
| CPU time | 481.88 seconds |
| Started | Feb 07 04:11:43 PM PST 24 |
| Finished | Feb 07 04:19:45 PM PST 24 |
| Peak memory | 567660 kb |
| Host | smart-7b4defca-1113-43a5-8d81-3934e6d31cf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701090915 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all _with_reset_error.1701090915 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.1208596760 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 458106778 ps |
| CPU time | 20.93 seconds |
| Started | Feb 07 04:11:39 PM PST 24 |
| Finished | Feb 07 04:12:01 PM PST 24 |
| Peak memory | 555204 kb |
| Host | smart-2530983f-4b82-4a6d-8ae9-13eabdbc37a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208596760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.1208596760 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.473233577 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 5180122616 ps |
| CPU time | 196.14 seconds |
| Started | Feb 07 04:12:06 PM PST 24 |
| Finished | Feb 07 04:15:23 PM PST 24 |
| Peak memory | 613180 kb |
| Host | smart-fc397055-0105-4e02-8e18-85ee6cb0dbfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473233577 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 10.chip_csr_mem_rw_with_rand_reset.473233577 |
| Directory | /workspace/10.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_rw.172521936 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 4426349282 ps |
| CPU time | 249.98 seconds |
| Started | Feb 07 04:12:09 PM PST 24 |
| Finished | Feb 07 04:16:19 PM PST 24 |
| Peak memory | 580980 kb |
| Host | smart-ded39309-bdf8-4629-aabf-fe8079a40351 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172521936 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.172521936 |
| Directory | /workspace/10.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_tl_errors.3738633881 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 3148475641 ps |
| CPU time | 139.93 seconds |
| Started | Feb 07 04:12:07 PM PST 24 |
| Finished | Feb 07 04:14:27 PM PST 24 |
| Peak memory | 580340 kb |
| Host | smart-db9f87f3-bab0-4d95-9f70-2e29373a5c87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738633881 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.3738633881 |
| Directory | /workspace/10.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device.1007946746 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 397874428 ps |
| CPU time | 35.58 seconds |
| Started | Feb 07 04:12:07 PM PST 24 |
| Finished | Feb 07 04:12:43 PM PST 24 |
| Peak memory | 555096 kb |
| Host | smart-93cb3e66-b1c0-423b-af92-a673cff32cd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007946746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device .1007946746 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1988163521 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 84192942365 ps |
| CPU time | 1544.83 seconds |
| Started | Feb 07 04:12:11 PM PST 24 |
| Finished | Feb 07 04:37:57 PM PST 24 |
| Peak memory | 555216 kb |
| Host | smart-285fcd0c-69ab-4338-a11d-bd5dfd414a78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988163521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_ device_slow_rsp.1988163521 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.125809825 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 259855001 ps |
| CPU time | 30.08 seconds |
| Started | Feb 07 04:12:11 PM PST 24 |
| Finished | Feb 07 04:12:41 PM PST 24 |
| Peak memory | 555656 kb |
| Host | smart-388634dc-8001-43ff-aae3-18f2bb61f9ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125809825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr .125809825 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_random.2091991229 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 33526498 ps |
| CPU time | 5.57 seconds |
| Started | Feb 07 04:12:11 PM PST 24 |
| Finished | Feb 07 04:12:17 PM PST 24 |
| Peak memory | 553268 kb |
| Host | smart-f4c4e954-e5e0-4701-9578-a991543f3047 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091991229 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2091991229 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random.545820719 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 2210951526 ps |
| CPU time | 82.17 seconds |
| Started | Feb 07 04:12:02 PM PST 24 |
| Finished | Feb 07 04:13:25 PM PST 24 |
| Peak memory | 555720 kb |
| Host | smart-eab17206-13ce-4fe0-a713-d2ac64b158b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545820719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.545820719 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.2129756676 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 80390570677 ps |
| CPU time | 878.01 seconds |
| Started | Feb 07 04:12:07 PM PST 24 |
| Finished | Feb 07 04:26:45 PM PST 24 |
| Peak memory | 559264 kb |
| Host | smart-5c8f8811-4c3e-469b-af47-a3fba2bbfc71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129756676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.2129756676 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.388526849 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 26782405982 ps |
| CPU time | 439.1 seconds |
| Started | Feb 07 04:12:11 PM PST 24 |
| Finished | Feb 07 04:19:31 PM PST 24 |
| Peak memory | 555468 kb |
| Host | smart-9e917ef9-fb2c-4ef3-baea-4923bfffcec3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388526849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.388526849 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.929861565 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 103511805 ps |
| CPU time | 11.29 seconds |
| Started | Feb 07 04:12:11 PM PST 24 |
| Finished | Feb 07 04:12:22 PM PST 24 |
| Peak memory | 555664 kb |
| Host | smart-d84a0e17-59f2-42ef-95d1-bd9bf21c59df |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929861565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_dela ys.929861565 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_same_source.3573631766 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 508329358 ps |
| CPU time | 33.95 seconds |
| Started | Feb 07 04:12:06 PM PST 24 |
| Finished | Feb 07 04:12:41 PM PST 24 |
| Peak memory | 555636 kb |
| Host | smart-ef38027e-bc1a-4820-a491-292f3e040905 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573631766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3573631766 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke.3887602365 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 47972256 ps |
| CPU time | 6.27 seconds |
| Started | Feb 07 04:12:11 PM PST 24 |
| Finished | Feb 07 04:12:18 PM PST 24 |
| Peak memory | 553296 kb |
| Host | smart-ad02e6f8-b34d-42cd-a0af-42ee06b14d7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887602365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.3887602365 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3967381742 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 9710246702 ps |
| CPU time | 89.33 seconds |
| Started | Feb 07 04:12:07 PM PST 24 |
| Finished | Feb 07 04:13:37 PM PST 24 |
| Peak memory | 553648 kb |
| Host | smart-20ac80fe-937e-4f33-9f25-5490d106d71c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967381742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3967381742 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.3881546143 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 4566204789 ps |
| CPU time | 87.14 seconds |
| Started | Feb 07 04:12:07 PM PST 24 |
| Finished | Feb 07 04:13:34 PM PST 24 |
| Peak memory | 553060 kb |
| Host | smart-bcfcdeab-8c7b-418d-8537-bef45a7f4025 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881546143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3881546143 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1228064927 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 35597597 ps |
| CPU time | 5.42 seconds |
| Started | Feb 07 04:12:05 PM PST 24 |
| Finished | Feb 07 04:12:11 PM PST 24 |
| Peak memory | 553588 kb |
| Host | smart-0c4dca7a-a62f-4540-9218-93c211c28196 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228064927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delay s.1228064927 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all.2618091970 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 3782659122 ps |
| CPU time | 325.78 seconds |
| Started | Feb 07 04:12:09 PM PST 24 |
| Finished | Feb 07 04:17:35 PM PST 24 |
| Peak memory | 557604 kb |
| Host | smart-7bfc3359-e69d-4a99-87c3-fb480f9e9b8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618091970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.2618091970 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.1534937717 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 1977663154 ps |
| CPU time | 68 seconds |
| Started | Feb 07 04:12:12 PM PST 24 |
| Finished | Feb 07 04:13:20 PM PST 24 |
| Peak memory | 555400 kb |
| Host | smart-747b656b-359d-4065-93de-40a14b4a03ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534937717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.1534937717 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2106319924 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 2242283808 ps |
| CPU time | 189.8 seconds |
| Started | Feb 07 04:12:11 PM PST 24 |
| Finished | Feb 07 04:15:21 PM PST 24 |
| Peak memory | 556940 kb |
| Host | smart-56da2336-c219-407e-9181-683df982b549 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106319924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all _with_rand_reset.2106319924 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.826451331 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 2898843915 ps |
| CPU time | 388.55 seconds |
| Started | Feb 07 04:12:11 PM PST 24 |
| Finished | Feb 07 04:18:40 PM PST 24 |
| Peak memory | 567636 kb |
| Host | smart-2eb142d2-983d-4697-b105-ed7b48821cdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826451331 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all _with_reset_error.826451331 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.4212355313 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 347224497 ps |
| CPU time | 14.84 seconds |
| Started | Feb 07 04:12:06 PM PST 24 |
| Finished | Feb 07 04:12:22 PM PST 24 |
| Peak memory | 555656 kb |
| Host | smart-6f26348a-76ff-4939-a7e3-7984c53f5666 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212355313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.4212355313 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.2136189288 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 9998426283 ps |
| CPU time | 371.4 seconds |
| Started | Feb 07 04:12:25 PM PST 24 |
| Finished | Feb 07 04:18:40 PM PST 24 |
| Peak memory | 628588 kb |
| Host | smart-d21a5be6-76ad-49c3-a218-a6480893a772 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136189288 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 11.chip_csr_mem_rw_with_rand_reset.2136189288 |
| Directory | /workspace/11.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_rw.2746989253 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 5148320300 ps |
| CPU time | 538.71 seconds |
| Started | Feb 07 04:12:35 PM PST 24 |
| Finished | Feb 07 04:21:35 PM PST 24 |
| Peak memory | 581424 kb |
| Host | smart-c66b3b0f-dccd-406d-9268-74ee0efb5e6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746989253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.2746989253 |
| Directory | /workspace/11.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.2728145344 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 28231714893 ps |
| CPU time | 3613.02 seconds |
| Started | Feb 07 04:12:09 PM PST 24 |
| Finished | Feb 07 05:12:22 PM PST 24 |
| Peak memory | 580292 kb |
| Host | smart-98dfb8cf-4ce3-41b1-8829-6e9355f3c87a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728145344 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 11.chip_same_csr_outstanding.2728145344 |
| Directory | /workspace/11.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_tl_errors.23826490 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 3720049175 ps |
| CPU time | 308.41 seconds |
| Started | Feb 07 04:12:08 PM PST 24 |
| Finished | Feb 07 04:17:17 PM PST 24 |
| Peak memory | 580364 kb |
| Host | smart-ac99c443-2401-410a-8e9e-f31d62b37e16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23826490 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.23826490 |
| Directory | /workspace/11.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device.179760236 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 2414604944 ps |
| CPU time | 111.74 seconds |
| Started | Feb 07 04:12:26 PM PST 24 |
| Finished | Feb 07 04:14:20 PM PST 24 |
| Peak memory | 555412 kb |
| Host | smart-0f094483-ba99-48e0-a860-b6dd8ea53d65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179760236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device. 179760236 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.9322737 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 40569333882 ps |
| CPU time | 674.66 seconds |
| Started | Feb 07 04:12:21 PM PST 24 |
| Finished | Feb 07 04:23:36 PM PST 24 |
| Peak memory | 555720 kb |
| Host | smart-24e6f149-3044-4164-84d0-9e0eaf151662 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9322737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_dev ice_slow_rsp.9322737 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.818520767 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 201763463 ps |
| CPU time | 18.46 seconds |
| Started | Feb 07 04:12:36 PM PST 24 |
| Finished | Feb 07 04:12:55 PM PST 24 |
| Peak memory | 555340 kb |
| Host | smart-788ef767-9833-4621-9109-b814db957f22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818520767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr .818520767 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_random.2346699999 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 1282037766 ps |
| CPU time | 37.77 seconds |
| Started | Feb 07 04:12:22 PM PST 24 |
| Finished | Feb 07 04:13:00 PM PST 24 |
| Peak memory | 555652 kb |
| Host | smart-2ed1d796-e1c1-4d49-938a-4e45454e35e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346699999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2346699999 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random.130607046 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 490867754 ps |
| CPU time | 21.54 seconds |
| Started | Feb 07 04:12:15 PM PST 24 |
| Finished | Feb 07 04:12:37 PM PST 24 |
| Peak memory | 555396 kb |
| Host | smart-48d7665a-de33-4804-b376-9014fd4dff70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130607046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.130607046 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.2226631484 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 90823462959 ps |
| CPU time | 903.37 seconds |
| Started | Feb 07 04:12:16 PM PST 24 |
| Finished | Feb 07 04:27:20 PM PST 24 |
| Peak memory | 555364 kb |
| Host | smart-12a1c30a-eb18-4232-aa6b-d5d24fe01687 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226631484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.2226631484 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2045412429 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 45116823085 ps |
| CPU time | 806.39 seconds |
| Started | Feb 07 04:12:21 PM PST 24 |
| Finished | Feb 07 04:25:49 PM PST 24 |
| Peak memory | 559244 kb |
| Host | smart-074351d6-aec4-499a-93a7-b49190d49b29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045412429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.2045412429 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3616139516 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 282807594 ps |
| CPU time | 30.44 seconds |
| Started | Feb 07 04:12:15 PM PST 24 |
| Finished | Feb 07 04:12:45 PM PST 24 |
| Peak memory | 555380 kb |
| Host | smart-1a0c2ce1-4ea0-47a0-8cd6-a171194548a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616139516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_del ays.3616139516 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_same_source.861459713 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 1996517170 ps |
| CPU time | 61.79 seconds |
| Started | Feb 07 04:12:33 PM PST 24 |
| Finished | Feb 07 04:13:35 PM PST 24 |
| Peak memory | 555576 kb |
| Host | smart-c03901a5-91aa-47e1-a8d1-4f9965e86bee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861459713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.861459713 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke.1818905410 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 202351210 ps |
| CPU time | 8.7 seconds |
| Started | Feb 07 04:12:33 PM PST 24 |
| Finished | Feb 07 04:12:43 PM PST 24 |
| Peak memory | 553536 kb |
| Host | smart-41a967be-b7e6-4997-bebd-68eee9dac734 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818905410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.1818905410 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.3054930776 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 7343568499 ps |
| CPU time | 78.87 seconds |
| Started | Feb 07 04:12:14 PM PST 24 |
| Finished | Feb 07 04:13:33 PM PST 24 |
| Peak memory | 553368 kb |
| Host | smart-e6a16e8e-078b-4d35-a508-155c476956de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054930776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.3054930776 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3627923762 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 2435926310 ps |
| CPU time | 40.88 seconds |
| Started | Feb 07 04:12:23 PM PST 24 |
| Finished | Feb 07 04:13:05 PM PST 24 |
| Peak memory | 553332 kb |
| Host | smart-dbd7f91a-4130-461f-9405-cd2615c5602b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627923762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3627923762 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2989763746 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 35154857 ps |
| CPU time | 5.51 seconds |
| Started | Feb 07 04:12:35 PM PST 24 |
| Finished | Feb 07 04:12:42 PM PST 24 |
| Peak memory | 553572 kb |
| Host | smart-5b4880c6-53b1-4fa7-9247-93728c7fc0fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989763746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delay s.2989763746 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all.2999194242 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 683331295 ps |
| CPU time | 56.11 seconds |
| Started | Feb 07 04:12:12 PM PST 24 |
| Finished | Feb 07 04:13:09 PM PST 24 |
| Peak memory | 556672 kb |
| Host | smart-d8422621-413b-4868-87c4-1efedb2daa86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999194242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.2999194242 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.1115117517 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 102405071 ps |
| CPU time | 8.41 seconds |
| Started | Feb 07 04:12:09 PM PST 24 |
| Finished | Feb 07 04:12:17 PM PST 24 |
| Peak memory | 555640 kb |
| Host | smart-79a1d32e-ba59-4045-a0d6-23a9e1c22c8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115117517 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1115117517 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3792962455 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 190678576 ps |
| CPU time | 83.88 seconds |
| Started | Feb 07 04:12:27 PM PST 24 |
| Finished | Feb 07 04:13:52 PM PST 24 |
| Peak memory | 556580 kb |
| Host | smart-b831cce5-d717-496e-8c76-ffb9dcae9e08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792962455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_rand_reset.3792962455 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.132180977 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 749293994 ps |
| CPU time | 279.14 seconds |
| Started | Feb 07 04:12:37 PM PST 24 |
| Finished | Feb 07 04:17:17 PM PST 24 |
| Peak memory | 559360 kb |
| Host | smart-ed95f7c0-ba0d-4b91-85fe-87b200431d6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132180977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_reset_error.132180977 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.4159648525 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 122050886 ps |
| CPU time | 17.87 seconds |
| Started | Feb 07 04:12:26 PM PST 24 |
| Finished | Feb 07 04:12:46 PM PST 24 |
| Peak memory | 555420 kb |
| Host | smart-d930c4c4-33b0-4adb-8225-0a1abffca6a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159648525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.4159648525 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.3106950202 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 6487282348 ps |
| CPU time | 321.55 seconds |
| Started | Feb 07 04:12:20 PM PST 24 |
| Finished | Feb 07 04:17:41 PM PST 24 |
| Peak memory | 631488 kb |
| Host | smart-1ca5d7fd-d6d5-4171-b9a2-1e0458d4190b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106950202 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 12.chip_csr_mem_rw_with_rand_reset.3106950202 |
| Directory | /workspace/12.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_rw.1290744395 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 6078001354 ps |
| CPU time | 608.2 seconds |
| Started | Feb 07 04:12:19 PM PST 24 |
| Finished | Feb 07 04:22:27 PM PST 24 |
| Peak memory | 581140 kb |
| Host | smart-f230d46c-ee3c-4aa3-9b13-8efeae9433a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290744395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.1290744395 |
| Directory | /workspace/12.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.386961815 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 15070569742 ps |
| CPU time | 2104.21 seconds |
| Started | Feb 07 04:12:12 PM PST 24 |
| Finished | Feb 07 04:47:17 PM PST 24 |
| Peak memory | 580236 kb |
| Host | smart-c714e5ed-9ecd-4869-be67-34169fcf13c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386961815 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 12.chip_same_csr_outstanding.386961815 |
| Directory | /workspace/12.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device.642786844 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 1902003597 ps |
| CPU time | 82.76 seconds |
| Started | Feb 07 04:12:15 PM PST 24 |
| Finished | Feb 07 04:13:38 PM PST 24 |
| Peak memory | 555396 kb |
| Host | smart-c607c9ce-8a73-462d-b7e7-822abafe0e4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642786844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device. 642786844 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2309648722 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 63349692471 ps |
| CPU time | 971.07 seconds |
| Started | Feb 07 04:12:16 PM PST 24 |
| Finished | Feb 07 04:28:28 PM PST 24 |
| Peak memory | 556784 kb |
| Host | smart-afeed379-0480-4202-972d-ae4df4244562 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309648722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_ device_slow_rsp.2309648722 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2493173007 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 204053296 ps |
| CPU time | 10.45 seconds |
| Started | Feb 07 04:12:26 PM PST 24 |
| Finished | Feb 07 04:12:39 PM PST 24 |
| Peak memory | 554048 kb |
| Host | smart-4de190b6-22e9-4d78-850b-ccf4fd1d8932 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493173007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_add r.2493173007 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_random.4190360528 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 1026380830 ps |
| CPU time | 33.9 seconds |
| Started | Feb 07 04:12:38 PM PST 24 |
| Finished | Feb 07 04:13:17 PM PST 24 |
| Peak memory | 555380 kb |
| Host | smart-4e5041ea-6c52-48a6-a696-45629a2e4791 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190360528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.4190360528 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random.1484488628 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 1263354649 ps |
| CPU time | 47.15 seconds |
| Started | Feb 07 04:12:18 PM PST 24 |
| Finished | Feb 07 04:13:05 PM PST 24 |
| Peak memory | 555464 kb |
| Host | smart-567fc75f-1d1f-4987-abd2-84f582858fec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484488628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.1484488628 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.999966423 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 76960915437 ps |
| CPU time | 831.07 seconds |
| Started | Feb 07 04:12:35 PM PST 24 |
| Finished | Feb 07 04:26:27 PM PST 24 |
| Peak memory | 555424 kb |
| Host | smart-f395f7d0-8d9a-401b-98c4-a672c8a443d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999966423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.999966423 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.3521660370 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 64500239124 ps |
| CPU time | 1064.7 seconds |
| Started | Feb 07 04:12:16 PM PST 24 |
| Finished | Feb 07 04:30:02 PM PST 24 |
| Peak memory | 555708 kb |
| Host | smart-d1fbb699-7175-4a32-bd11-55b37873920d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521660370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.3521660370 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.3354654513 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 233012101 ps |
| CPU time | 23.65 seconds |
| Started | Feb 07 04:12:19 PM PST 24 |
| Finished | Feb 07 04:12:43 PM PST 24 |
| Peak memory | 555652 kb |
| Host | smart-eaade7f4-1638-477c-81d0-5f264d39e515 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354654513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_del ays.3354654513 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_same_source.1903084973 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 417767163 ps |
| CPU time | 33.84 seconds |
| Started | Feb 07 04:12:27 PM PST 24 |
| Finished | Feb 07 04:13:02 PM PST 24 |
| Peak memory | 555308 kb |
| Host | smart-d107a939-0339-4d3f-ba20-ee536e6215da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903084973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.1903084973 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke.466829536 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 48775742 ps |
| CPU time | 6.33 seconds |
| Started | Feb 07 04:12:15 PM PST 24 |
| Finished | Feb 07 04:12:22 PM PST 24 |
| Peak memory | 553580 kb |
| Host | smart-12f08a82-813b-4c0b-9017-c8e01ca63561 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466829536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.466829536 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.1031218384 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 7597360279 ps |
| CPU time | 79.3 seconds |
| Started | Feb 07 04:12:16 PM PST 24 |
| Finished | Feb 07 04:13:36 PM PST 24 |
| Peak memory | 553264 kb |
| Host | smart-3c14eebf-81d9-45d4-af27-23ea6889bc55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031218384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.1031218384 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.703656254 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 5575882106 ps |
| CPU time | 93.91 seconds |
| Started | Feb 07 04:12:36 PM PST 24 |
| Finished | Feb 07 04:14:10 PM PST 24 |
| Peak memory | 553104 kb |
| Host | smart-7babe14a-8be3-40b6-8ec6-c1d0d44acc83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703656254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.703656254 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1358132505 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 55357955 ps |
| CPU time | 6.26 seconds |
| Started | Feb 07 04:12:35 PM PST 24 |
| Finished | Feb 07 04:12:42 PM PST 24 |
| Peak memory | 553304 kb |
| Host | smart-d64663ca-c8fb-4282-8586-ae09f6ef30fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358132505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delay s.1358132505 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all.1087500490 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 2877859589 ps |
| CPU time | 237.36 seconds |
| Started | Feb 07 04:12:23 PM PST 24 |
| Finished | Feb 07 04:16:21 PM PST 24 |
| Peak memory | 556672 kb |
| Host | smart-96c05b23-0a03-463b-b2a8-fbe3a9b67f21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087500490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.1087500490 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.3811322671 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 2672303573 ps |
| CPU time | 200.16 seconds |
| Started | Feb 07 04:12:26 PM PST 24 |
| Finished | Feb 07 04:15:49 PM PST 24 |
| Peak memory | 556540 kb |
| Host | smart-e9e7804c-c0d7-4100-8914-da83aa65836e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811322671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.3811322671 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1203539653 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 2246927353 ps |
| CPU time | 391.04 seconds |
| Started | Feb 07 04:12:35 PM PST 24 |
| Finished | Feb 07 04:19:07 PM PST 24 |
| Peak memory | 558964 kb |
| Host | smart-b3cee2df-135d-4d11-9267-6e5adcbbc40d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203539653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all _with_rand_reset.1203539653 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.372821120 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 692893492 ps |
| CPU time | 200.47 seconds |
| Started | Feb 07 04:12:24 PM PST 24 |
| Finished | Feb 07 04:15:49 PM PST 24 |
| Peak memory | 559320 kb |
| Host | smart-0cc3b242-d20d-4d86-b81c-5fbcbb58f572 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372821120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all _with_reset_error.372821120 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.70880406 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 233106769 ps |
| CPU time | 12.29 seconds |
| Started | Feb 07 04:12:15 PM PST 24 |
| Finished | Feb 07 04:12:28 PM PST 24 |
| Peak memory | 554664 kb |
| Host | smart-96d63fbe-75a0-45e0-a096-b9c29ec546a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70880406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.70880406 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.1422005744 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 4378250330 ps |
| CPU time | 209.71 seconds |
| Started | Feb 07 04:12:39 PM PST 24 |
| Finished | Feb 07 04:16:13 PM PST 24 |
| Peak memory | 615104 kb |
| Host | smart-2d88b1ef-eadb-43d3-a180-30d72194dec7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422005744 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 13.chip_csr_mem_rw_with_rand_reset.1422005744 |
| Directory | /workspace/13.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_rw.411446980 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 3974854400 ps |
| CPU time | 380.28 seconds |
| Started | Feb 07 04:12:36 PM PST 24 |
| Finished | Feb 07 04:18:58 PM PST 24 |
| Peak memory | 579488 kb |
| Host | smart-18b010b9-09d4-4d93-b2a7-8767d6b21fc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411446980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.411446980 |
| Directory | /workspace/13.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.633392506 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 16753487508 ps |
| CPU time | 2578.42 seconds |
| Started | Feb 07 04:12:19 PM PST 24 |
| Finished | Feb 07 04:55:18 PM PST 24 |
| Peak memory | 575220 kb |
| Host | smart-9ece149d-2a28-4d03-afaa-2a107691e979 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633392506 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 13.chip_same_csr_outstanding.633392506 |
| Directory | /workspace/13.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_tl_errors.1883577516 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 4019891276 ps |
| CPU time | 267.4 seconds |
| Started | Feb 07 04:12:33 PM PST 24 |
| Finished | Feb 07 04:17:01 PM PST 24 |
| Peak memory | 580300 kb |
| Host | smart-e51e2af1-81b7-4923-8b32-93f51910a194 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883577516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.1883577516 |
| Directory | /workspace/13.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device.2431007598 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 314899773 ps |
| CPU time | 23.21 seconds |
| Started | Feb 07 04:12:16 PM PST 24 |
| Finished | Feb 07 04:12:40 PM PST 24 |
| Peak memory | 555632 kb |
| Host | smart-4da37bab-8ab4-446f-b668-0301d4d8512a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431007598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device .2431007598 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.740539345 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 63825137905 ps |
| CPU time | 1090.45 seconds |
| Started | Feb 07 04:12:35 PM PST 24 |
| Finished | Feb 07 04:30:47 PM PST 24 |
| Peak memory | 556472 kb |
| Host | smart-28d5532d-51f7-4366-89bf-5fa4158699c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740539345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_d evice_slow_rsp.740539345 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3106466469 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 995563283 ps |
| CPU time | 42.1 seconds |
| Started | Feb 07 04:12:15 PM PST 24 |
| Finished | Feb 07 04:12:58 PM PST 24 |
| Peak memory | 555588 kb |
| Host | smart-d880aa4c-5c1a-424a-9681-a785701ccea1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106466469 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_add r.3106466469 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_random.3972904249 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 192218789 ps |
| CPU time | 10.52 seconds |
| Started | Feb 07 04:12:38 PM PST 24 |
| Finished | Feb 07 04:12:53 PM PST 24 |
| Peak memory | 553356 kb |
| Host | smart-75628982-03bd-4efd-8984-afde6e9b32a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972904249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3972904249 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random.903284139 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 984549242 ps |
| CPU time | 33.07 seconds |
| Started | Feb 07 04:12:35 PM PST 24 |
| Finished | Feb 07 04:13:09 PM PST 24 |
| Peak memory | 555120 kb |
| Host | smart-1af2cd3c-1a30-4042-8924-000dd1cb096d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903284139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.903284139 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.3342182946 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 72582636823 ps |
| CPU time | 782.68 seconds |
| Started | Feb 07 04:12:35 PM PST 24 |
| Finished | Feb 07 04:25:39 PM PST 24 |
| Peak memory | 555744 kb |
| Host | smart-411b99f6-aa2a-425a-b057-b538ea5dba61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342182946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3342182946 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.2656653479 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 62613090787 ps |
| CPU time | 1161.01 seconds |
| Started | Feb 07 04:12:33 PM PST 24 |
| Finished | Feb 07 04:31:55 PM PST 24 |
| Peak memory | 555676 kb |
| Host | smart-7b6a7e52-f820-49d6-a7d7-07453510ced4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656653479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2656653479 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.278955611 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 439787508 ps |
| CPU time | 41.51 seconds |
| Started | Feb 07 04:12:26 PM PST 24 |
| Finished | Feb 07 04:13:10 PM PST 24 |
| Peak memory | 555136 kb |
| Host | smart-eee1540a-9f73-44ab-99aa-69f3179eb47c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278955611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_dela ys.278955611 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_same_source.1738202989 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 2466089296 ps |
| CPU time | 61.8 seconds |
| Started | Feb 07 04:12:36 PM PST 24 |
| Finished | Feb 07 04:13:38 PM PST 24 |
| Peak memory | 555436 kb |
| Host | smart-d35ec2b0-3529-4df3-9a95-080645db370d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738202989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1738202989 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke.1326536151 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 165949746 ps |
| CPU time | 8.42 seconds |
| Started | Feb 07 04:12:18 PM PST 24 |
| Finished | Feb 07 04:12:27 PM PST 24 |
| Peak memory | 553592 kb |
| Host | smart-c242d656-4746-42d8-b56d-9e4d77b9fe77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326536151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1326536151 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3801263762 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 7317670281 ps |
| CPU time | 74.98 seconds |
| Started | Feb 07 04:12:19 PM PST 24 |
| Finished | Feb 07 04:13:34 PM PST 24 |
| Peak memory | 553392 kb |
| Host | smart-4ddec6e4-09f5-4cf4-993a-614b6265ed84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801263762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.3801263762 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.3245733789 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 4262708456 ps |
| CPU time | 67.8 seconds |
| Started | Feb 07 04:12:22 PM PST 24 |
| Finished | Feb 07 04:13:31 PM PST 24 |
| Peak memory | 553672 kb |
| Host | smart-846846cf-db13-49c0-829d-f264d61bee8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245733789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.3245733789 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.2513411443 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 42258055 ps |
| CPU time | 6.04 seconds |
| Started | Feb 07 04:12:21 PM PST 24 |
| Finished | Feb 07 04:12:27 PM PST 24 |
| Peak memory | 553584 kb |
| Host | smart-08aa8b18-644a-4703-bcc2-2e930a6bb264 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513411443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delay s.2513411443 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all.2496949667 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 3740365397 ps |
| CPU time | 167.11 seconds |
| Started | Feb 07 04:12:25 PM PST 24 |
| Finished | Feb 07 04:15:16 PM PST 24 |
| Peak memory | 556844 kb |
| Host | smart-32338793-e2aa-41b7-8921-99620b79ea1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496949667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.2496949667 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.4264713854 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 452118104 ps |
| CPU time | 216.51 seconds |
| Started | Feb 07 04:12:37 PM PST 24 |
| Finished | Feb 07 04:16:15 PM PST 24 |
| Peak memory | 556956 kb |
| Host | smart-5020139c-2fb6-4a92-b912-48ca80f0782d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264713854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all _with_rand_reset.4264713854 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.4011975409 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 88602396 ps |
| CPU time | 14.86 seconds |
| Started | Feb 07 04:12:25 PM PST 24 |
| Finished | Feb 07 04:12:43 PM PST 24 |
| Peak memory | 555472 kb |
| Host | smart-0a71137c-28f2-442a-aa4c-391d2e958b8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011975409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.4011975409 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.283339530 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 5526426790 ps |
| CPU time | 271.14 seconds |
| Started | Feb 07 04:12:36 PM PST 24 |
| Finished | Feb 07 04:17:08 PM PST 24 |
| Peak memory | 631524 kb |
| Host | smart-6fc231ea-faca-4cf4-991b-4c0905ca37b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283339530 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 14.chip_csr_mem_rw_with_rand_reset.283339530 |
| Directory | /workspace/14.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.2718855716 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 27786314919 ps |
| CPU time | 3700.42 seconds |
| Started | Feb 07 04:12:38 PM PST 24 |
| Finished | Feb 07 05:14:24 PM PST 24 |
| Peak memory | 575560 kb |
| Host | smart-96b6a711-2aca-41ec-b573-a55ff97dbb14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718855716 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 14.chip_same_csr_outstanding.2718855716 |
| Directory | /workspace/14.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device.2590611419 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 1160081071 ps |
| CPU time | 84.34 seconds |
| Started | Feb 07 04:12:35 PM PST 24 |
| Finished | Feb 07 04:14:00 PM PST 24 |
| Peak memory | 559208 kb |
| Host | smart-ae2543e7-4306-44f4-a885-a606d24c20e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590611419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device .2590611419 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1353247785 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 35155267264 ps |
| CPU time | 615.31 seconds |
| Started | Feb 07 04:12:36 PM PST 24 |
| Finished | Feb 07 04:22:52 PM PST 24 |
| Peak memory | 555748 kb |
| Host | smart-11f2e0a6-9b80-4ab8-8bb7-61d88b74b634 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353247785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_ device_slow_rsp.1353247785 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.2141039676 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 86620512 ps |
| CPU time | 12.01 seconds |
| Started | Feb 07 04:12:40 PM PST 24 |
| Finished | Feb 07 04:12:55 PM PST 24 |
| Peak memory | 555608 kb |
| Host | smart-fd186d75-e861-4a80-9683-8afcfa5bc879 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141039676 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_add r.2141039676 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_random.2571011295 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 1132362090 ps |
| CPU time | 39.8 seconds |
| Started | Feb 07 04:12:36 PM PST 24 |
| Finished | Feb 07 04:13:17 PM PST 24 |
| Peak memory | 555624 kb |
| Host | smart-a74e8164-f3a0-4702-85f5-8f0aebe9a74f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571011295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2571011295 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random.399022923 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 468135665 ps |
| CPU time | 40.5 seconds |
| Started | Feb 07 04:12:40 PM PST 24 |
| Finished | Feb 07 04:13:24 PM PST 24 |
| Peak memory | 559076 kb |
| Host | smart-9b9dd9e6-ee64-42e0-85ff-5c79532b8d35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399022923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.399022923 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.4108098967 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 62117266454 ps |
| CPU time | 709.01 seconds |
| Started | Feb 07 04:12:26 PM PST 24 |
| Finished | Feb 07 04:24:18 PM PST 24 |
| Peak memory | 555460 kb |
| Host | smart-9194f435-ffa0-41c6-9a38-9d317a3a62b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108098967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.4108098967 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.2142390474 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 39738080498 ps |
| CPU time | 737.67 seconds |
| Started | Feb 07 04:12:39 PM PST 24 |
| Finished | Feb 07 04:25:01 PM PST 24 |
| Peak memory | 555432 kb |
| Host | smart-e96357c4-109f-4fcb-8966-8a10d9514226 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142390474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.2142390474 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.2910838874 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 83427377 ps |
| CPU time | 10.67 seconds |
| Started | Feb 07 04:12:27 PM PST 24 |
| Finished | Feb 07 04:12:39 PM PST 24 |
| Peak memory | 555632 kb |
| Host | smart-cdd186c2-410b-495b-b1a2-11f6cbebee9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910838874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_del ays.2910838874 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_same_source.2772637913 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 2082592082 ps |
| CPU time | 62.18 seconds |
| Started | Feb 07 04:12:22 PM PST 24 |
| Finished | Feb 07 04:13:25 PM PST 24 |
| Peak memory | 555296 kb |
| Host | smart-8a07125b-ce7a-4ad5-9b26-6aa058545985 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772637913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.2772637913 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke.2830685490 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 54145401 ps |
| CPU time | 6.76 seconds |
| Started | Feb 07 04:12:35 PM PST 24 |
| Finished | Feb 07 04:12:43 PM PST 24 |
| Peak memory | 553044 kb |
| Host | smart-a0871e14-aca5-4d06-bbed-6f92d8f3e794 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830685490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.2830685490 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.2508583834 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 7078739757 ps |
| CPU time | 72.67 seconds |
| Started | Feb 07 04:12:39 PM PST 24 |
| Finished | Feb 07 04:13:56 PM PST 24 |
| Peak memory | 553312 kb |
| Host | smart-bdbeff65-fda9-40db-9e61-949c7ae1cb52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508583834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2508583834 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1672142924 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 4690722252 ps |
| CPU time | 82.41 seconds |
| Started | Feb 07 04:12:41 PM PST 24 |
| Finished | Feb 07 04:14:06 PM PST 24 |
| Peak memory | 553640 kb |
| Host | smart-359813d6-6e5b-4b6d-826b-b1df58e85dd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672142924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.1672142924 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.1844560433 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 57475994 ps |
| CPU time | 7.1 seconds |
| Started | Feb 07 04:12:40 PM PST 24 |
| Finished | Feb 07 04:12:51 PM PST 24 |
| Peak memory | 553272 kb |
| Host | smart-eb70c7af-9443-4aea-9bab-5aac7c0a5985 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844560433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delay s.1844560433 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all.2595369186 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 10905875535 ps |
| CPU time | 408.11 seconds |
| Started | Feb 07 04:12:32 PM PST 24 |
| Finished | Feb 07 04:19:21 PM PST 24 |
| Peak memory | 556644 kb |
| Host | smart-9b2ba91b-3d01-4b97-9a4b-58dfe96b2d78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595369186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2595369186 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.2240804084 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 940398443 ps |
| CPU time | 66.9 seconds |
| Started | Feb 07 04:12:22 PM PST 24 |
| Finished | Feb 07 04:13:30 PM PST 24 |
| Peak memory | 556752 kb |
| Host | smart-646eb288-e046-4847-bd67-e679e84f5abf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240804084 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.2240804084 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.3175534109 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 2522536785 ps |
| CPU time | 340.33 seconds |
| Started | Feb 07 04:12:28 PM PST 24 |
| Finished | Feb 07 04:18:09 PM PST 24 |
| Peak memory | 557816 kb |
| Host | smart-54ade178-42e0-49ad-a77a-430ea945c499 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175534109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all _with_rand_reset.3175534109 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.1264388593 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 500784308 ps |
| CPU time | 153.74 seconds |
| Started | Feb 07 04:12:37 PM PST 24 |
| Finished | Feb 07 04:15:12 PM PST 24 |
| Peak memory | 558192 kb |
| Host | smart-ca9b986d-73eb-4616-ba23-1614ea6cdff9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264388593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_al l_with_reset_error.1264388593 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.2695096264 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 322742482 ps |
| CPU time | 15.72 seconds |
| Started | Feb 07 04:12:23 PM PST 24 |
| Finished | Feb 07 04:12:39 PM PST 24 |
| Peak memory | 555396 kb |
| Host | smart-97e3eb64-83b0-4116-b028-685edf01082d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695096264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2695096264 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.2110089209 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 8059037608 ps |
| CPU time | 348.38 seconds |
| Started | Feb 07 04:12:35 PM PST 24 |
| Finished | Feb 07 04:18:24 PM PST 24 |
| Peak memory | 623356 kb |
| Host | smart-d0089eea-572f-4544-8ae7-dd20cc4bbb99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110089209 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 15.chip_csr_mem_rw_with_rand_reset.2110089209 |
| Directory | /workspace/15.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_rw.3472822888 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 5007483664 ps |
| CPU time | 374.41 seconds |
| Started | Feb 07 04:12:36 PM PST 24 |
| Finished | Feb 07 04:18:51 PM PST 24 |
| Peak memory | 580280 kb |
| Host | smart-6b7d64f0-3ab1-44a8-8815-5b19320f4c0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472822888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.3472822888 |
| Directory | /workspace/15.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.2111192640 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 15645275412 ps |
| CPU time | 1805.91 seconds |
| Started | Feb 07 04:12:35 PM PST 24 |
| Finished | Feb 07 04:42:42 PM PST 24 |
| Peak memory | 574088 kb |
| Host | smart-ef2d216b-4162-4e1c-933c-d019a0c7e629 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111192640 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.chip_same_csr_outstanding.2111192640 |
| Directory | /workspace/15.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device.3099200354 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 3058084506 ps |
| CPU time | 114.6 seconds |
| Started | Feb 07 04:12:38 PM PST 24 |
| Finished | Feb 07 04:14:38 PM PST 24 |
| Peak memory | 555700 kb |
| Host | smart-2bbb84f8-6168-41e3-a860-ef463e5216f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099200354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device .3099200354 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.2803170370 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 82703235175 ps |
| CPU time | 1407.79 seconds |
| Started | Feb 07 04:12:36 PM PST 24 |
| Finished | Feb 07 04:36:05 PM PST 24 |
| Peak memory | 555796 kb |
| Host | smart-85efc349-009e-4379-abb8-a727797a0d2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803170370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_ device_slow_rsp.2803170370 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.2745739341 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 222281330 ps |
| CPU time | 26.53 seconds |
| Started | Feb 07 04:12:33 PM PST 24 |
| Finished | Feb 07 04:13:00 PM PST 24 |
| Peak memory | 555328 kb |
| Host | smart-18445701-5cc3-4eb3-80a3-57f4426fa9b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745739341 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_add r.2745739341 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_random.3802022717 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 310002142 ps |
| CPU time | 27.83 seconds |
| Started | Feb 07 04:12:31 PM PST 24 |
| Finished | Feb 07 04:13:00 PM PST 24 |
| Peak memory | 555068 kb |
| Host | smart-6b11d550-5c59-4d7d-b734-c6992adc0e22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802022717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3802022717 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random.1072607926 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 646637931 ps |
| CPU time | 26.47 seconds |
| Started | Feb 07 04:12:26 PM PST 24 |
| Finished | Feb 07 04:12:55 PM PST 24 |
| Peak memory | 555136 kb |
| Host | smart-e5eee6c7-63e2-4a7d-8287-a282661c641e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072607926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.1072607926 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.2902880487 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 46982904316 ps |
| CPU time | 742.41 seconds |
| Started | Feb 07 04:12:37 PM PST 24 |
| Finished | Feb 07 04:25:01 PM PST 24 |
| Peak memory | 555704 kb |
| Host | smart-c48f3317-259f-439d-a7e8-d71453a866cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902880487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.2902880487 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.618063257 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 408764921 ps |
| CPU time | 37.45 seconds |
| Started | Feb 07 04:12:36 PM PST 24 |
| Finished | Feb 07 04:13:15 PM PST 24 |
| Peak memory | 555376 kb |
| Host | smart-25e9f0e5-14cd-4243-b553-be5acad6154d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618063257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_dela ys.618063257 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_same_source.2681475459 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 546128319 ps |
| CPU time | 41.83 seconds |
| Started | Feb 07 04:12:31 PM PST 24 |
| Finished | Feb 07 04:13:13 PM PST 24 |
| Peak memory | 555352 kb |
| Host | smart-39f08a1c-1fda-4e12-8e7c-aebcf64a997d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681475459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2681475459 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke.4140811654 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 41114649 ps |
| CPU time | 5.59 seconds |
| Started | Feb 07 04:12:38 PM PST 24 |
| Finished | Feb 07 04:12:48 PM PST 24 |
| Peak memory | 553604 kb |
| Host | smart-9b0a9d44-2f64-4dc4-b075-c64391ee12ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140811654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.4140811654 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.2081330994 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 7096454582 ps |
| CPU time | 71.23 seconds |
| Started | Feb 07 04:12:32 PM PST 24 |
| Finished | Feb 07 04:13:43 PM PST 24 |
| Peak memory | 553656 kb |
| Host | smart-24328c29-a008-4196-bb6b-45a7e4fc85c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081330994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.2081330994 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.3099183849 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 5852753675 ps |
| CPU time | 86.9 seconds |
| Started | Feb 07 04:12:35 PM PST 24 |
| Finished | Feb 07 04:14:02 PM PST 24 |
| Peak memory | 553684 kb |
| Host | smart-903e5848-6bd7-4cde-94d5-a602f6ff361c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099183849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.3099183849 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.3198282831 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 47205205 ps |
| CPU time | 5.78 seconds |
| Started | Feb 07 04:12:35 PM PST 24 |
| Finished | Feb 07 04:12:41 PM PST 24 |
| Peak memory | 553288 kb |
| Host | smart-a916cf08-d91f-4b89-a301-c860843fc22e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198282831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delay s.3198282831 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all.4245443167 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 12584949523 ps |
| CPU time | 492.56 seconds |
| Started | Feb 07 04:12:32 PM PST 24 |
| Finished | Feb 07 04:20:45 PM PST 24 |
| Peak memory | 558108 kb |
| Host | smart-03455662-3d92-455d-a43d-0b0d1447b70c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245443167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.4245443167 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.3544654125 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 264230350 ps |
| CPU time | 13.03 seconds |
| Started | Feb 07 04:12:33 PM PST 24 |
| Finished | Feb 07 04:12:47 PM PST 24 |
| Peak memory | 553040 kb |
| Host | smart-99577e90-47d5-43d7-990f-4cd93843fa36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544654125 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.3544654125 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.3691771601 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 7403579 ps |
| CPU time | 3.51 seconds |
| Started | Feb 07 04:12:40 PM PST 24 |
| Finished | Feb 07 04:12:47 PM PST 24 |
| Peak memory | 544612 kb |
| Host | smart-f67ef168-8461-406e-9395-8275d26f60b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691771601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_al l_with_reset_error.3691771601 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.3712145803 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 1327572868 ps |
| CPU time | 54.55 seconds |
| Started | Feb 07 04:12:39 PM PST 24 |
| Finished | Feb 07 04:13:38 PM PST 24 |
| Peak memory | 555672 kb |
| Host | smart-5bd1fc8b-c40e-45cc-b769-c5f99a73c9fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712145803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3712145803 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.576579642 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 5374418056 ps |
| CPU time | 210.46 seconds |
| Started | Feb 07 04:12:29 PM PST 24 |
| Finished | Feb 07 04:16:00 PM PST 24 |
| Peak memory | 615776 kb |
| Host | smart-8c854945-e1ee-45eb-b1e4-daffa903c132 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576579642 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 16.chip_csr_mem_rw_with_rand_reset.576579642 |
| Directory | /workspace/16.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_rw.2608206253 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 5351709744 ps |
| CPU time | 586.12 seconds |
| Started | Feb 07 04:12:42 PM PST 24 |
| Finished | Feb 07 04:22:30 PM PST 24 |
| Peak memory | 580756 kb |
| Host | smart-7d64689d-afba-4df3-af7b-b47379c3086f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608206253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.2608206253 |
| Directory | /workspace/16.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.4195449556 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 17780253002 ps |
| CPU time | 2713.75 seconds |
| Started | Feb 07 04:12:32 PM PST 24 |
| Finished | Feb 07 04:57:47 PM PST 24 |
| Peak memory | 580212 kb |
| Host | smart-dbc66af0-0001-441a-b679-e1c51a6b5449 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195449556 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.chip_same_csr_outstanding.4195449556 |
| Directory | /workspace/16.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_tl_errors.1066232168 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 2130275080 ps |
| CPU time | 86.45 seconds |
| Started | Feb 07 04:12:33 PM PST 24 |
| Finished | Feb 07 04:14:00 PM PST 24 |
| Peak memory | 580244 kb |
| Host | smart-ff25f109-db14-42a9-8772-09de3156b0f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066232168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.1066232168 |
| Directory | /workspace/16.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device.3683046687 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 2155484692 ps |
| CPU time | 96.58 seconds |
| Started | Feb 07 04:12:27 PM PST 24 |
| Finished | Feb 07 04:14:05 PM PST 24 |
| Peak memory | 555176 kb |
| Host | smart-9ba3ef20-f08b-4346-96b4-c813533c4272 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683046687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device .3683046687 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.3821397594 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 20645391815 ps |
| CPU time | 345.63 seconds |
| Started | Feb 07 04:12:31 PM PST 24 |
| Finished | Feb 07 04:18:18 PM PST 24 |
| Peak memory | 555680 kb |
| Host | smart-d2ad0fc8-397d-4e37-8b0a-691e78b9ae60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821397594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_ device_slow_rsp.3821397594 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.3061788556 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 194784415 ps |
| CPU time | 24.06 seconds |
| Started | Feb 07 04:12:31 PM PST 24 |
| Finished | Feb 07 04:12:56 PM PST 24 |
| Peak memory | 555124 kb |
| Host | smart-20e66548-909f-40be-b2b2-0a66d32eb342 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061788556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_add r.3061788556 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_random.2566430082 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 480140973 ps |
| CPU time | 16.24 seconds |
| Started | Feb 07 04:12:36 PM PST 24 |
| Finished | Feb 07 04:12:53 PM PST 24 |
| Peak memory | 555352 kb |
| Host | smart-76cfc9c2-a351-4896-9e86-25901ad0774a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566430082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.2566430082 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random.1215030242 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 2161162634 ps |
| CPU time | 87.04 seconds |
| Started | Feb 07 04:12:28 PM PST 24 |
| Finished | Feb 07 04:13:56 PM PST 24 |
| Peak memory | 555388 kb |
| Host | smart-974e648c-8ffb-45cb-a6f7-f606d2106ece |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215030242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.1215030242 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.1924904405 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 12865347918 ps |
| CPU time | 133.2 seconds |
| Started | Feb 07 04:12:36 PM PST 24 |
| Finished | Feb 07 04:14:51 PM PST 24 |
| Peak memory | 555440 kb |
| Host | smart-9493a7eb-f6d9-46fb-95a9-fb840d671b41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924904405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.1924904405 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.1417098591 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 3247684343 ps |
| CPU time | 58.28 seconds |
| Started | Feb 07 04:12:24 PM PST 24 |
| Finished | Feb 07 04:13:26 PM PST 24 |
| Peak memory | 553596 kb |
| Host | smart-d74848f5-6556-47f1-b935-c99e0b046245 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417098591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1417098591 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.4075445654 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 550884225 ps |
| CPU time | 52.72 seconds |
| Started | Feb 07 04:12:20 PM PST 24 |
| Finished | Feb 07 04:13:14 PM PST 24 |
| Peak memory | 555356 kb |
| Host | smart-0352b4a5-a40a-46cb-b0b6-27272e1f80ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075445654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_del ays.4075445654 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_same_source.2527072598 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 652318363 ps |
| CPU time | 19.77 seconds |
| Started | Feb 07 04:12:31 PM PST 24 |
| Finished | Feb 07 04:12:52 PM PST 24 |
| Peak memory | 555320 kb |
| Host | smart-21f091e9-ab8b-46c9-a709-561191f90bab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527072598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2527072598 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke.1289790284 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 178378074 ps |
| CPU time | 8.64 seconds |
| Started | Feb 07 04:12:33 PM PST 24 |
| Finished | Feb 07 04:12:42 PM PST 24 |
| Peak memory | 553300 kb |
| Host | smart-e91b97a8-2994-4777-a8fa-8ed968b12ead |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289790284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1289790284 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.3792940646 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 6231563935 ps |
| CPU time | 64.93 seconds |
| Started | Feb 07 04:12:32 PM PST 24 |
| Finished | Feb 07 04:13:37 PM PST 24 |
| Peak memory | 553360 kb |
| Host | smart-b21478ae-cf66-4bdc-b8cb-3e2cb71a51a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792940646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3792940646 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.916755216 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 5265948194 ps |
| CPU time | 90.01 seconds |
| Started | Feb 07 04:12:39 PM PST 24 |
| Finished | Feb 07 04:14:13 PM PST 24 |
| Peak memory | 553384 kb |
| Host | smart-c6eeae8e-4c82-4efc-b250-4b7f5046732c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916755216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.916755216 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.2014368369 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 42400757 ps |
| CPU time | 5.71 seconds |
| Started | Feb 07 04:12:23 PM PST 24 |
| Finished | Feb 07 04:12:29 PM PST 24 |
| Peak memory | 553276 kb |
| Host | smart-ad7eebac-51cc-485e-9c97-8314497f52d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014368369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delay s.2014368369 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all.93195033 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 8434573177 ps |
| CPU time | 351.6 seconds |
| Started | Feb 07 04:12:29 PM PST 24 |
| Finished | Feb 07 04:18:23 PM PST 24 |
| Peak memory | 557356 kb |
| Host | smart-90a216ca-d1c4-441a-90e0-54ee4120a255 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93195033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.93195033 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.1363887308 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 11223322261 ps |
| CPU time | 427.32 seconds |
| Started | Feb 07 04:12:28 PM PST 24 |
| Finished | Feb 07 04:19:37 PM PST 24 |
| Peak memory | 556868 kb |
| Host | smart-cd9d668b-81b2-4f44-a815-0ae538b15123 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363887308 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1363887308 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.3330324867 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 217792599 ps |
| CPU time | 134.41 seconds |
| Started | Feb 07 04:12:49 PM PST 24 |
| Finished | Feb 07 04:15:07 PM PST 24 |
| Peak memory | 557248 kb |
| Host | smart-c757f963-3cf2-4064-92c7-319ec0ba257a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330324867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all _with_rand_reset.3330324867 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.1544974394 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 8760581003 ps |
| CPU time | 843.35 seconds |
| Started | Feb 07 04:12:49 PM PST 24 |
| Finished | Feb 07 04:26:56 PM PST 24 |
| Peak memory | 567512 kb |
| Host | smart-4414371d-7699-43b3-af1a-028e4a8bfa64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544974394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_al l_with_reset_error.1544974394 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.3446314033 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 76763255 ps |
| CPU time | 5.85 seconds |
| Started | Feb 07 04:12:35 PM PST 24 |
| Finished | Feb 07 04:12:42 PM PST 24 |
| Peak memory | 553292 kb |
| Host | smart-abc9a1a8-fa79-4e4b-b8c7-26afb04d86a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446314033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.3446314033 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.4226068073 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 6572003965 ps |
| CPU time | 295.74 seconds |
| Started | Feb 07 04:12:54 PM PST 24 |
| Finished | Feb 07 04:17:52 PM PST 24 |
| Peak memory | 623300 kb |
| Host | smart-abcd3192-249c-476b-ad32-bb8194ce3dc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226068073 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 17.chip_csr_mem_rw_with_rand_reset.4226068073 |
| Directory | /workspace/17.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_rw.3547628576 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 3665816184 ps |
| CPU time | 246.19 seconds |
| Started | Feb 07 04:12:46 PM PST 24 |
| Finished | Feb 07 04:16:54 PM PST 24 |
| Peak memory | 580360 kb |
| Host | smart-8f811a86-a1ed-4355-a0b4-57a64dc979fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547628576 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.3547628576 |
| Directory | /workspace/17.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.1905316449 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 16530094044 ps |
| CPU time | 2580.41 seconds |
| Started | Feb 07 04:12:29 PM PST 24 |
| Finished | Feb 07 04:55:32 PM PST 24 |
| Peak memory | 580244 kb |
| Host | smart-8e4dd465-027d-4476-b6ba-9930d5e350f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905316449 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.chip_same_csr_outstanding.1905316449 |
| Directory | /workspace/17.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_tl_errors.930316670 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 3669981181 ps |
| CPU time | 223.06 seconds |
| Started | Feb 07 04:12:27 PM PST 24 |
| Finished | Feb 07 04:16:12 PM PST 24 |
| Peak memory | 580320 kb |
| Host | smart-b0a21226-b164-4bee-a484-d03c3133d53c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930316670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.930316670 |
| Directory | /workspace/17.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device.1241791524 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 1330900714 ps |
| CPU time | 49.19 seconds |
| Started | Feb 07 04:12:38 PM PST 24 |
| Finished | Feb 07 04:13:32 PM PST 24 |
| Peak memory | 556700 kb |
| Host | smart-4b49e326-0fbd-4129-ac8b-e605770e4fb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241791524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device .1241791524 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.3083594955 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 84126170964 ps |
| CPU time | 1425.6 seconds |
| Started | Feb 07 04:12:37 PM PST 24 |
| Finished | Feb 07 04:36:24 PM PST 24 |
| Peak memory | 556488 kb |
| Host | smart-5dec7cd6-e457-4b89-b0a7-d8dfbb9f34ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083594955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_ device_slow_rsp.3083594955 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.1534620536 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 1248814025 ps |
| CPU time | 50.47 seconds |
| Started | Feb 07 04:12:45 PM PST 24 |
| Finished | Feb 07 04:13:38 PM PST 24 |
| Peak memory | 555604 kb |
| Host | smart-afcac66b-eedc-4016-9844-9f48bc44ccd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534620536 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_add r.1534620536 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_random.3987039429 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 541968971 ps |
| CPU time | 42.73 seconds |
| Started | Feb 07 04:12:32 PM PST 24 |
| Finished | Feb 07 04:13:15 PM PST 24 |
| Peak memory | 555616 kb |
| Host | smart-8b4102c5-bf1c-450c-949e-109b76e47b7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987039429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3987039429 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random.1999822950 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 386262826 ps |
| CPU time | 31.05 seconds |
| Started | Feb 07 04:12:43 PM PST 24 |
| Finished | Feb 07 04:13:16 PM PST 24 |
| Peak memory | 555340 kb |
| Host | smart-55b207e6-de2b-4ea1-8c1e-bc743656a522 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999822950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.1999822950 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.3063126347 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 80146024203 ps |
| CPU time | 837.87 seconds |
| Started | Feb 07 04:12:49 PM PST 24 |
| Finished | Feb 07 04:26:50 PM PST 24 |
| Peak memory | 555416 kb |
| Host | smart-6eb3a3b2-30aa-4385-ae66-4109ec3bcca5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063126347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.3063126347 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.3239641985 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 7118164395 ps |
| CPU time | 124.13 seconds |
| Started | Feb 07 04:12:29 PM PST 24 |
| Finished | Feb 07 04:14:34 PM PST 24 |
| Peak memory | 559244 kb |
| Host | smart-934838da-47bd-45b8-9ce9-4f8b6983ccc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239641985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3239641985 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.2435173935 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 469044403 ps |
| CPU time | 34.98 seconds |
| Started | Feb 07 04:12:49 PM PST 24 |
| Finished | Feb 07 04:13:27 PM PST 24 |
| Peak memory | 555636 kb |
| Host | smart-b460fdb5-9a72-49fe-88c4-ebb9ef4eaafa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435173935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_del ays.2435173935 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_same_source.3002469154 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 289082801 ps |
| CPU time | 20.41 seconds |
| Started | Feb 07 04:12:44 PM PST 24 |
| Finished | Feb 07 04:13:07 PM PST 24 |
| Peak memory | 555296 kb |
| Host | smart-2f947de4-5cd7-44cc-aad1-6b30fdeb6cb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002469154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.3002469154 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke.4262195827 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 238466008 ps |
| CPU time | 9.99 seconds |
| Started | Feb 07 04:12:49 PM PST 24 |
| Finished | Feb 07 04:13:02 PM PST 24 |
| Peak memory | 559104 kb |
| Host | smart-3561eeb5-9422-43a2-9df5-bf6931b8487d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262195827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.4262195827 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.967126116 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 7332752332 ps |
| CPU time | 80.22 seconds |
| Started | Feb 07 04:12:49 PM PST 24 |
| Finished | Feb 07 04:14:12 PM PST 24 |
| Peak memory | 553164 kb |
| Host | smart-baeb1d27-a76c-46b7-8d3c-9b46ae5c6bf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967126116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.967126116 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.3340016879 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 4626285569 ps |
| CPU time | 84.08 seconds |
| Started | Feb 07 04:12:27 PM PST 24 |
| Finished | Feb 07 04:13:53 PM PST 24 |
| Peak memory | 553352 kb |
| Host | smart-ecf35696-7d96-4d17-b5ad-253cb61b06ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340016879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.3340016879 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.4110737926 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 39809655 ps |
| CPU time | 5.82 seconds |
| Started | Feb 07 04:12:44 PM PST 24 |
| Finished | Feb 07 04:12:52 PM PST 24 |
| Peak memory | 553544 kb |
| Host | smart-403ddff1-6e78-49cb-9f95-311f4d6ee457 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110737926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delay s.4110737926 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all.214333874 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 555114162 ps |
| CPU time | 49.22 seconds |
| Started | Feb 07 04:12:43 PM PST 24 |
| Finished | Feb 07 04:13:34 PM PST 24 |
| Peak memory | 556768 kb |
| Host | smart-b252c710-08e8-491a-aa9e-c15a0351a683 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214333874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.214333874 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.3623687744 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 6953552491 ps |
| CPU time | 247.51 seconds |
| Started | Feb 07 04:12:42 PM PST 24 |
| Finished | Feb 07 04:16:51 PM PST 24 |
| Peak memory | 556876 kb |
| Host | smart-f18217a4-f1a2-4a65-8b8b-84d566bc5e16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623687744 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3623687744 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.2068738494 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 5732943921 ps |
| CPU time | 384.26 seconds |
| Started | Feb 07 04:12:42 PM PST 24 |
| Finished | Feb 07 04:19:08 PM PST 24 |
| Peak memory | 559360 kb |
| Host | smart-807f6300-68b8-49f9-864c-b2783c7c7e3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068738494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_rand_reset.2068738494 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.3755826079 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 85126871 ps |
| CPU time | 12.5 seconds |
| Started | Feb 07 04:12:31 PM PST 24 |
| Finished | Feb 07 04:12:44 PM PST 24 |
| Peak memory | 555648 kb |
| Host | smart-6f08885d-b141-4b8a-82f3-4f0428046eb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755826079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.3755826079 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.1208667099 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 7970972596 ps |
| CPU time | 304.83 seconds |
| Started | Feb 07 04:13:09 PM PST 24 |
| Finished | Feb 07 04:18:15 PM PST 24 |
| Peak memory | 630272 kb |
| Host | smart-9207835f-81c4-43c5-9f50-3aa77c77197f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208667099 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 18.chip_csr_mem_rw_with_rand_reset.1208667099 |
| Directory | /workspace/18.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_rw.2141279196 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 4046188380 ps |
| CPU time | 272.57 seconds |
| Started | Feb 07 04:13:05 PM PST 24 |
| Finished | Feb 07 04:17:38 PM PST 24 |
| Peak memory | 580292 kb |
| Host | smart-1dc6eae4-2030-4ead-99e2-6b1e126f9ce1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141279196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.2141279196 |
| Directory | /workspace/18.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.1916340623 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 17174472392 ps |
| CPU time | 2042.77 seconds |
| Started | Feb 07 04:12:55 PM PST 24 |
| Finished | Feb 07 04:46:59 PM PST 24 |
| Peak memory | 575384 kb |
| Host | smart-780217bd-e992-45ce-a8c5-f8cf23637c20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916340623 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 18.chip_same_csr_outstanding.1916340623 |
| Directory | /workspace/18.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_tl_errors.2347678892 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 3234807351 ps |
| CPU time | 90.84 seconds |
| Started | Feb 07 04:12:41 PM PST 24 |
| Finished | Feb 07 04:14:14 PM PST 24 |
| Peak memory | 580280 kb |
| Host | smart-4e09f3c8-32f0-40ed-9306-bb1036548eb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347678892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.2347678892 |
| Directory | /workspace/18.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device.240899992 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 2642141718 ps |
| CPU time | 120.44 seconds |
| Started | Feb 07 04:12:54 PM PST 24 |
| Finished | Feb 07 04:14:56 PM PST 24 |
| Peak memory | 556756 kb |
| Host | smart-f62e9443-deb3-4f7d-9bdd-250f0ef8bf9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240899992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device. 240899992 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.1333450483 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 95628651680 ps |
| CPU time | 1692.49 seconds |
| Started | Feb 07 04:13:03 PM PST 24 |
| Finished | Feb 07 04:41:16 PM PST 24 |
| Peak memory | 555500 kb |
| Host | smart-6d2f1d65-7d12-4c6d-bf8f-957991da4f42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333450483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_ device_slow_rsp.1333450483 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.4173285604 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 880021044 ps |
| CPU time | 37.23 seconds |
| Started | Feb 07 04:12:59 PM PST 24 |
| Finished | Feb 07 04:13:37 PM PST 24 |
| Peak memory | 555628 kb |
| Host | smart-e49c36f7-5627-4f79-ad4f-936414e51e2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173285604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_add r.4173285604 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_random.2607271130 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 67105964 ps |
| CPU time | 8.57 seconds |
| Started | Feb 07 04:12:59 PM PST 24 |
| Finished | Feb 07 04:13:08 PM PST 24 |
| Peak memory | 553584 kb |
| Host | smart-847575ea-236e-415c-b03c-ec9660ced27c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607271130 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.2607271130 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random.3895849228 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 551468973 ps |
| CPU time | 22.52 seconds |
| Started | Feb 07 04:12:40 PM PST 24 |
| Finished | Feb 07 04:13:06 PM PST 24 |
| Peak memory | 555628 kb |
| Host | smart-627e52f3-62c7-4c97-8b9b-79f8522b73b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895849228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.3895849228 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.1977397334 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 97014527024 ps |
| CPU time | 1155.41 seconds |
| Started | Feb 07 04:13:00 PM PST 24 |
| Finished | Feb 07 04:32:16 PM PST 24 |
| Peak memory | 555408 kb |
| Host | smart-a0cc2238-d2f7-4ba5-a0ad-dfddc5bb9dc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977397334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.1977397334 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.4013275382 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 14704390166 ps |
| CPU time | 259.6 seconds |
| Started | Feb 07 04:13:04 PM PST 24 |
| Finished | Feb 07 04:17:24 PM PST 24 |
| Peak memory | 555420 kb |
| Host | smart-b13f9eb3-1530-4243-8730-0cd75cf3fafe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013275382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.4013275382 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.3273826783 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 447772519 ps |
| CPU time | 40.88 seconds |
| Started | Feb 07 04:13:02 PM PST 24 |
| Finished | Feb 07 04:13:44 PM PST 24 |
| Peak memory | 555700 kb |
| Host | smart-0563c388-78d7-4e4d-a38b-388989413dd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273826783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_del ays.3273826783 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_same_source.2232997124 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 502712115 ps |
| CPU time | 40.15 seconds |
| Started | Feb 07 04:13:01 PM PST 24 |
| Finished | Feb 07 04:13:41 PM PST 24 |
| Peak memory | 555304 kb |
| Host | smart-014b5038-e76b-49c8-94f5-655ecee61a45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232997124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2232997124 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke.2113269251 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 44547664 ps |
| CPU time | 5.78 seconds |
| Started | Feb 07 04:12:54 PM PST 24 |
| Finished | Feb 07 04:13:02 PM PST 24 |
| Peak memory | 553544 kb |
| Host | smart-5dc18619-dea5-4682-9fce-d711a6d03706 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113269251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.2113269251 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.2066928278 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 8474934133 ps |
| CPU time | 92.68 seconds |
| Started | Feb 07 04:12:40 PM PST 24 |
| Finished | Feb 07 04:14:16 PM PST 24 |
| Peak memory | 553412 kb |
| Host | smart-4b8b48c2-5017-42ee-8d1b-9872560e49b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066928278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.2066928278 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.3752520546 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 3254584084 ps |
| CPU time | 54.9 seconds |
| Started | Feb 07 04:12:46 PM PST 24 |
| Finished | Feb 07 04:13:42 PM PST 24 |
| Peak memory | 553356 kb |
| Host | smart-0db8a174-a843-4cc9-a51d-209e4fd2e64f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752520546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.3752520546 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.521708852 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 46920937 ps |
| CPU time | 5.87 seconds |
| Started | Feb 07 04:12:56 PM PST 24 |
| Finished | Feb 07 04:13:02 PM PST 24 |
| Peak memory | 553132 kb |
| Host | smart-b9668b2f-a398-418a-8b6d-556bde8533c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521708852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays .521708852 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all.4126363082 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 3502783404 ps |
| CPU time | 264.31 seconds |
| Started | Feb 07 04:13:17 PM PST 24 |
| Finished | Feb 07 04:17:42 PM PST 24 |
| Peak memory | 556948 kb |
| Host | smart-c5506ba6-e8ce-4a95-957e-b6aba2c645f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126363082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.4126363082 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.4123189349 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 9942218817 ps |
| CPU time | 365.76 seconds |
| Started | Feb 07 04:13:03 PM PST 24 |
| Finished | Feb 07 04:19:09 PM PST 24 |
| Peak memory | 556600 kb |
| Host | smart-36069d5e-6c27-406f-b8cb-f73ea7b0941a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123189349 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.4123189349 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.1766634509 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 605063882 ps |
| CPU time | 239.94 seconds |
| Started | Feb 07 04:13:04 PM PST 24 |
| Finished | Feb 07 04:17:04 PM PST 24 |
| Peak memory | 557632 kb |
| Host | smart-85d413a4-6b79-4c4d-9158-a141194dac33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766634509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all _with_rand_reset.1766634509 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.2640166973 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 332661092 ps |
| CPU time | 77.15 seconds |
| Started | Feb 07 04:13:13 PM PST 24 |
| Finished | Feb 07 04:14:31 PM PST 24 |
| Peak memory | 556836 kb |
| Host | smart-b0a7038e-7030-4e23-83f5-7269095c54fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640166973 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_al l_with_reset_error.2640166973 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.126722194 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 95587686 ps |
| CPU time | 13.3 seconds |
| Started | Feb 07 04:13:02 PM PST 24 |
| Finished | Feb 07 04:13:16 PM PST 24 |
| Peak memory | 555676 kb |
| Host | smart-00915215-52ab-4c3d-8bbb-a2e4f7bc4b4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126722194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.126722194 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.4001052236 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 8112609656 ps |
| CPU time | 368.78 seconds |
| Started | Feb 07 04:13:13 PM PST 24 |
| Finished | Feb 07 04:19:22 PM PST 24 |
| Peak memory | 630792 kb |
| Host | smart-ce3ec6e9-d82b-4350-aabc-1d51444ab346 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001052236 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 19.chip_csr_mem_rw_with_rand_reset.4001052236 |
| Directory | /workspace/19.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_rw.1667149406 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 3903793655 ps |
| CPU time | 275.32 seconds |
| Started | Feb 07 04:13:13 PM PST 24 |
| Finished | Feb 07 04:17:49 PM PST 24 |
| Peak memory | 580216 kb |
| Host | smart-89a08b72-466a-4e45-bb09-cca427dec41a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667149406 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.1667149406 |
| Directory | /workspace/19.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.2919503217 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 14794275732 ps |
| CPU time | 1549.8 seconds |
| Started | Feb 07 04:13:11 PM PST 24 |
| Finished | Feb 07 04:39:01 PM PST 24 |
| Peak memory | 580288 kb |
| Host | smart-88ac3380-3cff-41e8-997a-d973ef8d95ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919503217 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.chip_same_csr_outstanding.2919503217 |
| Directory | /workspace/19.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_tl_errors.3119012549 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 2976771352 ps |
| CPU time | 189.27 seconds |
| Started | Feb 07 04:13:10 PM PST 24 |
| Finished | Feb 07 04:16:20 PM PST 24 |
| Peak memory | 580352 kb |
| Host | smart-26c01881-d15b-46f0-b657-c02ceec681b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119012549 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.3119012549 |
| Directory | /workspace/19.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device.2594514861 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 508710377 ps |
| CPU time | 48.12 seconds |
| Started | Feb 07 04:13:11 PM PST 24 |
| Finished | Feb 07 04:13:59 PM PST 24 |
| Peak memory | 555204 kb |
| Host | smart-261a2470-d4f6-4f88-a2a6-702767c3739b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594514861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device .2594514861 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.4194396424 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 44703672263 ps |
| CPU time | 762.57 seconds |
| Started | Feb 07 04:13:11 PM PST 24 |
| Finished | Feb 07 04:25:54 PM PST 24 |
| Peak memory | 555728 kb |
| Host | smart-422795c9-c41a-47dd-b0a7-6c46e01aa2da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194396424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_ device_slow_rsp.4194396424 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.3576552264 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 437275504 ps |
| CPU time | 21.75 seconds |
| Started | Feb 07 04:13:11 PM PST 24 |
| Finished | Feb 07 04:13:34 PM PST 24 |
| Peak memory | 555336 kb |
| Host | smart-4ff3bd05-9b28-403a-9a21-faa562908e9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576552264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_add r.3576552264 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_random.3436441484 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 84372689 ps |
| CPU time | 9.33 seconds |
| Started | Feb 07 04:13:02 PM PST 24 |
| Finished | Feb 07 04:13:12 PM PST 24 |
| Peak memory | 555616 kb |
| Host | smart-f86af6d3-3fe0-4193-b484-606c18a6f138 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436441484 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.3436441484 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random.773755236 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 148027254 ps |
| CPU time | 8.13 seconds |
| Started | Feb 07 04:13:15 PM PST 24 |
| Finished | Feb 07 04:13:24 PM PST 24 |
| Peak memory | 553568 kb |
| Host | smart-3189778c-c10b-4f5b-8b93-d1eee3c808c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773755236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.773755236 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.2354483867 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 97816735178 ps |
| CPU time | 1057.42 seconds |
| Started | Feb 07 04:13:02 PM PST 24 |
| Finished | Feb 07 04:30:40 PM PST 24 |
| Peak memory | 555776 kb |
| Host | smart-6face8c3-c519-4acc-b8f7-e03ef8fa0a9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354483867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2354483867 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.1351567175 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 386875850 ps |
| CPU time | 37.1 seconds |
| Started | Feb 07 04:13:03 PM PST 24 |
| Finished | Feb 07 04:13:41 PM PST 24 |
| Peak memory | 555500 kb |
| Host | smart-42b85ddb-6baf-4144-9546-b087d42d79eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351567175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_del ays.1351567175 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_same_source.3509286440 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 388457482 ps |
| CPU time | 32.05 seconds |
| Started | Feb 07 04:13:10 PM PST 24 |
| Finished | Feb 07 04:13:43 PM PST 24 |
| Peak memory | 555392 kb |
| Host | smart-dd64ae0c-0038-4921-8d49-827d82c85847 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509286440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3509286440 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke.2356269743 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 41922562 ps |
| CPU time | 6.22 seconds |
| Started | Feb 07 04:13:02 PM PST 24 |
| Finished | Feb 07 04:13:09 PM PST 24 |
| Peak memory | 553596 kb |
| Host | smart-d104d40b-93fd-4c7a-a078-268c12e5e5f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356269743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2356269743 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.2752861729 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 5524212080 ps |
| CPU time | 60.17 seconds |
| Started | Feb 07 04:13:17 PM PST 24 |
| Finished | Feb 07 04:14:18 PM PST 24 |
| Peak memory | 553380 kb |
| Host | smart-33a9f3ed-2e39-46cc-92d2-aeee42ef34db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752861729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.2752861729 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.1887360859 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 5423231619 ps |
| CPU time | 95.16 seconds |
| Started | Feb 07 04:13:02 PM PST 24 |
| Finished | Feb 07 04:14:38 PM PST 24 |
| Peak memory | 553376 kb |
| Host | smart-cb943e30-8a4b-420e-bd0f-07b8e0a8537f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887360859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1887360859 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.1778810409 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 39065233 ps |
| CPU time | 5.39 seconds |
| Started | Feb 07 04:13:10 PM PST 24 |
| Finished | Feb 07 04:13:16 PM PST 24 |
| Peak memory | 553592 kb |
| Host | smart-0bdc65cb-abdc-4692-8230-0fb6e60c2b29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778810409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delay s.1778810409 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all.329651745 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 10670770368 ps |
| CPU time | 352.98 seconds |
| Started | Feb 07 04:13:13 PM PST 24 |
| Finished | Feb 07 04:19:06 PM PST 24 |
| Peak memory | 556900 kb |
| Host | smart-77a190ac-ff38-411e-b268-14dfd5398e64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329651745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.329651745 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.437915778 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 11414077288 ps |
| CPU time | 382.88 seconds |
| Started | Feb 07 04:13:25 PM PST 24 |
| Finished | Feb 07 04:19:48 PM PST 24 |
| Peak memory | 557644 kb |
| Host | smart-13b75a37-eee8-4646-98df-fbe60fb5b84b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437915778 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.437915778 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.2276544034 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 11152539661 ps |
| CPU time | 581.89 seconds |
| Started | Feb 07 04:13:28 PM PST 24 |
| Finished | Feb 07 04:23:10 PM PST 24 |
| Peak memory | 559112 kb |
| Host | smart-54eca2f0-7006-400a-b623-0a79b51313c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276544034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all _with_rand_reset.2276544034 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.2997308382 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 4826813038 ps |
| CPU time | 602.99 seconds |
| Started | Feb 07 04:13:14 PM PST 24 |
| Finished | Feb 07 04:23:17 PM PST 24 |
| Peak memory | 567608 kb |
| Host | smart-d2eea641-c596-4f1a-be8d-da5d6679a80a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997308382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_al l_with_reset_error.2997308382 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.634159732 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 662156511 ps |
| CPU time | 30.72 seconds |
| Started | Feb 07 04:13:13 PM PST 24 |
| Finished | Feb 07 04:13:44 PM PST 24 |
| Peak memory | 555708 kb |
| Host | smart-2974a0dc-d8b5-4d11-8f04-51e04900b8ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634159732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.634159732 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_aliasing.2742896395 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 29478456322 ps |
| CPU time | 5621.8 seconds |
| Started | Feb 07 04:11:48 PM PST 24 |
| Finished | Feb 07 05:45:30 PM PST 24 |
| Peak memory | 580248 kb |
| Host | smart-e1a3c984-f310-41e7-a9bf-ed75d5e54ed9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742896395 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.chip_csr_aliasing.2742896395 |
| Directory | /workspace/2.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.335623250 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 56013339630 ps |
| CPU time | 5904.75 seconds |
| Started | Feb 07 04:11:37 PM PST 24 |
| Finished | Feb 07 05:50:03 PM PST 24 |
| Peak memory | 580232 kb |
| Host | smart-da49710e-2eb5-4a5e-9511-0be67c05607a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335623250 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.335623250 |
| Directory | /workspace/2.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.2565482423 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 5487250662 ps |
| CPU time | 249.34 seconds |
| Started | Feb 07 04:11:41 PM PST 24 |
| Finished | Feb 07 04:15:51 PM PST 24 |
| Peak memory | 613280 kb |
| Host | smart-79821451-4e9c-45b7-a614-de65ff54ad41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565482423 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.chip_csr_mem_rw_with_rand_reset.2565482423 |
| Directory | /workspace/2.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_rw.4262212221 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 3962935408 ps |
| CPU time | 318.79 seconds |
| Started | Feb 07 04:11:41 PM PST 24 |
| Finished | Feb 07 04:17:00 PM PST 24 |
| Peak memory | 580280 kb |
| Host | smart-c194a5c4-1993-4667-8445-ad21030a602f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262212221 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.4262212221 |
| Directory | /workspace/2.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.2437899159 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 10906188546 ps |
| CPU time | 562.38 seconds |
| Started | Feb 07 04:11:39 PM PST 24 |
| Finished | Feb 07 04:21:02 PM PST 24 |
| Peak memory | 572092 kb |
| Host | smart-ede9affd-a9a0-4aff-93b9-d9b28eb1feb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437899159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.2437899159 |
| Directory | /workspace/2.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.3360414676 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 6243815156 ps |
| CPU time | 230.75 seconds |
| Started | Feb 07 04:11:34 PM PST 24 |
| Finished | Feb 07 04:15:25 PM PST 24 |
| Peak memory | 571716 kb |
| Host | smart-7ab97d73-2839-4c51-9382-012ddfc190d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360414676 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_lc_disabled.3360414676 |
| Directory | /workspace/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.1949690284 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 29363081551 ps |
| CPU time | 3722.62 seconds |
| Started | Feb 07 04:11:42 PM PST 24 |
| Finished | Feb 07 05:13:45 PM PST 24 |
| Peak memory | 580256 kb |
| Host | smart-4dc4552f-8b35-4bae-a41d-fc7a72b503cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949690284 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 2.chip_same_csr_outstanding.1949690284 |
| Directory | /workspace/2.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_tl_errors.2499075806 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 2635756304 ps |
| CPU time | 80.84 seconds |
| Started | Feb 07 04:11:28 PM PST 24 |
| Finished | Feb 07 04:12:49 PM PST 24 |
| Peak memory | 580368 kb |
| Host | smart-5ce04cfe-4ad7-4de2-9f2a-e8ae49116fbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499075806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.2499075806 |
| Directory | /workspace/2.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device.4172866650 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 2064769426 ps |
| CPU time | 93.44 seconds |
| Started | Feb 07 04:11:42 PM PST 24 |
| Finished | Feb 07 04:13:15 PM PST 24 |
| Peak memory | 555368 kb |
| Host | smart-ba6e0fbd-f352-49e8-bbe3-4f0f59a03c4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172866650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device. 4172866650 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.35204092 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 43197010417 ps |
| CPU time | 733.46 seconds |
| Started | Feb 07 04:11:42 PM PST 24 |
| Finished | Feb 07 04:23:56 PM PST 24 |
| Peak memory | 556700 kb |
| Host | smart-1bb59413-9f6c-4c93-af5a-55bdb8fc18db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35204092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_dev ice_slow_rsp.35204092 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.875712172 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 71549850 ps |
| CPU time | 5.95 seconds |
| Started | Feb 07 04:11:46 PM PST 24 |
| Finished | Feb 07 04:11:52 PM PST 24 |
| Peak memory | 553260 kb |
| Host | smart-76ec91ee-f924-45f2-ab47-811affcca580 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875712172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr. 875712172 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_random.2892419487 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 1599026139 ps |
| CPU time | 54.37 seconds |
| Started | Feb 07 04:11:44 PM PST 24 |
| Finished | Feb 07 04:12:39 PM PST 24 |
| Peak memory | 555328 kb |
| Host | smart-0101c172-d963-45ff-953a-8e54e7a9d47a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892419487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2892419487 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random.130281675 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 876206740 ps |
| CPU time | 33.88 seconds |
| Started | Feb 07 04:11:48 PM PST 24 |
| Finished | Feb 07 04:12:22 PM PST 24 |
| Peak memory | 555472 kb |
| Host | smart-2df142c2-572a-4cf3-b3bf-4a49c54e539c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130281675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.130281675 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.2285526654 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 17494581945 ps |
| CPU time | 198.74 seconds |
| Started | Feb 07 04:11:59 PM PST 24 |
| Finished | Feb 07 04:15:19 PM PST 24 |
| Peak memory | 555420 kb |
| Host | smart-f20d9c2c-8da5-4783-8406-6076b7ab2ae9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285526654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.2285526654 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.602890923 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 57754880792 ps |
| CPU time | 1007.76 seconds |
| Started | Feb 07 04:11:37 PM PST 24 |
| Finished | Feb 07 04:28:25 PM PST 24 |
| Peak memory | 555404 kb |
| Host | smart-abd05d39-efa0-4eec-adbe-6495d6b8a84d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602890923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.602890923 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.3479100815 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 371295265 ps |
| CPU time | 28.18 seconds |
| Started | Feb 07 04:11:55 PM PST 24 |
| Finished | Feb 07 04:12:23 PM PST 24 |
| Peak memory | 555684 kb |
| Host | smart-4a0f8ec1-7952-4c6e-aea9-8d6a6b9fe43e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479100815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_dela ys.3479100815 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_same_source.1873948998 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 2478195841 ps |
| CPU time | 71.73 seconds |
| Started | Feb 07 04:12:01 PM PST 24 |
| Finished | Feb 07 04:13:13 PM PST 24 |
| Peak memory | 555176 kb |
| Host | smart-e30a997c-e332-4a84-ba3f-3713395ea957 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873948998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.1873948998 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke.2242764298 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 49968354 ps |
| CPU time | 6.39 seconds |
| Started | Feb 07 04:11:42 PM PST 24 |
| Finished | Feb 07 04:11:49 PM PST 24 |
| Peak memory | 553596 kb |
| Host | smart-325f10c0-833e-4ea4-b4ac-10ba5b1bc817 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242764298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2242764298 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.1297922153 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 9000361938 ps |
| CPU time | 92.31 seconds |
| Started | Feb 07 04:11:39 PM PST 24 |
| Finished | Feb 07 04:13:11 PM PST 24 |
| Peak memory | 559200 kb |
| Host | smart-03763c60-8247-4147-bbc7-fd91a64ca6fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297922153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.1297922153 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.3960496307 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 4250529840 ps |
| CPU time | 73.82 seconds |
| Started | Feb 07 04:11:34 PM PST 24 |
| Finished | Feb 07 04:12:48 PM PST 24 |
| Peak memory | 553372 kb |
| Host | smart-7e1d210e-1ec0-4caa-a288-24065bef918d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960496307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.3960496307 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.722781615 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 46654697 ps |
| CPU time | 6.37 seconds |
| Started | Feb 07 04:11:41 PM PST 24 |
| Finished | Feb 07 04:11:48 PM PST 24 |
| Peak memory | 553580 kb |
| Host | smart-c20d6448-1ad9-4926-95c0-aa3fb5a911ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722781615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays. 722781615 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all.4037688300 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 3999369706 ps |
| CPU time | 312.05 seconds |
| Started | Feb 07 04:11:44 PM PST 24 |
| Finished | Feb 07 04:16:57 PM PST 24 |
| Peak memory | 556368 kb |
| Host | smart-af8e5a1f-54da-4bac-b677-7d95095c1d2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037688300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.4037688300 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.1902384044 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 4104969262 ps |
| CPU time | 333.29 seconds |
| Started | Feb 07 04:11:43 PM PST 24 |
| Finished | Feb 07 04:17:17 PM PST 24 |
| Peak memory | 556584 kb |
| Host | smart-421749e1-b44e-4680-b6e4-5ce57951d37c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902384044 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1902384044 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.619515701 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 5160239610 ps |
| CPU time | 241.93 seconds |
| Started | Feb 07 04:11:42 PM PST 24 |
| Finished | Feb 07 04:15:45 PM PST 24 |
| Peak memory | 556604 kb |
| Host | smart-11d60b35-c080-4344-932c-3cf6173686b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619515701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_w ith_rand_reset.619515701 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.3629846749 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 944537603 ps |
| CPU time | 297.91 seconds |
| Started | Feb 07 04:11:40 PM PST 24 |
| Finished | Feb 07 04:16:39 PM PST 24 |
| Peak memory | 559340 kb |
| Host | smart-c0f28e9f-5d26-493b-a21e-4d6b6d66701f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629846749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all _with_reset_error.3629846749 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.1855515054 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 321989048 ps |
| CPU time | 14.66 seconds |
| Started | Feb 07 04:12:00 PM PST 24 |
| Finished | Feb 07 04:12:16 PM PST 24 |
| Peak memory | 555636 kb |
| Host | smart-804f807e-a8cd-48fb-974f-bf2741d2892f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855515054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.1855515054 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.chip_tl_errors.224819417 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 3763207500 ps |
| CPU time | 159.02 seconds |
| Started | Feb 07 04:13:16 PM PST 24 |
| Finished | Feb 07 04:15:55 PM PST 24 |
| Peak memory | 580300 kb |
| Host | smart-f3a05ae0-6e06-4b40-b4a2-a34e149b3b79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224819417 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.224819417 |
| Directory | /workspace/20.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device.1073925285 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 2361365868 ps |
| CPU time | 85.37 seconds |
| Started | Feb 07 04:13:20 PM PST 24 |
| Finished | Feb 07 04:14:47 PM PST 24 |
| Peak memory | 555788 kb |
| Host | smart-3d6265f8-e653-414d-bdbc-a81a608e0345 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073925285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device .1073925285 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.2806488504 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 105659419289 ps |
| CPU time | 1875.95 seconds |
| Started | Feb 07 04:13:27 PM PST 24 |
| Finished | Feb 07 04:44:44 PM PST 24 |
| Peak memory | 555776 kb |
| Host | smart-04d89c11-12e8-4a30-b416-4a3e45edee7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806488504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_ device_slow_rsp.2806488504 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.3711706183 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 201220436 ps |
| CPU time | 25.66 seconds |
| Started | Feb 07 04:13:28 PM PST 24 |
| Finished | Feb 07 04:13:54 PM PST 24 |
| Peak memory | 555076 kb |
| Host | smart-edb94fb7-4fdc-431c-8fa8-e43b47c18f01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711706183 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_add r.3711706183 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_random.3087027062 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 110095602 ps |
| CPU time | 10.94 seconds |
| Started | Feb 07 04:13:31 PM PST 24 |
| Finished | Feb 07 04:13:43 PM PST 24 |
| Peak memory | 555304 kb |
| Host | smart-571cd9ea-e247-4a3d-b53f-de2f4bc7a52e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087027062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3087027062 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random.2857543964 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 42977007 ps |
| CPU time | 6.68 seconds |
| Started | Feb 07 04:13:26 PM PST 24 |
| Finished | Feb 07 04:13:33 PM PST 24 |
| Peak memory | 553028 kb |
| Host | smart-20e9df8d-f850-4907-b44f-6337032707e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857543964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.2857543964 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.3559656598 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 105033012346 ps |
| CPU time | 1082.16 seconds |
| Started | Feb 07 04:13:14 PM PST 24 |
| Finished | Feb 07 04:31:16 PM PST 24 |
| Peak memory | 555728 kb |
| Host | smart-45287725-908e-428b-acb2-87c307d3fa6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559656598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.3559656598 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.592982140 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 18065943318 ps |
| CPU time | 316.6 seconds |
| Started | Feb 07 04:13:12 PM PST 24 |
| Finished | Feb 07 04:18:30 PM PST 24 |
| Peak memory | 555420 kb |
| Host | smart-27f4f41a-b3cc-4405-9a9d-4a93f97c9e60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592982140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.592982140 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.1709806315 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 518221299 ps |
| CPU time | 46.13 seconds |
| Started | Feb 07 04:13:11 PM PST 24 |
| Finished | Feb 07 04:13:58 PM PST 24 |
| Peak memory | 555416 kb |
| Host | smart-7120a195-6740-4b02-9b80-85d3592e999f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709806315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_del ays.1709806315 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_same_source.460806955 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 1373700952 ps |
| CPU time | 43.17 seconds |
| Started | Feb 07 04:13:12 PM PST 24 |
| Finished | Feb 07 04:13:56 PM PST 24 |
| Peak memory | 555368 kb |
| Host | smart-342e844e-b763-467f-9763-d185b044ee34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460806955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.460806955 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke.1348787209 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 176803166 ps |
| CPU time | 7.87 seconds |
| Started | Feb 07 04:13:12 PM PST 24 |
| Finished | Feb 07 04:13:21 PM PST 24 |
| Peak memory | 553284 kb |
| Host | smart-dac963d2-0bbb-4e70-8701-945b87f5a7b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348787209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.1348787209 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.605175229 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 10694591616 ps |
| CPU time | 104.54 seconds |
| Started | Feb 07 04:13:27 PM PST 24 |
| Finished | Feb 07 04:15:12 PM PST 24 |
| Peak memory | 553648 kb |
| Host | smart-db156614-2ac2-41f1-b2f8-718780265788 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605175229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.605175229 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.3227705253 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 4917737746 ps |
| CPU time | 82.71 seconds |
| Started | Feb 07 04:13:27 PM PST 24 |
| Finished | Feb 07 04:14:50 PM PST 24 |
| Peak memory | 553660 kb |
| Host | smart-3e17b622-502d-4cd8-a0c6-a0bf5dcf794e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227705253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.3227705253 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.84669051 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 54154106 ps |
| CPU time | 6.94 seconds |
| Started | Feb 07 04:13:11 PM PST 24 |
| Finished | Feb 07 04:13:18 PM PST 24 |
| Peak memory | 553300 kb |
| Host | smart-d625cb21-9c42-4673-87d7-21f7e1a68b81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84669051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.84669051 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all.4005522794 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 9405902382 ps |
| CPU time | 331.39 seconds |
| Started | Feb 07 04:13:29 PM PST 24 |
| Finished | Feb 07 04:19:01 PM PST 24 |
| Peak memory | 556868 kb |
| Host | smart-2c86a538-840c-49f2-92e3-4a6b033d2c6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005522794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.4005522794 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.2153715936 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 12283023679 ps |
| CPU time | 458.14 seconds |
| Started | Feb 07 04:24:55 PM PST 24 |
| Finished | Feb 07 04:32:34 PM PST 24 |
| Peak memory | 556356 kb |
| Host | smart-332d1c15-b678-4b7d-b98d-704d67c6edc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153715936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.2153715936 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.377529502 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 381360221 ps |
| CPU time | 202.84 seconds |
| Started | Feb 07 04:13:31 PM PST 24 |
| Finished | Feb 07 04:16:54 PM PST 24 |
| Peak memory | 559356 kb |
| Host | smart-c64053f0-5774-4dff-89c4-9699342a83c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377529502 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all _with_reset_error.377529502 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.1581275559 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 221659726 ps |
| CPU time | 26.5 seconds |
| Started | Feb 07 04:13:32 PM PST 24 |
| Finished | Feb 07 04:13:59 PM PST 24 |
| Peak memory | 555328 kb |
| Host | smart-877941f2-feb2-48db-9837-7bc1d2b94db5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581275559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1581275559 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.3208026474 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 1021062990 ps |
| CPU time | 49.93 seconds |
| Started | Feb 07 04:13:29 PM PST 24 |
| Finished | Feb 07 04:14:20 PM PST 24 |
| Peak memory | 555636 kb |
| Host | smart-e56accc7-4198-4332-bef5-9d1decf91960 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208026474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device .3208026474 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.1270716124 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 136876130587 ps |
| CPU time | 2501.87 seconds |
| Started | Feb 07 04:25:48 PM PST 24 |
| Finished | Feb 07 05:07:31 PM PST 24 |
| Peak memory | 556308 kb |
| Host | smart-455f134a-b4b7-4066-9910-4e31daea3daf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270716124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_ device_slow_rsp.1270716124 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.3128179450 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 670915142 ps |
| CPU time | 24.04 seconds |
| Started | Feb 07 04:13:26 PM PST 24 |
| Finished | Feb 07 04:13:51 PM PST 24 |
| Peak memory | 555616 kb |
| Host | smart-0324d86f-5390-4912-b53a-a1033cb1c293 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128179450 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_add r.3128179450 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_random.1901011576 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 206939330 ps |
| CPU time | 19.37 seconds |
| Started | Feb 07 04:23:37 PM PST 24 |
| Finished | Feb 07 04:23:57 PM PST 24 |
| Peak memory | 555312 kb |
| Host | smart-371044c1-afc0-4e42-bad4-de5e8c91d7a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901011576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.1901011576 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random.3904428845 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 378479536 ps |
| CPU time | 30.2 seconds |
| Started | Feb 07 04:13:31 PM PST 24 |
| Finished | Feb 07 04:14:01 PM PST 24 |
| Peak memory | 555328 kb |
| Host | smart-accb3d03-0e5e-4b14-913e-1b7fb1971c31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904428845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.3904428845 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.810796178 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 89628151324 ps |
| CPU time | 1047.54 seconds |
| Started | Feb 07 04:13:27 PM PST 24 |
| Finished | Feb 07 04:30:56 PM PST 24 |
| Peak memory | 555432 kb |
| Host | smart-5dd0fc3f-67fc-4323-9995-3c335289ea7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810796178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.810796178 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.33041839 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 6441016132 ps |
| CPU time | 109.81 seconds |
| Started | Feb 07 04:13:31 PM PST 24 |
| Finished | Feb 07 04:15:22 PM PST 24 |
| Peak memory | 553648 kb |
| Host | smart-25faed72-ed6a-40af-96b8-dda197a51078 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33041839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.33041839 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.1363884307 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 187507759 ps |
| CPU time | 18.57 seconds |
| Started | Feb 07 04:31:57 PM PST 24 |
| Finished | Feb 07 04:32:19 PM PST 24 |
| Peak memory | 555612 kb |
| Host | smart-04cb18be-26dd-4143-ac75-b29624dac517 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363884307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_del ays.1363884307 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_same_source.4072293808 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 38781236 ps |
| CPU time | 5.89 seconds |
| Started | Feb 07 04:13:28 PM PST 24 |
| Finished | Feb 07 04:13:34 PM PST 24 |
| Peak memory | 553304 kb |
| Host | smart-73ce64ca-bdf0-43ab-aad1-2905506f2c8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072293808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.4072293808 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke.2548675125 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 213945537 ps |
| CPU time | 9.31 seconds |
| Started | Feb 07 04:13:32 PM PST 24 |
| Finished | Feb 07 04:13:42 PM PST 24 |
| Peak memory | 553296 kb |
| Host | smart-73f5a0fd-5775-47a6-972b-4e71e556a748 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548675125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.2548675125 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.469453089 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 10315849616 ps |
| CPU time | 119.71 seconds |
| Started | Feb 07 04:13:30 PM PST 24 |
| Finished | Feb 07 04:15:30 PM PST 24 |
| Peak memory | 553336 kb |
| Host | smart-32a413b7-cfeb-4cf2-924c-82540e8aea2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469453089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.469453089 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.1934104158 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 4301055899 ps |
| CPU time | 68.93 seconds |
| Started | Feb 07 04:22:19 PM PST 24 |
| Finished | Feb 07 04:23:28 PM PST 24 |
| Peak memory | 553652 kb |
| Host | smart-a189ce34-6187-4070-8c5f-6c9429037497 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934104158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.1934104158 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.1660227580 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 36738753 ps |
| CPU time | 6.1 seconds |
| Started | Feb 07 04:33:37 PM PST 24 |
| Finished | Feb 07 04:33:47 PM PST 24 |
| Peak memory | 553588 kb |
| Host | smart-add7f876-d7ae-4352-8628-76f3457a3054 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660227580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delay s.1660227580 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all.3640471830 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 6861132738 ps |
| CPU time | 272.59 seconds |
| Started | Feb 07 04:13:39 PM PST 24 |
| Finished | Feb 07 04:18:12 PM PST 24 |
| Peak memory | 556876 kb |
| Host | smart-ec8ece1d-a187-4ac4-b8d3-ff853e93da8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640471830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.3640471830 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.1079485292 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 1443562356 ps |
| CPU time | 57.14 seconds |
| Started | Feb 07 04:13:36 PM PST 24 |
| Finished | Feb 07 04:14:34 PM PST 24 |
| Peak memory | 555356 kb |
| Host | smart-2af7309e-ac86-498c-bb23-1b57db9b804b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079485292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.1079485292 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.1670809638 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 1427500904 ps |
| CPU time | 226.52 seconds |
| Started | Feb 07 04:13:43 PM PST 24 |
| Finished | Feb 07 04:17:30 PM PST 24 |
| Peak memory | 556948 kb |
| Host | smart-c51a4b63-a78b-4063-8d9a-1d82a4d114a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670809638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_rand_reset.1670809638 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.2014806971 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 436758941 ps |
| CPU time | 144.66 seconds |
| Started | Feb 07 04:13:34 PM PST 24 |
| Finished | Feb 07 04:15:59 PM PST 24 |
| Peak memory | 558668 kb |
| Host | smart-303b06d8-5c04-4b1b-8bb0-51cd6ecd19b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014806971 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_al l_with_reset_error.2014806971 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.655782245 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 309044269 ps |
| CPU time | 45.37 seconds |
| Started | Feb 07 04:30:45 PM PST 24 |
| Finished | Feb 07 04:31:31 PM PST 24 |
| Peak memory | 555696 kb |
| Host | smart-908a6193-195b-4458-b0a4-430ddb28caf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655782245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.655782245 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device.808577619 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 860352106 ps |
| CPU time | 65.66 seconds |
| Started | Feb 07 04:13:41 PM PST 24 |
| Finished | Feb 07 04:14:48 PM PST 24 |
| Peak memory | 555412 kb |
| Host | smart-3893efcf-5b48-4536-a46e-ca87272a8a71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808577619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device. 808577619 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.2777404564 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 35806793441 ps |
| CPU time | 674.32 seconds |
| Started | Feb 07 04:13:36 PM PST 24 |
| Finished | Feb 07 04:24:51 PM PST 24 |
| Peak memory | 555424 kb |
| Host | smart-b3f9affa-b389-4de8-b2ae-bdb408148ce9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777404564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_ device_slow_rsp.2777404564 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.1889082497 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 1009072620 ps |
| CPU time | 39.46 seconds |
| Started | Feb 07 04:13:38 PM PST 24 |
| Finished | Feb 07 04:14:18 PM PST 24 |
| Peak memory | 555596 kb |
| Host | smart-2a1717ba-c75f-453c-b65f-75eac2e0a1aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889082497 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_add r.1889082497 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_random.2272593158 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 550060638 ps |
| CPU time | 43.93 seconds |
| Started | Feb 07 04:13:32 PM PST 24 |
| Finished | Feb 07 04:14:17 PM PST 24 |
| Peak memory | 555360 kb |
| Host | smart-a28328e3-3bfe-46fa-b03c-8402379f2c8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272593158 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2272593158 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random.183878706 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 2023292214 ps |
| CPU time | 85.8 seconds |
| Started | Feb 07 04:13:39 PM PST 24 |
| Finished | Feb 07 04:15:06 PM PST 24 |
| Peak memory | 555172 kb |
| Host | smart-c9b93daf-5ace-44d0-8eb2-a06f2e82b92f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183878706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.183878706 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.2515511572 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 78489742912 ps |
| CPU time | 893.59 seconds |
| Started | Feb 07 04:13:28 PM PST 24 |
| Finished | Feb 07 04:28:22 PM PST 24 |
| Peak memory | 555400 kb |
| Host | smart-85a169a2-78b0-4658-80a2-b804ebeb7eeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515511572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2515511572 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.2415396059 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 55039712901 ps |
| CPU time | 934.09 seconds |
| Started | Feb 07 04:13:29 PM PST 24 |
| Finished | Feb 07 04:29:04 PM PST 24 |
| Peak memory | 555708 kb |
| Host | smart-3c292465-1120-4228-8ae1-6a630b7900b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415396059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.2415396059 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.2108706417 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 249346676 ps |
| CPU time | 25.76 seconds |
| Started | Feb 07 04:13:29 PM PST 24 |
| Finished | Feb 07 04:13:55 PM PST 24 |
| Peak memory | 555380 kb |
| Host | smart-4082a78c-be8e-46f7-ac57-407496444b20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108706417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_del ays.2108706417 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_same_source.1540403902 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 429341852 ps |
| CPU time | 36.17 seconds |
| Started | Feb 07 04:13:38 PM PST 24 |
| Finished | Feb 07 04:14:15 PM PST 24 |
| Peak memory | 555664 kb |
| Host | smart-5f731fb2-3d57-4584-b11a-bc44e0182f54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540403902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.1540403902 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke.588199620 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 39100986 ps |
| CPU time | 6.11 seconds |
| Started | Feb 07 04:13:41 PM PST 24 |
| Finished | Feb 07 04:13:48 PM PST 24 |
| Peak memory | 553000 kb |
| Host | smart-f47f3d0e-f9f0-475e-a296-e138b73eb1d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588199620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.588199620 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.76692718 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 10082147775 ps |
| CPU time | 109.31 seconds |
| Started | Feb 07 04:13:43 PM PST 24 |
| Finished | Feb 07 04:15:32 PM PST 24 |
| Peak memory | 553332 kb |
| Host | smart-11319035-0676-467d-8098-4cbfa6a920b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76692718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.76692718 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.3815171846 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 6836499806 ps |
| CPU time | 114.53 seconds |
| Started | Feb 07 04:13:38 PM PST 24 |
| Finished | Feb 07 04:15:33 PM PST 24 |
| Peak memory | 553712 kb |
| Host | smart-642d56be-195d-4821-bafa-734718b3aabe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815171846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3815171846 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.1522867385 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 40667825 ps |
| CPU time | 6.11 seconds |
| Started | Feb 07 04:13:37 PM PST 24 |
| Finished | Feb 07 04:13:44 PM PST 24 |
| Peak memory | 553584 kb |
| Host | smart-aba98a5d-d59b-4ff4-a655-e98280566e0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522867385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delay s.1522867385 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all.3041553814 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 10351187865 ps |
| CPU time | 397.21 seconds |
| Started | Feb 07 04:13:32 PM PST 24 |
| Finished | Feb 07 04:20:10 PM PST 24 |
| Peak memory | 556592 kb |
| Host | smart-483d04cc-e159-42ec-b644-3c1350b531e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041553814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.3041553814 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.3587723099 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 10335014430 ps |
| CPU time | 359.82 seconds |
| Started | Feb 07 04:13:33 PM PST 24 |
| Finished | Feb 07 04:19:34 PM PST 24 |
| Peak memory | 556880 kb |
| Host | smart-bcb01dec-f413-49d0-a31e-fc6060ef35f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587723099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3587723099 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.3759900483 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 1531341232 ps |
| CPU time | 199.55 seconds |
| Started | Feb 07 04:13:42 PM PST 24 |
| Finished | Feb 07 04:17:02 PM PST 24 |
| Peak memory | 557844 kb |
| Host | smart-d184f006-6fc0-438a-91e2-9de820050dd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759900483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all _with_rand_reset.3759900483 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.3981287889 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 1715764986 ps |
| CPU time | 211.82 seconds |
| Started | Feb 07 04:13:34 PM PST 24 |
| Finished | Feb 07 04:17:07 PM PST 24 |
| Peak memory | 557392 kb |
| Host | smart-aa340de7-7a8c-4dea-9e12-4efa7f69be6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981287889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al l_with_reset_error.3981287889 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.3886532996 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 877537010 ps |
| CPU time | 34.17 seconds |
| Started | Feb 07 04:13:38 PM PST 24 |
| Finished | Feb 07 04:14:13 PM PST 24 |
| Peak memory | 555680 kb |
| Host | smart-bc5be271-d984-4d17-98b8-d91b3efdaae1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886532996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3886532996 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.chip_tl_errors.4048560790 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 3392669873 ps |
| CPU time | 124.15 seconds |
| Started | Feb 07 04:13:38 PM PST 24 |
| Finished | Feb 07 04:15:42 PM PST 24 |
| Peak memory | 580392 kb |
| Host | smart-2a534ab5-3096-4fdc-9016-8e8d3b903df8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048560790 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.4048560790 |
| Directory | /workspace/23.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device.546279240 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 783594499 ps |
| CPU time | 62.79 seconds |
| Started | Feb 07 04:13:44 PM PST 24 |
| Finished | Feb 07 04:14:47 PM PST 24 |
| Peak memory | 555596 kb |
| Host | smart-b356597a-1849-448b-8f1e-c1073357508a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546279240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device. 546279240 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.3251602257 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 133604045 ps |
| CPU time | 15.37 seconds |
| Started | Feb 07 04:13:49 PM PST 24 |
| Finished | Feb 07 04:14:04 PM PST 24 |
| Peak memory | 555356 kb |
| Host | smart-d83633bf-6035-4e63-a3d5-703b825f4976 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251602257 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_add r.3251602257 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_random.3504786796 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 174560409 ps |
| CPU time | 17.2 seconds |
| Started | Feb 07 04:13:39 PM PST 24 |
| Finished | Feb 07 04:13:57 PM PST 24 |
| Peak memory | 555072 kb |
| Host | smart-da8ddb6e-e8ad-4686-82b5-f83a964281a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504786796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3504786796 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random.2508817858 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 2090952755 ps |
| CPU time | 68.73 seconds |
| Started | Feb 07 04:13:38 PM PST 24 |
| Finished | Feb 07 04:14:47 PM PST 24 |
| Peak memory | 555672 kb |
| Host | smart-bb220bbe-08ea-46a3-8639-6f0d79597efe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508817858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.2508817858 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.4224138849 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 65020208773 ps |
| CPU time | 687.77 seconds |
| Started | Feb 07 04:13:38 PM PST 24 |
| Finished | Feb 07 04:25:06 PM PST 24 |
| Peak memory | 555428 kb |
| Host | smart-72a1046e-3b4d-4087-987c-97e1afbdd985 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224138849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.4224138849 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.3403332071 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 57602544833 ps |
| CPU time | 1053.52 seconds |
| Started | Feb 07 04:13:41 PM PST 24 |
| Finished | Feb 07 04:31:15 PM PST 24 |
| Peak memory | 555748 kb |
| Host | smart-d888f37a-e682-44dd-8503-a4ecdda1528a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403332071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3403332071 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.1380614534 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 197393226 ps |
| CPU time | 19.83 seconds |
| Started | Feb 07 04:13:38 PM PST 24 |
| Finished | Feb 07 04:13:58 PM PST 24 |
| Peak memory | 555416 kb |
| Host | smart-3904baec-ed2f-4917-a47b-50a0f76572fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380614534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_del ays.1380614534 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_same_source.2799553967 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 484045537 ps |
| CPU time | 37.05 seconds |
| Started | Feb 07 04:13:41 PM PST 24 |
| Finished | Feb 07 04:14:19 PM PST 24 |
| Peak memory | 555360 kb |
| Host | smart-7958749d-ae29-44ee-970f-188d2c98b959 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799553967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.2799553967 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke.1285596157 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 49281938 ps |
| CPU time | 6.89 seconds |
| Started | Feb 07 04:13:42 PM PST 24 |
| Finished | Feb 07 04:13:50 PM PST 24 |
| Peak memory | 553548 kb |
| Host | smart-c9c69d64-8c49-43e7-999a-322c98f9a42f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285596157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.1285596157 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.381155476 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 7505181379 ps |
| CPU time | 75.97 seconds |
| Started | Feb 07 04:13:33 PM PST 24 |
| Finished | Feb 07 04:14:50 PM PST 24 |
| Peak memory | 553680 kb |
| Host | smart-b0056340-7f0f-46f5-b642-cc2883c49e1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381155476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.381155476 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.1555676626 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 5530745088 ps |
| CPU time | 80.93 seconds |
| Started | Feb 07 04:13:36 PM PST 24 |
| Finished | Feb 07 04:14:58 PM PST 24 |
| Peak memory | 553672 kb |
| Host | smart-4dfd7e98-d539-489c-bdf9-7ee084d25357 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555676626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.1555676626 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.451026788 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 56013744 ps |
| CPU time | 6.84 seconds |
| Started | Feb 07 04:13:41 PM PST 24 |
| Finished | Feb 07 04:13:48 PM PST 24 |
| Peak memory | 553256 kb |
| Host | smart-17631578-b30d-499f-98bf-6a8a14a7cecc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451026788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays .451026788 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all.317593007 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 5470429639 ps |
| CPU time | 478.63 seconds |
| Started | Feb 07 04:13:56 PM PST 24 |
| Finished | Feb 07 04:21:55 PM PST 24 |
| Peak memory | 559212 kb |
| Host | smart-48e7daed-f836-44f1-878a-27288bc8b5f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317593007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.317593007 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.320411119 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 2582463058 ps |
| CPU time | 85.5 seconds |
| Started | Feb 07 04:13:50 PM PST 24 |
| Finished | Feb 07 04:15:16 PM PST 24 |
| Peak memory | 559260 kb |
| Host | smart-ea4cfe8f-691c-4939-80d6-21d7c00c96cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320411119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.320411119 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.2455477464 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 548776112 ps |
| CPU time | 205.65 seconds |
| Started | Feb 07 04:13:57 PM PST 24 |
| Finished | Feb 07 04:17:23 PM PST 24 |
| Peak memory | 557748 kb |
| Host | smart-aba2b1cc-86f9-4cbc-9dab-645881df6675 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455477464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all _with_rand_reset.2455477464 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.3100041377 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 4889470989 ps |
| CPU time | 241.67 seconds |
| Started | Feb 07 04:13:47 PM PST 24 |
| Finished | Feb 07 04:17:49 PM PST 24 |
| Peak memory | 556888 kb |
| Host | smart-827fca4c-1638-46a1-b881-6ff830bd6f43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100041377 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_al l_with_reset_error.3100041377 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.1738105911 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 909204506 ps |
| CPU time | 37.89 seconds |
| Started | Feb 07 04:13:49 PM PST 24 |
| Finished | Feb 07 04:14:28 PM PST 24 |
| Peak memory | 555404 kb |
| Host | smart-c5799484-2549-49b2-ad1e-f0fbd640a115 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738105911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1738105911 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.chip_tl_errors.4213926328 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 3789473124 ps |
| CPU time | 295.72 seconds |
| Started | Feb 07 04:13:51 PM PST 24 |
| Finished | Feb 07 04:18:47 PM PST 24 |
| Peak memory | 580352 kb |
| Host | smart-606153bf-52f3-43b9-9878-2a3f2fced5f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213926328 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.4213926328 |
| Directory | /workspace/24.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device.2619262133 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 1782519454 ps |
| CPU time | 79.21 seconds |
| Started | Feb 07 04:13:49 PM PST 24 |
| Finished | Feb 07 04:15:09 PM PST 24 |
| Peak memory | 559184 kb |
| Host | smart-297aa4e4-a015-459e-98b5-ee00265f22ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619262133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device .2619262133 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.1495798720 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 11786148176 ps |
| CPU time | 199.65 seconds |
| Started | Feb 07 04:13:48 PM PST 24 |
| Finished | Feb 07 04:17:08 PM PST 24 |
| Peak memory | 555756 kb |
| Host | smart-21c5689a-f101-495a-b8ce-9d2ef39a6c2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495798720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_ device_slow_rsp.1495798720 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_random.3477447761 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 1357153676 ps |
| CPU time | 48.34 seconds |
| Started | Feb 07 04:13:52 PM PST 24 |
| Finished | Feb 07 04:14:41 PM PST 24 |
| Peak memory | 555364 kb |
| Host | smart-af67a654-9143-4d97-8a93-e6127a8cc6f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477447761 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.3477447761 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random.3940508552 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 290259030 ps |
| CPU time | 13.84 seconds |
| Started | Feb 07 04:13:49 PM PST 24 |
| Finished | Feb 07 04:14:04 PM PST 24 |
| Peak memory | 553268 kb |
| Host | smart-9a6895ab-954d-4531-ac14-755cb4a8124a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940508552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.3940508552 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.4144543220 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 85071752370 ps |
| CPU time | 946.41 seconds |
| Started | Feb 07 04:13:47 PM PST 24 |
| Finished | Feb 07 04:29:34 PM PST 24 |
| Peak memory | 555736 kb |
| Host | smart-3a0b2e23-6294-47eb-bbbb-9cc173cb1483 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144543220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.4144543220 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.1234847558 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 66595035154 ps |
| CPU time | 1230.75 seconds |
| Started | Feb 07 04:13:55 PM PST 24 |
| Finished | Feb 07 04:34:26 PM PST 24 |
| Peak memory | 555496 kb |
| Host | smart-4b749091-31d8-440d-a336-def017a12521 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234847558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.1234847558 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.3826080391 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 482483665 ps |
| CPU time | 46.38 seconds |
| Started | Feb 07 04:13:49 PM PST 24 |
| Finished | Feb 07 04:14:36 PM PST 24 |
| Peak memory | 555688 kb |
| Host | smart-1a81bb88-1a6f-47df-911d-dd630bfeb78f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826080391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_del ays.3826080391 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_same_source.532455304 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 572084126 ps |
| CPU time | 46.38 seconds |
| Started | Feb 07 04:13:47 PM PST 24 |
| Finished | Feb 07 04:14:34 PM PST 24 |
| Peak memory | 555640 kb |
| Host | smart-067fe9ab-cfaa-453e-9647-83a961833fe9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532455304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.532455304 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke.1498552202 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 176927956 ps |
| CPU time | 8.15 seconds |
| Started | Feb 07 04:13:51 PM PST 24 |
| Finished | Feb 07 04:13:59 PM PST 24 |
| Peak memory | 553280 kb |
| Host | smart-853e5810-de30-416a-8ea1-51fb1c80b379 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498552202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1498552202 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.986517831 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 9603979928 ps |
| CPU time | 102.06 seconds |
| Started | Feb 07 04:13:58 PM PST 24 |
| Finished | Feb 07 04:15:40 PM PST 24 |
| Peak memory | 553624 kb |
| Host | smart-d1e994a9-6ee2-48f3-b6c3-e686a0502ae8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986517831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.986517831 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.686912212 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 5496372419 ps |
| CPU time | 81.7 seconds |
| Started | Feb 07 04:13:49 PM PST 24 |
| Finished | Feb 07 04:15:11 PM PST 24 |
| Peak memory | 553060 kb |
| Host | smart-fb172b7d-4948-4e6c-aebf-a0af9a96b089 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686912212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.686912212 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.1868208333 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 51526796 ps |
| CPU time | 6.38 seconds |
| Started | Feb 07 04:13:46 PM PST 24 |
| Finished | Feb 07 04:13:52 PM PST 24 |
| Peak memory | 553588 kb |
| Host | smart-bddc3aa4-09e3-4489-a76d-ab262e66ba89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868208333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delay s.1868208333 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all.782303043 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 5094563744 ps |
| CPU time | 231.13 seconds |
| Started | Feb 07 04:13:53 PM PST 24 |
| Finished | Feb 07 04:17:45 PM PST 24 |
| Peak memory | 558004 kb |
| Host | smart-77ba2fcd-4270-4615-84c9-6bfeb068bb81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782303043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.782303043 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.655450248 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 1513958923 ps |
| CPU time | 129.64 seconds |
| Started | Feb 07 04:14:01 PM PST 24 |
| Finished | Feb 07 04:16:11 PM PST 24 |
| Peak memory | 556716 kb |
| Host | smart-c9fda4a2-330e-4033-80bf-a8f2967be67e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655450248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.655450248 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.1463185708 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 10004654133 ps |
| CPU time | 773.06 seconds |
| Started | Feb 07 04:13:51 PM PST 24 |
| Finished | Feb 07 04:26:44 PM PST 24 |
| Peak memory | 558992 kb |
| Host | smart-8783a499-3624-4f26-8aac-8a832e7c36df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463185708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all _with_rand_reset.1463185708 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.1197713552 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 4379777116 ps |
| CPU time | 427.1 seconds |
| Started | Feb 07 04:14:00 PM PST 24 |
| Finished | Feb 07 04:21:08 PM PST 24 |
| Peak memory | 567640 kb |
| Host | smart-f7ebb4aa-0ec4-4f1f-9b84-e87eb3535e4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197713552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_al l_with_reset_error.1197713552 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.1751559766 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 311293019 ps |
| CPU time | 15.8 seconds |
| Started | Feb 07 04:13:49 PM PST 24 |
| Finished | Feb 07 04:14:05 PM PST 24 |
| Peak memory | 555360 kb |
| Host | smart-f5fe81c9-687a-4794-85cd-efc2f8d71f5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751559766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.1751559766 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device.3862603701 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 1613355097 ps |
| CPU time | 55.68 seconds |
| Started | Feb 07 04:14:07 PM PST 24 |
| Finished | Feb 07 04:15:03 PM PST 24 |
| Peak memory | 554324 kb |
| Host | smart-4a7eecc9-4e3a-4ec2-b6fd-49306fd8622f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862603701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device .3862603701 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.3435608217 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 37494690953 ps |
| CPU time | 653.27 seconds |
| Started | Feb 07 04:13:56 PM PST 24 |
| Finished | Feb 07 04:24:50 PM PST 24 |
| Peak memory | 556444 kb |
| Host | smart-c516fc20-1428-49e1-9b8b-90d9556818ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435608217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_ device_slow_rsp.3435608217 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.3714725370 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 1200858710 ps |
| CPU time | 50.17 seconds |
| Started | Feb 07 04:14:08 PM PST 24 |
| Finished | Feb 07 04:14:59 PM PST 24 |
| Peak memory | 555624 kb |
| Host | smart-81590218-4ce4-4d5e-bc9f-5944a0ab51c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714725370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_add r.3714725370 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_random.1080930509 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 293050919 ps |
| CPU time | 13.97 seconds |
| Started | Feb 07 04:14:06 PM PST 24 |
| Finished | Feb 07 04:14:20 PM PST 24 |
| Peak memory | 554628 kb |
| Host | smart-12ccb0ed-ed09-4e6d-b6fd-51126324683d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080930509 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.1080930509 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random.3963212546 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 2160205966 ps |
| CPU time | 72.26 seconds |
| Started | Feb 07 04:13:55 PM PST 24 |
| Finished | Feb 07 04:15:08 PM PST 24 |
| Peak memory | 555580 kb |
| Host | smart-c069c395-45c9-4a82-947e-67c07b33bdd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963212546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.3963212546 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.2681230443 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 18499031637 ps |
| CPU time | 198.68 seconds |
| Started | Feb 07 04:14:02 PM PST 24 |
| Finished | Feb 07 04:17:21 PM PST 24 |
| Peak memory | 555672 kb |
| Host | smart-657814e0-1e39-4376-aba9-428171b7ef3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681230443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2681230443 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.18951407 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 37376393834 ps |
| CPU time | 657.02 seconds |
| Started | Feb 07 04:14:05 PM PST 24 |
| Finished | Feb 07 04:25:02 PM PST 24 |
| Peak memory | 555744 kb |
| Host | smart-92c3794f-c490-4b5f-b547-d09be6005eff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18951407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.18951407 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.2469036297 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 189333946 ps |
| CPU time | 18.22 seconds |
| Started | Feb 07 04:13:58 PM PST 24 |
| Finished | Feb 07 04:14:16 PM PST 24 |
| Peak memory | 555680 kb |
| Host | smart-dc85281c-6445-4e2e-b0cb-8da90ff97b87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469036297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_del ays.2469036297 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_same_source.669029453 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 417379061 ps |
| CPU time | 31.09 seconds |
| Started | Feb 07 04:14:07 PM PST 24 |
| Finished | Feb 07 04:14:39 PM PST 24 |
| Peak memory | 555348 kb |
| Host | smart-7b1c093a-c9ca-41f4-ad5d-be806f2ddd0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669029453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.669029453 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke.701287971 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 200538663 ps |
| CPU time | 9.84 seconds |
| Started | Feb 07 04:13:57 PM PST 24 |
| Finished | Feb 07 04:14:07 PM PST 24 |
| Peak memory | 559164 kb |
| Host | smart-4ffe6a98-719c-4832-91e8-405d4fda3f73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701287971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.701287971 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.1694840848 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 7394461193 ps |
| CPU time | 80.84 seconds |
| Started | Feb 07 04:14:05 PM PST 24 |
| Finished | Feb 07 04:15:26 PM PST 24 |
| Peak memory | 553132 kb |
| Host | smart-fbebc027-d775-4b6a-85c2-40fdfaa407dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694840848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.1694840848 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.3959909959 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 6932871261 ps |
| CPU time | 123.85 seconds |
| Started | Feb 07 04:14:07 PM PST 24 |
| Finished | Feb 07 04:16:11 PM PST 24 |
| Peak memory | 553656 kb |
| Host | smart-db678b53-90e6-4385-af44-3ec05b2aecfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959909959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.3959909959 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.165719910 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 47055203 ps |
| CPU time | 6.62 seconds |
| Started | Feb 07 04:13:59 PM PST 24 |
| Finished | Feb 07 04:14:06 PM PST 24 |
| Peak memory | 553264 kb |
| Host | smart-5f8cafa7-9866-40ec-8d6d-b825cfb415e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165719910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays .165719910 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all.2688327530 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 9614575683 ps |
| CPU time | 336.31 seconds |
| Started | Feb 07 04:13:56 PM PST 24 |
| Finished | Feb 07 04:19:33 PM PST 24 |
| Peak memory | 556880 kb |
| Host | smart-5c6a646d-eaa3-480a-b2e5-cb125b0c4970 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688327530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.2688327530 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.3854111918 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 4914058800 ps |
| CPU time | 202.01 seconds |
| Started | Feb 07 04:14:00 PM PST 24 |
| Finished | Feb 07 04:17:22 PM PST 24 |
| Peak memory | 556504 kb |
| Host | smart-7a2f140c-7410-4bce-935c-735dfa7075b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854111918 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.3854111918 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.1896512964 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 266307742 ps |
| CPU time | 75.52 seconds |
| Started | Feb 07 04:14:02 PM PST 24 |
| Finished | Feb 07 04:15:18 PM PST 24 |
| Peak memory | 556580 kb |
| Host | smart-078cc3cd-1c66-4a41-b5c7-fe2c07299a62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896512964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all _with_rand_reset.1896512964 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.1197832289 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 141442067 ps |
| CPU time | 79.35 seconds |
| Started | Feb 07 04:14:04 PM PST 24 |
| Finished | Feb 07 04:15:24 PM PST 24 |
| Peak memory | 556680 kb |
| Host | smart-377e9a8e-a760-4522-bf04-72430aa73d55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197832289 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_al l_with_reset_error.1197832289 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.542423872 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 324653504 ps |
| CPU time | 16.86 seconds |
| Started | Feb 07 04:14:04 PM PST 24 |
| Finished | Feb 07 04:14:21 PM PST 24 |
| Peak memory | 555652 kb |
| Host | smart-54e0a797-3f6e-4fc9-8b93-f5d7b5cb873e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542423872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.542423872 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.chip_tl_errors.2713202795 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 3913710578 ps |
| CPU time | 222.35 seconds |
| Started | Feb 07 04:14:08 PM PST 24 |
| Finished | Feb 07 04:17:51 PM PST 24 |
| Peak memory | 580360 kb |
| Host | smart-7b863648-2813-4b40-9701-2cdffad16996 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713202795 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.2713202795 |
| Directory | /workspace/26.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device.3306040590 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 1306577382 ps |
| CPU time | 50.32 seconds |
| Started | Feb 07 04:14:14 PM PST 24 |
| Finished | Feb 07 04:15:07 PM PST 24 |
| Peak memory | 556380 kb |
| Host | smart-994e0514-f708-4c73-8132-a4b046a5a060 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306040590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device .3306040590 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.2689467066 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 21388714012 ps |
| CPU time | 372.25 seconds |
| Started | Feb 07 04:14:12 PM PST 24 |
| Finished | Feb 07 04:20:26 PM PST 24 |
| Peak memory | 555736 kb |
| Host | smart-fa9b5010-1e3a-4a35-912f-c1b4756203f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689467066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_ device_slow_rsp.2689467066 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.3134009701 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 91208818 ps |
| CPU time | 13.13 seconds |
| Started | Feb 07 04:14:16 PM PST 24 |
| Finished | Feb 07 04:14:30 PM PST 24 |
| Peak memory | 555328 kb |
| Host | smart-e59206d7-4e7e-4b78-b8ec-af22593480d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134009701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add r.3134009701 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_random.3371838308 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 1044123006 ps |
| CPU time | 34.15 seconds |
| Started | Feb 07 04:14:15 PM PST 24 |
| Finished | Feb 07 04:14:51 PM PST 24 |
| Peak memory | 555304 kb |
| Host | smart-bb70c7ef-5554-4ec3-a091-5764216342f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371838308 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3371838308 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random.3655150451 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 1111370420 ps |
| CPU time | 43.97 seconds |
| Started | Feb 07 04:14:08 PM PST 24 |
| Finished | Feb 07 04:14:53 PM PST 24 |
| Peak memory | 555340 kb |
| Host | smart-295f1d2e-342d-4550-b5d9-bf498b9dfd93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655150451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.3655150451 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.288823488 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 26511407456 ps |
| CPU time | 297.08 seconds |
| Started | Feb 07 04:14:14 PM PST 24 |
| Finished | Feb 07 04:19:14 PM PST 24 |
| Peak memory | 555736 kb |
| Host | smart-ec137281-0912-4edc-b3d4-34f1bd731fc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288823488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.288823488 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.2182321722 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 13673154935 ps |
| CPU time | 247 seconds |
| Started | Feb 07 04:14:14 PM PST 24 |
| Finished | Feb 07 04:18:22 PM PST 24 |
| Peak memory | 555400 kb |
| Host | smart-ce96f733-0199-4df0-85e8-32e5863c5202 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182321722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.2182321722 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.2531922213 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 498515873 ps |
| CPU time | 47.77 seconds |
| Started | Feb 07 04:14:16 PM PST 24 |
| Finished | Feb 07 04:15:05 PM PST 24 |
| Peak memory | 555684 kb |
| Host | smart-a67f5e75-1768-4bbc-aed6-78f2e17ba79e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531922213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_del ays.2531922213 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_same_source.4089469029 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 509190374 ps |
| CPU time | 41.47 seconds |
| Started | Feb 07 04:14:16 PM PST 24 |
| Finished | Feb 07 04:14:59 PM PST 24 |
| Peak memory | 555640 kb |
| Host | smart-2b10bccf-3bf0-483a-ba38-09624d567dfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089469029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.4089469029 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke.1734743131 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 136057192 ps |
| CPU time | 7.3 seconds |
| Started | Feb 07 04:13:56 PM PST 24 |
| Finished | Feb 07 04:14:04 PM PST 24 |
| Peak memory | 553232 kb |
| Host | smart-a7422c9e-89f2-4cb7-af10-7f7c1df90ac2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734743131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1734743131 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.3317608976 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 9997971322 ps |
| CPU time | 111.19 seconds |
| Started | Feb 07 04:14:12 PM PST 24 |
| Finished | Feb 07 04:16:05 PM PST 24 |
| Peak memory | 553664 kb |
| Host | smart-52b7373a-dde1-4e2f-b2a7-e48034122dd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317608976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3317608976 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.730578677 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 5021937509 ps |
| CPU time | 87.9 seconds |
| Started | Feb 07 04:14:05 PM PST 24 |
| Finished | Feb 07 04:15:33 PM PST 24 |
| Peak memory | 553348 kb |
| Host | smart-5a98d218-687f-4c99-b0a0-b860dd70ae5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730578677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.730578677 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.3417891957 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 47165648 ps |
| CPU time | 6.93 seconds |
| Started | Feb 07 04:14:12 PM PST 24 |
| Finished | Feb 07 04:14:20 PM PST 24 |
| Peak memory | 553592 kb |
| Host | smart-ea99eee5-b45d-4628-a5bb-598bd90e62fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417891957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delay s.3417891957 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all.833979626 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 6596710179 ps |
| CPU time | 258.03 seconds |
| Started | Feb 07 04:14:18 PM PST 24 |
| Finished | Feb 07 04:18:37 PM PST 24 |
| Peak memory | 559360 kb |
| Host | smart-4bd2ec86-f830-4568-ac51-c17fcb3ae6ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833979626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.833979626 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.1358957151 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 1382925527 ps |
| CPU time | 97.42 seconds |
| Started | Feb 07 04:14:14 PM PST 24 |
| Finished | Feb 07 04:15:52 PM PST 24 |
| Peak memory | 556660 kb |
| Host | smart-eb869e5b-c230-4e6a-93b0-0db79945fdc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358957151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1358957151 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.3743779662 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 538708104 ps |
| CPU time | 194.52 seconds |
| Started | Feb 07 04:14:19 PM PST 24 |
| Finished | Feb 07 04:17:34 PM PST 24 |
| Peak memory | 557584 kb |
| Host | smart-5950f910-a4da-4c4a-957c-e75190c0e308 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743779662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_rand_reset.3743779662 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.250919612 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 324251932 ps |
| CPU time | 110.99 seconds |
| Started | Feb 07 04:14:18 PM PST 24 |
| Finished | Feb 07 04:16:09 PM PST 24 |
| Peak memory | 557616 kb |
| Host | smart-977c936d-8e4a-4980-8ddb-c088b1ce45b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250919612 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_reset_error.250919612 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.2888002735 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 199244285 ps |
| CPU time | 27.86 seconds |
| Started | Feb 07 04:14:18 PM PST 24 |
| Finished | Feb 07 04:14:46 PM PST 24 |
| Peak memory | 555688 kb |
| Host | smart-c48cbd72-4063-4191-8117-076d9b6855a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888002735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2888002735 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.chip_tl_errors.2782787448 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 3351099706 ps |
| CPU time | 218.37 seconds |
| Started | Feb 07 04:14:20 PM PST 24 |
| Finished | Feb 07 04:17:58 PM PST 24 |
| Peak memory | 580236 kb |
| Host | smart-f82587e8-a9c7-4296-b7ac-1207cf14f50a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782787448 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.2782787448 |
| Directory | /workspace/27.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device.2762247334 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 408199612 ps |
| CPU time | 37.11 seconds |
| Started | Feb 07 04:14:13 PM PST 24 |
| Finished | Feb 07 04:14:51 PM PST 24 |
| Peak memory | 555360 kb |
| Host | smart-36fb96ef-f142-4b25-bf3f-dcc15cc175b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762247334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device .2762247334 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.134235679 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 83869152969 ps |
| CPU time | 1551.39 seconds |
| Started | Feb 07 04:14:18 PM PST 24 |
| Finished | Feb 07 04:40:10 PM PST 24 |
| Peak memory | 555740 kb |
| Host | smart-1626ab93-aa78-49b8-9ca4-6e6ed4a7d99d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134235679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_d evice_slow_rsp.134235679 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.2817882086 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 243916082 ps |
| CPU time | 29.26 seconds |
| Started | Feb 07 04:14:17 PM PST 24 |
| Finished | Feb 07 04:14:47 PM PST 24 |
| Peak memory | 555344 kb |
| Host | smart-19b3f15e-5689-45f9-beef-ee12ef55efc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817882086 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_add r.2817882086 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_random.4042291713 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 576986969 ps |
| CPU time | 20.85 seconds |
| Started | Feb 07 04:14:12 PM PST 24 |
| Finished | Feb 07 04:14:34 PM PST 24 |
| Peak memory | 555588 kb |
| Host | smart-d1b188cb-9357-42ec-a47e-a063269e16a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042291713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.4042291713 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random.3394874202 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 1783159067 ps |
| CPU time | 57 seconds |
| Started | Feb 07 04:14:18 PM PST 24 |
| Finished | Feb 07 04:15:15 PM PST 24 |
| Peak memory | 555116 kb |
| Host | smart-73b9e8e0-21c5-4bc9-bba2-ef27bc01281f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394874202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.3394874202 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.289233199 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 62021441022 ps |
| CPU time | 667.34 seconds |
| Started | Feb 07 04:14:19 PM PST 24 |
| Finished | Feb 07 04:25:27 PM PST 24 |
| Peak memory | 555668 kb |
| Host | smart-22c0810a-c3ea-4a6b-a258-7e2ddd5bedd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289233199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.289233199 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.2711773229 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 46708395485 ps |
| CPU time | 809.48 seconds |
| Started | Feb 07 04:14:16 PM PST 24 |
| Finished | Feb 07 04:27:47 PM PST 24 |
| Peak memory | 555696 kb |
| Host | smart-cd57ea10-e9d3-4d91-ab99-07f0ae80ad92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711773229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.2711773229 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.2835061834 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 284332611 ps |
| CPU time | 26.48 seconds |
| Started | Feb 07 04:14:16 PM PST 24 |
| Finished | Feb 07 04:14:44 PM PST 24 |
| Peak memory | 555632 kb |
| Host | smart-2b9e4f7a-70a6-448b-a1f7-f5389919b1f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835061834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_del ays.2835061834 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_same_source.4262576003 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 1565819314 ps |
| CPU time | 38.63 seconds |
| Started | Feb 07 04:14:18 PM PST 24 |
| Finished | Feb 07 04:14:58 PM PST 24 |
| Peak memory | 555400 kb |
| Host | smart-9143e7d0-eab3-4b44-abd3-0d32a8ee6111 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262576003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.4262576003 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke.1718582111 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 55782239 ps |
| CPU time | 6.85 seconds |
| Started | Feb 07 04:14:15 PM PST 24 |
| Finished | Feb 07 04:14:24 PM PST 24 |
| Peak memory | 553252 kb |
| Host | smart-e9f7a00d-e0be-4357-8862-9107413a33a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718582111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.1718582111 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.3420731244 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 8177709622 ps |
| CPU time | 85.31 seconds |
| Started | Feb 07 04:14:14 PM PST 24 |
| Finished | Feb 07 04:15:42 PM PST 24 |
| Peak memory | 553372 kb |
| Host | smart-844c68a8-16da-459a-aaf8-47c48c6b1a3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420731244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.3420731244 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.1421433662 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 5721428404 ps |
| CPU time | 95.86 seconds |
| Started | Feb 07 04:14:20 PM PST 24 |
| Finished | Feb 07 04:15:57 PM PST 24 |
| Peak memory | 553072 kb |
| Host | smart-63914cab-3fde-45ee-b267-8bbd4af9ec69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421433662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.1421433662 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.775832461 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 51097883 ps |
| CPU time | 7.09 seconds |
| Started | Feb 07 04:14:18 PM PST 24 |
| Finished | Feb 07 04:14:26 PM PST 24 |
| Peak memory | 553608 kb |
| Host | smart-ba25b0cf-21cb-4c4b-93cf-5e873106f94f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775832461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays .775832461 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all.4119037545 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 1291545256 ps |
| CPU time | 102.33 seconds |
| Started | Feb 07 04:14:18 PM PST 24 |
| Finished | Feb 07 04:16:00 PM PST 24 |
| Peak memory | 556456 kb |
| Host | smart-43f01696-d2c0-4be8-8dc5-bd81347c33f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119037545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.4119037545 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.1127928215 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 1504802121 ps |
| CPU time | 42.97 seconds |
| Started | Feb 07 04:14:17 PM PST 24 |
| Finished | Feb 07 04:15:00 PM PST 24 |
| Peak memory | 555596 kb |
| Host | smart-98e5c9ac-989c-4e8f-8076-44462d006b19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127928215 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.1127928215 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.2333545804 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 3380636236 ps |
| CPU time | 486.64 seconds |
| Started | Feb 07 04:14:14 PM PST 24 |
| Finished | Feb 07 04:22:23 PM PST 24 |
| Peak memory | 558560 kb |
| Host | smart-49b57c3e-50d8-4e1c-8b04-6e30d8e89e3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333545804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all _with_rand_reset.2333545804 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.3442257313 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 706980320 ps |
| CPU time | 173.95 seconds |
| Started | Feb 07 04:14:18 PM PST 24 |
| Finished | Feb 07 04:17:13 PM PST 24 |
| Peak memory | 559332 kb |
| Host | smart-db24e55d-66f6-4e3e-b14a-f05d54f4dfa4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442257313 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_al l_with_reset_error.3442257313 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.2454279006 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 317851394 ps |
| CPU time | 38.96 seconds |
| Started | Feb 07 04:14:16 PM PST 24 |
| Finished | Feb 07 04:14:56 PM PST 24 |
| Peak memory | 555656 kb |
| Host | smart-9b610b1b-ba33-44b0-835c-8cfdfdd8bd23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454279006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.2454279006 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device.14100955 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 3373395328 ps |
| CPU time | 133.59 seconds |
| Started | Feb 07 04:14:24 PM PST 24 |
| Finished | Feb 07 04:16:39 PM PST 24 |
| Peak memory | 555420 kb |
| Host | smart-50c668d6-56e7-4c27-ba7f-6008c7224b60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14100955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.14100955 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.3318158853 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 98098087420 ps |
| CPU time | 1674.03 seconds |
| Started | Feb 07 04:14:26 PM PST 24 |
| Finished | Feb 07 04:42:25 PM PST 24 |
| Peak memory | 559296 kb |
| Host | smart-ca50076f-2c4b-4ddf-951c-29b643fc35e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318158853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_ device_slow_rsp.3318158853 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.367070662 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 719228578 ps |
| CPU time | 28.01 seconds |
| Started | Feb 07 04:14:20 PM PST 24 |
| Finished | Feb 07 04:14:49 PM PST 24 |
| Peak memory | 555624 kb |
| Host | smart-209c7eba-8be7-4f68-bcce-c136dfd26367 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367070662 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr .367070662 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_random.2172348014 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 358489777 ps |
| CPU time | 35.78 seconds |
| Started | Feb 07 04:14:31 PM PST 24 |
| Finished | Feb 07 04:15:08 PM PST 24 |
| Peak memory | 555092 kb |
| Host | smart-26edd77e-1a1f-4702-a6bc-4773c17891c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172348014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.2172348014 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random.1220792299 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 174530584 ps |
| CPU time | 8.39 seconds |
| Started | Feb 07 04:14:18 PM PST 24 |
| Finished | Feb 07 04:14:27 PM PST 24 |
| Peak memory | 553580 kb |
| Host | smart-8c7e75fc-839a-4bd4-a4c4-688bbaacd717 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220792299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.1220792299 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.200011695 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 27886138839 ps |
| CPU time | 305.34 seconds |
| Started | Feb 07 04:14:24 PM PST 24 |
| Finished | Feb 07 04:19:31 PM PST 24 |
| Peak memory | 555188 kb |
| Host | smart-4e5af080-9d87-469a-a9b0-fbb6e40f4e3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200011695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.200011695 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.1751035372 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 56136563242 ps |
| CPU time | 1090.41 seconds |
| Started | Feb 07 04:14:26 PM PST 24 |
| Finished | Feb 07 04:32:41 PM PST 24 |
| Peak memory | 555460 kb |
| Host | smart-e7d43e24-84dc-4741-9bc5-e39b10dd0c56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751035372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.1751035372 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.2194335123 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 279767333 ps |
| CPU time | 23.81 seconds |
| Started | Feb 07 04:14:24 PM PST 24 |
| Finished | Feb 07 04:14:50 PM PST 24 |
| Peak memory | 555668 kb |
| Host | smart-f502e319-bcb7-43b5-8235-eed3c46164b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194335123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_del ays.2194335123 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_same_source.69657985 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 350091683 ps |
| CPU time | 24.46 seconds |
| Started | Feb 07 04:14:26 PM PST 24 |
| Finished | Feb 07 04:14:55 PM PST 24 |
| Peak memory | 555652 kb |
| Host | smart-1f6c9b53-4e00-40b6-8c77-96905ae0c5d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69657985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.69657985 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke.4108830600 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 48166642 ps |
| CPU time | 6.03 seconds |
| Started | Feb 07 04:14:18 PM PST 24 |
| Finished | Feb 07 04:14:24 PM PST 24 |
| Peak memory | 553600 kb |
| Host | smart-8325c2a2-65a1-400a-81f0-128179f367f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108830600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.4108830600 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.3224911899 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 4969249296 ps |
| CPU time | 53.14 seconds |
| Started | Feb 07 04:14:17 PM PST 24 |
| Finished | Feb 07 04:15:11 PM PST 24 |
| Peak memory | 553384 kb |
| Host | smart-91e19b22-2ead-437e-8f3e-18d1d1e81148 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224911899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.3224911899 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.3077430942 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 4961954191 ps |
| CPU time | 87.63 seconds |
| Started | Feb 07 04:14:16 PM PST 24 |
| Finished | Feb 07 04:15:45 PM PST 24 |
| Peak memory | 553608 kb |
| Host | smart-ffad501c-194e-4d13-aacd-7ab39f1dcee7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077430942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3077430942 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.1551135372 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 49883120 ps |
| CPU time | 6.28 seconds |
| Started | Feb 07 04:14:15 PM PST 24 |
| Finished | Feb 07 04:14:23 PM PST 24 |
| Peak memory | 553244 kb |
| Host | smart-b1372d49-3093-4a0c-b2b7-d3206e589831 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551135372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delay s.1551135372 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all.1947737212 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 2813022456 ps |
| CPU time | 224.95 seconds |
| Started | Feb 07 04:14:31 PM PST 24 |
| Finished | Feb 07 04:18:17 PM PST 24 |
| Peak memory | 556612 kb |
| Host | smart-e60d37a3-78a5-4a27-8c02-9539ac6b038c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947737212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.1947737212 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.1006257455 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 10840736252 ps |
| CPU time | 351.16 seconds |
| Started | Feb 07 04:14:24 PM PST 24 |
| Finished | Feb 07 04:20:17 PM PST 24 |
| Peak memory | 556616 kb |
| Host | smart-ecd06e73-a2d3-407f-b8fa-39cedf9a77c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006257455 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.1006257455 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.2385416453 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1533379147 ps |
| CPU time | 118.97 seconds |
| Started | Feb 07 04:14:24 PM PST 24 |
| Finished | Feb 07 04:16:25 PM PST 24 |
| Peak memory | 556608 kb |
| Host | smart-ab0f3c24-55f3-42cc-a6e1-e8331efefa73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385416453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all _with_rand_reset.2385416453 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.3214181749 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 182699279 ps |
| CPU time | 44.38 seconds |
| Started | Feb 07 04:14:24 PM PST 24 |
| Finished | Feb 07 04:15:09 PM PST 24 |
| Peak memory | 556588 kb |
| Host | smart-1672674f-1257-42fb-a157-912653d8b700 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214181749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_al l_with_reset_error.3214181749 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.2167562561 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 231129151 ps |
| CPU time | 26.08 seconds |
| Started | Feb 07 04:14:24 PM PST 24 |
| Finished | Feb 07 04:14:51 PM PST 24 |
| Peak memory | 555440 kb |
| Host | smart-6a99d029-fcb2-4087-aa18-b4005e7682ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167562561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.2167562561 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device.2882404099 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 876654941 ps |
| CPU time | 71.72 seconds |
| Started | Feb 07 04:14:31 PM PST 24 |
| Finished | Feb 07 04:15:47 PM PST 24 |
| Peak memory | 555116 kb |
| Host | smart-34a42a3c-3fa0-411f-9221-463886cbd884 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882404099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device .2882404099 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.3555350477 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 30502430053 ps |
| CPU time | 531.93 seconds |
| Started | Feb 07 04:14:32 PM PST 24 |
| Finished | Feb 07 04:23:27 PM PST 24 |
| Peak memory | 559256 kb |
| Host | smart-a272ec45-708c-4ce0-9f1e-dd55e10e76ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555350477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_ device_slow_rsp.3555350477 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.3152194188 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 565637133 ps |
| CPU time | 24.14 seconds |
| Started | Feb 07 04:14:32 PM PST 24 |
| Finished | Feb 07 04:14:59 PM PST 24 |
| Peak memory | 555640 kb |
| Host | smart-ca1274a6-8793-4783-ac6e-1c75839f6287 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152194188 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_add r.3152194188 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_random.393051972 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 546939332 ps |
| CPU time | 41.12 seconds |
| Started | Feb 07 04:14:32 PM PST 24 |
| Finished | Feb 07 04:15:16 PM PST 24 |
| Peak memory | 555644 kb |
| Host | smart-03abdcf6-2b0c-4959-9315-95b8fde2a31b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393051972 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.393051972 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random.129904195 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 270039796 ps |
| CPU time | 23.26 seconds |
| Started | Feb 07 04:14:23 PM PST 24 |
| Finished | Feb 07 04:14:47 PM PST 24 |
| Peak memory | 559184 kb |
| Host | smart-59f69e71-5746-4fbc-af92-202927e7c445 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129904195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.129904195 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.1809005039 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 79354751145 ps |
| CPU time | 874.39 seconds |
| Started | Feb 07 04:14:31 PM PST 24 |
| Finished | Feb 07 04:29:07 PM PST 24 |
| Peak memory | 555720 kb |
| Host | smart-b6aecf59-ae23-476a-8df7-8a36ce95bee8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809005039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.1809005039 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.1696653682 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 52885072371 ps |
| CPU time | 914.27 seconds |
| Started | Feb 07 04:14:30 PM PST 24 |
| Finished | Feb 07 04:29:46 PM PST 24 |
| Peak memory | 555732 kb |
| Host | smart-807f466a-bd67-4a90-8bb9-718ec4a23096 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696653682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1696653682 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.1045719680 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 39611990 ps |
| CPU time | 7.05 seconds |
| Started | Feb 07 04:14:23 PM PST 24 |
| Finished | Feb 07 04:14:31 PM PST 24 |
| Peak memory | 553100 kb |
| Host | smart-f33f946e-3bcd-4dfd-a364-c8ff4ec6b117 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045719680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_del ays.1045719680 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_same_source.4226573698 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 1192430111 ps |
| CPU time | 34.57 seconds |
| Started | Feb 07 04:14:32 PM PST 24 |
| Finished | Feb 07 04:15:10 PM PST 24 |
| Peak memory | 555644 kb |
| Host | smart-395dc499-4af9-430a-a30a-13e31f82b2de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226573698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.4226573698 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke.2740270810 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 170018209 ps |
| CPU time | 7.84 seconds |
| Started | Feb 07 04:14:22 PM PST 24 |
| Finished | Feb 07 04:14:30 PM PST 24 |
| Peak memory | 553608 kb |
| Host | smart-73d99fb7-7a91-4be1-8137-bf076cca6f21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740270810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2740270810 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.3651843999 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 9972438329 ps |
| CPU time | 113.44 seconds |
| Started | Feb 07 04:14:24 PM PST 24 |
| Finished | Feb 07 04:16:19 PM PST 24 |
| Peak memory | 553396 kb |
| Host | smart-d0e587c5-7309-4556-9d0e-cfddb2c09c8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651843999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3651843999 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.3837922935 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 6019768036 ps |
| CPU time | 103.29 seconds |
| Started | Feb 07 04:14:25 PM PST 24 |
| Finished | Feb 07 04:16:09 PM PST 24 |
| Peak memory | 553384 kb |
| Host | smart-1edff0e4-03c7-479e-b7e6-5d23a078baef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837922935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.3837922935 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.2352380110 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 52940670 ps |
| CPU time | 5.9 seconds |
| Started | Feb 07 04:14:25 PM PST 24 |
| Finished | Feb 07 04:14:32 PM PST 24 |
| Peak memory | 553028 kb |
| Host | smart-7ef87dfe-f930-4532-a2ba-e89321001a2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352380110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delay s.2352380110 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all.3443811797 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 2212090142 ps |
| CPU time | 197.61 seconds |
| Started | Feb 07 04:14:35 PM PST 24 |
| Finished | Feb 07 04:17:54 PM PST 24 |
| Peak memory | 556592 kb |
| Host | smart-5abeb064-d6cf-4b94-aeb4-c04e95849e96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443811797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.3443811797 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.4095371114 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 16675436136 ps |
| CPU time | 594.48 seconds |
| Started | Feb 07 04:14:29 PM PST 24 |
| Finished | Feb 07 04:24:26 PM PST 24 |
| Peak memory | 558076 kb |
| Host | smart-6d790ac2-2709-47c3-a2f8-fb35d74fc243 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095371114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.4095371114 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.1356272987 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 8731875634 ps |
| CPU time | 364.01 seconds |
| Started | Feb 07 04:14:29 PM PST 24 |
| Finished | Feb 07 04:20:35 PM PST 24 |
| Peak memory | 557820 kb |
| Host | smart-1f1fe4af-3545-49ca-beb1-8661f6bafc3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356272987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all _with_rand_reset.1356272987 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.1665028128 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 291962596 ps |
| CPU time | 95.3 seconds |
| Started | Feb 07 04:14:32 PM PST 24 |
| Finished | Feb 07 04:16:11 PM PST 24 |
| Peak memory | 556624 kb |
| Host | smart-860025ca-8275-404d-8fa6-d636471ed638 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665028128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_al l_with_reset_error.1665028128 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.1164473744 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 281851187 ps |
| CPU time | 35.66 seconds |
| Started | Feb 07 04:14:31 PM PST 24 |
| Finished | Feb 07 04:15:11 PM PST 24 |
| Peak memory | 555404 kb |
| Host | smart-1d28b7b5-57b8-44af-8bec-6e86312cfa02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164473744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.1164473744 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.3945904548 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 61335149351 ps |
| CPU time | 9903.27 seconds |
| Started | Feb 07 04:11:57 PM PST 24 |
| Finished | Feb 07 06:57:02 PM PST 24 |
| Peak memory | 624532 kb |
| Host | smart-e474f9e6-8b91-44a9-bc45-ebd0de582042 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945904548 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.chip_csr_aliasing.3945904548 |
| Directory | /workspace/3.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.407966420 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 65238175144 ps |
| CPU time | 7014.18 seconds |
| Started | Feb 07 04:11:55 PM PST 24 |
| Finished | Feb 07 06:08:50 PM PST 24 |
| Peak memory | 580300 kb |
| Host | smart-ecbd4b61-3703-4023-b307-3ba2fd4269b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407966420 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.407966420 |
| Directory | /workspace/3.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.3867877507 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 4439964508 ps |
| CPU time | 239.16 seconds |
| Started | Feb 07 04:12:00 PM PST 24 |
| Finished | Feb 07 04:16:00 PM PST 24 |
| Peak memory | 640024 kb |
| Host | smart-2b0e8901-1a26-4dd2-98b1-4760a7c549ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867877507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_r eset.3867877507 |
| Directory | /workspace/3.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.4105654622 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 6178988745 ps |
| CPU time | 234.63 seconds |
| Started | Feb 07 04:12:00 PM PST 24 |
| Finished | Feb 07 04:15:55 PM PST 24 |
| Peak memory | 613432 kb |
| Host | smart-a7a8633a-a314-4966-b7b5-41d2bd0d4a34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105654622 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.chip_csr_mem_rw_with_rand_reset.4105654622 |
| Directory | /workspace/3.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_rw.3934780307 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 4922688545 ps |
| CPU time | 509.03 seconds |
| Started | Feb 07 04:11:59 PM PST 24 |
| Finished | Feb 07 04:20:28 PM PST 24 |
| Peak memory | 581492 kb |
| Host | smart-caa2a58c-d192-43c5-b596-715a3e016388 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934780307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.3934780307 |
| Directory | /workspace/3.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.369233569 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 29338987726 ps |
| CPU time | 3954.2 seconds |
| Started | Feb 07 04:11:43 PM PST 24 |
| Finished | Feb 07 05:17:38 PM PST 24 |
| Peak memory | 580256 kb |
| Host | smart-ea01eede-86fc-4d78-9a7e-52a6069464b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369233569 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 3.chip_same_csr_outstanding.369233569 |
| Directory | /workspace/3.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device.1826100157 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 2339108132 ps |
| CPU time | 93.31 seconds |
| Started | Feb 07 04:11:49 PM PST 24 |
| Finished | Feb 07 04:13:23 PM PST 24 |
| Peak memory | 555404 kb |
| Host | smart-2791e20e-bdfa-460d-b9dc-2b22eb79fcbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826100157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device. 1826100157 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.2380378045 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 95008745411 ps |
| CPU time | 1662.88 seconds |
| Started | Feb 07 04:11:46 PM PST 24 |
| Finished | Feb 07 04:39:30 PM PST 24 |
| Peak memory | 556764 kb |
| Host | smart-49b7093e-2546-4fb5-af6b-a0c12e21f20b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380378045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_d evice_slow_rsp.2380378045 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.2910060171 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 246894134 ps |
| CPU time | 25.67 seconds |
| Started | Feb 07 04:11:49 PM PST 24 |
| Finished | Feb 07 04:12:15 PM PST 24 |
| Peak memory | 555328 kb |
| Host | smart-a376b570-282c-4122-9cdf-d02df69fb38f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910060171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr .2910060171 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_random.1539184194 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 985760946 ps |
| CPU time | 36.47 seconds |
| Started | Feb 07 04:11:48 PM PST 24 |
| Finished | Feb 07 04:12:25 PM PST 24 |
| Peak memory | 555608 kb |
| Host | smart-79dbd5bb-e0fe-4571-9bd9-3ba0188cada7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539184194 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.1539184194 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random.1339618164 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 306154618 ps |
| CPU time | 29.39 seconds |
| Started | Feb 07 04:11:54 PM PST 24 |
| Finished | Feb 07 04:12:24 PM PST 24 |
| Peak memory | 555420 kb |
| Host | smart-a8627dc1-22c8-4cae-85fd-4977f9a20d90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339618164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.1339618164 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.4198585479 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 60774480622 ps |
| CPU time | 651.55 seconds |
| Started | Feb 07 04:11:53 PM PST 24 |
| Finished | Feb 07 04:22:46 PM PST 24 |
| Peak memory | 555736 kb |
| Host | smart-9d38c905-8a39-4126-92cf-e27f33809307 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198585479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.4198585479 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.2644767463 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 28204543295 ps |
| CPU time | 527.62 seconds |
| Started | Feb 07 04:11:57 PM PST 24 |
| Finished | Feb 07 04:20:45 PM PST 24 |
| Peak memory | 555420 kb |
| Host | smart-eea13654-8395-4f11-b90c-473aefd2192b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644767463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.2644767463 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.3111243178 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 280209083 ps |
| CPU time | 26.24 seconds |
| Started | Feb 07 04:11:54 PM PST 24 |
| Finished | Feb 07 04:12:20 PM PST 24 |
| Peak memory | 555412 kb |
| Host | smart-c9d576ef-2232-4178-9cc9-62c9d7146140 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111243178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_dela ys.3111243178 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_same_source.1220631986 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 2504263133 ps |
| CPU time | 73.14 seconds |
| Started | Feb 07 04:11:48 PM PST 24 |
| Finished | Feb 07 04:13:02 PM PST 24 |
| Peak memory | 555436 kb |
| Host | smart-5f8be3a5-18df-43e2-981a-5dd0bf46c7ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220631986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1220631986 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke.1780226393 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 45700603 ps |
| CPU time | 6.13 seconds |
| Started | Feb 07 04:11:48 PM PST 24 |
| Finished | Feb 07 04:11:55 PM PST 24 |
| Peak memory | 553608 kb |
| Host | smart-f38a851d-5d14-4a1b-9433-c0d1fcc467fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780226393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.1780226393 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.2099594287 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 9672943364 ps |
| CPU time | 97.04 seconds |
| Started | Feb 07 04:11:53 PM PST 24 |
| Finished | Feb 07 04:13:30 PM PST 24 |
| Peak memory | 553392 kb |
| Host | smart-7a064154-efda-41e4-abac-13c3118a1ec3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099594287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.2099594287 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.2614916272 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 5435282158 ps |
| CPU time | 93.19 seconds |
| Started | Feb 07 04:11:53 PM PST 24 |
| Finished | Feb 07 04:13:27 PM PST 24 |
| Peak memory | 553692 kb |
| Host | smart-2e9e7d5b-f173-47b0-bf58-99bc02d7767a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614916272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.2614916272 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.1713434174 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 45498373 ps |
| CPU time | 6.03 seconds |
| Started | Feb 07 04:11:47 PM PST 24 |
| Finished | Feb 07 04:11:53 PM PST 24 |
| Peak memory | 552972 kb |
| Host | smart-2aa126e2-9fb5-446b-a75f-97f43e0e0e5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713434174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays .1713434174 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all.2219724070 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 898949729 ps |
| CPU time | 74.58 seconds |
| Started | Feb 07 04:11:44 PM PST 24 |
| Finished | Feb 07 04:12:59 PM PST 24 |
| Peak memory | 556812 kb |
| Host | smart-0f61152a-c9d0-49fd-9fd6-2e0de2b6f05c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219724070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.2219724070 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.1762935365 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 2590850435 ps |
| CPU time | 78.58 seconds |
| Started | Feb 07 04:12:00 PM PST 24 |
| Finished | Feb 07 04:13:19 PM PST 24 |
| Peak memory | 555432 kb |
| Host | smart-9b1e565f-95d0-4cec-a653-9f53e4fd7c27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762935365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.1762935365 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.2877358357 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 2615181773 ps |
| CPU time | 466.99 seconds |
| Started | Feb 07 04:11:46 PM PST 24 |
| Finished | Feb 07 04:19:34 PM PST 24 |
| Peak memory | 558516 kb |
| Host | smart-506982ad-0f71-466f-989a-54f7050d77f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877358357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_ with_rand_reset.2877358357 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.2668427507 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 2204368268 ps |
| CPU time | 324.34 seconds |
| Started | Feb 07 04:11:43 PM PST 24 |
| Finished | Feb 07 04:17:08 PM PST 24 |
| Peak memory | 567544 kb |
| Host | smart-15bbccd6-2441-4f30-b19b-e00e9f722149 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668427507 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all _with_reset_error.2668427507 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.3319517840 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 107759025 ps |
| CPU time | 14.37 seconds |
| Started | Feb 07 04:11:48 PM PST 24 |
| Finished | Feb 07 04:12:02 PM PST 24 |
| Peak memory | 555652 kb |
| Host | smart-13342603-7a0b-4204-ace8-87508fe780a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319517840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.3319517840 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device.2156704845 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 2127735868 ps |
| CPU time | 90.53 seconds |
| Started | Feb 07 04:14:39 PM PST 24 |
| Finished | Feb 07 04:16:12 PM PST 24 |
| Peak memory | 555384 kb |
| Host | smart-5389bf0e-321e-43e4-9bb0-8d450391324e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156704845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device .2156704845 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.4161457801 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 36321028064 ps |
| CPU time | 641.56 seconds |
| Started | Feb 07 04:14:39 PM PST 24 |
| Finished | Feb 07 04:25:23 PM PST 24 |
| Peak memory | 555424 kb |
| Host | smart-6049b4ca-7eef-48bf-9519-849ca0a86d04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161457801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_ device_slow_rsp.4161457801 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.3530501910 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 1298998588 ps |
| CPU time | 48.62 seconds |
| Started | Feb 07 04:14:39 PM PST 24 |
| Finished | Feb 07 04:15:30 PM PST 24 |
| Peak memory | 555636 kb |
| Host | smart-67aba610-3008-404f-9bb2-c838b876138b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530501910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_add r.3530501910 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_random.1598717808 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 1398989550 ps |
| CPU time | 48.08 seconds |
| Started | Feb 07 04:14:40 PM PST 24 |
| Finished | Feb 07 04:15:30 PM PST 24 |
| Peak memory | 555428 kb |
| Host | smart-d5296410-d494-48b1-8352-9cb28d1937f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598717808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.1598717808 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random.3636226224 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 149100095 ps |
| CPU time | 14.4 seconds |
| Started | Feb 07 04:14:41 PM PST 24 |
| Finished | Feb 07 04:14:58 PM PST 24 |
| Peak memory | 555092 kb |
| Host | smart-2fbb2f26-25d2-44c8-b381-a11acdf9063e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636226224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.3636226224 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.4018449474 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 103919824676 ps |
| CPU time | 1135.98 seconds |
| Started | Feb 07 04:14:40 PM PST 24 |
| Finished | Feb 07 04:33:38 PM PST 24 |
| Peak memory | 555708 kb |
| Host | smart-0d05b741-1ece-4d0b-9807-f5d92126346e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018449474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.4018449474 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.3138282757 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 18420120347 ps |
| CPU time | 309.07 seconds |
| Started | Feb 07 04:14:45 PM PST 24 |
| Finished | Feb 07 04:19:55 PM PST 24 |
| Peak memory | 555732 kb |
| Host | smart-1f81d4e4-e9a3-4dbc-bd7d-053b4ef385b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138282757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3138282757 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.2211591511 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 294553566 ps |
| CPU time | 23.62 seconds |
| Started | Feb 07 04:14:43 PM PST 24 |
| Finished | Feb 07 04:15:08 PM PST 24 |
| Peak memory | 559140 kb |
| Host | smart-52fa7a45-ce7e-4a3b-834a-139bb827e405 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211591511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_del ays.2211591511 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_same_source.2693264891 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 1770780877 ps |
| CPU time | 56.56 seconds |
| Started | Feb 07 04:14:44 PM PST 24 |
| Finished | Feb 07 04:15:41 PM PST 24 |
| Peak memory | 555336 kb |
| Host | smart-dc12a983-7bb3-4702-bfbe-4766e249b46a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693264891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.2693264891 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke.975507591 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 45637009 ps |
| CPU time | 6.64 seconds |
| Started | Feb 07 04:14:31 PM PST 24 |
| Finished | Feb 07 04:14:40 PM PST 24 |
| Peak memory | 553600 kb |
| Host | smart-d0a318dd-3851-409b-880a-7666f242e8d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975507591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.975507591 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.2013119349 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 8125471712 ps |
| CPU time | 87.97 seconds |
| Started | Feb 07 04:14:33 PM PST 24 |
| Finished | Feb 07 04:16:04 PM PST 24 |
| Peak memory | 553356 kb |
| Host | smart-e4236a37-750b-4b3a-98c4-f5cfa74b1697 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013119349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.2013119349 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.1731652419 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 6196309303 ps |
| CPU time | 109.18 seconds |
| Started | Feb 07 04:14:31 PM PST 24 |
| Finished | Feb 07 04:16:21 PM PST 24 |
| Peak memory | 553640 kb |
| Host | smart-e980a624-8288-4c11-8280-349b342c2af2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731652419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.1731652419 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.77234672 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 40927819 ps |
| CPU time | 5.93 seconds |
| Started | Feb 07 04:14:35 PM PST 24 |
| Finished | Feb 07 04:14:42 PM PST 24 |
| Peak memory | 553572 kb |
| Host | smart-7122f54c-9a94-48e8-a1bc-37310ea14c9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77234672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.77234672 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all.3494721055 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 3161972023 ps |
| CPU time | 112.29 seconds |
| Started | Feb 07 04:14:46 PM PST 24 |
| Finished | Feb 07 04:16:38 PM PST 24 |
| Peak memory | 555528 kb |
| Host | smart-f0a1f3ad-dad0-4623-93af-241a9e701dee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494721055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.3494721055 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.1065744534 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 1050282140 ps |
| CPU time | 70.42 seconds |
| Started | Feb 07 04:14:41 PM PST 24 |
| Finished | Feb 07 04:15:53 PM PST 24 |
| Peak memory | 556496 kb |
| Host | smart-2cae4727-8f56-4ccb-a623-7f6535874cc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065744534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.1065744534 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.1336320590 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 331954419 ps |
| CPU time | 152.26 seconds |
| Started | Feb 07 04:14:42 PM PST 24 |
| Finished | Feb 07 04:17:17 PM PST 24 |
| Peak memory | 556312 kb |
| Host | smart-bcb8e7e3-6b9c-419b-aef3-7cd56d128efe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336320590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all _with_rand_reset.1336320590 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.2523455100 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 1464136156 ps |
| CPU time | 177.03 seconds |
| Started | Feb 07 04:14:39 PM PST 24 |
| Finished | Feb 07 04:17:38 PM PST 24 |
| Peak memory | 558592 kb |
| Host | smart-9019cf1a-e9b0-4b4c-a3a8-bf103bbb7a7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523455100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_al l_with_reset_error.2523455100 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.2899844688 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 432747115 ps |
| CPU time | 19.68 seconds |
| Started | Feb 07 04:14:41 PM PST 24 |
| Finished | Feb 07 04:15:02 PM PST 24 |
| Peak memory | 555436 kb |
| Host | smart-10d3d266-0e49-4b66-9e7e-327ca0aa0dae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899844688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.2899844688 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device.2232568690 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 2816675489 ps |
| CPU time | 107.66 seconds |
| Started | Feb 07 04:14:54 PM PST 24 |
| Finished | Feb 07 04:16:42 PM PST 24 |
| Peak memory | 556780 kb |
| Host | smart-e9a6c89d-ec5d-4209-8369-4e6c7d64b4dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232568690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device .2232568690 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.575773227 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 51973951278 ps |
| CPU time | 836.79 seconds |
| Started | Feb 07 04:14:53 PM PST 24 |
| Finished | Feb 07 04:28:51 PM PST 24 |
| Peak memory | 555700 kb |
| Host | smart-bfe2696d-6e57-4bc2-9cab-617ea5a5cd44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575773227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_d evice_slow_rsp.575773227 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.3037039313 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 1272118867 ps |
| CPU time | 50.98 seconds |
| Started | Feb 07 04:14:53 PM PST 24 |
| Finished | Feb 07 04:15:44 PM PST 24 |
| Peak memory | 555600 kb |
| Host | smart-75fcf34b-0602-4f2a-800f-9d55fe97f680 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037039313 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_add r.3037039313 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_random.188560965 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 505043469 ps |
| CPU time | 42.84 seconds |
| Started | Feb 07 04:14:53 PM PST 24 |
| Finished | Feb 07 04:15:37 PM PST 24 |
| Peak memory | 555356 kb |
| Host | smart-40d5219e-ff3d-4f41-80d3-8832bb67c8a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188560965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.188560965 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random.407822165 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 322640169 ps |
| CPU time | 29.84 seconds |
| Started | Feb 07 04:14:40 PM PST 24 |
| Finished | Feb 07 04:15:12 PM PST 24 |
| Peak memory | 555140 kb |
| Host | smart-aab3b9ca-b867-4adc-9de7-6d5906cf1b6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407822165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.407822165 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.52496013 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 72990032471 ps |
| CPU time | 823.77 seconds |
| Started | Feb 07 04:14:50 PM PST 24 |
| Finished | Feb 07 04:28:35 PM PST 24 |
| Peak memory | 555720 kb |
| Host | smart-039ccaba-2c20-4228-85c1-4a238536a821 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52496013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.52496013 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.628853848 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 50790403504 ps |
| CPU time | 925.98 seconds |
| Started | Feb 07 04:15:03 PM PST 24 |
| Finished | Feb 07 04:30:30 PM PST 24 |
| Peak memory | 555492 kb |
| Host | smart-951ce6ae-4faf-49db-916a-a8ca5d2feed1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628853848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.628853848 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.752646610 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 116654379 ps |
| CPU time | 13.46 seconds |
| Started | Feb 07 04:14:51 PM PST 24 |
| Finished | Feb 07 04:15:05 PM PST 24 |
| Peak memory | 559132 kb |
| Host | smart-52ea823e-3667-44a8-9ff9-2eca718b7c60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752646610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_dela ys.752646610 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_same_source.4018882552 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 434958686 ps |
| CPU time | 36.54 seconds |
| Started | Feb 07 04:14:50 PM PST 24 |
| Finished | Feb 07 04:15:27 PM PST 24 |
| Peak memory | 555284 kb |
| Host | smart-0333309e-d07c-4f95-a01e-1c195c0b7f99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018882552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.4018882552 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke.362034386 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 218347937 ps |
| CPU time | 9.28 seconds |
| Started | Feb 07 04:14:45 PM PST 24 |
| Finished | Feb 07 04:14:54 PM PST 24 |
| Peak memory | 553308 kb |
| Host | smart-acd43172-0436-4dbc-ac96-7f53c0f8ec8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362034386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.362034386 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.1747399371 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 8214459332 ps |
| CPU time | 88.1 seconds |
| Started | Feb 07 04:14:39 PM PST 24 |
| Finished | Feb 07 04:16:09 PM PST 24 |
| Peak memory | 553556 kb |
| Host | smart-758799b0-50ff-4b6a-b2c7-6f14190589af |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747399371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.1747399371 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.4116280977 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 6300677962 ps |
| CPU time | 105.81 seconds |
| Started | Feb 07 04:14:43 PM PST 24 |
| Finished | Feb 07 04:16:30 PM PST 24 |
| Peak memory | 553676 kb |
| Host | smart-b2dec2e6-adac-46c9-bba4-606558707803 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116280977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.4116280977 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.1225811086 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 49179425 ps |
| CPU time | 6 seconds |
| Started | Feb 07 04:14:41 PM PST 24 |
| Finished | Feb 07 04:14:50 PM PST 24 |
| Peak memory | 553592 kb |
| Host | smart-ef6f6813-f660-47aa-bfbe-1c7c10f38625 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225811086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delay s.1225811086 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all.2220451276 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 3265403946 ps |
| CPU time | 108.48 seconds |
| Started | Feb 07 04:15:04 PM PST 24 |
| Finished | Feb 07 04:16:53 PM PST 24 |
| Peak memory | 556848 kb |
| Host | smart-6131321c-5695-40eb-b8cb-1b36aac4a5b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220451276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.2220451276 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.3925615245 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 7468635018 ps |
| CPU time | 290.45 seconds |
| Started | Feb 07 04:14:58 PM PST 24 |
| Finished | Feb 07 04:19:49 PM PST 24 |
| Peak memory | 556644 kb |
| Host | smart-83e4a0d6-67cc-4ab4-94ea-dc611f1ac973 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925615245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3925615245 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.2424091613 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 194438341 ps |
| CPU time | 50.2 seconds |
| Started | Feb 07 04:14:57 PM PST 24 |
| Finished | Feb 07 04:15:48 PM PST 24 |
| Peak memory | 556600 kb |
| Host | smart-a2e19582-287a-4947-acd6-6ef52aea31ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424091613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all _with_rand_reset.2424091613 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.3571327434 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 209558965 ps |
| CPU time | 108.35 seconds |
| Started | Feb 07 04:14:50 PM PST 24 |
| Finished | Feb 07 04:16:39 PM PST 24 |
| Peak memory | 556832 kb |
| Host | smart-9b5e8faa-cdd1-4c90-a45c-41de3efcf80a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571327434 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_al l_with_reset_error.3571327434 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.17102055 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 1272278018 ps |
| CPU time | 52.67 seconds |
| Started | Feb 07 04:14:52 PM PST 24 |
| Finished | Feb 07 04:15:45 PM PST 24 |
| Peak memory | 555420 kb |
| Host | smart-ad3a463d-c979-4df2-953d-4905419d44e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17102055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.17102055 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.2423884459 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 379899384 ps |
| CPU time | 16.46 seconds |
| Started | Feb 07 04:15:05 PM PST 24 |
| Finished | Feb 07 04:15:22 PM PST 24 |
| Peak memory | 554572 kb |
| Host | smart-50246162-9ab3-4a6d-b6ec-fa7bce42a215 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423884459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device .2423884459 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.1193631826 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 38749308450 ps |
| CPU time | 737.38 seconds |
| Started | Feb 07 04:15:01 PM PST 24 |
| Finished | Feb 07 04:27:19 PM PST 24 |
| Peak memory | 556756 kb |
| Host | smart-93c92857-a77b-4e4f-b8fc-993e8c3cf01f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193631826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_ device_slow_rsp.1193631826 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.1814926113 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 67187465 ps |
| CPU time | 11.33 seconds |
| Started | Feb 07 04:14:57 PM PST 24 |
| Finished | Feb 07 04:15:09 PM PST 24 |
| Peak memory | 559196 kb |
| Host | smart-89141f55-0d3a-4ace-a5de-5daff96a3c15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814926113 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_add r.1814926113 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_random.639031767 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 634128792 ps |
| CPU time | 26.32 seconds |
| Started | Feb 07 04:14:58 PM PST 24 |
| Finished | Feb 07 04:15:25 PM PST 24 |
| Peak memory | 555588 kb |
| Host | smart-4d2ce222-1c1a-4ffd-8534-69ea7a479517 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639031767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.639031767 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random.1392470374 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 729215505 ps |
| CPU time | 28.79 seconds |
| Started | Feb 07 04:15:04 PM PST 24 |
| Finished | Feb 07 04:15:34 PM PST 24 |
| Peak memory | 555220 kb |
| Host | smart-c4cd989d-c97a-4b27-8db0-ed144ab5ebde |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392470374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.1392470374 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.284809594 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 19754820096 ps |
| CPU time | 209.15 seconds |
| Started | Feb 07 04:15:03 PM PST 24 |
| Finished | Feb 07 04:18:33 PM PST 24 |
| Peak memory | 555724 kb |
| Host | smart-92534617-dad6-40de-b609-fe5d8c6e5c16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284809594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.284809594 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.1393323068 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 63751668043 ps |
| CPU time | 1002.33 seconds |
| Started | Feb 07 04:15:06 PM PST 24 |
| Finished | Feb 07 04:31:49 PM PST 24 |
| Peak memory | 555668 kb |
| Host | smart-df8d96a0-08c4-4888-bd84-b1f1cde46322 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393323068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.1393323068 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.2517784199 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 479749269 ps |
| CPU time | 42.62 seconds |
| Started | Feb 07 04:14:57 PM PST 24 |
| Finished | Feb 07 04:15:40 PM PST 24 |
| Peak memory | 555400 kb |
| Host | smart-f5271d40-10e6-4915-8599-376dfa4d0d17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517784199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_del ays.2517784199 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_same_source.750434604 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 147912748 ps |
| CPU time | 8.21 seconds |
| Started | Feb 07 04:15:01 PM PST 24 |
| Finished | Feb 07 04:15:10 PM PST 24 |
| Peak memory | 553024 kb |
| Host | smart-0065fd73-b82f-4d1d-b6b9-beb32ed6bab0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750434604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.750434604 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke.2001024186 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 41765232 ps |
| CPU time | 6.18 seconds |
| Started | Feb 07 04:14:53 PM PST 24 |
| Finished | Feb 07 04:15:00 PM PST 24 |
| Peak memory | 553312 kb |
| Host | smart-b488ca27-d228-478a-9fe5-bbba41be9620 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001024186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.2001024186 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.2334277004 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 7467903558 ps |
| CPU time | 73.41 seconds |
| Started | Feb 07 04:15:04 PM PST 24 |
| Finished | Feb 07 04:16:19 PM PST 24 |
| Peak memory | 553380 kb |
| Host | smart-2b9a1901-8ddb-433f-92d7-8898263621a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334277004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.2334277004 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.3622798999 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 3804504095 ps |
| CPU time | 65.21 seconds |
| Started | Feb 07 04:14:59 PM PST 24 |
| Finished | Feb 07 04:16:05 PM PST 24 |
| Peak memory | 553680 kb |
| Host | smart-7de73c8a-e080-4dd1-b9d7-4cb2300ba155 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622798999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.3622798999 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.3615952122 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 47039582 ps |
| CPU time | 6.33 seconds |
| Started | Feb 07 04:15:06 PM PST 24 |
| Finished | Feb 07 04:15:13 PM PST 24 |
| Peak memory | 553296 kb |
| Host | smart-75551b4b-b862-49b0-80bc-550ca7f73b7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615952122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delay s.3615952122 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all.1715136948 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 5936763015 ps |
| CPU time | 229.02 seconds |
| Started | Feb 07 04:14:58 PM PST 24 |
| Finished | Feb 07 04:18:48 PM PST 24 |
| Peak memory | 556620 kb |
| Host | smart-cbd09aa6-8958-4021-b44e-de3a419c9adc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715136948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.1715136948 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.3385946999 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 4169111288 ps |
| CPU time | 370.22 seconds |
| Started | Feb 07 04:15:01 PM PST 24 |
| Finished | Feb 07 04:21:12 PM PST 24 |
| Peak memory | 557696 kb |
| Host | smart-7b864bc7-036a-4b43-b1ca-377a3e202388 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385946999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.3385946999 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.890191326 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 5208542258 ps |
| CPU time | 455.45 seconds |
| Started | Feb 07 04:14:59 PM PST 24 |
| Finished | Feb 07 04:22:35 PM PST 24 |
| Peak memory | 558956 kb |
| Host | smart-038d0e31-195d-407b-b7d4-acca72889a10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890191326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_ with_rand_reset.890191326 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.1789317542 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 730982686 ps |
| CPU time | 251.33 seconds |
| Started | Feb 07 04:15:04 PM PST 24 |
| Finished | Feb 07 04:19:16 PM PST 24 |
| Peak memory | 559376 kb |
| Host | smart-f3b2ecc4-61a8-44bf-8c75-8f47f840f706 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789317542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_al l_with_reset_error.1789317542 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.1237676813 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 291173442 ps |
| CPU time | 35.75 seconds |
| Started | Feb 07 04:15:01 PM PST 24 |
| Finished | Feb 07 04:15:37 PM PST 24 |
| Peak memory | 555716 kb |
| Host | smart-f33aa531-02a7-4ca1-bb54-2a5e1c853d56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237676813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1237676813 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device.858848741 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 376496221 ps |
| CPU time | 34.72 seconds |
| Started | Feb 07 04:15:01 PM PST 24 |
| Finished | Feb 07 04:15:37 PM PST 24 |
| Peak memory | 555668 kb |
| Host | smart-e214b907-a3d4-441c-bd50-c8d6e593c15e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858848741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device. 858848741 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.3610228257 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 102408231640 ps |
| CPU time | 1751.01 seconds |
| Started | Feb 07 04:15:06 PM PST 24 |
| Finished | Feb 07 04:44:18 PM PST 24 |
| Peak memory | 556844 kb |
| Host | smart-c22d8e82-064f-4c48-a7ad-7375e4043863 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610228257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_ device_slow_rsp.3610228257 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.1032667516 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 202009382 ps |
| CPU time | 11.61 seconds |
| Started | Feb 07 04:15:11 PM PST 24 |
| Finished | Feb 07 04:15:23 PM PST 24 |
| Peak memory | 553560 kb |
| Host | smart-7820d628-a01a-4e65-9aaa-08064ba37eea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032667516 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_add r.1032667516 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_random.709473432 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 581826006 ps |
| CPU time | 43.43 seconds |
| Started | Feb 07 04:15:07 PM PST 24 |
| Finished | Feb 07 04:15:51 PM PST 24 |
| Peak memory | 555320 kb |
| Host | smart-add2ae1e-0db3-459f-8345-5f066f6dcf8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709473432 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.709473432 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random.1536707069 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 476214819 ps |
| CPU time | 20.57 seconds |
| Started | Feb 07 04:15:01 PM PST 24 |
| Finished | Feb 07 04:15:22 PM PST 24 |
| Peak memory | 555320 kb |
| Host | smart-dd456f32-5718-4d63-9005-d23c3f6364e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536707069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.1536707069 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.1653363646 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 44529717989 ps |
| CPU time | 441.86 seconds |
| Started | Feb 07 04:15:03 PM PST 24 |
| Finished | Feb 07 04:22:26 PM PST 24 |
| Peak memory | 555424 kb |
| Host | smart-321fd662-691a-45aa-9e9e-eca51ea5de52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653363646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.1653363646 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.4279424155 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 46430385434 ps |
| CPU time | 877.46 seconds |
| Started | Feb 07 04:15:05 PM PST 24 |
| Finished | Feb 07 04:29:43 PM PST 24 |
| Peak memory | 555576 kb |
| Host | smart-97579d9f-dc63-4115-9c9c-a4bf91ebc71f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279424155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.4279424155 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.2423587790 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 36237198 ps |
| CPU time | 5.99 seconds |
| Started | Feb 07 04:15:06 PM PST 24 |
| Finished | Feb 07 04:15:12 PM PST 24 |
| Peak memory | 553288 kb |
| Host | smart-1385020c-54e8-494e-8227-746c2f2237ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423587790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_del ays.2423587790 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_same_source.2919249110 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 94172220 ps |
| CPU time | 9.78 seconds |
| Started | Feb 07 04:15:07 PM PST 24 |
| Finished | Feb 07 04:15:17 PM PST 24 |
| Peak memory | 555380 kb |
| Host | smart-c807a1b6-564a-4ad8-967d-0ed7ccedbb3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919249110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.2919249110 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke.2470650051 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 41377434 ps |
| CPU time | 6.16 seconds |
| Started | Feb 07 04:15:06 PM PST 24 |
| Finished | Feb 07 04:15:13 PM PST 24 |
| Peak memory | 553304 kb |
| Host | smart-725c63f1-4221-4048-aebe-139f2016a4c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470650051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2470650051 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.3271226916 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 8734462446 ps |
| CPU time | 87.9 seconds |
| Started | Feb 07 04:15:06 PM PST 24 |
| Finished | Feb 07 04:16:34 PM PST 24 |
| Peak memory | 559224 kb |
| Host | smart-a291f7a4-a0bc-48ab-b5b4-9c81fad548a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271226916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.3271226916 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.4169394843 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 6664610150 ps |
| CPU time | 116.28 seconds |
| Started | Feb 07 04:15:00 PM PST 24 |
| Finished | Feb 07 04:16:57 PM PST 24 |
| Peak memory | 553104 kb |
| Host | smart-e7ccbc86-8418-450f-b04f-a5f5db237fcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169394843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.4169394843 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.4219316553 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 46150109 ps |
| CPU time | 5.86 seconds |
| Started | Feb 07 04:15:04 PM PST 24 |
| Finished | Feb 07 04:15:10 PM PST 24 |
| Peak memory | 553588 kb |
| Host | smart-383e46fb-2b67-4bbc-846d-2b2d4974adb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219316553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delay s.4219316553 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all.1880907576 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 1541465381 ps |
| CPU time | 145.18 seconds |
| Started | Feb 07 04:15:10 PM PST 24 |
| Finished | Feb 07 04:17:35 PM PST 24 |
| Peak memory | 556804 kb |
| Host | smart-55ebbf56-7147-43d6-be8f-1f56ab7f88f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880907576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.1880907576 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.985549781 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 5206184172 ps |
| CPU time | 201.69 seconds |
| Started | Feb 07 04:15:06 PM PST 24 |
| Finished | Feb 07 04:18:28 PM PST 24 |
| Peak memory | 556516 kb |
| Host | smart-c6bcbade-1e2b-49e6-83e2-f167e440e644 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985549781 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.985549781 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.2172667534 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 7456162601 ps |
| CPU time | 463.24 seconds |
| Started | Feb 07 04:15:07 PM PST 24 |
| Finished | Feb 07 04:22:51 PM PST 24 |
| Peak memory | 557680 kb |
| Host | smart-4156caf4-6045-4a43-9ff5-e0a5246cc90f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172667534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all _with_rand_reset.2172667534 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.2552437816 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 2627293235 ps |
| CPU time | 192.53 seconds |
| Started | Feb 07 04:15:05 PM PST 24 |
| Finished | Feb 07 04:18:18 PM PST 24 |
| Peak memory | 557316 kb |
| Host | smart-b9e88ab4-d022-4c79-867e-238178590992 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552437816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al l_with_reset_error.2552437816 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.4079989292 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 148590692 ps |
| CPU time | 20.02 seconds |
| Started | Feb 07 04:15:11 PM PST 24 |
| Finished | Feb 07 04:15:31 PM PST 24 |
| Peak memory | 555620 kb |
| Host | smart-ade4a286-04ae-4c34-80ce-226f0043c36b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079989292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.4079989292 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.1308532711 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 1772716955 ps |
| CPU time | 73.29 seconds |
| Started | Feb 07 04:15:13 PM PST 24 |
| Finished | Feb 07 04:16:26 PM PST 24 |
| Peak memory | 555472 kb |
| Host | smart-d9c55ded-7ec5-4eb8-898f-38fa57ffa876 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308532711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device .1308532711 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.1308208500 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 98860604515 ps |
| CPU time | 1642.31 seconds |
| Started | Feb 07 04:15:16 PM PST 24 |
| Finished | Feb 07 04:42:39 PM PST 24 |
| Peak memory | 556300 kb |
| Host | smart-5cebccbb-c141-4e93-b56c-ac35fbedf638 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308208500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_ device_slow_rsp.1308208500 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.647588613 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 307395645 ps |
| CPU time | 35.39 seconds |
| Started | Feb 07 04:15:13 PM PST 24 |
| Finished | Feb 07 04:15:49 PM PST 24 |
| Peak memory | 555616 kb |
| Host | smart-d3e4de05-37e0-4178-96cc-57c2e9a41c04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647588613 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr .647588613 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_random.1929589036 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 729559423 ps |
| CPU time | 27.33 seconds |
| Started | Feb 07 04:15:13 PM PST 24 |
| Finished | Feb 07 04:15:41 PM PST 24 |
| Peak memory | 555320 kb |
| Host | smart-875c734c-186f-4042-808e-780301c84632 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929589036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1929589036 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random.3424444066 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 2497798325 ps |
| CPU time | 83.66 seconds |
| Started | Feb 07 04:15:07 PM PST 24 |
| Finished | Feb 07 04:16:31 PM PST 24 |
| Peak memory | 555700 kb |
| Host | smart-756a254a-b2ec-4b6a-ab84-1b7dea114ddd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424444066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.3424444066 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.711360199 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 24566803185 ps |
| CPU time | 279.02 seconds |
| Started | Feb 07 04:15:11 PM PST 24 |
| Finished | Feb 07 04:19:51 PM PST 24 |
| Peak memory | 555468 kb |
| Host | smart-ad4aaba5-4878-4b31-888f-9c85cb4aedc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711360199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.711360199 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.872257613 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 73917689499 ps |
| CPU time | 1263.74 seconds |
| Started | Feb 07 04:15:19 PM PST 24 |
| Finished | Feb 07 04:36:23 PM PST 24 |
| Peak memory | 555384 kb |
| Host | smart-d7921dc7-721f-4223-bd9a-3aa47becdbe9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872257613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.872257613 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.4126624710 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 328610017 ps |
| CPU time | 29.99 seconds |
| Started | Feb 07 04:15:12 PM PST 24 |
| Finished | Feb 07 04:15:42 PM PST 24 |
| Peak memory | 555652 kb |
| Host | smart-4d0fa2d0-1ec2-433e-b0b8-2aeb421b29a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126624710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_del ays.4126624710 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_same_source.195596547 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 2303418930 ps |
| CPU time | 74.28 seconds |
| Started | Feb 07 04:15:12 PM PST 24 |
| Finished | Feb 07 04:16:27 PM PST 24 |
| Peak memory | 555444 kb |
| Host | smart-7b710c10-0a02-41ff-b6f6-06ff1836afb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195596547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.195596547 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke.1599328700 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 51546768 ps |
| CPU time | 6.83 seconds |
| Started | Feb 07 04:15:09 PM PST 24 |
| Finished | Feb 07 04:15:17 PM PST 24 |
| Peak memory | 553276 kb |
| Host | smart-b31d515e-1da8-4351-a732-b14bc5faf769 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599328700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.1599328700 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.3038949805 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 8681089280 ps |
| CPU time | 89.89 seconds |
| Started | Feb 07 04:15:08 PM PST 24 |
| Finished | Feb 07 04:16:39 PM PST 24 |
| Peak memory | 553336 kb |
| Host | smart-81c952a4-e0d9-4a2f-9d34-55d0835cc745 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038949805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.3038949805 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.3673830249 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 3845868891 ps |
| CPU time | 67.13 seconds |
| Started | Feb 07 04:15:07 PM PST 24 |
| Finished | Feb 07 04:16:15 PM PST 24 |
| Peak memory | 553192 kb |
| Host | smart-6e031a2d-3771-4c22-b056-3ec0a88bc40e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673830249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.3673830249 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.391979981 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 48581771 ps |
| CPU time | 6.56 seconds |
| Started | Feb 07 04:15:10 PM PST 24 |
| Finished | Feb 07 04:15:17 PM PST 24 |
| Peak memory | 553580 kb |
| Host | smart-57eeda47-babd-4f59-b343-9a66aa8219e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391979981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays .391979981 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all.167278467 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 16261396693 ps |
| CPU time | 594.33 seconds |
| Started | Feb 07 04:15:15 PM PST 24 |
| Finished | Feb 07 04:25:10 PM PST 24 |
| Peak memory | 556560 kb |
| Host | smart-69770113-ad83-435d-9a1f-8f073d74ab87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167278467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.167278467 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.1426508249 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 6978900464 ps |
| CPU time | 229.38 seconds |
| Started | Feb 07 04:15:25 PM PST 24 |
| Finished | Feb 07 04:19:15 PM PST 24 |
| Peak memory | 556612 kb |
| Host | smart-6c247214-b035-466a-b595-c99980c129ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426508249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1426508249 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.2058274905 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 1265381651 ps |
| CPU time | 171.99 seconds |
| Started | Feb 07 04:15:28 PM PST 24 |
| Finished | Feb 07 04:18:20 PM PST 24 |
| Peak memory | 556584 kb |
| Host | smart-7e8c2f31-3c07-487c-a806-07361d448dd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058274905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_al l_with_reset_error.2058274905 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.3121919713 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 166026859 ps |
| CPU time | 8.78 seconds |
| Started | Feb 07 04:15:15 PM PST 24 |
| Finished | Feb 07 04:15:25 PM PST 24 |
| Peak memory | 559172 kb |
| Host | smart-88955b9a-adda-4595-add5-37490eae652f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121919713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3121919713 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device.2889770049 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 1562699733 ps |
| CPU time | 71.99 seconds |
| Started | Feb 07 04:15:24 PM PST 24 |
| Finished | Feb 07 04:16:36 PM PST 24 |
| Peak memory | 555644 kb |
| Host | smart-96ae40fc-307d-484c-b3b9-14a5f11ece9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889770049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device .2889770049 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.2797759719 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 89665172300 ps |
| CPU time | 1702.7 seconds |
| Started | Feb 07 04:15:25 PM PST 24 |
| Finished | Feb 07 04:43:48 PM PST 24 |
| Peak memory | 556708 kb |
| Host | smart-46959331-7fdb-4472-a83c-b36bfe4bde57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797759719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_ device_slow_rsp.2797759719 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.3096679205 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 28229205 ps |
| CPU time | 6.04 seconds |
| Started | Feb 07 04:15:38 PM PST 24 |
| Finished | Feb 07 04:15:45 PM PST 24 |
| Peak memory | 553028 kb |
| Host | smart-74374068-085b-456f-8571-9a45315c0652 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096679205 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_add r.3096679205 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_random.804971219 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 240964629 ps |
| CPU time | 21.76 seconds |
| Started | Feb 07 04:15:38 PM PST 24 |
| Finished | Feb 07 04:16:01 PM PST 24 |
| Peak memory | 555616 kb |
| Host | smart-02d14b6b-e689-44f1-9c82-6e98192b5bb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804971219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.804971219 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random.422565306 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 2442270595 ps |
| CPU time | 82.65 seconds |
| Started | Feb 07 04:15:23 PM PST 24 |
| Finished | Feb 07 04:16:46 PM PST 24 |
| Peak memory | 555492 kb |
| Host | smart-7e4ece32-3f89-4bf4-9716-3b3ac39f418e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422565306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.422565306 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.1006298138 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 88840901968 ps |
| CPU time | 967.46 seconds |
| Started | Feb 07 04:15:26 PM PST 24 |
| Finished | Feb 07 04:31:34 PM PST 24 |
| Peak memory | 555708 kb |
| Host | smart-beae83d7-62ef-448f-ba89-530d427278d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006298138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.1006298138 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.1098710872 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 62356436061 ps |
| CPU time | 1153.38 seconds |
| Started | Feb 07 04:15:26 PM PST 24 |
| Finished | Feb 07 04:34:40 PM PST 24 |
| Peak memory | 555216 kb |
| Host | smart-37767f7e-1cc5-4f22-9dc6-802518c8c800 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098710872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.1098710872 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.2843241516 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 543151501 ps |
| CPU time | 48.51 seconds |
| Started | Feb 07 04:15:26 PM PST 24 |
| Finished | Feb 07 04:16:15 PM PST 24 |
| Peak memory | 555380 kb |
| Host | smart-1ff38487-52da-4f13-b788-89aaead09f44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843241516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_del ays.2843241516 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_same_source.4211384902 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 99608164 ps |
| CPU time | 10.5 seconds |
| Started | Feb 07 04:15:28 PM PST 24 |
| Finished | Feb 07 04:15:39 PM PST 24 |
| Peak memory | 555308 kb |
| Host | smart-7ede114a-523a-4134-ae32-5593b1183da3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211384902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.4211384902 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke.1523800596 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 41643247 ps |
| CPU time | 5.87 seconds |
| Started | Feb 07 04:15:25 PM PST 24 |
| Finished | Feb 07 04:15:31 PM PST 24 |
| Peak memory | 553272 kb |
| Host | smart-b49e08d9-e162-4d2d-a2d9-5a4620aec989 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523800596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1523800596 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.1130949820 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 5561627103 ps |
| CPU time | 57.68 seconds |
| Started | Feb 07 04:15:27 PM PST 24 |
| Finished | Feb 07 04:16:25 PM PST 24 |
| Peak memory | 553716 kb |
| Host | smart-83de8f8b-6b17-4978-b4f6-9645636427cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130949820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1130949820 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.2866593018 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 5450825972 ps |
| CPU time | 94.45 seconds |
| Started | Feb 07 04:15:26 PM PST 24 |
| Finished | Feb 07 04:17:01 PM PST 24 |
| Peak memory | 553344 kb |
| Host | smart-8988872d-48fc-425a-8818-94f93f05bac8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866593018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.2866593018 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.1931156239 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 45317450 ps |
| CPU time | 6.66 seconds |
| Started | Feb 07 04:15:24 PM PST 24 |
| Finished | Feb 07 04:15:31 PM PST 24 |
| Peak memory | 553292 kb |
| Host | smart-c64fe19c-a64a-4b62-ae30-52b7f40edcb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931156239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delay s.1931156239 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all.3733806239 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 13480231538 ps |
| CPU time | 531.88 seconds |
| Started | Feb 07 04:15:36 PM PST 24 |
| Finished | Feb 07 04:24:28 PM PST 24 |
| Peak memory | 557368 kb |
| Host | smart-c6649540-632b-4466-8af0-61d1ef5ee249 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733806239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.3733806239 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.226828517 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 13059965467 ps |
| CPU time | 445.38 seconds |
| Started | Feb 07 04:15:41 PM PST 24 |
| Finished | Feb 07 04:23:07 PM PST 24 |
| Peak memory | 556896 kb |
| Host | smart-eca94979-675b-4c17-9426-8ee9a5d94542 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226828517 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.226828517 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.1473265150 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 5785196512 ps |
| CPU time | 462.34 seconds |
| Started | Feb 07 04:15:35 PM PST 24 |
| Finished | Feb 07 04:23:17 PM PST 24 |
| Peak memory | 558308 kb |
| Host | smart-c577b125-7002-49b3-b8b5-2d624414cfba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473265150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all _with_rand_reset.1473265150 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.3750562924 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 321928723 ps |
| CPU time | 74.39 seconds |
| Started | Feb 07 04:15:36 PM PST 24 |
| Finished | Feb 07 04:16:50 PM PST 24 |
| Peak memory | 556560 kb |
| Host | smart-5010cfe7-a0ff-4472-a06b-4d4d9a9555a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750562924 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_al l_with_reset_error.3750562924 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.584338607 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 496329944 ps |
| CPU time | 22.6 seconds |
| Started | Feb 07 04:15:35 PM PST 24 |
| Finished | Feb 07 04:15:58 PM PST 24 |
| Peak memory | 555644 kb |
| Host | smart-df85fa5d-73cb-48f6-b92d-11cbfd50366a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584338607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.584338607 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device.519983767 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 1061978986 ps |
| CPU time | 52.29 seconds |
| Started | Feb 07 04:15:47 PM PST 24 |
| Finished | Feb 07 04:16:40 PM PST 24 |
| Peak memory | 555304 kb |
| Host | smart-cfc8e852-0e23-4595-a344-0b27c1bf152d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519983767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device. 519983767 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.960562749 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 18117914073 ps |
| CPU time | 341.68 seconds |
| Started | Feb 07 04:15:45 PM PST 24 |
| Finished | Feb 07 04:21:27 PM PST 24 |
| Peak memory | 555716 kb |
| Host | smart-316de4c3-b4ca-4d0c-81e1-9515ccb2df72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960562749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_d evice_slow_rsp.960562749 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.3747743985 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 823003346 ps |
| CPU time | 31.78 seconds |
| Started | Feb 07 04:15:48 PM PST 24 |
| Finished | Feb 07 04:16:21 PM PST 24 |
| Peak memory | 555084 kb |
| Host | smart-33d01dc2-25a5-4459-87de-7ea8f6a99ea4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747743985 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_add r.3747743985 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_random.4263391743 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 524720460 ps |
| CPU time | 38.46 seconds |
| Started | Feb 07 04:15:45 PM PST 24 |
| Finished | Feb 07 04:16:23 PM PST 24 |
| Peak memory | 555604 kb |
| Host | smart-38ad8240-d86f-4ba5-805a-2fe8a0344caa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263391743 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.4263391743 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random.181415226 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 280559144 ps |
| CPU time | 13.66 seconds |
| Started | Feb 07 04:15:41 PM PST 24 |
| Finished | Feb 07 04:15:55 PM PST 24 |
| Peak memory | 555136 kb |
| Host | smart-38cad683-7bd2-406a-9691-c4dba54d0148 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181415226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.181415226 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.2403079673 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 18597130721 ps |
| CPU time | 231.07 seconds |
| Started | Feb 07 04:15:37 PM PST 24 |
| Finished | Feb 07 04:19:28 PM PST 24 |
| Peak memory | 555452 kb |
| Host | smart-41359594-a83a-41ba-9cff-0ab6e58efa74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403079673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2403079673 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.584932942 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 46907094481 ps |
| CPU time | 861.05 seconds |
| Started | Feb 07 04:15:46 PM PST 24 |
| Finished | Feb 07 04:30:08 PM PST 24 |
| Peak memory | 555680 kb |
| Host | smart-bda38cf3-e311-4bb0-90ae-e070fc1f3655 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584932942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.584932942 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.611926134 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 164741116 ps |
| CPU time | 17.19 seconds |
| Started | Feb 07 04:15:44 PM PST 24 |
| Finished | Feb 07 04:16:01 PM PST 24 |
| Peak memory | 555388 kb |
| Host | smart-2d5a3167-e0f0-49e8-9598-a263a649f59e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611926134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_dela ys.611926134 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_same_source.1739846889 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 704039457 ps |
| CPU time | 22.86 seconds |
| Started | Feb 07 04:15:48 PM PST 24 |
| Finished | Feb 07 04:16:11 PM PST 24 |
| Peak memory | 555668 kb |
| Host | smart-6a41e81c-943d-473b-b296-671c8cf78117 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739846889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.1739846889 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke.467484925 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 43502847 ps |
| CPU time | 6.2 seconds |
| Started | Feb 07 04:15:38 PM PST 24 |
| Finished | Feb 07 04:15:44 PM PST 24 |
| Peak memory | 553520 kb |
| Host | smart-74d1c295-9aa4-47de-984d-ddabf8d21f4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467484925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.467484925 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.1731543495 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 6623242146 ps |
| CPU time | 75.42 seconds |
| Started | Feb 07 04:15:36 PM PST 24 |
| Finished | Feb 07 04:16:52 PM PST 24 |
| Peak memory | 553388 kb |
| Host | smart-fddc6f68-313a-423b-a44a-a275cbcdc67a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731543495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.1731543495 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.1317750985 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 5260672001 ps |
| CPU time | 91.04 seconds |
| Started | Feb 07 04:15:36 PM PST 24 |
| Finished | Feb 07 04:17:07 PM PST 24 |
| Peak memory | 553652 kb |
| Host | smart-ef32a2b7-8bf8-4487-891c-3afb97937a5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317750985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.1317750985 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.502426755 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 45782095 ps |
| CPU time | 6.53 seconds |
| Started | Feb 07 04:15:37 PM PST 24 |
| Finished | Feb 07 04:15:44 PM PST 24 |
| Peak memory | 553580 kb |
| Host | smart-f92a273e-17df-4146-a255-efb9f14775a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502426755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays .502426755 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all.2835703316 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 1989244519 ps |
| CPU time | 160.55 seconds |
| Started | Feb 07 04:15:47 PM PST 24 |
| Finished | Feb 07 04:18:28 PM PST 24 |
| Peak memory | 556832 kb |
| Host | smart-a8b2621b-f0c6-4858-ab69-38df98947053 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835703316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.2835703316 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.517254142 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 1694227283 ps |
| CPU time | 118.38 seconds |
| Started | Feb 07 04:15:47 PM PST 24 |
| Finished | Feb 07 04:17:45 PM PST 24 |
| Peak memory | 556792 kb |
| Host | smart-327f22e5-c0c7-4e24-8008-ae87e3c3fb2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517254142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.517254142 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.3548547566 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 415610694 ps |
| CPU time | 139.19 seconds |
| Started | Feb 07 04:15:46 PM PST 24 |
| Finished | Feb 07 04:18:06 PM PST 24 |
| Peak memory | 557612 kb |
| Host | smart-fd48605c-9304-4564-8bf2-398533246194 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548547566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all _with_rand_reset.3548547566 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.1892042523 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 4037407147 ps |
| CPU time | 444.84 seconds |
| Started | Feb 07 04:15:47 PM PST 24 |
| Finished | Feb 07 04:23:12 PM PST 24 |
| Peak memory | 559360 kb |
| Host | smart-8fe8b70e-3836-4a71-b0db-ecd90e9f1586 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892042523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_al l_with_reset_error.1892042523 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.2275725077 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 71049981 ps |
| CPU time | 10.12 seconds |
| Started | Feb 07 04:15:52 PM PST 24 |
| Finished | Feb 07 04:16:03 PM PST 24 |
| Peak memory | 555404 kb |
| Host | smart-776d3be8-a6ea-4520-86f1-25d28bd0123f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275725077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2275725077 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device.3437789276 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 265603462 ps |
| CPU time | 15.52 seconds |
| Started | Feb 07 04:15:52 PM PST 24 |
| Finished | Feb 07 04:16:08 PM PST 24 |
| Peak memory | 555656 kb |
| Host | smart-c584b8f6-802a-433d-ac3b-b13f7098db1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437789276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device .3437789276 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.2789615265 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 81184919914 ps |
| CPU time | 1286.44 seconds |
| Started | Feb 07 04:16:09 PM PST 24 |
| Finished | Feb 07 04:37:36 PM PST 24 |
| Peak memory | 556504 kb |
| Host | smart-102c6619-a240-44d0-9f9b-bdb76f1e3805 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789615265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_ device_slow_rsp.2789615265 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.3895317774 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 741917867 ps |
| CPU time | 27.7 seconds |
| Started | Feb 07 04:15:50 PM PST 24 |
| Finished | Feb 07 04:16:18 PM PST 24 |
| Peak memory | 555636 kb |
| Host | smart-d05ff4a3-3852-445c-bda8-e5bd6ac99d5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895317774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_add r.3895317774 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_random.472613634 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 497688910 ps |
| CPU time | 39.93 seconds |
| Started | Feb 07 04:15:58 PM PST 24 |
| Finished | Feb 07 04:16:38 PM PST 24 |
| Peak memory | 555492 kb |
| Host | smart-edf4fdbf-dc38-4285-a0fd-f5ff813570ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472613634 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.472613634 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random.898788324 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 1155289889 ps |
| CPU time | 41.53 seconds |
| Started | Feb 07 04:15:46 PM PST 24 |
| Finished | Feb 07 04:16:28 PM PST 24 |
| Peak memory | 555684 kb |
| Host | smart-6dd19601-7cc3-49b9-8518-4ad0b4d1c589 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898788324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.898788324 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.191460475 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 46151276717 ps |
| CPU time | 510.69 seconds |
| Started | Feb 07 04:16:06 PM PST 24 |
| Finished | Feb 07 04:24:38 PM PST 24 |
| Peak memory | 555708 kb |
| Host | smart-b7174101-7098-4e8c-83de-45831f3fed92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191460475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.191460475 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.643752637 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 54584207556 ps |
| CPU time | 944.29 seconds |
| Started | Feb 07 04:15:55 PM PST 24 |
| Finished | Feb 07 04:31:40 PM PST 24 |
| Peak memory | 555724 kb |
| Host | smart-e4e0f2d7-1934-40e7-87af-032feb5b680b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643752637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.643752637 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.1715066036 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 517293774 ps |
| CPU time | 46.21 seconds |
| Started | Feb 07 04:15:45 PM PST 24 |
| Finished | Feb 07 04:16:32 PM PST 24 |
| Peak memory | 555656 kb |
| Host | smart-c87f20c8-13ad-4b19-b400-0c74c25e712c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715066036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_del ays.1715066036 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_same_source.2996310800 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 112666779 ps |
| CPU time | 10.7 seconds |
| Started | Feb 07 04:15:52 PM PST 24 |
| Finished | Feb 07 04:16:03 PM PST 24 |
| Peak memory | 555604 kb |
| Host | smart-69fd2a1f-c205-4b05-8e2c-2d2b262a2285 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996310800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2996310800 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke.1591574586 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 47551013 ps |
| CPU time | 6.84 seconds |
| Started | Feb 07 04:15:48 PM PST 24 |
| Finished | Feb 07 04:15:55 PM PST 24 |
| Peak memory | 553248 kb |
| Host | smart-97f6a326-7b6a-47a2-a5cb-9ec22809b01e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591574586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.1591574586 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.741558671 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 10008713917 ps |
| CPU time | 112.65 seconds |
| Started | Feb 07 04:15:47 PM PST 24 |
| Finished | Feb 07 04:17:40 PM PST 24 |
| Peak memory | 553380 kb |
| Host | smart-4e6c1cf9-2154-4aa9-868f-99ccbb43d662 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741558671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.741558671 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.2105474051 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 5749350135 ps |
| CPU time | 100.44 seconds |
| Started | Feb 07 04:15:46 PM PST 24 |
| Finished | Feb 07 04:17:27 PM PST 24 |
| Peak memory | 559244 kb |
| Host | smart-55e3e8a6-0823-48e1-b8d2-bafa18c31f3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105474051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.2105474051 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.2401763220 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 38736392 ps |
| CPU time | 5.82 seconds |
| Started | Feb 07 04:15:46 PM PST 24 |
| Finished | Feb 07 04:15:52 PM PST 24 |
| Peak memory | 553300 kb |
| Host | smart-f4f251db-cd55-4799-bdf5-ef29055b0ec0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401763220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delay s.2401763220 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all.1078698960 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 2069086149 ps |
| CPU time | 190.36 seconds |
| Started | Feb 07 04:15:52 PM PST 24 |
| Finished | Feb 07 04:19:03 PM PST 24 |
| Peak memory | 557804 kb |
| Host | smart-d985d410-d7a4-42f6-a999-4d8bbf8fb880 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078698960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.1078698960 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.3780110653 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 540727039 ps |
| CPU time | 35.55 seconds |
| Started | Feb 07 04:15:57 PM PST 24 |
| Finished | Feb 07 04:16:34 PM PST 24 |
| Peak memory | 555544 kb |
| Host | smart-be83f0e7-c8ee-4565-9a5e-6bbf03c6d222 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780110653 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.3780110653 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.4204889635 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 699574189 ps |
| CPU time | 135.41 seconds |
| Started | Feb 07 04:15:52 PM PST 24 |
| Finished | Feb 07 04:18:08 PM PST 24 |
| Peak memory | 556588 kb |
| Host | smart-c5c1e67a-4019-49f5-862e-51a0e8f07fbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204889635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all _with_rand_reset.4204889635 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.1635682053 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 4779742108 ps |
| CPU time | 525.54 seconds |
| Started | Feb 07 04:16:08 PM PST 24 |
| Finished | Feb 07 04:24:54 PM PST 24 |
| Peak memory | 559428 kb |
| Host | smart-750397e3-208a-4164-aab1-a987ffd9501e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635682053 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_al l_with_reset_error.1635682053 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.1150395132 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 94372834 ps |
| CPU time | 12.98 seconds |
| Started | Feb 07 04:15:54 PM PST 24 |
| Finished | Feb 07 04:16:07 PM PST 24 |
| Peak memory | 555680 kb |
| Host | smart-362e076d-c9ad-42b0-923e-5b6030a84764 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150395132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1150395132 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device.1565950726 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 415913247 ps |
| CPU time | 38.81 seconds |
| Started | Feb 07 04:16:04 PM PST 24 |
| Finished | Feb 07 04:16:44 PM PST 24 |
| Peak memory | 556496 kb |
| Host | smart-cf991a23-6fa4-418e-939b-7cc46ce4024f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565950726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device .1565950726 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.2618916990 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 105227128162 ps |
| CPU time | 1906.07 seconds |
| Started | Feb 07 04:16:06 PM PST 24 |
| Finished | Feb 07 04:47:53 PM PST 24 |
| Peak memory | 556220 kb |
| Host | smart-8470b535-06d7-4215-84a9-bba815ee4f8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618916990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_ device_slow_rsp.2618916990 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.3878870304 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 1342318755 ps |
| CPU time | 59.02 seconds |
| Started | Feb 07 04:15:56 PM PST 24 |
| Finished | Feb 07 04:16:56 PM PST 24 |
| Peak memory | 555336 kb |
| Host | smart-704c3331-468b-4d81-802e-dfdce76a9e98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878870304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_add r.3878870304 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_random.773743215 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 501299501 ps |
| CPU time | 44.79 seconds |
| Started | Feb 07 04:15:59 PM PST 24 |
| Finished | Feb 07 04:16:48 PM PST 24 |
| Peak memory | 555328 kb |
| Host | smart-7d097d7d-4885-43d4-93d1-733f1ca5e879 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773743215 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.773743215 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random.1854756130 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 863119998 ps |
| CPU time | 32.47 seconds |
| Started | Feb 07 04:15:59 PM PST 24 |
| Finished | Feb 07 04:16:32 PM PST 24 |
| Peak memory | 555308 kb |
| Host | smart-a1ea7c4f-1ae1-4b49-9aaa-fa0633f61f46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854756130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.1854756130 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.2793418658 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 75723689248 ps |
| CPU time | 884.27 seconds |
| Started | Feb 07 04:16:02 PM PST 24 |
| Finished | Feb 07 04:30:49 PM PST 24 |
| Peak memory | 555428 kb |
| Host | smart-bd9a4928-f990-4500-8ae3-714bf1e6eee1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793418658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.2793418658 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.991555307 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 21241083101 ps |
| CPU time | 368.01 seconds |
| Started | Feb 07 04:16:03 PM PST 24 |
| Finished | Feb 07 04:22:12 PM PST 24 |
| Peak memory | 559260 kb |
| Host | smart-1b25e10d-cd54-487c-8eaf-34aec4d2756d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991555307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.991555307 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.1908789241 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 43593591 ps |
| CPU time | 7.26 seconds |
| Started | Feb 07 04:16:03 PM PST 24 |
| Finished | Feb 07 04:16:11 PM PST 24 |
| Peak memory | 553272 kb |
| Host | smart-4bb3c2b3-cb64-46a6-b101-123fae76c7a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908789241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_del ays.1908789241 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_same_source.3630413874 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 261958536 ps |
| CPU time | 19.84 seconds |
| Started | Feb 07 04:15:59 PM PST 24 |
| Finished | Feb 07 04:16:20 PM PST 24 |
| Peak memory | 555380 kb |
| Host | smart-9cdfc29c-e2e5-4304-90d7-bf71bd07d674 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630413874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.3630413874 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke.1286022077 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 163889125 ps |
| CPU time | 8.46 seconds |
| Started | Feb 07 04:15:54 PM PST 24 |
| Finished | Feb 07 04:16:03 PM PST 24 |
| Peak memory | 553300 kb |
| Host | smart-23aee1b4-9b89-4489-952f-d9049fee6179 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286022077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.1286022077 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.2435096573 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 10520957498 ps |
| CPU time | 112.19 seconds |
| Started | Feb 07 04:15:53 PM PST 24 |
| Finished | Feb 07 04:17:45 PM PST 24 |
| Peak memory | 553624 kb |
| Host | smart-c0fe1ac3-0c0a-4b62-ab4d-c8ea2859af56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435096573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2435096573 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.970996075 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 6897603203 ps |
| CPU time | 128.18 seconds |
| Started | Feb 07 04:15:56 PM PST 24 |
| Finished | Feb 07 04:18:05 PM PST 24 |
| Peak memory | 553404 kb |
| Host | smart-5367dedf-7d83-4de0-84e4-3aea6e8b15fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970996075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.970996075 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.1676984733 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 49141067 ps |
| CPU time | 6.24 seconds |
| Started | Feb 07 04:15:55 PM PST 24 |
| Finished | Feb 07 04:16:01 PM PST 24 |
| Peak memory | 553560 kb |
| Host | smart-11a4bdf8-e3fa-4e6b-997a-77a504df1a21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676984733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delay s.1676984733 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all.3151512005 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 6688000790 ps |
| CPU time | 262.89 seconds |
| Started | Feb 07 04:16:07 PM PST 24 |
| Finished | Feb 07 04:20:30 PM PST 24 |
| Peak memory | 556864 kb |
| Host | smart-ec057c8c-4b84-4899-aaa8-de0e6d23eef2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151512005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.3151512005 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.1747992301 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 763655309 ps |
| CPU time | 28.16 seconds |
| Started | Feb 07 04:16:07 PM PST 24 |
| Finished | Feb 07 04:16:36 PM PST 24 |
| Peak memory | 556680 kb |
| Host | smart-59ddb0fb-dcd3-486f-b668-ad83b956d74e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747992301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.1747992301 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.2918347027 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 5190550904 ps |
| CPU time | 211.09 seconds |
| Started | Feb 07 04:16:04 PM PST 24 |
| Finished | Feb 07 04:19:36 PM PST 24 |
| Peak memory | 557096 kb |
| Host | smart-9e0d6852-1bee-4dc8-adb5-5113597ed3ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918347027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all _with_rand_reset.2918347027 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.945651589 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 774373273 ps |
| CPU time | 121.7 seconds |
| Started | Feb 07 04:16:08 PM PST 24 |
| Finished | Feb 07 04:18:11 PM PST 24 |
| Peak memory | 557224 kb |
| Host | smart-d168dcd0-6595-4d39-829e-8f6a69775793 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945651589 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all _with_reset_error.945651589 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.271753737 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 1153972024 ps |
| CPU time | 53.17 seconds |
| Started | Feb 07 04:15:59 PM PST 24 |
| Finished | Feb 07 04:16:53 PM PST 24 |
| Peak memory | 555392 kb |
| Host | smart-c31b264a-7564-41c0-a673-adfe5114833e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271753737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.271753737 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device.1439001285 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 461443436 ps |
| CPU time | 37.46 seconds |
| Started | Feb 07 04:16:09 PM PST 24 |
| Finished | Feb 07 04:16:47 PM PST 24 |
| Peak memory | 555408 kb |
| Host | smart-85c0abca-7f71-4149-b3f0-64a5e7dabe16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439001285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device .1439001285 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.4239114431 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 123154067136 ps |
| CPU time | 2347.07 seconds |
| Started | Feb 07 04:16:11 PM PST 24 |
| Finished | Feb 07 04:55:21 PM PST 24 |
| Peak memory | 556820 kb |
| Host | smart-2947272e-3ea9-4287-8b69-425be4b760c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239114431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_ device_slow_rsp.4239114431 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.1479686542 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 779802585 ps |
| CPU time | 36.91 seconds |
| Started | Feb 07 04:16:11 PM PST 24 |
| Finished | Feb 07 04:16:51 PM PST 24 |
| Peak memory | 555608 kb |
| Host | smart-910de847-29af-4553-9e07-5369ddf7f1cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479686542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_add r.1479686542 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_random.2410416499 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 211419865 ps |
| CPU time | 18.71 seconds |
| Started | Feb 07 04:16:08 PM PST 24 |
| Finished | Feb 07 04:16:27 PM PST 24 |
| Peak memory | 555636 kb |
| Host | smart-7b151abe-873a-47d6-b1c9-74b9ff51b816 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410416499 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.2410416499 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random.2739704721 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 1877861100 ps |
| CPU time | 73.09 seconds |
| Started | Feb 07 04:16:11 PM PST 24 |
| Finished | Feb 07 04:17:27 PM PST 24 |
| Peak memory | 555108 kb |
| Host | smart-7dd78d49-3c0d-47a4-a896-d24eb8bbf450 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739704721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.2739704721 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.3788154776 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 88205568365 ps |
| CPU time | 1082.38 seconds |
| Started | Feb 07 04:16:08 PM PST 24 |
| Finished | Feb 07 04:34:11 PM PST 24 |
| Peak memory | 555752 kb |
| Host | smart-2a45b0ff-e3e6-4c35-9e16-78de88b0eeb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788154776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.3788154776 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.2736135432 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 7034080129 ps |
| CPU time | 131.62 seconds |
| Started | Feb 07 04:16:13 PM PST 24 |
| Finished | Feb 07 04:18:26 PM PST 24 |
| Peak memory | 554692 kb |
| Host | smart-a909abe8-a5cf-4cf3-833e-93628167f587 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736135432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.2736135432 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.4130653113 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 326980342 ps |
| CPU time | 30.2 seconds |
| Started | Feb 07 04:16:10 PM PST 24 |
| Finished | Feb 07 04:16:44 PM PST 24 |
| Peak memory | 555376 kb |
| Host | smart-f8891ffc-9e4c-4c8a-9b78-fe4d2fb2b743 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130653113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_del ays.4130653113 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_same_source.88605045 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 1990761267 ps |
| CPU time | 64.47 seconds |
| Started | Feb 07 04:16:13 PM PST 24 |
| Finished | Feb 07 04:17:18 PM PST 24 |
| Peak memory | 555484 kb |
| Host | smart-18536b63-21a5-43ea-8b44-020c57e8c34a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88605045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.88605045 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke.3746410276 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 251215400 ps |
| CPU time | 10.67 seconds |
| Started | Feb 07 04:16:02 PM PST 24 |
| Finished | Feb 07 04:16:15 PM PST 24 |
| Peak memory | 553304 kb |
| Host | smart-fcca1a17-e5c0-4575-b865-a96c15257d53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746410276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.3746410276 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.1371750036 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 8276417200 ps |
| CPU time | 89.85 seconds |
| Started | Feb 07 04:16:12 PM PST 24 |
| Finished | Feb 07 04:17:44 PM PST 24 |
| Peak memory | 553260 kb |
| Host | smart-d9868deb-d887-4886-a284-c9bf1d5255d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371750036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.1371750036 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.2367315372 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 5399579175 ps |
| CPU time | 97.91 seconds |
| Started | Feb 07 04:16:09 PM PST 24 |
| Finished | Feb 07 04:17:48 PM PST 24 |
| Peak memory | 553684 kb |
| Host | smart-22f0627e-4181-4d04-a2a7-525d359fc246 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367315372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.2367315372 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.1774867710 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 43656828 ps |
| CPU time | 6.27 seconds |
| Started | Feb 07 04:16:10 PM PST 24 |
| Finished | Feb 07 04:16:20 PM PST 24 |
| Peak memory | 553272 kb |
| Host | smart-c6554c74-7b1d-4101-953d-62d67ea946f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774867710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delay s.1774867710 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all.498512779 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 12844503936 ps |
| CPU time | 470.12 seconds |
| Started | Feb 07 04:16:10 PM PST 24 |
| Finished | Feb 07 04:24:04 PM PST 24 |
| Peak memory | 556624 kb |
| Host | smart-ad7e0983-0e56-44d6-8346-a1c35191f13e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498512779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.498512779 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.423070574 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 1749181712 ps |
| CPU time | 139.26 seconds |
| Started | Feb 07 04:16:24 PM PST 24 |
| Finished | Feb 07 04:18:46 PM PST 24 |
| Peak memory | 556768 kb |
| Host | smart-b024564f-5152-4eb8-bbb3-6083d975ef6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423070574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.423070574 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.2779768058 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 81053958 ps |
| CPU time | 30.24 seconds |
| Started | Feb 07 04:16:27 PM PST 24 |
| Finished | Feb 07 04:16:59 PM PST 24 |
| Peak memory | 555852 kb |
| Host | smart-b55ebf4f-edf0-4e50-a41c-4415c8b8a75b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779768058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all _with_rand_reset.2779768058 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.3723387125 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 221269134 ps |
| CPU time | 137.01 seconds |
| Started | Feb 07 04:16:23 PM PST 24 |
| Finished | Feb 07 04:18:42 PM PST 24 |
| Peak memory | 559324 kb |
| Host | smart-6be7fd26-df8f-4c60-8dc4-435798103203 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723387125 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_al l_with_reset_error.3723387125 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.2145048872 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 1176662296 ps |
| CPU time | 52.65 seconds |
| Started | Feb 07 04:16:07 PM PST 24 |
| Finished | Feb 07 04:17:01 PM PST 24 |
| Peak memory | 555396 kb |
| Host | smart-f8f0d5e7-d826-4cd2-bab4-117a6e39cd7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145048872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.2145048872 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.3766291 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 32212082836 ps |
| CPU time | 5841.46 seconds |
| Started | Feb 07 04:11:48 PM PST 24 |
| Finished | Feb 07 05:49:11 PM PST 24 |
| Peak memory | 579460 kb |
| Host | smart-6e1f6c1d-aba9-4117-bf49-eafab75fadba |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766291 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.chip_csr_aliasing.3766291 |
| Directory | /workspace/4.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.4099434871 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 11955915472 ps |
| CPU time | 1125.34 seconds |
| Started | Feb 07 04:11:46 PM PST 24 |
| Finished | Feb 07 04:30:32 PM PST 24 |
| Peak memory | 580232 kb |
| Host | smart-f6ab01b0-ad67-4c18-98f8-223f6c8bf936 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099434871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.4099434871 |
| Directory | /workspace/4.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.4215166633 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 10586718545 ps |
| CPU time | 348.51 seconds |
| Started | Feb 07 04:11:50 PM PST 24 |
| Finished | Feb 07 04:17:39 PM PST 24 |
| Peak memory | 621228 kb |
| Host | smart-31644e08-8ea0-463f-b74b-cb98524647d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215166633 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 4.chip_csr_mem_rw_with_rand_reset.4215166633 |
| Directory | /workspace/4.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_rw.3447606874 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 5428657460 ps |
| CPU time | 595.42 seconds |
| Started | Feb 07 04:11:52 PM PST 24 |
| Finished | Feb 07 04:21:48 PM PST 24 |
| Peak memory | 579832 kb |
| Host | smart-6c187ba5-f700-49a5-9b24-0871ca66ca99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447606874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.3447606874 |
| Directory | /workspace/4.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.3639535588 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 16034130900 ps |
| CPU time | 1539.8 seconds |
| Started | Feb 07 04:11:48 PM PST 24 |
| Finished | Feb 07 04:37:28 PM PST 24 |
| Peak memory | 580224 kb |
| Host | smart-e52c4c96-301f-4b7d-bffa-8103fea5be1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639535588 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 4.chip_same_csr_outstanding.3639535588 |
| Directory | /workspace/4.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_tl_errors.933870054 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 4476836560 ps |
| CPU time | 405.96 seconds |
| Started | Feb 07 04:11:45 PM PST 24 |
| Finished | Feb 07 04:18:31 PM PST 24 |
| Peak memory | 580348 kb |
| Host | smart-f2850274-64ed-49e5-a786-d6e4d50054a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933870054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.933870054 |
| Directory | /workspace/4.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device.85968245 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 15943220 ps |
| CPU time | 5.62 seconds |
| Started | Feb 07 04:11:49 PM PST 24 |
| Finished | Feb 07 04:11:55 PM PST 24 |
| Peak memory | 553292 kb |
| Host | smart-ac55c84b-886e-4ffa-aa42-0ad74baa2e45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85968245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.85968245 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.3902044798 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 142088914239 ps |
| CPU time | 2328.7 seconds |
| Started | Feb 07 04:11:47 PM PST 24 |
| Finished | Feb 07 04:50:36 PM PST 24 |
| Peak memory | 556596 kb |
| Host | smart-ed441e96-0b64-4404-b89f-071585a1aca8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902044798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_d evice_slow_rsp.3902044798 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.45625273 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 251492547 ps |
| CPU time | 26.47 seconds |
| Started | Feb 07 04:11:47 PM PST 24 |
| Finished | Feb 07 04:12:14 PM PST 24 |
| Peak memory | 555304 kb |
| Host | smart-93d1f340-eae5-4475-8b2b-32e96c25d37c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45625273 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.45625273 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_random.3472176350 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 1392896043 ps |
| CPU time | 44.16 seconds |
| Started | Feb 07 04:11:41 PM PST 24 |
| Finished | Feb 07 04:12:25 PM PST 24 |
| Peak memory | 555300 kb |
| Host | smart-4d45dbff-7a2a-4c31-a257-60982edc9da2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472176350 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3472176350 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random.1575369728 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 584961118 ps |
| CPU time | 26.92 seconds |
| Started | Feb 07 04:11:43 PM PST 24 |
| Finished | Feb 07 04:12:11 PM PST 24 |
| Peak memory | 555320 kb |
| Host | smart-6c8f61d6-bff8-428b-bb46-e98347f42794 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575369728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.1575369728 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.3900563088 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 17221749479 ps |
| CPU time | 202.27 seconds |
| Started | Feb 07 04:11:47 PM PST 24 |
| Finished | Feb 07 04:15:09 PM PST 24 |
| Peak memory | 555684 kb |
| Host | smart-f0e03964-1bdb-4f78-8cf5-78ceb96af221 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900563088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.3900563088 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.1639693629 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 12614580416 ps |
| CPU time | 209.06 seconds |
| Started | Feb 07 04:11:48 PM PST 24 |
| Finished | Feb 07 04:15:17 PM PST 24 |
| Peak memory | 555584 kb |
| Host | smart-f0e548fd-3f2e-4012-9654-c2409d44137e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639693629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1639693629 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.1499508212 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 377638338 ps |
| CPU time | 35.55 seconds |
| Started | Feb 07 04:11:47 PM PST 24 |
| Finished | Feb 07 04:12:23 PM PST 24 |
| Peak memory | 555676 kb |
| Host | smart-f018971d-d870-4ea4-b499-4325e477249f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499508212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_dela ys.1499508212 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_same_source.751959525 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 524225038 ps |
| CPU time | 35.9 seconds |
| Started | Feb 07 04:11:52 PM PST 24 |
| Finished | Feb 07 04:12:28 PM PST 24 |
| Peak memory | 555664 kb |
| Host | smart-0936b42c-ea58-4282-b585-dfc85bcbdbe6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751959525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.751959525 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke.3855090864 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 44608128 ps |
| CPU time | 5.78 seconds |
| Started | Feb 07 04:11:57 PM PST 24 |
| Finished | Feb 07 04:12:03 PM PST 24 |
| Peak memory | 559140 kb |
| Host | smart-7444efa0-fb80-4f9c-89ce-fb2a0bbb519c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855090864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.3855090864 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.2827304033 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 9831042140 ps |
| CPU time | 96.28 seconds |
| Started | Feb 07 04:11:47 PM PST 24 |
| Finished | Feb 07 04:13:24 PM PST 24 |
| Peak memory | 553668 kb |
| Host | smart-eedaf252-77c5-4cea-8dba-b374bd78d072 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827304033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2827304033 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.2659067840 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 4678829667 ps |
| CPU time | 79.93 seconds |
| Started | Feb 07 04:11:44 PM PST 24 |
| Finished | Feb 07 04:13:04 PM PST 24 |
| Peak memory | 553344 kb |
| Host | smart-1778eb31-3ec3-4333-8724-6736f1be1411 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659067840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2659067840 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.3034244462 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 52680105 ps |
| CPU time | 5.95 seconds |
| Started | Feb 07 04:11:44 PM PST 24 |
| Finished | Feb 07 04:11:51 PM PST 24 |
| Peak memory | 553576 kb |
| Host | smart-73e987ef-17ce-4469-a92f-4ec33ee641c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034244462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays .3034244462 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all.3074197527 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 11372668546 ps |
| CPU time | 422.49 seconds |
| Started | Feb 07 04:12:01 PM PST 24 |
| Finished | Feb 07 04:19:04 PM PST 24 |
| Peak memory | 556880 kb |
| Host | smart-c92701c2-cacf-4f62-b6e8-2257005fb8fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074197527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.3074197527 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.3766368513 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 2758878332 ps |
| CPU time | 218.8 seconds |
| Started | Feb 07 04:11:46 PM PST 24 |
| Finished | Feb 07 04:15:25 PM PST 24 |
| Peak memory | 556660 kb |
| Host | smart-d9feeef7-2590-4b10-ac4d-c58313ef2620 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766368513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.3766368513 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.621155479 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 15498538 ps |
| CPU time | 30.42 seconds |
| Started | Feb 07 04:11:48 PM PST 24 |
| Finished | Feb 07 04:12:19 PM PST 24 |
| Peak memory | 555816 kb |
| Host | smart-72bd8f91-66a9-4558-82c4-8c235d09a003 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621155479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_w ith_rand_reset.621155479 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.3668441302 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 737036261 ps |
| CPU time | 40.29 seconds |
| Started | Feb 07 04:11:39 PM PST 24 |
| Finished | Feb 07 04:12:20 PM PST 24 |
| Peak memory | 559248 kb |
| Host | smart-c4060077-9842-4f69-a633-a7f463f6ccf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668441302 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all _with_reset_error.3668441302 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.3618965112 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 255179272 ps |
| CPU time | 27.94 seconds |
| Started | Feb 07 04:11:57 PM PST 24 |
| Finished | Feb 07 04:12:25 PM PST 24 |
| Peak memory | 555292 kb |
| Host | smart-23a502e8-c806-4bfd-b5de-7d3ef1c6e96b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618965112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.3618965112 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device.3208589910 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 743694262 ps |
| CPU time | 61.87 seconds |
| Started | Feb 07 04:16:22 PM PST 24 |
| Finished | Feb 07 04:17:27 PM PST 24 |
| Peak memory | 555352 kb |
| Host | smart-b0e1de91-c9bb-4e7e-8af9-d3f08702e9bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208589910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device .3208589910 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.1343497569 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 25345838509 ps |
| CPU time | 480.23 seconds |
| Started | Feb 07 04:16:20 PM PST 24 |
| Finished | Feb 07 04:24:25 PM PST 24 |
| Peak memory | 556784 kb |
| Host | smart-268df451-3a09-4536-977c-639036b750c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343497569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_ device_slow_rsp.1343497569 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.2387342893 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 348075486 ps |
| CPU time | 36.01 seconds |
| Started | Feb 07 04:16:27 PM PST 24 |
| Finished | Feb 07 04:17:05 PM PST 24 |
| Peak memory | 555648 kb |
| Host | smart-13db6a4b-af6d-4de3-9e4a-b609aed4a0ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387342893 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_add r.2387342893 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_random.2905465330 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 1356888698 ps |
| CPU time | 53.38 seconds |
| Started | Feb 07 04:16:18 PM PST 24 |
| Finished | Feb 07 04:17:13 PM PST 24 |
| Peak memory | 555304 kb |
| Host | smart-5395365c-277e-4429-b9e3-f245ae0685d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905465330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.2905465330 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random.2388428095 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 269974662 ps |
| CPU time | 24.24 seconds |
| Started | Feb 07 04:16:21 PM PST 24 |
| Finished | Feb 07 04:16:50 PM PST 24 |
| Peak memory | 555528 kb |
| Host | smart-fa371f72-53c7-49da-b849-0eeb4be30b9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388428095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.2388428095 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.3594177125 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 100568467697 ps |
| CPU time | 1134.64 seconds |
| Started | Feb 07 04:16:25 PM PST 24 |
| Finished | Feb 07 04:35:22 PM PST 24 |
| Peak memory | 555496 kb |
| Host | smart-0c9d7ab6-7157-486b-8966-297e5de979f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594177125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.3594177125 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.2184368181 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 65206557846 ps |
| CPU time | 1242.03 seconds |
| Started | Feb 07 04:16:18 PM PST 24 |
| Finished | Feb 07 04:37:01 PM PST 24 |
| Peak memory | 555728 kb |
| Host | smart-a12f5c26-b403-47de-b986-faefc4ca2b37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184368181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2184368181 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.1289164496 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 401862864 ps |
| CPU time | 39.38 seconds |
| Started | Feb 07 04:16:26 PM PST 24 |
| Finished | Feb 07 04:17:08 PM PST 24 |
| Peak memory | 555388 kb |
| Host | smart-ced77e9b-c4a0-4f3a-8a54-a37aa7001132 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289164496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_del ays.1289164496 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_same_source.1785633131 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 148157983 ps |
| CPU time | 7.22 seconds |
| Started | Feb 07 04:16:26 PM PST 24 |
| Finished | Feb 07 04:16:35 PM PST 24 |
| Peak memory | 553588 kb |
| Host | smart-fe280f09-4d01-40aa-89d5-c99ee6fbe959 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785633131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.1785633131 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke.343922236 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 226622827 ps |
| CPU time | 9.9 seconds |
| Started | Feb 07 04:16:22 PM PST 24 |
| Finished | Feb 07 04:16:35 PM PST 24 |
| Peak memory | 553620 kb |
| Host | smart-f207768c-4c3e-4311-a7ba-ce12488ef948 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343922236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.343922236 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.1215970859 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 9543430452 ps |
| CPU time | 100.76 seconds |
| Started | Feb 07 04:16:18 PM PST 24 |
| Finished | Feb 07 04:18:00 PM PST 24 |
| Peak memory | 553708 kb |
| Host | smart-88d795ae-123b-476a-b5e2-e72f8a1b41e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215970859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.1215970859 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.36045875 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 5574769852 ps |
| CPU time | 102.8 seconds |
| Started | Feb 07 04:16:15 PM PST 24 |
| Finished | Feb 07 04:18:00 PM PST 24 |
| Peak memory | 559196 kb |
| Host | smart-975f9d00-2c8b-4069-a480-8495338669f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36045875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.36045875 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.2041732813 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 46195551 ps |
| CPU time | 5.96 seconds |
| Started | Feb 07 04:16:22 PM PST 24 |
| Finished | Feb 07 04:16:31 PM PST 24 |
| Peak memory | 559144 kb |
| Host | smart-e13adf63-2c80-4ef7-98ba-b50698ca226c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041732813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delay s.2041732813 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all.4097041700 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 20407803985 ps |
| CPU time | 820.83 seconds |
| Started | Feb 07 04:16:22 PM PST 24 |
| Finished | Feb 07 04:30:06 PM PST 24 |
| Peak memory | 559400 kb |
| Host | smart-23a38a4b-f42e-4cfb-88a8-254cf8c7e989 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097041700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.4097041700 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.3997824006 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 144117429 ps |
| CPU time | 15.07 seconds |
| Started | Feb 07 04:16:18 PM PST 24 |
| Finished | Feb 07 04:16:34 PM PST 24 |
| Peak memory | 555656 kb |
| Host | smart-4c2fb3bd-78d8-4a52-8a31-5639edc48159 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997824006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.3997824006 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.535214024 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 3926507174 ps |
| CPU time | 212.95 seconds |
| Started | Feb 07 04:16:20 PM PST 24 |
| Finished | Feb 07 04:19:58 PM PST 24 |
| Peak memory | 556432 kb |
| Host | smart-fe33718a-245b-4e0f-9ff7-d1b9c168ebe6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535214024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_ with_rand_reset.535214024 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.2467104440 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 491712849 ps |
| CPU time | 141.32 seconds |
| Started | Feb 07 04:16:18 PM PST 24 |
| Finished | Feb 07 04:18:40 PM PST 24 |
| Peak memory | 558904 kb |
| Host | smart-78bbbce7-22db-413b-ac3a-b451bed235b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467104440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_al l_with_reset_error.2467104440 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.3411617882 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 911944233 ps |
| CPU time | 38.34 seconds |
| Started | Feb 07 04:16:19 PM PST 24 |
| Finished | Feb 07 04:16:58 PM PST 24 |
| Peak memory | 555320 kb |
| Host | smart-e3f28dfd-d448-4879-bbf2-3159ed26a770 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411617882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3411617882 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device.709927706 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 1037474020 ps |
| CPU time | 48.09 seconds |
| Started | Feb 07 04:16:30 PM PST 24 |
| Finished | Feb 07 04:17:18 PM PST 24 |
| Peak memory | 555424 kb |
| Host | smart-7cef8490-29f0-418f-94b7-69d1cd90e190 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709927706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device. 709927706 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.1845100035 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 128872416607 ps |
| CPU time | 2430.06 seconds |
| Started | Feb 07 04:16:28 PM PST 24 |
| Finished | Feb 07 04:56:59 PM PST 24 |
| Peak memory | 556588 kb |
| Host | smart-5ca3d378-8f2d-4be5-a1cb-d43f31be5a2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845100035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_ device_slow_rsp.1845100035 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.2765003729 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 126224489 ps |
| CPU time | 14.33 seconds |
| Started | Feb 07 04:16:35 PM PST 24 |
| Finished | Feb 07 04:16:50 PM PST 24 |
| Peak memory | 555648 kb |
| Host | smart-a5606f53-c73f-4b50-b3ce-e012249818e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765003729 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_add r.2765003729 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_random.832481187 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 2485774680 ps |
| CPU time | 94.74 seconds |
| Started | Feb 07 04:16:28 PM PST 24 |
| Finished | Feb 07 04:18:04 PM PST 24 |
| Peak memory | 555384 kb |
| Host | smart-5e377f0e-cce3-43ad-b09f-a14fb5be730f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832481187 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.832481187 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random.1873994634 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 111487751 ps |
| CPU time | 6.83 seconds |
| Started | Feb 07 04:16:21 PM PST 24 |
| Finished | Feb 07 04:16:32 PM PST 24 |
| Peak memory | 553556 kb |
| Host | smart-545acd53-8bca-4b9d-9e5d-b862dcbedfb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873994634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.1873994634 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.1042551079 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 51624839349 ps |
| CPU time | 631.35 seconds |
| Started | Feb 07 04:16:28 PM PST 24 |
| Finished | Feb 07 04:27:00 PM PST 24 |
| Peak memory | 555732 kb |
| Host | smart-3a67eac9-12c7-4a98-be79-f6cfe4301c1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042551079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.1042551079 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.4181645075 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 50669517233 ps |
| CPU time | 918.73 seconds |
| Started | Feb 07 04:16:28 PM PST 24 |
| Finished | Feb 07 04:31:48 PM PST 24 |
| Peak memory | 555464 kb |
| Host | smart-101b2865-89e3-4595-b05c-2af3a1731185 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181645075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.4181645075 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.2060375679 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 542908201 ps |
| CPU time | 45.83 seconds |
| Started | Feb 07 04:16:26 PM PST 24 |
| Finished | Feb 07 04:17:14 PM PST 24 |
| Peak memory | 555392 kb |
| Host | smart-b9faab67-8b44-4ec2-9290-c19f72d5db34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060375679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_del ays.2060375679 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_same_source.3709080047 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 361909947 ps |
| CPU time | 30.71 seconds |
| Started | Feb 07 04:16:26 PM PST 24 |
| Finished | Feb 07 04:16:59 PM PST 24 |
| Peak memory | 555632 kb |
| Host | smart-e45edcd4-59df-460b-be25-68ffc9d3d6d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709080047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.3709080047 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke.1452557593 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 48342725 ps |
| CPU time | 5.95 seconds |
| Started | Feb 07 04:16:27 PM PST 24 |
| Finished | Feb 07 04:16:35 PM PST 24 |
| Peak memory | 553612 kb |
| Host | smart-973f8fb6-2d9c-4ba0-a5ab-6637518af83f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452557593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1452557593 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.498534453 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 5300036435 ps |
| CPU time | 56.17 seconds |
| Started | Feb 07 04:16:19 PM PST 24 |
| Finished | Feb 07 04:17:15 PM PST 24 |
| Peak memory | 553352 kb |
| Host | smart-0c000d0a-0b25-4a6a-9d87-2b32f6e7871f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498534453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.498534453 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.2995836136 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 5602369311 ps |
| CPU time | 98.52 seconds |
| Started | Feb 07 04:16:20 PM PST 24 |
| Finished | Feb 07 04:18:03 PM PST 24 |
| Peak memory | 553712 kb |
| Host | smart-5d70cc04-0980-425a-9b3c-00a6b1ed1e38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995836136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2995836136 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.4181183889 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 45227819 ps |
| CPU time | 5.96 seconds |
| Started | Feb 07 04:16:24 PM PST 24 |
| Finished | Feb 07 04:16:31 PM PST 24 |
| Peak memory | 553044 kb |
| Host | smart-bcf89df2-5988-420d-8ed4-ef0d06eac60e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181183889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delay s.4181183889 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all.3580884182 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 15845272502 ps |
| CPU time | 553.54 seconds |
| Started | Feb 07 04:16:25 PM PST 24 |
| Finished | Feb 07 04:25:42 PM PST 24 |
| Peak memory | 559348 kb |
| Host | smart-ea282dfe-977f-4653-b8bc-06bb3e12318c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580884182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.3580884182 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.3574674615 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 1664556716 ps |
| CPU time | 73.53 seconds |
| Started | Feb 07 04:16:26 PM PST 24 |
| Finished | Feb 07 04:17:42 PM PST 24 |
| Peak memory | 556400 kb |
| Host | smart-dd5f1070-b3e3-444c-8d7b-5a139b17b33b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574674615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3574674615 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.1781960850 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 1776807710 ps |
| CPU time | 489.84 seconds |
| Started | Feb 07 04:16:27 PM PST 24 |
| Finished | Feb 07 04:24:38 PM PST 24 |
| Peak memory | 558088 kb |
| Host | smart-38594112-8129-4a1d-b52e-10ab5ddf8617 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781960850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_rand_reset.1781960850 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.868552351 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 6786445505 ps |
| CPU time | 392.17 seconds |
| Started | Feb 07 04:16:27 PM PST 24 |
| Finished | Feb 07 04:23:01 PM PST 24 |
| Peak memory | 559468 kb |
| Host | smart-737b097f-8c0e-4dac-95a1-b3f0469a4845 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868552351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_reset_error.868552351 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.4199274797 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 44068068 ps |
| CPU time | 7.08 seconds |
| Started | Feb 07 04:16:36 PM PST 24 |
| Finished | Feb 07 04:16:43 PM PST 24 |
| Peak memory | 553388 kb |
| Host | smart-c58fadf8-d96b-4da1-80f5-b48b7e86cc9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199274797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.4199274797 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device.972133287 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 814713184 ps |
| CPU time | 66.79 seconds |
| Started | Feb 07 04:16:39 PM PST 24 |
| Finished | Feb 07 04:17:47 PM PST 24 |
| Peak memory | 555668 kb |
| Host | smart-187c810c-ba17-4c00-8153-d7f1fd418830 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972133287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device. 972133287 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.3002301867 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 46927135708 ps |
| CPU time | 834.9 seconds |
| Started | Feb 07 04:16:39 PM PST 24 |
| Finished | Feb 07 04:30:35 PM PST 24 |
| Peak memory | 555736 kb |
| Host | smart-09d9dd6f-f8d0-4cdb-967e-1953480369bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002301867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_ device_slow_rsp.3002301867 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.4212885927 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 1121757516 ps |
| CPU time | 44.75 seconds |
| Started | Feb 07 04:16:42 PM PST 24 |
| Finished | Feb 07 04:17:27 PM PST 24 |
| Peak memory | 555628 kb |
| Host | smart-cb4e1ff0-835a-4a69-a0fc-b63522c10770 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212885927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_add r.4212885927 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_random.1066626551 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 1463763493 ps |
| CPU time | 52.21 seconds |
| Started | Feb 07 04:16:36 PM PST 24 |
| Finished | Feb 07 04:17:29 PM PST 24 |
| Peak memory | 559120 kb |
| Host | smart-dcdb57f7-50c4-4bb2-bec5-dd18e2733047 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066626551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.1066626551 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random.777288551 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 805853293 ps |
| CPU time | 28.96 seconds |
| Started | Feb 07 04:16:28 PM PST 24 |
| Finished | Feb 07 04:16:58 PM PST 24 |
| Peak memory | 555352 kb |
| Host | smart-a8eb6aa1-0460-4e5b-9dec-766e79bdebc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777288551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.777288551 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.2582257397 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 112036898858 ps |
| CPU time | 1206.43 seconds |
| Started | Feb 07 04:16:37 PM PST 24 |
| Finished | Feb 07 04:36:45 PM PST 24 |
| Peak memory | 555728 kb |
| Host | smart-a521e927-da7a-419b-aa8e-cc1c91ec8933 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582257397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.2582257397 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.2762046654 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 8082523233 ps |
| CPU time | 142.86 seconds |
| Started | Feb 07 04:16:38 PM PST 24 |
| Finished | Feb 07 04:19:02 PM PST 24 |
| Peak memory | 555760 kb |
| Host | smart-12ec8b05-603e-4908-8a60-e5b652d9e096 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762046654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2762046654 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.1595886407 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 200961449 ps |
| CPU time | 20.23 seconds |
| Started | Feb 07 04:16:27 PM PST 24 |
| Finished | Feb 07 04:16:49 PM PST 24 |
| Peak memory | 555624 kb |
| Host | smart-0dd8dab1-76c6-449d-bf51-6c8dd45bb3c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595886407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_del ays.1595886407 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_same_source.1752776628 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 1212649852 ps |
| CPU time | 41.45 seconds |
| Started | Feb 07 04:16:39 PM PST 24 |
| Finished | Feb 07 04:17:21 PM PST 24 |
| Peak memory | 555676 kb |
| Host | smart-fa90d5ee-21d2-46fc-8035-14b37e187b39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752776628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.1752776628 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke.3810086910 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 232901251 ps |
| CPU time | 8.98 seconds |
| Started | Feb 07 04:16:27 PM PST 24 |
| Finished | Feb 07 04:16:38 PM PST 24 |
| Peak memory | 553556 kb |
| Host | smart-9874f387-7489-4c85-9ef3-70e7482346c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810086910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.3810086910 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.354824420 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 7356843838 ps |
| CPU time | 82.28 seconds |
| Started | Feb 07 04:16:29 PM PST 24 |
| Finished | Feb 07 04:17:52 PM PST 24 |
| Peak memory | 553628 kb |
| Host | smart-2cae3441-1322-4b39-9726-bc52ab17c705 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354824420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.354824420 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.3051650760 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 5068048449 ps |
| CPU time | 92.35 seconds |
| Started | Feb 07 04:16:27 PM PST 24 |
| Finished | Feb 07 04:18:01 PM PST 24 |
| Peak memory | 559112 kb |
| Host | smart-cadbfef4-7e8c-4dc3-9476-7822d4964904 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051650760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3051650760 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.3019382073 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 44180379 ps |
| CPU time | 6.64 seconds |
| Started | Feb 07 04:16:24 PM PST 24 |
| Finished | Feb 07 04:16:33 PM PST 24 |
| Peak memory | 553592 kb |
| Host | smart-7572553a-71b9-4787-94ba-fe604e888492 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019382073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delay s.3019382073 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.880543106 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 3196428636 ps |
| CPU time | 96.52 seconds |
| Started | Feb 07 04:16:36 PM PST 24 |
| Finished | Feb 07 04:18:13 PM PST 24 |
| Peak memory | 556780 kb |
| Host | smart-3b429b43-9870-4c78-89e9-218df318e00a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880543106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.880543106 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.1303658526 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 737313203 ps |
| CPU time | 466.21 seconds |
| Started | Feb 07 04:16:38 PM PST 24 |
| Finished | Feb 07 04:24:25 PM PST 24 |
| Peak memory | 559176 kb |
| Host | smart-9ea5c1f9-b878-4301-87c1-35d6943f49f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303658526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_rand_reset.1303658526 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.3631984550 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 478998713 ps |
| CPU time | 25.58 seconds |
| Started | Feb 07 04:16:36 PM PST 24 |
| Finished | Feb 07 04:17:03 PM PST 24 |
| Peak memory | 555372 kb |
| Host | smart-e7cc05a5-39de-4e3a-8d89-c663fb0b1ea4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631984550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3631984550 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device.770352410 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 927211302 ps |
| CPU time | 39.81 seconds |
| Started | Feb 07 04:16:45 PM PST 24 |
| Finished | Feb 07 04:17:26 PM PST 24 |
| Peak memory | 555400 kb |
| Host | smart-51637832-84c8-44f8-b390-2cb6d507111f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770352410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device. 770352410 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.3809276688 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 126682744634 ps |
| CPU time | 2129.61 seconds |
| Started | Feb 07 04:16:48 PM PST 24 |
| Finished | Feb 07 04:52:18 PM PST 24 |
| Peak memory | 555824 kb |
| Host | smart-a1e527a1-d0bd-4f1c-8e01-0786a5a136a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809276688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_ device_slow_rsp.3809276688 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.2186227549 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 1389746618 ps |
| CPU time | 56.46 seconds |
| Started | Feb 07 04:16:47 PM PST 24 |
| Finished | Feb 07 04:17:44 PM PST 24 |
| Peak memory | 555400 kb |
| Host | smart-a8c965ef-98ca-44e2-99bf-7ee43b69ffeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186227549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_add r.2186227549 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_random.33932497 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 617770686 ps |
| CPU time | 51.77 seconds |
| Started | Feb 07 04:16:45 PM PST 24 |
| Finished | Feb 07 04:17:37 PM PST 24 |
| Peak memory | 555580 kb |
| Host | smart-2de3c18f-7581-4a68-9503-53f9d7001d45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33932497 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.33932497 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random.2997044373 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 448197845 ps |
| CPU time | 44.56 seconds |
| Started | Feb 07 04:16:45 PM PST 24 |
| Finished | Feb 07 04:17:30 PM PST 24 |
| Peak memory | 555644 kb |
| Host | smart-c34b56ce-3f3e-4be8-a352-9665d590bcf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997044373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.2997044373 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.579292187 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 28955791115 ps |
| CPU time | 317.66 seconds |
| Started | Feb 07 04:16:46 PM PST 24 |
| Finished | Feb 07 04:22:04 PM PST 24 |
| Peak memory | 555208 kb |
| Host | smart-f69e158e-b997-4595-b743-937c080988f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579292187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.579292187 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.3205786777 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 9974897555 ps |
| CPU time | 165.37 seconds |
| Started | Feb 07 04:16:45 PM PST 24 |
| Finished | Feb 07 04:19:31 PM PST 24 |
| Peak memory | 555676 kb |
| Host | smart-81957447-edb6-4c1f-ae80-96d2e9c761a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205786777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.3205786777 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.1114150737 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 214912334 ps |
| CPU time | 20.51 seconds |
| Started | Feb 07 04:16:45 PM PST 24 |
| Finished | Feb 07 04:17:07 PM PST 24 |
| Peak memory | 555404 kb |
| Host | smart-a909a783-dcdc-40f7-9c1a-9bbd7eb64b66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114150737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_del ays.1114150737 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_same_source.1208862877 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 831049039 ps |
| CPU time | 26.46 seconds |
| Started | Feb 07 04:16:47 PM PST 24 |
| Finished | Feb 07 04:17:14 PM PST 24 |
| Peak memory | 555352 kb |
| Host | smart-c7c560c1-b254-41cb-91bb-4f762f992f58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208862877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.1208862877 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke.1523949602 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 165284160 ps |
| CPU time | 8.48 seconds |
| Started | Feb 07 04:16:36 PM PST 24 |
| Finished | Feb 07 04:16:45 PM PST 24 |
| Peak memory | 553536 kb |
| Host | smart-94a06128-2f70-42d0-967a-4147bd0dfb07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523949602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1523949602 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.2474883428 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 9073101679 ps |
| CPU time | 94.44 seconds |
| Started | Feb 07 04:16:37 PM PST 24 |
| Finished | Feb 07 04:18:12 PM PST 24 |
| Peak memory | 553700 kb |
| Host | smart-e0bec816-95fb-497b-9818-b884aa405136 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474883428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2474883428 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.2196630736 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 6031080649 ps |
| CPU time | 102.59 seconds |
| Started | Feb 07 04:16:44 PM PST 24 |
| Finished | Feb 07 04:18:28 PM PST 24 |
| Peak memory | 553684 kb |
| Host | smart-01ae441e-68c2-4dd4-b9be-314c65593ba1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196630736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2196630736 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.2899415981 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 34747314 ps |
| CPU time | 5.88 seconds |
| Started | Feb 07 04:16:40 PM PST 24 |
| Finished | Feb 07 04:16:47 PM PST 24 |
| Peak memory | 553564 kb |
| Host | smart-c404eb65-9d5f-415f-9378-ac856c48dd6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899415981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delay s.2899415981 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all.2137133506 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 18660502003 ps |
| CPU time | 769.15 seconds |
| Started | Feb 07 04:16:50 PM PST 24 |
| Finished | Feb 07 04:29:40 PM PST 24 |
| Peak memory | 556892 kb |
| Host | smart-47b9be00-5b34-458c-82f2-a59beb1c38eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137133506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2137133506 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.4110604314 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 2199408521 ps |
| CPU time | 131.66 seconds |
| Started | Feb 07 04:16:45 PM PST 24 |
| Finished | Feb 07 04:18:58 PM PST 24 |
| Peak memory | 556924 kb |
| Host | smart-166b1f25-591b-4071-9335-e961178cbc84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110604314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_rand_reset.4110604314 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.560365087 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 2898092744 ps |
| CPU time | 395.49 seconds |
| Started | Feb 07 04:16:50 PM PST 24 |
| Finished | Feb 07 04:23:26 PM PST 24 |
| Peak memory | 567648 kb |
| Host | smart-2f635216-2593-4a18-84b8-4bf42b9d3cfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560365087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_reset_error.560365087 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.655713930 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 123561645 ps |
| CPU time | 8.53 seconds |
| Started | Feb 07 04:16:49 PM PST 24 |
| Finished | Feb 07 04:16:58 PM PST 24 |
| Peak memory | 553332 kb |
| Host | smart-8ee05e3a-b234-483d-b5a5-452ecccaead0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655713930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.655713930 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device.3707756959 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 963281922 ps |
| CPU time | 86.46 seconds |
| Started | Feb 07 04:16:48 PM PST 24 |
| Finished | Feb 07 04:18:15 PM PST 24 |
| Peak memory | 555336 kb |
| Host | smart-61b4d892-28ab-4ece-bbc4-4ff336942a22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707756959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device .3707756959 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.3672739513 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 35029214588 ps |
| CPU time | 584.43 seconds |
| Started | Feb 07 04:16:50 PM PST 24 |
| Finished | Feb 07 04:26:35 PM PST 24 |
| Peak memory | 555740 kb |
| Host | smart-daf4c00a-4449-4be0-844b-5f95f796126b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672739513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_ device_slow_rsp.3672739513 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.765271767 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 691728847 ps |
| CPU time | 29.21 seconds |
| Started | Feb 07 04:16:56 PM PST 24 |
| Finished | Feb 07 04:17:25 PM PST 24 |
| Peak memory | 555316 kb |
| Host | smart-33eec3e6-5426-4b32-b55e-e210cb4987ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765271767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr .765271767 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_random.1935666567 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 1959513062 ps |
| CPU time | 63.38 seconds |
| Started | Feb 07 04:16:49 PM PST 24 |
| Finished | Feb 07 04:17:52 PM PST 24 |
| Peak memory | 555324 kb |
| Host | smart-b59b1f82-4f6c-4a33-8780-7a8ee45e96d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935666567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.1935666567 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random.1335821860 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 633609369 ps |
| CPU time | 55.55 seconds |
| Started | Feb 07 04:16:51 PM PST 24 |
| Finished | Feb 07 04:17:47 PM PST 24 |
| Peak memory | 555284 kb |
| Host | smart-96f4399f-0d0b-4e6d-a099-d15bb9dd52f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335821860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.1335821860 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.2938567710 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 93120778830 ps |
| CPU time | 1175.73 seconds |
| Started | Feb 07 04:16:55 PM PST 24 |
| Finished | Feb 07 04:36:32 PM PST 24 |
| Peak memory | 559232 kb |
| Host | smart-00335c4f-3d13-48b9-9e9b-5fbc4cba78dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938567710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2938567710 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.1564220272 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 36763974840 ps |
| CPU time | 664.96 seconds |
| Started | Feb 07 04:17:07 PM PST 24 |
| Finished | Feb 07 04:28:12 PM PST 24 |
| Peak memory | 555380 kb |
| Host | smart-f3faae5a-dad4-45f4-baa2-ad16f5827cab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564220272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.1564220272 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.3811430526 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 271695415 ps |
| CPU time | 24.44 seconds |
| Started | Feb 07 04:16:53 PM PST 24 |
| Finished | Feb 07 04:17:18 PM PST 24 |
| Peak memory | 555380 kb |
| Host | smart-051c80ff-5ae2-44dd-a2df-40c58a6a5437 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811430526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_del ays.3811430526 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_same_source.425835818 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 535989305 ps |
| CPU time | 37.44 seconds |
| Started | Feb 07 04:16:53 PM PST 24 |
| Finished | Feb 07 04:17:31 PM PST 24 |
| Peak memory | 555624 kb |
| Host | smart-051c1c0d-2ecc-4bcf-8317-2843ac14749f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425835818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.425835818 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke.3457462969 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 32252007 ps |
| CPU time | 5.7 seconds |
| Started | Feb 07 04:16:49 PM PST 24 |
| Finished | Feb 07 04:16:55 PM PST 24 |
| Peak memory | 552832 kb |
| Host | smart-eb07677c-a50f-4eea-8f48-2fbc7c9f84cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457462969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.3457462969 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.77887392 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 7397927269 ps |
| CPU time | 78.73 seconds |
| Started | Feb 07 04:16:53 PM PST 24 |
| Finished | Feb 07 04:18:13 PM PST 24 |
| Peak memory | 553368 kb |
| Host | smart-e1db9ca9-7e93-438f-82b6-5b98cdde455a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77887392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.77887392 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.2344897508 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 4866647229 ps |
| CPU time | 84.17 seconds |
| Started | Feb 07 04:16:53 PM PST 24 |
| Finished | Feb 07 04:18:18 PM PST 24 |
| Peak memory | 553016 kb |
| Host | smart-31ace378-be4c-4993-8fbf-e3678f74ecd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344897508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2344897508 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.1373100843 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 49704437 ps |
| CPU time | 6.79 seconds |
| Started | Feb 07 04:16:44 PM PST 24 |
| Finished | Feb 07 04:16:52 PM PST 24 |
| Peak memory | 553264 kb |
| Host | smart-540b219b-91f7-4f04-9936-7ace8063637a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373100843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delay s.1373100843 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all.3704327934 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 2315243020 ps |
| CPU time | 213.27 seconds |
| Started | Feb 07 04:16:56 PM PST 24 |
| Finished | Feb 07 04:20:30 PM PST 24 |
| Peak memory | 556836 kb |
| Host | smart-a588ba2d-38ae-4593-9a99-b8cd6eb6e82b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704327934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.3704327934 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.2087036141 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 2520679049 ps |
| CPU time | 91.68 seconds |
| Started | Feb 07 04:17:07 PM PST 24 |
| Finished | Feb 07 04:18:39 PM PST 24 |
| Peak memory | 556444 kb |
| Host | smart-b398ff9d-b4e8-482b-b11c-b47eca4eff5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087036141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2087036141 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.3178959771 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 371928560 ps |
| CPU time | 137.77 seconds |
| Started | Feb 07 04:16:50 PM PST 24 |
| Finished | Feb 07 04:19:08 PM PST 24 |
| Peak memory | 557552 kb |
| Host | smart-d81ff178-8166-431c-bb24-7cfda797f513 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178959771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all _with_rand_reset.3178959771 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.538923863 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 4604097678 ps |
| CPU time | 247.59 seconds |
| Started | Feb 07 04:16:53 PM PST 24 |
| Finished | Feb 07 04:21:01 PM PST 24 |
| Peak memory | 558936 kb |
| Host | smart-a8bee980-6562-483b-830a-a153e7a01519 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538923863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all _with_reset_error.538923863 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.3935036424 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 941640253 ps |
| CPU time | 42.07 seconds |
| Started | Feb 07 04:16:53 PM PST 24 |
| Finished | Feb 07 04:17:36 PM PST 24 |
| Peak memory | 555364 kb |
| Host | smart-5c3b1aa7-c7aa-499d-ab17-d9262ae3eba9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935036424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.3935036424 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.3483091380 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 536564446 ps |
| CPU time | 38.54 seconds |
| Started | Feb 07 04:16:57 PM PST 24 |
| Finished | Feb 07 04:17:36 PM PST 24 |
| Peak memory | 555384 kb |
| Host | smart-f6906a17-b3db-4396-897f-9d5b1dc8a803 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483091380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device .3483091380 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.3596069911 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 116117064821 ps |
| CPU time | 2356.29 seconds |
| Started | Feb 07 04:16:56 PM PST 24 |
| Finished | Feb 07 04:56:13 PM PST 24 |
| Peak memory | 556608 kb |
| Host | smart-dd2fc095-8a97-40f7-8ece-2e6f4b0827e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596069911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_ device_slow_rsp.3596069911 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.3929799158 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 314208490 ps |
| CPU time | 35.23 seconds |
| Started | Feb 07 04:16:57 PM PST 24 |
| Finished | Feb 07 04:17:33 PM PST 24 |
| Peak memory | 555628 kb |
| Host | smart-8b709452-ce4b-430c-b3bf-482c76db9eeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929799158 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_add r.3929799158 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_random.401428742 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 327108409 ps |
| CPU time | 14.44 seconds |
| Started | Feb 07 04:16:56 PM PST 24 |
| Finished | Feb 07 04:17:11 PM PST 24 |
| Peak memory | 555340 kb |
| Host | smart-d9588ae7-f435-4582-a72b-ab81a1d99dba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401428742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.401428742 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random.1834047222 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 181513807 ps |
| CPU time | 16.76 seconds |
| Started | Feb 07 04:16:58 PM PST 24 |
| Finished | Feb 07 04:17:15 PM PST 24 |
| Peak memory | 555340 kb |
| Host | smart-1c8994ed-3234-4dcd-a076-0b14597aad4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834047222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.1834047222 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.3358272180 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 32009957087 ps |
| CPU time | 337.6 seconds |
| Started | Feb 07 04:16:59 PM PST 24 |
| Finished | Feb 07 04:22:37 PM PST 24 |
| Peak memory | 555292 kb |
| Host | smart-af5a66d0-d794-4c60-9b30-bd675e2e10b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358272180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.3358272180 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.1488497290 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 6928340711 ps |
| CPU time | 115.2 seconds |
| Started | Feb 07 04:16:57 PM PST 24 |
| Finished | Feb 07 04:18:53 PM PST 24 |
| Peak memory | 555720 kb |
| Host | smart-1c53e1ac-80d0-4a21-b7a6-30369e8b495c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488497290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.1488497290 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.3742396522 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 132094297 ps |
| CPU time | 15.41 seconds |
| Started | Feb 07 04:16:56 PM PST 24 |
| Finished | Feb 07 04:17:12 PM PST 24 |
| Peak memory | 555660 kb |
| Host | smart-ec51a1fd-4278-4600-986c-8e832739c480 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742396522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_del ays.3742396522 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_same_source.1460801697 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 481154389 ps |
| CPU time | 15.34 seconds |
| Started | Feb 07 04:17:16 PM PST 24 |
| Finished | Feb 07 04:17:31 PM PST 24 |
| Peak memory | 555572 kb |
| Host | smart-2c575b59-a18a-47fe-bd50-70c1b46bc17b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460801697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1460801697 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke.2863041705 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 52991838 ps |
| CPU time | 6.27 seconds |
| Started | Feb 07 04:16:50 PM PST 24 |
| Finished | Feb 07 04:16:56 PM PST 24 |
| Peak memory | 553580 kb |
| Host | smart-0110f48b-ea9b-4844-9911-71ec8b84fb8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863041705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.2863041705 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.267229829 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 6830397931 ps |
| CPU time | 68.62 seconds |
| Started | Feb 07 04:17:15 PM PST 24 |
| Finished | Feb 07 04:18:24 PM PST 24 |
| Peak memory | 553328 kb |
| Host | smart-f492266e-fb51-4375-8d9a-e7e9e5f47a0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267229829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.267229829 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.123109564 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 3952605899 ps |
| CPU time | 64.39 seconds |
| Started | Feb 07 04:17:15 PM PST 24 |
| Finished | Feb 07 04:18:20 PM PST 24 |
| Peak memory | 553592 kb |
| Host | smart-34a6a079-67e1-4484-85ac-528fff8baf18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123109564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.123109564 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.2781759338 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 43103027 ps |
| CPU time | 6.23 seconds |
| Started | Feb 07 04:16:50 PM PST 24 |
| Finished | Feb 07 04:16:57 PM PST 24 |
| Peak memory | 553228 kb |
| Host | smart-5ac51ad3-1b23-45da-b486-1825b100d0a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781759338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delay s.2781759338 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all.3397863152 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 1456151837 ps |
| CPU time | 152.53 seconds |
| Started | Feb 07 04:16:58 PM PST 24 |
| Finished | Feb 07 04:19:31 PM PST 24 |
| Peak memory | 559316 kb |
| Host | smart-b45b1312-2a47-4b30-a0d0-eace37222e83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397863152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3397863152 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.1098882030 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 14138308665 ps |
| CPU time | 556.04 seconds |
| Started | Feb 07 04:16:58 PM PST 24 |
| Finished | Feb 07 04:26:14 PM PST 24 |
| Peak memory | 556828 kb |
| Host | smart-dd666a00-4aac-475a-aee9-fe114372d258 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098882030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.1098882030 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.3436818965 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 500826457 ps |
| CPU time | 184.62 seconds |
| Started | Feb 07 04:17:15 PM PST 24 |
| Finished | Feb 07 04:20:20 PM PST 24 |
| Peak memory | 557632 kb |
| Host | smart-f645206a-39d5-4c27-94bc-c40e2aa9fce3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436818965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all _with_rand_reset.3436818965 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.1619283066 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 1278346595 ps |
| CPU time | 91.48 seconds |
| Started | Feb 07 04:16:57 PM PST 24 |
| Finished | Feb 07 04:18:29 PM PST 24 |
| Peak memory | 556856 kb |
| Host | smart-560385c5-205e-4ff0-b365-b7d79b3957e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619283066 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_al l_with_reset_error.1619283066 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.1087835203 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 23546297 ps |
| CPU time | 5.19 seconds |
| Started | Feb 07 04:17:16 PM PST 24 |
| Finished | Feb 07 04:17:21 PM PST 24 |
| Peak memory | 553520 kb |
| Host | smart-843a1556-0a17-4a55-9165-66a7bdf0b6df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087835203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.1087835203 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device.864619780 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 1580574807 ps |
| CPU time | 67.49 seconds |
| Started | Feb 07 04:17:14 PM PST 24 |
| Finished | Feb 07 04:18:22 PM PST 24 |
| Peak memory | 555612 kb |
| Host | smart-7180cba6-da70-4bae-8412-c56c8f418c22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864619780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device. 864619780 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.2698329268 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 86631079192 ps |
| CPU time | 1700.31 seconds |
| Started | Feb 07 04:17:13 PM PST 24 |
| Finished | Feb 07 04:45:34 PM PST 24 |
| Peak memory | 556316 kb |
| Host | smart-3212f040-1768-43a5-ae1d-49dd77e190e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698329268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_ device_slow_rsp.2698329268 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.61343796 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 49767395 ps |
| CPU time | 7.8 seconds |
| Started | Feb 07 04:17:13 PM PST 24 |
| Finished | Feb 07 04:17:21 PM PST 24 |
| Peak memory | 553280 kb |
| Host | smart-b8eabf08-569a-465a-832a-4297816e9515 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61343796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.61343796 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_random.3639027343 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 1059789339 ps |
| CPU time | 38.64 seconds |
| Started | Feb 07 04:17:15 PM PST 24 |
| Finished | Feb 07 04:17:54 PM PST 24 |
| Peak memory | 555048 kb |
| Host | smart-47088308-96f4-45ff-9205-4f6e9cb7cfdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639027343 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.3639027343 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random.2487900833 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 642863146 ps |
| CPU time | 24.89 seconds |
| Started | Feb 07 04:17:08 PM PST 24 |
| Finished | Feb 07 04:17:33 PM PST 24 |
| Peak memory | 555396 kb |
| Host | smart-d2e2f472-ffe8-4c89-b323-34161fce49ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487900833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.2487900833 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.294362636 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 93153516233 ps |
| CPU time | 1002.83 seconds |
| Started | Feb 07 04:17:14 PM PST 24 |
| Finished | Feb 07 04:33:57 PM PST 24 |
| Peak memory | 555692 kb |
| Host | smart-cd2e9e4f-205c-487b-971e-922b7281ab15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294362636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.294362636 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.2248426767 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 54751144135 ps |
| CPU time | 1052.28 seconds |
| Started | Feb 07 04:17:18 PM PST 24 |
| Finished | Feb 07 04:34:51 PM PST 24 |
| Peak memory | 555728 kb |
| Host | smart-42d6c954-160a-43ad-9bf9-84152b4a161e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248426767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2248426767 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.3777979332 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 34814056 ps |
| CPU time | 6.17 seconds |
| Started | Feb 07 04:17:14 PM PST 24 |
| Finished | Feb 07 04:17:20 PM PST 24 |
| Peak memory | 553340 kb |
| Host | smart-1cd791ea-ee89-4f90-8141-b8a3db3c1321 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777979332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_del ays.3777979332 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_same_source.617632940 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 2729827644 ps |
| CPU time | 89.6 seconds |
| Started | Feb 07 04:17:15 PM PST 24 |
| Finished | Feb 07 04:18:45 PM PST 24 |
| Peak memory | 555728 kb |
| Host | smart-685d0257-53e1-4b1f-bedf-19788912188e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617632940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.617632940 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke.481906561 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 169273065 ps |
| CPU time | 8.7 seconds |
| Started | Feb 07 04:17:10 PM PST 24 |
| Finished | Feb 07 04:17:19 PM PST 24 |
| Peak memory | 553276 kb |
| Host | smart-addf98c7-9556-497f-9408-49f19e189b08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481906561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.481906561 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.1273406064 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 9161768866 ps |
| CPU time | 97.14 seconds |
| Started | Feb 07 04:17:08 PM PST 24 |
| Finished | Feb 07 04:18:46 PM PST 24 |
| Peak memory | 553340 kb |
| Host | smart-de3dadec-0d2f-40d5-843d-513ad99274bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273406064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1273406064 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.2707620855 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 3824051308 ps |
| CPU time | 68.95 seconds |
| Started | Feb 07 04:17:14 PM PST 24 |
| Finished | Feb 07 04:18:23 PM PST 24 |
| Peak memory | 553644 kb |
| Host | smart-e60bab52-fb79-4fbe-887a-764611cf28af |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707620855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.2707620855 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.2773150771 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 37051798 ps |
| CPU time | 5.59 seconds |
| Started | Feb 07 04:17:12 PM PST 24 |
| Finished | Feb 07 04:17:18 PM PST 24 |
| Peak memory | 553264 kb |
| Host | smart-91b71eca-fb3f-4d19-8395-d851f6c4ea94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773150771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delay s.2773150771 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all.2720540061 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 5199333188 ps |
| CPU time | 182.65 seconds |
| Started | Feb 07 04:17:13 PM PST 24 |
| Finished | Feb 07 04:20:16 PM PST 24 |
| Peak memory | 556604 kb |
| Host | smart-2f7e512c-a636-4c7b-99c4-2a711e04ae55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720540061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2720540061 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.618326689 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 2425363314 ps |
| CPU time | 196.29 seconds |
| Started | Feb 07 04:17:16 PM PST 24 |
| Finished | Feb 07 04:20:33 PM PST 24 |
| Peak memory | 556904 kb |
| Host | smart-40b8e7bf-72a0-4937-95ab-9675b857c742 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618326689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.618326689 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.1281970817 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 317854216 ps |
| CPU time | 139.24 seconds |
| Started | Feb 07 04:17:17 PM PST 24 |
| Finished | Feb 07 04:19:36 PM PST 24 |
| Peak memory | 556612 kb |
| Host | smart-7ade0b92-5c32-4c4e-8cb6-6fb2db058abe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281970817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all _with_rand_reset.1281970817 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.3854891327 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 44463621 ps |
| CPU time | 13.27 seconds |
| Started | Feb 07 04:17:14 PM PST 24 |
| Finished | Feb 07 04:17:28 PM PST 24 |
| Peak memory | 554384 kb |
| Host | smart-3e9eb829-493b-46dd-98be-0ab466fa5a38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854891327 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_al l_with_reset_error.3854891327 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.1377770122 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 352002643 ps |
| CPU time | 43.1 seconds |
| Started | Feb 07 04:17:15 PM PST 24 |
| Finished | Feb 07 04:17:59 PM PST 24 |
| Peak memory | 559176 kb |
| Host | smart-9f274941-e040-4212-8962-5978fd12fde8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377770122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.1377770122 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device.1521704320 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 1046878498 ps |
| CPU time | 35.1 seconds |
| Started | Feb 07 04:17:22 PM PST 24 |
| Finished | Feb 07 04:17:57 PM PST 24 |
| Peak memory | 554312 kb |
| Host | smart-e4b13c22-7780-46c5-b8fd-bb98bf217910 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521704320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device .1521704320 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.2157074433 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 118670831191 ps |
| CPU time | 2161.82 seconds |
| Started | Feb 07 04:17:21 PM PST 24 |
| Finished | Feb 07 04:53:24 PM PST 24 |
| Peak memory | 556456 kb |
| Host | smart-8380f179-4b7f-4b1b-8cba-739f4fc17d0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157074433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_ device_slow_rsp.2157074433 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.2561072152 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 310601499 ps |
| CPU time | 16.75 seconds |
| Started | Feb 07 04:17:20 PM PST 24 |
| Finished | Feb 07 04:17:37 PM PST 24 |
| Peak memory | 555660 kb |
| Host | smart-df3f961e-dfa4-430a-8a89-124545f6ad7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561072152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_add r.2561072152 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_random.680837718 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 614047290 ps |
| CPU time | 50.15 seconds |
| Started | Feb 07 04:17:21 PM PST 24 |
| Finished | Feb 07 04:18:11 PM PST 24 |
| Peak memory | 559168 kb |
| Host | smart-cb592a20-29ac-424f-b868-77dce6882ca0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680837718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.680837718 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random.3634340922 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 1131311187 ps |
| CPU time | 39.77 seconds |
| Started | Feb 07 04:17:21 PM PST 24 |
| Finished | Feb 07 04:18:02 PM PST 24 |
| Peak memory | 555652 kb |
| Host | smart-d649a12a-0bbd-44a6-b53a-add01a4e2baf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634340922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.3634340922 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.1143441696 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 13634826360 ps |
| CPU time | 138.56 seconds |
| Started | Feb 07 04:17:22 PM PST 24 |
| Finished | Feb 07 04:19:41 PM PST 24 |
| Peak memory | 555452 kb |
| Host | smart-344c963c-8b04-4012-a153-f69b50ec2a64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143441696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1143441696 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.849437184 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 40967827923 ps |
| CPU time | 670.76 seconds |
| Started | Feb 07 04:17:20 PM PST 24 |
| Finished | Feb 07 04:28:31 PM PST 24 |
| Peak memory | 555716 kb |
| Host | smart-94275b4e-7f07-4c80-a8a2-217f0cb9634d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849437184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.849437184 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.2341095055 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 569970131 ps |
| CPU time | 47.76 seconds |
| Started | Feb 07 04:17:31 PM PST 24 |
| Finished | Feb 07 04:18:19 PM PST 24 |
| Peak memory | 555328 kb |
| Host | smart-7146ed78-f7f8-4831-8ea0-802d5c45c1f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341095055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_del ays.2341095055 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_same_source.2275356034 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 1539706029 ps |
| CPU time | 44.37 seconds |
| Started | Feb 07 04:17:27 PM PST 24 |
| Finished | Feb 07 04:18:11 PM PST 24 |
| Peak memory | 559172 kb |
| Host | smart-d6990eb8-e4a3-4995-8d4c-ca9ff7985736 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275356034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2275356034 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke.4290294704 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 211933462 ps |
| CPU time | 8.78 seconds |
| Started | Feb 07 04:17:30 PM PST 24 |
| Finished | Feb 07 04:17:39 PM PST 24 |
| Peak memory | 553568 kb |
| Host | smart-c0744827-827e-430e-813a-15bc0d65991b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290294704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.4290294704 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.3838258044 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 8314766868 ps |
| CPU time | 93.03 seconds |
| Started | Feb 07 04:17:28 PM PST 24 |
| Finished | Feb 07 04:19:02 PM PST 24 |
| Peak memory | 559236 kb |
| Host | smart-7f035f9e-6310-49a5-8871-3239b11993ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838258044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.3838258044 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.3190132875 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 5725014403 ps |
| CPU time | 91.24 seconds |
| Started | Feb 07 04:17:24 PM PST 24 |
| Finished | Feb 07 04:18:56 PM PST 24 |
| Peak memory | 553620 kb |
| Host | smart-ad8caf10-d1d4-45dc-a02d-e080db818582 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190132875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3190132875 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.4031852036 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 33713786 ps |
| CPU time | 5.97 seconds |
| Started | Feb 07 04:17:28 PM PST 24 |
| Finished | Feb 07 04:17:35 PM PST 24 |
| Peak memory | 553120 kb |
| Host | smart-24e0226f-d9c8-469e-a125-48542d1c9e1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031852036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delay s.4031852036 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all.3509977679 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 4179429108 ps |
| CPU time | 149.68 seconds |
| Started | Feb 07 04:17:21 PM PST 24 |
| Finished | Feb 07 04:19:51 PM PST 24 |
| Peak memory | 556548 kb |
| Host | smart-1761571b-1cf3-42c3-a116-76ecfaf2fc13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509977679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.3509977679 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.3749187751 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 4881971577 ps |
| CPU time | 403.79 seconds |
| Started | Feb 07 04:17:21 PM PST 24 |
| Finished | Feb 07 04:24:05 PM PST 24 |
| Peak memory | 557788 kb |
| Host | smart-f78eb115-98ed-4f48-8041-baa6e4a9efbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749187751 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3749187751 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.2483762316 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 9835837 ps |
| CPU time | 3.78 seconds |
| Started | Feb 07 04:17:22 PM PST 24 |
| Finished | Feb 07 04:17:26 PM PST 24 |
| Peak memory | 545300 kb |
| Host | smart-b8a396ff-6fd8-4265-9158-78427cd0b279 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483762316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all _with_rand_reset.2483762316 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.481447127 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 868395123 ps |
| CPU time | 227.2 seconds |
| Started | Feb 07 04:17:31 PM PST 24 |
| Finished | Feb 07 04:21:19 PM PST 24 |
| Peak memory | 559300 kb |
| Host | smart-a78bb1e5-3a0d-471f-b0cb-28e992ca7155 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481447127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all _with_reset_error.481447127 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.2491181394 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 813918820 ps |
| CPU time | 29.09 seconds |
| Started | Feb 07 04:17:29 PM PST 24 |
| Finished | Feb 07 04:17:58 PM PST 24 |
| Peak memory | 555404 kb |
| Host | smart-ffe20df5-0b91-49e7-b634-e131e159ee6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491181394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.2491181394 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device.3634469813 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 1338397861 ps |
| CPU time | 67 seconds |
| Started | Feb 07 04:17:22 PM PST 24 |
| Finished | Feb 07 04:18:30 PM PST 24 |
| Peak memory | 555144 kb |
| Host | smart-20986bde-008b-408c-a726-6f3cb2ad840a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634469813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device .3634469813 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.3469921535 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 111453208765 ps |
| CPU time | 2060.07 seconds |
| Started | Feb 07 04:17:27 PM PST 24 |
| Finished | Feb 07 04:51:48 PM PST 24 |
| Peak memory | 556808 kb |
| Host | smart-38b980f1-5f5e-451f-ac01-b7305b703f3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469921535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_ device_slow_rsp.3469921535 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.438865139 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 488312797 ps |
| CPU time | 20.25 seconds |
| Started | Feb 07 04:17:31 PM PST 24 |
| Finished | Feb 07 04:17:52 PM PST 24 |
| Peak memory | 555076 kb |
| Host | smart-e9dcda06-2b69-49d3-8600-1599da46724d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438865139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr .438865139 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_random.3192178197 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 2308849920 ps |
| CPU time | 71.94 seconds |
| Started | Feb 07 04:17:32 PM PST 24 |
| Finished | Feb 07 04:18:44 PM PST 24 |
| Peak memory | 555676 kb |
| Host | smart-89fd8025-d74b-455e-82cd-3a50797db200 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192178197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.3192178197 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random.2639501050 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 772255425 ps |
| CPU time | 26.64 seconds |
| Started | Feb 07 04:17:23 PM PST 24 |
| Finished | Feb 07 04:17:50 PM PST 24 |
| Peak memory | 555112 kb |
| Host | smart-84cc4958-bfd1-4019-ba7f-3e8452a0e6a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639501050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.2639501050 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.3968658146 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 99532171611 ps |
| CPU time | 1008.82 seconds |
| Started | Feb 07 04:17:22 PM PST 24 |
| Finished | Feb 07 04:34:11 PM PST 24 |
| Peak memory | 554864 kb |
| Host | smart-e06238bd-fdb6-43cb-b5e1-c8d2bd0515da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968658146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.3968658146 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.1965255039 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 19253761696 ps |
| CPU time | 311.23 seconds |
| Started | Feb 07 04:17:30 PM PST 24 |
| Finished | Feb 07 04:22:42 PM PST 24 |
| Peak memory | 555732 kb |
| Host | smart-8d6883e1-38dd-4171-b408-2801faa99910 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965255039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.1965255039 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.593824851 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 460407546 ps |
| CPU time | 38.51 seconds |
| Started | Feb 07 04:17:29 PM PST 24 |
| Finished | Feb 07 04:18:08 PM PST 24 |
| Peak memory | 555676 kb |
| Host | smart-88ba0c67-e70b-4340-9123-23c6bb5cf8f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593824851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_dela ys.593824851 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_same_source.598685323 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 129078331 ps |
| CPU time | 11.92 seconds |
| Started | Feb 07 04:17:29 PM PST 24 |
| Finished | Feb 07 04:17:42 PM PST 24 |
| Peak memory | 555332 kb |
| Host | smart-0aebd8e1-4045-4221-9ba2-e5ed754c5939 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598685323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.598685323 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke.3501743625 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 41664373 ps |
| CPU time | 5.93 seconds |
| Started | Feb 07 04:17:32 PM PST 24 |
| Finished | Feb 07 04:17:39 PM PST 24 |
| Peak memory | 553612 kb |
| Host | smart-d3c0b76e-5107-4744-988f-b5e73ba22a22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501743625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.3501743625 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.1826213814 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 8224669672 ps |
| CPU time | 92.77 seconds |
| Started | Feb 07 04:17:24 PM PST 24 |
| Finished | Feb 07 04:18:57 PM PST 24 |
| Peak memory | 553340 kb |
| Host | smart-40a01cb4-2eb2-46a0-abfe-3cbf90fb28d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826213814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.1826213814 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.4002270123 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 5385725623 ps |
| CPU time | 94.92 seconds |
| Started | Feb 07 04:17:21 PM PST 24 |
| Finished | Feb 07 04:18:57 PM PST 24 |
| Peak memory | 553116 kb |
| Host | smart-af0fb827-765c-4c4f-adf3-7b480a661cc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002270123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.4002270123 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.1140291753 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 49323281 ps |
| CPU time | 6.61 seconds |
| Started | Feb 07 04:17:22 PM PST 24 |
| Finished | Feb 07 04:17:29 PM PST 24 |
| Peak memory | 553016 kb |
| Host | smart-9864c7a6-6e7e-463e-8d2a-4e411cb3cc40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140291753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delay s.1140291753 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all.1790278711 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 833717090 ps |
| CPU time | 79.65 seconds |
| Started | Feb 07 04:17:33 PM PST 24 |
| Finished | Feb 07 04:18:53 PM PST 24 |
| Peak memory | 555676 kb |
| Host | smart-4766e381-773e-4859-bb3f-6bd17d783a8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790278711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.1790278711 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.2000191354 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 1837379025 ps |
| CPU time | 168.87 seconds |
| Started | Feb 07 04:17:32 PM PST 24 |
| Finished | Feb 07 04:20:22 PM PST 24 |
| Peak memory | 556548 kb |
| Host | smart-f6f9f5d0-681b-4b7f-8732-187d650f2a94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000191354 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.2000191354 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.3739727068 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 263985881 ps |
| CPU time | 115.93 seconds |
| Started | Feb 07 04:17:31 PM PST 24 |
| Finished | Feb 07 04:19:27 PM PST 24 |
| Peak memory | 556604 kb |
| Host | smart-d1d5844b-6813-4227-adb6-30cf36f4f465 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739727068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_rand_reset.3739727068 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.1990615522 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 434632375 ps |
| CPU time | 142.49 seconds |
| Started | Feb 07 04:17:31 PM PST 24 |
| Finished | Feb 07 04:19:54 PM PST 24 |
| Peak memory | 558244 kb |
| Host | smart-77df509b-d751-4619-9683-bf493b61af01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990615522 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_al l_with_reset_error.1990615522 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.896628464 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 20981308 ps |
| CPU time | 5.54 seconds |
| Started | Feb 07 04:17:29 PM PST 24 |
| Finished | Feb 07 04:17:35 PM PST 24 |
| Peak memory | 553256 kb |
| Host | smart-df06ac10-0f4d-4008-a68c-935bd641032a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896628464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.896628464 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device.2409779695 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 1444565333 ps |
| CPU time | 73.79 seconds |
| Started | Feb 07 04:17:40 PM PST 24 |
| Finished | Feb 07 04:18:54 PM PST 24 |
| Peak memory | 555432 kb |
| Host | smart-cca0d9ae-1639-4a02-abe5-f03227fa61c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409779695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device .2409779695 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.4042651490 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 79360850081 ps |
| CPU time | 1578.24 seconds |
| Started | Feb 07 04:17:41 PM PST 24 |
| Finished | Feb 07 04:44:00 PM PST 24 |
| Peak memory | 556256 kb |
| Host | smart-fe5ec8cd-8f92-4644-a572-65d54b7a044e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042651490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_ device_slow_rsp.4042651490 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.3768713644 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 216707689 ps |
| CPU time | 23.76 seconds |
| Started | Feb 07 04:17:38 PM PST 24 |
| Finished | Feb 07 04:18:03 PM PST 24 |
| Peak memory | 555368 kb |
| Host | smart-dec02bee-0af7-446d-b063-cb2e58f7d1a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768713644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_add r.3768713644 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_random.491363948 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 479802008 ps |
| CPU time | 39.11 seconds |
| Started | Feb 07 04:17:42 PM PST 24 |
| Finished | Feb 07 04:18:22 PM PST 24 |
| Peak memory | 555648 kb |
| Host | smart-25505be8-a6fa-473b-89b9-74fee6c89efd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491363948 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.491363948 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random.2967394405 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 861292380 ps |
| CPU time | 36.06 seconds |
| Started | Feb 07 04:17:36 PM PST 24 |
| Finished | Feb 07 04:18:13 PM PST 24 |
| Peak memory | 555400 kb |
| Host | smart-1dc8b04b-ef3d-4f9b-91c3-ca19966bb7ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967394405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.2967394405 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.870451506 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 85529238696 ps |
| CPU time | 1096.18 seconds |
| Started | Feb 07 04:17:37 PM PST 24 |
| Finished | Feb 07 04:35:54 PM PST 24 |
| Peak memory | 555796 kb |
| Host | smart-32511023-83f7-4e5a-9826-5d000153ef4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870451506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.870451506 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.1573691178 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 41852809224 ps |
| CPU time | 747.31 seconds |
| Started | Feb 07 04:17:43 PM PST 24 |
| Finished | Feb 07 04:30:10 PM PST 24 |
| Peak memory | 555208 kb |
| Host | smart-662cfcf1-8140-4ab4-9d19-eb28f786832e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573691178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.1573691178 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.2978139319 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 448353688 ps |
| CPU time | 37.18 seconds |
| Started | Feb 07 04:17:39 PM PST 24 |
| Finished | Feb 07 04:18:16 PM PST 24 |
| Peak memory | 555624 kb |
| Host | smart-b53371b1-d1ea-4946-b46e-4acf5c21b4b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978139319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_del ays.2978139319 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_same_source.2321366187 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 498107495 ps |
| CPU time | 36.82 seconds |
| Started | Feb 07 04:17:39 PM PST 24 |
| Finished | Feb 07 04:18:16 PM PST 24 |
| Peak memory | 555628 kb |
| Host | smart-607aa9d2-76c5-40ec-a703-0d6c83be851e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321366187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2321366187 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke.1045608678 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 47047101 ps |
| CPU time | 6.08 seconds |
| Started | Feb 07 04:17:32 PM PST 24 |
| Finished | Feb 07 04:17:39 PM PST 24 |
| Peak memory | 553620 kb |
| Host | smart-6dd64ad5-6542-415a-bc61-50253041b59c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045608678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1045608678 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.1309105092 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 8855129680 ps |
| CPU time | 91.99 seconds |
| Started | Feb 07 04:17:33 PM PST 24 |
| Finished | Feb 07 04:19:06 PM PST 24 |
| Peak memory | 553388 kb |
| Host | smart-f1e0e57e-a209-470c-a546-e71bdb25fd62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309105092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1309105092 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.3533073830 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 5055698328 ps |
| CPU time | 83.14 seconds |
| Started | Feb 07 04:17:41 PM PST 24 |
| Finished | Feb 07 04:19:05 PM PST 24 |
| Peak memory | 552964 kb |
| Host | smart-0092c13e-987a-4584-84e2-98e1a920c530 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533073830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.3533073830 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.1021836195 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 56608571 ps |
| CPU time | 7.17 seconds |
| Started | Feb 07 04:17:34 PM PST 24 |
| Finished | Feb 07 04:17:42 PM PST 24 |
| Peak memory | 553588 kb |
| Host | smart-d79d0d1a-3dd1-4422-8205-f85a69d61764 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021836195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delay s.1021836195 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all.3375502920 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 13334571886 ps |
| CPU time | 470.6 seconds |
| Started | Feb 07 04:17:39 PM PST 24 |
| Finished | Feb 07 04:25:31 PM PST 24 |
| Peak memory | 556676 kb |
| Host | smart-09a6b926-3635-4f57-b410-c8117b983beb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375502920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3375502920 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.3962318314 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 7468077888 ps |
| CPU time | 272 seconds |
| Started | Feb 07 04:17:39 PM PST 24 |
| Finished | Feb 07 04:22:12 PM PST 24 |
| Peak memory | 556888 kb |
| Host | smart-31be9a83-0c74-4442-88cd-f7efacd1ca54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962318314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.3962318314 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.3857488 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 2101899233 ps |
| CPU time | 389.68 seconds |
| Started | Feb 07 04:17:39 PM PST 24 |
| Finished | Feb 07 04:24:09 PM PST 24 |
| Peak memory | 558528 kb |
| Host | smart-28432590-9227-4f5f-9c06-0da870ff2d20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_wi th_rand_reset.3857488 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.1452864370 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 156590294 ps |
| CPU time | 31.42 seconds |
| Started | Feb 07 04:17:39 PM PST 24 |
| Finished | Feb 07 04:18:10 PM PST 24 |
| Peak memory | 556840 kb |
| Host | smart-5e63afac-dad6-4d76-b1e5-b4a4581dae53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452864370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_al l_with_reset_error.1452864370 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.576748695 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 261616381 ps |
| CPU time | 33.66 seconds |
| Started | Feb 07 04:17:37 PM PST 24 |
| Finished | Feb 07 04:18:11 PM PST 24 |
| Peak memory | 555656 kb |
| Host | smart-021d822a-9f3c-454f-8806-8fed2bae60f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576748695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.576748695 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.1744638989 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 10319550361 ps |
| CPU time | 343.08 seconds |
| Started | Feb 07 04:11:50 PM PST 24 |
| Finished | Feb 07 04:17:34 PM PST 24 |
| Peak memory | 628788 kb |
| Host | smart-bdde0e70-7cd3-4b12-8dea-0ad4b72e7667 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744638989 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 5.chip_csr_mem_rw_with_rand_reset.1744638989 |
| Directory | /workspace/5.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_rw.1471780742 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 4889390957 ps |
| CPU time | 314.19 seconds |
| Started | Feb 07 04:11:53 PM PST 24 |
| Finished | Feb 07 04:17:08 PM PST 24 |
| Peak memory | 579656 kb |
| Host | smart-57389698-ea1c-4b07-99c5-3902c1795d33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471780742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.1471780742 |
| Directory | /workspace/5.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.2360543038 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 27571620685 ps |
| CPU time | 4199.8 seconds |
| Started | Feb 07 04:11:53 PM PST 24 |
| Finished | Feb 07 05:21:54 PM PST 24 |
| Peak memory | 580172 kb |
| Host | smart-55b4adbb-1a43-49e8-a5c2-5e6f6f0d4ada |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360543038 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.chip_same_csr_outstanding.2360543038 |
| Directory | /workspace/5.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_tl_errors.1278185181 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 3185875489 ps |
| CPU time | 144.21 seconds |
| Started | Feb 07 04:11:53 PM PST 24 |
| Finished | Feb 07 04:14:18 PM PST 24 |
| Peak memory | 580188 kb |
| Host | smart-671037bd-ab23-4001-bd4d-d0d5942332dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278185181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.1278185181 |
| Directory | /workspace/5.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device.2964117214 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 742155205 ps |
| CPU time | 30.07 seconds |
| Started | Feb 07 04:11:53 PM PST 24 |
| Finished | Feb 07 04:12:24 PM PST 24 |
| Peak memory | 555392 kb |
| Host | smart-b9029733-9e33-441a-97c7-1bc0172e333b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964117214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device. 2964117214 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.3482131059 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 53636415097 ps |
| CPU time | 832.9 seconds |
| Started | Feb 07 04:11:54 PM PST 24 |
| Finished | Feb 07 04:25:48 PM PST 24 |
| Peak memory | 555584 kb |
| Host | smart-85c9612f-92a8-4f6a-a53d-5f9ced8cf5dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482131059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_d evice_slow_rsp.3482131059 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.2294395933 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 139699418 ps |
| CPU time | 7.61 seconds |
| Started | Feb 07 04:11:53 PM PST 24 |
| Finished | Feb 07 04:12:01 PM PST 24 |
| Peak memory | 553560 kb |
| Host | smart-d4ab4986-f35d-4ad8-861d-fe771ccb3837 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294395933 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr .2294395933 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_random.2551816148 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 61929952 ps |
| CPU time | 7.98 seconds |
| Started | Feb 07 04:11:48 PM PST 24 |
| Finished | Feb 07 04:11:56 PM PST 24 |
| Peak memory | 554328 kb |
| Host | smart-c89d8c00-945b-439b-b800-e30d248aef9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551816148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.2551816148 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random.1956194413 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 90785242 ps |
| CPU time | 9.5 seconds |
| Started | Feb 07 04:11:47 PM PST 24 |
| Finished | Feb 07 04:11:57 PM PST 24 |
| Peak memory | 555388 kb |
| Host | smart-86c5525c-1fa2-4b3d-8c79-51c45cb90110 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956194413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.1956194413 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.1911856979 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 97632228045 ps |
| CPU time | 987.73 seconds |
| Started | Feb 07 04:11:49 PM PST 24 |
| Finished | Feb 07 04:28:18 PM PST 24 |
| Peak memory | 555696 kb |
| Host | smart-f6d96bc6-6d78-4702-8c28-e67e9a43e42a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911856979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1911856979 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.4071605760 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 16965598504 ps |
| CPU time | 263.05 seconds |
| Started | Feb 07 04:11:52 PM PST 24 |
| Finished | Feb 07 04:16:16 PM PST 24 |
| Peak memory | 555152 kb |
| Host | smart-cca35ace-5fe2-4514-9fcc-3702d5d1fdab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071605760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.4071605760 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.1458072601 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 88966327 ps |
| CPU time | 10.66 seconds |
| Started | Feb 07 04:11:53 PM PST 24 |
| Finished | Feb 07 04:12:05 PM PST 24 |
| Peak memory | 559124 kb |
| Host | smart-6b650b0b-41b6-4be4-8f7e-01935ee62308 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458072601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_dela ys.1458072601 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_same_source.637116200 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 1320165976 ps |
| CPU time | 42.18 seconds |
| Started | Feb 07 04:11:51 PM PST 24 |
| Finished | Feb 07 04:12:33 PM PST 24 |
| Peak memory | 555360 kb |
| Host | smart-7b869754-1005-45e6-840e-dd9c2e16a9eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637116200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.637116200 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke.2566286399 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 272850739 ps |
| CPU time | 11.09 seconds |
| Started | Feb 07 04:11:47 PM PST 24 |
| Finished | Feb 07 04:11:59 PM PST 24 |
| Peak memory | 553224 kb |
| Host | smart-7ae0740a-9346-496d-8982-9af6c3577436 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566286399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2566286399 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.2244329719 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 8622805696 ps |
| CPU time | 94.51 seconds |
| Started | Feb 07 04:11:53 PM PST 24 |
| Finished | Feb 07 04:13:28 PM PST 24 |
| Peak memory | 553644 kb |
| Host | smart-bf769759-b3c1-40aa-9605-a10290b5c635 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244329719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.2244329719 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.3771078732 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 3696564851 ps |
| CPU time | 65.2 seconds |
| Started | Feb 07 04:11:54 PM PST 24 |
| Finished | Feb 07 04:12:59 PM PST 24 |
| Peak memory | 553640 kb |
| Host | smart-bb24854d-2a76-4c90-bd4c-8ed04fa13a97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771078732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.3771078732 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.2865658143 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 46825236 ps |
| CPU time | 5.87 seconds |
| Started | Feb 07 04:11:52 PM PST 24 |
| Finished | Feb 07 04:11:58 PM PST 24 |
| Peak memory | 553540 kb |
| Host | smart-04fbfd6c-cb00-4151-921c-3d85419d36b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865658143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays .2865658143 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.790413787 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 1261386452 ps |
| CPU time | 111.73 seconds |
| Started | Feb 07 04:11:44 PM PST 24 |
| Finished | Feb 07 04:13:36 PM PST 24 |
| Peak memory | 556520 kb |
| Host | smart-0e7758f9-ce1a-4322-9a41-4d010404aab0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790413787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.790413787 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.3029054605 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 203995541 ps |
| CPU time | 69.39 seconds |
| Started | Feb 07 04:11:52 PM PST 24 |
| Finished | Feb 07 04:13:02 PM PST 24 |
| Peak memory | 556672 kb |
| Host | smart-cc2d45a7-2538-47db-9745-5e5a826b0684 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029054605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_ with_rand_reset.3029054605 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.1715262337 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 185309928 ps |
| CPU time | 57.63 seconds |
| Started | Feb 07 04:11:50 PM PST 24 |
| Finished | Feb 07 04:12:48 PM PST 24 |
| Peak memory | 556724 kb |
| Host | smart-319f4992-8ed5-4208-a8f7-1d738223dd80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715262337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all _with_reset_error.1715262337 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.1063219991 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 945462005 ps |
| CPU time | 34.75 seconds |
| Started | Feb 07 04:11:52 PM PST 24 |
| Finished | Feb 07 04:12:27 PM PST 24 |
| Peak memory | 555620 kb |
| Host | smart-27c8def3-17f5-4b67-b447-b50adbf096ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063219991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.1063219991 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device.2238294091 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 890553466 ps |
| CPU time | 38.8 seconds |
| Started | Feb 07 04:17:48 PM PST 24 |
| Finished | Feb 07 04:18:28 PM PST 24 |
| Peak memory | 555672 kb |
| Host | smart-b00cf5d0-515d-49af-85b7-06de949c9fc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238294091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device .2238294091 |
| Directory | /workspace/50.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.3563613626 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 68397904526 ps |
| CPU time | 1385.55 seconds |
| Started | Feb 07 04:17:52 PM PST 24 |
| Finished | Feb 07 04:41:00 PM PST 24 |
| Peak memory | 555552 kb |
| Host | smart-c0daf774-1f8c-4eb7-8490-aaec5b60fb5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563613626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_ device_slow_rsp.3563613626 |
| Directory | /workspace/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.3636477604 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 382581306 ps |
| CPU time | 17.91 seconds |
| Started | Feb 07 04:17:52 PM PST 24 |
| Finished | Feb 07 04:18:12 PM PST 24 |
| Peak memory | 555308 kb |
| Host | smart-fa364899-5c25-4fdc-a377-b91288476f47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636477604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_add r.3636477604 |
| Directory | /workspace/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_random.2637198722 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 564594021 ps |
| CPU time | 46.02 seconds |
| Started | Feb 07 04:17:48 PM PST 24 |
| Finished | Feb 07 04:18:35 PM PST 24 |
| Peak memory | 559180 kb |
| Host | smart-50d4abfa-ee45-4855-b523-49f7049109cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637198722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.2637198722 |
| Directory | /workspace/50.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random.609827963 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 897003318 ps |
| CPU time | 36.71 seconds |
| Started | Feb 07 04:17:41 PM PST 24 |
| Finished | Feb 07 04:18:18 PM PST 24 |
| Peak memory | 555328 kb |
| Host | smart-fd12f037-0561-4a44-b794-f1aecc71d1db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609827963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.609827963 |
| Directory | /workspace/50.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.3057033900 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 63621241386 ps |
| CPU time | 726.05 seconds |
| Started | Feb 07 04:17:40 PM PST 24 |
| Finished | Feb 07 04:29:47 PM PST 24 |
| Peak memory | 555712 kb |
| Host | smart-79fa00aa-f579-4ea6-8056-e9ca8be3c9af |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057033900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.3057033900 |
| Directory | /workspace/50.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.1149771786 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 50899044339 ps |
| CPU time | 965.7 seconds |
| Started | Feb 07 04:17:52 PM PST 24 |
| Finished | Feb 07 04:34:00 PM PST 24 |
| Peak memory | 555708 kb |
| Host | smart-6c9ec538-6f19-4446-9809-937dfa1afe0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149771786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.1149771786 |
| Directory | /workspace/50.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.11438803 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 513633701 ps |
| CPU time | 41.44 seconds |
| Started | Feb 07 04:17:39 PM PST 24 |
| Finished | Feb 07 04:18:21 PM PST 24 |
| Peak memory | 555336 kb |
| Host | smart-e0688c72-4e39-459c-aadd-51ae75c5e938 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11438803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_delay s.11438803 |
| Directory | /workspace/50.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_same_source.1127936059 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 547399844 ps |
| CPU time | 44.5 seconds |
| Started | Feb 07 04:17:50 PM PST 24 |
| Finished | Feb 07 04:18:38 PM PST 24 |
| Peak memory | 555664 kb |
| Host | smart-a99a3235-f425-4061-a8d7-0abc11f7c8f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127936059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.1127936059 |
| Directory | /workspace/50.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke.464658913 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 46399771 ps |
| CPU time | 6.12 seconds |
| Started | Feb 07 04:17:37 PM PST 24 |
| Finished | Feb 07 04:17:43 PM PST 24 |
| Peak memory | 553304 kb |
| Host | smart-d9bacfb5-68cd-4a6c-90c2-998ea6058ac3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464658913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.464658913 |
| Directory | /workspace/50.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.2885277891 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 8135365055 ps |
| CPU time | 86.05 seconds |
| Started | Feb 07 04:17:40 PM PST 24 |
| Finished | Feb 07 04:19:07 PM PST 24 |
| Peak memory | 553668 kb |
| Host | smart-a52286ae-2337-4998-b2a9-654a8f2455a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885277891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.2885277891 |
| Directory | /workspace/50.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.942384922 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 5987489426 ps |
| CPU time | 98.22 seconds |
| Started | Feb 07 04:17:38 PM PST 24 |
| Finished | Feb 07 04:19:17 PM PST 24 |
| Peak memory | 553648 kb |
| Host | smart-7c069360-c091-4f7e-a715-d9bcea12cd2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942384922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.942384922 |
| Directory | /workspace/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.3097158188 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 41372967 ps |
| CPU time | 5.91 seconds |
| Started | Feb 07 04:17:42 PM PST 24 |
| Finished | Feb 07 04:17:48 PM PST 24 |
| Peak memory | 553276 kb |
| Host | smart-23988012-fdd4-4f43-a6e7-fe588cd131ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097158188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delay s.3097158188 |
| Directory | /workspace/50.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all.501037918 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 2149729846 ps |
| CPU time | 193.75 seconds |
| Started | Feb 07 04:17:53 PM PST 24 |
| Finished | Feb 07 04:21:09 PM PST 24 |
| Peak memory | 556676 kb |
| Host | smart-d1feb393-76a8-41a5-871e-feb4332c029a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501037918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.501037918 |
| Directory | /workspace/50.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.97722393 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 2091061722 ps |
| CPU time | 165.01 seconds |
| Started | Feb 07 04:17:54 PM PST 24 |
| Finished | Feb 07 04:20:41 PM PST 24 |
| Peak memory | 556572 kb |
| Host | smart-fe5c1efc-2254-4cb6-8e04-cf597cd22646 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97722393 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.97722393 |
| Directory | /workspace/50.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.3894795024 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 354648162 ps |
| CPU time | 176.29 seconds |
| Started | Feb 07 04:17:53 PM PST 24 |
| Finished | Feb 07 04:20:52 PM PST 24 |
| Peak memory | 556448 kb |
| Host | smart-9232a3f2-de87-4fe1-8053-787c3b301bb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894795024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_rand_reset.3894795024 |
| Directory | /workspace/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.704157215 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 287564876 ps |
| CPU time | 106.03 seconds |
| Started | Feb 07 04:17:48 PM PST 24 |
| Finished | Feb 07 04:19:35 PM PST 24 |
| Peak memory | 556660 kb |
| Host | smart-88ce95ed-fd19-4184-a0e3-b1a46e5aaaf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704157215 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_reset_error.704157215 |
| Directory | /workspace/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.3424864902 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 273230859 ps |
| CPU time | 30.1 seconds |
| Started | Feb 07 04:17:51 PM PST 24 |
| Finished | Feb 07 04:18:24 PM PST 24 |
| Peak memory | 555340 kb |
| Host | smart-6b8b4c26-b5a3-496f-8180-8ea76b9264cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424864902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.3424864902 |
| Directory | /workspace/50.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device.778613831 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 3050327467 ps |
| CPU time | 140.78 seconds |
| Started | Feb 07 04:18:00 PM PST 24 |
| Finished | Feb 07 04:20:21 PM PST 24 |
| Peak memory | 555296 kb |
| Host | smart-12ac0ed1-8cda-4d18-805c-59aff0fe719f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778613831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device. 778613831 |
| Directory | /workspace/51.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.932848576 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 123162965658 ps |
| CPU time | 2336.98 seconds |
| Started | Feb 07 04:17:57 PM PST 24 |
| Finished | Feb 07 04:56:56 PM PST 24 |
| Peak memory | 556572 kb |
| Host | smart-7107d6a2-5de4-47c4-a1ac-b00e52b92a27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932848576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_d evice_slow_rsp.932848576 |
| Directory | /workspace/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.3201380743 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 1129205132 ps |
| CPU time | 43.23 seconds |
| Started | Feb 07 04:18:03 PM PST 24 |
| Finished | Feb 07 04:18:47 PM PST 24 |
| Peak memory | 555652 kb |
| Host | smart-bb9f14ca-13f9-4f69-a953-f5441cf76e4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201380743 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_add r.3201380743 |
| Directory | /workspace/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_random.1328980784 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 389634010 ps |
| CPU time | 30.25 seconds |
| Started | Feb 07 04:18:04 PM PST 24 |
| Finished | Feb 07 04:18:35 PM PST 24 |
| Peak memory | 555312 kb |
| Host | smart-f5b752de-dee9-4518-b14b-5bb25cb7550d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328980784 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.1328980784 |
| Directory | /workspace/51.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random.3673680573 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 1035038720 ps |
| CPU time | 37.6 seconds |
| Started | Feb 07 04:17:55 PM PST 24 |
| Finished | Feb 07 04:18:34 PM PST 24 |
| Peak memory | 555340 kb |
| Host | smart-debff11d-8d20-490b-b8df-c8e4b5005491 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673680573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.3673680573 |
| Directory | /workspace/51.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.2052489697 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 60943979335 ps |
| CPU time | 613.25 seconds |
| Started | Feb 07 04:17:56 PM PST 24 |
| Finished | Feb 07 04:28:10 PM PST 24 |
| Peak memory | 555704 kb |
| Host | smart-fc91eff0-fe27-4bc3-a0af-627c867cc4b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052489697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.2052489697 |
| Directory | /workspace/51.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.1532484363 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 4068188716 ps |
| CPU time | 72.91 seconds |
| Started | Feb 07 04:18:00 PM PST 24 |
| Finished | Feb 07 04:19:13 PM PST 24 |
| Peak memory | 553548 kb |
| Host | smart-3c6581cc-fc04-4b3f-9e85-9631b37176d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532484363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.1532484363 |
| Directory | /workspace/51.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.3187827019 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 97501705 ps |
| CPU time | 10.77 seconds |
| Started | Feb 07 04:18:00 PM PST 24 |
| Finished | Feb 07 04:18:11 PM PST 24 |
| Peak memory | 555668 kb |
| Host | smart-d73f60a0-143c-47c2-a9e9-ef6b7e022039 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187827019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_del ays.3187827019 |
| Directory | /workspace/51.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_same_source.1552434060 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 222754383 ps |
| CPU time | 19.17 seconds |
| Started | Feb 07 04:18:03 PM PST 24 |
| Finished | Feb 07 04:18:22 PM PST 24 |
| Peak memory | 555368 kb |
| Host | smart-c17ba289-06f3-4046-9946-bafcd91cedd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552434060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.1552434060 |
| Directory | /workspace/51.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke.3897045650 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 39355900 ps |
| CPU time | 5.97 seconds |
| Started | Feb 07 04:17:52 PM PST 24 |
| Finished | Feb 07 04:18:00 PM PST 24 |
| Peak memory | 552996 kb |
| Host | smart-57887e57-f99c-45b4-9475-d951ae1b9511 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897045650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.3897045650 |
| Directory | /workspace/51.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.2382301262 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 4131433466 ps |
| CPU time | 43.95 seconds |
| Started | Feb 07 04:17:50 PM PST 24 |
| Finished | Feb 07 04:18:38 PM PST 24 |
| Peak memory | 553680 kb |
| Host | smart-c5eca24d-ccf7-4624-acc7-97b684f17d1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382301262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.2382301262 |
| Directory | /workspace/51.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.2003924783 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 3913494681 ps |
| CPU time | 67.65 seconds |
| Started | Feb 07 04:17:53 PM PST 24 |
| Finished | Feb 07 04:19:03 PM PST 24 |
| Peak memory | 553040 kb |
| Host | smart-c4df9a2e-f872-42f3-a01b-a9e7ad5476c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003924783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.2003924783 |
| Directory | /workspace/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.4204063022 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 42394677 ps |
| CPU time | 5.62 seconds |
| Started | Feb 07 04:17:51 PM PST 24 |
| Finished | Feb 07 04:18:00 PM PST 24 |
| Peak memory | 553244 kb |
| Host | smart-f5a6cad2-8474-4010-8039-2a4f7b62c291 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204063022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delay s.4204063022 |
| Directory | /workspace/51.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all.1193517422 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 4389814825 ps |
| CPU time | 388.81 seconds |
| Started | Feb 07 04:18:06 PM PST 24 |
| Finished | Feb 07 04:24:35 PM PST 24 |
| Peak memory | 557380 kb |
| Host | smart-db84bfc4-50b0-43d5-8f1d-e6649bd20a93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193517422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.1193517422 |
| Directory | /workspace/51.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.2762673889 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 12628673454 ps |
| CPU time | 464.29 seconds |
| Started | Feb 07 04:18:05 PM PST 24 |
| Finished | Feb 07 04:25:51 PM PST 24 |
| Peak memory | 556628 kb |
| Host | smart-a8e7b0be-e21a-4b94-a3ad-5bf26c0cf0f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762673889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.2762673889 |
| Directory | /workspace/51.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.235017074 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 3948882833 ps |
| CPU time | 390.01 seconds |
| Started | Feb 07 04:18:03 PM PST 24 |
| Finished | Feb 07 04:24:34 PM PST 24 |
| Peak memory | 558860 kb |
| Host | smart-2d750c75-bd53-46ff-a1f7-77d5d8cd5b2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235017074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_ with_rand_reset.235017074 |
| Directory | /workspace/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.3195194767 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 619522791 ps |
| CPU time | 27.56 seconds |
| Started | Feb 07 04:17:58 PM PST 24 |
| Finished | Feb 07 04:18:26 PM PST 24 |
| Peak memory | 555092 kb |
| Host | smart-3e199df7-29af-47f6-bf6f-5b79618b17d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195194767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.3195194767 |
| Directory | /workspace/51.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device.3610622700 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 1833543761 ps |
| CPU time | 87.65 seconds |
| Started | Feb 07 04:18:12 PM PST 24 |
| Finished | Feb 07 04:19:41 PM PST 24 |
| Peak memory | 555660 kb |
| Host | smart-3bdf3802-1860-481d-bfe3-376bb4d61a21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610622700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device .3610622700 |
| Directory | /workspace/52.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.3022352479 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 94043647655 ps |
| CPU time | 1702.18 seconds |
| Started | Feb 07 04:18:05 PM PST 24 |
| Finished | Feb 07 04:46:28 PM PST 24 |
| Peak memory | 556524 kb |
| Host | smart-ea0aae2e-806f-4004-9c5f-025774d94959 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022352479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_ device_slow_rsp.3022352479 |
| Directory | /workspace/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.3188235064 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 101265904 ps |
| CPU time | 6.9 seconds |
| Started | Feb 07 04:18:08 PM PST 24 |
| Finished | Feb 07 04:18:18 PM PST 24 |
| Peak memory | 553268 kb |
| Host | smart-8c385350-2f85-484b-b06a-b439ad192f92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188235064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_add r.3188235064 |
| Directory | /workspace/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_random.188414803 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 1544215877 ps |
| CPU time | 49.57 seconds |
| Started | Feb 07 04:18:07 PM PST 24 |
| Finished | Feb 07 04:19:00 PM PST 24 |
| Peak memory | 555328 kb |
| Host | smart-afacdace-427f-409b-9136-18e67ffa8e8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188414803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.188414803 |
| Directory | /workspace/52.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random.1099989190 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 526265378 ps |
| CPU time | 43.3 seconds |
| Started | Feb 07 04:18:12 PM PST 24 |
| Finished | Feb 07 04:18:56 PM PST 24 |
| Peak memory | 555340 kb |
| Host | smart-e148c076-ed34-4af2-91c3-ef402bfeed50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099989190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.1099989190 |
| Directory | /workspace/52.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.4112999490 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 37953094430 ps |
| CPU time | 414.07 seconds |
| Started | Feb 07 04:18:08 PM PST 24 |
| Finished | Feb 07 04:25:05 PM PST 24 |
| Peak memory | 555696 kb |
| Host | smart-44bb94f2-9abf-4d6d-855b-d8156b86d584 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112999490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.4112999490 |
| Directory | /workspace/52.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.1787429771 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 28828068374 ps |
| CPU time | 518.44 seconds |
| Started | Feb 07 04:18:08 PM PST 24 |
| Finished | Feb 07 04:26:49 PM PST 24 |
| Peak memory | 555724 kb |
| Host | smart-250ddc3e-06cc-4ba8-aa6b-e55a2f040553 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787429771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.1787429771 |
| Directory | /workspace/52.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.2271770216 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 62801172 ps |
| CPU time | 7.59 seconds |
| Started | Feb 07 04:18:07 PM PST 24 |
| Finished | Feb 07 04:18:18 PM PST 24 |
| Peak memory | 553656 kb |
| Host | smart-fd8a8e19-8e58-43b1-964e-fa2f2fc39849 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271770216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_del ays.2271770216 |
| Directory | /workspace/52.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_same_source.2153905626 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 63487057 ps |
| CPU time | 7.24 seconds |
| Started | Feb 07 04:18:05 PM PST 24 |
| Finished | Feb 07 04:18:13 PM PST 24 |
| Peak memory | 553564 kb |
| Host | smart-c60d1c09-4f87-4595-858b-b9ed7b950949 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153905626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.2153905626 |
| Directory | /workspace/52.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke.1395581072 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 40406227 ps |
| CPU time | 6.27 seconds |
| Started | Feb 07 04:18:05 PM PST 24 |
| Finished | Feb 07 04:18:13 PM PST 24 |
| Peak memory | 553016 kb |
| Host | smart-5d62d71d-8ad3-4a00-90da-ebaeb47d7664 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395581072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.1395581072 |
| Directory | /workspace/52.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.2927496545 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 7083230173 ps |
| CPU time | 79.7 seconds |
| Started | Feb 07 04:18:06 PM PST 24 |
| Finished | Feb 07 04:19:26 PM PST 24 |
| Peak memory | 553632 kb |
| Host | smart-3de11b3e-b9ad-40b4-92ae-debfc4d4169c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927496545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.2927496545 |
| Directory | /workspace/52.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.2597740442 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 5485147593 ps |
| CPU time | 99.4 seconds |
| Started | Feb 07 04:18:08 PM PST 24 |
| Finished | Feb 07 04:19:50 PM PST 24 |
| Peak memory | 553668 kb |
| Host | smart-534f6615-51a8-4fbb-8570-208ea2ffe1ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597740442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.2597740442 |
| Directory | /workspace/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.2934160722 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 47760292 ps |
| CPU time | 6.52 seconds |
| Started | Feb 07 04:18:07 PM PST 24 |
| Finished | Feb 07 04:18:18 PM PST 24 |
| Peak memory | 553292 kb |
| Host | smart-48df3225-d872-4da5-bb84-adc3a3a8bfe5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934160722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delay s.2934160722 |
| Directory | /workspace/52.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all.729103993 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 16912401271 ps |
| CPU time | 682.23 seconds |
| Started | Feb 07 04:18:07 PM PST 24 |
| Finished | Feb 07 04:29:33 PM PST 24 |
| Peak memory | 557760 kb |
| Host | smart-8b699223-a93d-4bc9-906d-997d9ac8a3dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729103993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.729103993 |
| Directory | /workspace/52.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.922370596 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 1119828774 ps |
| CPU time | 96.43 seconds |
| Started | Feb 07 04:18:10 PM PST 24 |
| Finished | Feb 07 04:19:47 PM PST 24 |
| Peak memory | 556480 kb |
| Host | smart-3c1a1264-f924-4e94-8807-7fc09da2201f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922370596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.922370596 |
| Directory | /workspace/52.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.1035413636 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 63699944 ps |
| CPU time | 24.34 seconds |
| Started | Feb 07 04:18:09 PM PST 24 |
| Finished | Feb 07 04:18:35 PM PST 24 |
| Peak memory | 555788 kb |
| Host | smart-4c97e4b2-9870-4ff7-865b-398ae30d0b10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035413636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all _with_rand_reset.1035413636 |
| Directory | /workspace/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.1851704721 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 83577067 ps |
| CPU time | 24.51 seconds |
| Started | Feb 07 04:18:09 PM PST 24 |
| Finished | Feb 07 04:18:35 PM PST 24 |
| Peak memory | 554180 kb |
| Host | smart-a3dd286c-ee00-43b9-82e4-e4deb01e1e53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851704721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_al l_with_reset_error.1851704721 |
| Directory | /workspace/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.3408214314 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 261295542 ps |
| CPU time | 28.55 seconds |
| Started | Feb 07 04:18:08 PM PST 24 |
| Finished | Feb 07 04:18:40 PM PST 24 |
| Peak memory | 555636 kb |
| Host | smart-dc8e2517-d360-4ac1-b38c-ef917b6b67af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408214314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.3408214314 |
| Directory | /workspace/52.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device.1252337862 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 1094177030 ps |
| CPU time | 47.04 seconds |
| Started | Feb 07 04:18:15 PM PST 24 |
| Finished | Feb 07 04:19:03 PM PST 24 |
| Peak memory | 555396 kb |
| Host | smart-19f6aa9d-2a51-4208-a4d4-5f51f1f40069 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252337862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device .1252337862 |
| Directory | /workspace/53.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.1310434851 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 46251870208 ps |
| CPU time | 877.26 seconds |
| Started | Feb 07 04:18:20 PM PST 24 |
| Finished | Feb 07 04:32:58 PM PST 24 |
| Peak memory | 556512 kb |
| Host | smart-ce8a8fa2-d362-45c2-8639-7d2e47db62fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310434851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_ device_slow_rsp.1310434851 |
| Directory | /workspace/53.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.3161885990 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 1284090508 ps |
| CPU time | 53.08 seconds |
| Started | Feb 07 04:18:16 PM PST 24 |
| Finished | Feb 07 04:19:09 PM PST 24 |
| Peak memory | 555404 kb |
| Host | smart-5f2cbd29-6cfd-4ac6-8388-b11033348bfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161885990 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_add r.3161885990 |
| Directory | /workspace/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_random.2893456010 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 566749620 ps |
| CPU time | 40.53 seconds |
| Started | Feb 07 04:18:18 PM PST 24 |
| Finished | Feb 07 04:18:59 PM PST 24 |
| Peak memory | 555292 kb |
| Host | smart-85771a00-0243-49cb-a3e2-c2e638aab433 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893456010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.2893456010 |
| Directory | /workspace/53.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random.659811682 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 1624271469 ps |
| CPU time | 61.41 seconds |
| Started | Feb 07 04:18:05 PM PST 24 |
| Finished | Feb 07 04:19:08 PM PST 24 |
| Peak memory | 555232 kb |
| Host | smart-0969af3f-6e75-4eb6-9f65-fc5ecea6f3f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659811682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.659811682 |
| Directory | /workspace/53.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.4158113637 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 59883795863 ps |
| CPU time | 713.58 seconds |
| Started | Feb 07 04:18:05 PM PST 24 |
| Finished | Feb 07 04:30:00 PM PST 24 |
| Peak memory | 555724 kb |
| Host | smart-3a0dff23-b7d5-4de9-bd21-99b2b9a16a26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158113637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.4158113637 |
| Directory | /workspace/53.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.4198073531 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 61104815959 ps |
| CPU time | 1150.38 seconds |
| Started | Feb 07 04:18:09 PM PST 24 |
| Finished | Feb 07 04:37:21 PM PST 24 |
| Peak memory | 555740 kb |
| Host | smart-43965ec8-db0c-45ee-9e75-50d60648f4db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198073531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.4198073531 |
| Directory | /workspace/53.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.2552968129 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 234989454 ps |
| CPU time | 19.28 seconds |
| Started | Feb 07 04:18:09 PM PST 24 |
| Finished | Feb 07 04:18:30 PM PST 24 |
| Peak memory | 555408 kb |
| Host | smart-ae26f42e-8fb6-4c30-ae9c-ec32b44479fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552968129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_del ays.2552968129 |
| Directory | /workspace/53.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_same_source.322460410 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 108461526 ps |
| CPU time | 11.28 seconds |
| Started | Feb 07 04:18:14 PM PST 24 |
| Finished | Feb 07 04:18:26 PM PST 24 |
| Peak memory | 555328 kb |
| Host | smart-c7c2cddd-afa2-46d6-bb12-695c2e26503e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322460410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.322460410 |
| Directory | /workspace/53.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke.2215228417 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 43747881 ps |
| CPU time | 5.89 seconds |
| Started | Feb 07 04:18:08 PM PST 24 |
| Finished | Feb 07 04:18:17 PM PST 24 |
| Peak memory | 553228 kb |
| Host | smart-f2fd13f5-d182-4a49-93dd-9ca997d2a35c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215228417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.2215228417 |
| Directory | /workspace/53.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.165027840 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 7545393583 ps |
| CPU time | 76.38 seconds |
| Started | Feb 07 04:18:09 PM PST 24 |
| Finished | Feb 07 04:19:28 PM PST 24 |
| Peak memory | 559168 kb |
| Host | smart-d709b877-313a-4776-a60c-b730223bdfe1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165027840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.165027840 |
| Directory | /workspace/53.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.1294886560 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 5096456775 ps |
| CPU time | 86.84 seconds |
| Started | Feb 07 04:18:08 PM PST 24 |
| Finished | Feb 07 04:19:38 PM PST 24 |
| Peak memory | 553676 kb |
| Host | smart-068b3c81-1a59-403c-a45a-16c9f8927964 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294886560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.1294886560 |
| Directory | /workspace/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.399804408 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 42937250 ps |
| CPU time | 5.93 seconds |
| Started | Feb 07 04:18:11 PM PST 24 |
| Finished | Feb 07 04:18:18 PM PST 24 |
| Peak memory | 553580 kb |
| Host | smart-ce89cff8-975f-4052-953a-5f9c965d647e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399804408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delays .399804408 |
| Directory | /workspace/53.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all.1871275719 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 9266997308 ps |
| CPU time | 381.6 seconds |
| Started | Feb 07 04:18:19 PM PST 24 |
| Finished | Feb 07 04:24:41 PM PST 24 |
| Peak memory | 556652 kb |
| Host | smart-7e215b4e-1379-44ba-9d88-7bda191fa62b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871275719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.1871275719 |
| Directory | /workspace/53.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.541183516 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 1604972567 ps |
| CPU time | 94.52 seconds |
| Started | Feb 07 04:18:13 PM PST 24 |
| Finished | Feb 07 04:19:49 PM PST 24 |
| Peak memory | 556472 kb |
| Host | smart-5c1eca4e-c703-4815-a663-fc1d22839d24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541183516 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.541183516 |
| Directory | /workspace/53.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.610478613 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 670662413 ps |
| CPU time | 285.17 seconds |
| Started | Feb 07 04:18:13 PM PST 24 |
| Finished | Feb 07 04:23:00 PM PST 24 |
| Peak memory | 557192 kb |
| Host | smart-18029d0a-3437-4d8b-820e-1ea379f6aa8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610478613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_ with_rand_reset.610478613 |
| Directory | /workspace/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.496664871 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 6612995063 ps |
| CPU time | 669.39 seconds |
| Started | Feb 07 04:18:15 PM PST 24 |
| Finished | Feb 07 04:29:25 PM PST 24 |
| Peak memory | 559436 kb |
| Host | smart-7250e0f1-ac62-4df7-9094-6b7ee25f7b13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496664871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_reset_error.496664871 |
| Directory | /workspace/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.2264477370 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 1079659186 ps |
| CPU time | 42.42 seconds |
| Started | Feb 07 04:18:18 PM PST 24 |
| Finished | Feb 07 04:19:01 PM PST 24 |
| Peak memory | 555712 kb |
| Host | smart-8768d88d-c61c-4fe2-b346-ba307a5a31b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264477370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.2264477370 |
| Directory | /workspace/53.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device.322500264 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 245300917 ps |
| CPU time | 10.34 seconds |
| Started | Feb 07 04:18:29 PM PST 24 |
| Finished | Feb 07 04:18:40 PM PST 24 |
| Peak memory | 553612 kb |
| Host | smart-600045c0-e58a-4e60-a124-476e96032e2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322500264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device. 322500264 |
| Directory | /workspace/54.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.1944854864 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 63449028760 ps |
| CPU time | 1256.22 seconds |
| Started | Feb 07 04:18:34 PM PST 24 |
| Finished | Feb 07 04:39:30 PM PST 24 |
| Peak memory | 556820 kb |
| Host | smart-467895ae-5f3a-4597-ba49-defc28143bd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944854864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_ device_slow_rsp.1944854864 |
| Directory | /workspace/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.109919379 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 229203819 ps |
| CPU time | 13.37 seconds |
| Started | Feb 07 04:18:24 PM PST 24 |
| Finished | Feb 07 04:18:37 PM PST 24 |
| Peak memory | 555600 kb |
| Host | smart-3ba0a1c7-7a6e-4fba-909a-1111e98f642c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109919379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_addr .109919379 |
| Directory | /workspace/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_random.2500095743 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 36728957 ps |
| CPU time | 5.91 seconds |
| Started | Feb 07 04:18:31 PM PST 24 |
| Finished | Feb 07 04:18:37 PM PST 24 |
| Peak memory | 553564 kb |
| Host | smart-aebb4041-2dbc-44bc-85aa-3b138287af21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500095743 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.2500095743 |
| Directory | /workspace/54.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random.326690366 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 508428867 ps |
| CPU time | 39.69 seconds |
| Started | Feb 07 04:18:32 PM PST 24 |
| Finished | Feb 07 04:19:12 PM PST 24 |
| Peak memory | 555372 kb |
| Host | smart-f3ab4fa9-1ab0-441a-bf80-03f7ade473ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326690366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.326690366 |
| Directory | /workspace/54.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.2065807736 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 23470445832 ps |
| CPU time | 279.05 seconds |
| Started | Feb 07 04:18:28 PM PST 24 |
| Finished | Feb 07 04:23:07 PM PST 24 |
| Peak memory | 555036 kb |
| Host | smart-d5a975c8-0dc6-43cb-a23e-9ab964ab6127 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065807736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.2065807736 |
| Directory | /workspace/54.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.167418515 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 30292636644 ps |
| CPU time | 561.08 seconds |
| Started | Feb 07 04:18:30 PM PST 24 |
| Finished | Feb 07 04:27:52 PM PST 24 |
| Peak memory | 555424 kb |
| Host | smart-49dc8181-595f-4a29-b485-f6a727a3a229 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167418515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.167418515 |
| Directory | /workspace/54.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.3854305114 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 36264295 ps |
| CPU time | 6.22 seconds |
| Started | Feb 07 04:18:32 PM PST 24 |
| Finished | Feb 07 04:18:39 PM PST 24 |
| Peak memory | 553396 kb |
| Host | smart-c8ff619e-c8e2-4128-8b9c-144bc3591052 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854305114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_del ays.3854305114 |
| Directory | /workspace/54.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_same_source.1146578194 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 116956582 ps |
| CPU time | 10.78 seconds |
| Started | Feb 07 04:18:35 PM PST 24 |
| Finished | Feb 07 04:18:46 PM PST 24 |
| Peak memory | 555652 kb |
| Host | smart-05465881-a9b8-4058-a4ec-925c70e4410f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146578194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.1146578194 |
| Directory | /workspace/54.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke.3522833016 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 207455317 ps |
| CPU time | 9.03 seconds |
| Started | Feb 07 04:18:15 PM PST 24 |
| Finished | Feb 07 04:18:25 PM PST 24 |
| Peak memory | 553596 kb |
| Host | smart-b67e760e-4df7-4301-8293-d75463325dae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522833016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.3522833016 |
| Directory | /workspace/54.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.654624487 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 9096237353 ps |
| CPU time | 95.92 seconds |
| Started | Feb 07 04:18:24 PM PST 24 |
| Finished | Feb 07 04:20:01 PM PST 24 |
| Peak memory | 553648 kb |
| Host | smart-7f2aa9b7-622f-48c6-81db-101182569856 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654624487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.654624487 |
| Directory | /workspace/54.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.808594433 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 6786039775 ps |
| CPU time | 111.76 seconds |
| Started | Feb 07 04:18:23 PM PST 24 |
| Finished | Feb 07 04:20:15 PM PST 24 |
| Peak memory | 553332 kb |
| Host | smart-14c741f0-aded-4a47-82fa-8c98baa824aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808594433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.808594433 |
| Directory | /workspace/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.3240033294 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 46786126 ps |
| CPU time | 6.09 seconds |
| Started | Feb 07 04:18:32 PM PST 24 |
| Finished | Feb 07 04:18:39 PM PST 24 |
| Peak memory | 553012 kb |
| Host | smart-7522b38e-114f-4f21-b690-3c2557e60db2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240033294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delay s.3240033294 |
| Directory | /workspace/54.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all.3250628684 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 2373873959 ps |
| CPU time | 73.12 seconds |
| Started | Feb 07 04:18:33 PM PST 24 |
| Finished | Feb 07 04:19:46 PM PST 24 |
| Peak memory | 555476 kb |
| Host | smart-cacdea59-9120-480f-8198-2a17b274bacf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250628684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.3250628684 |
| Directory | /workspace/54.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.3259332527 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 1958087540 ps |
| CPU time | 186.81 seconds |
| Started | Feb 07 04:18:30 PM PST 24 |
| Finished | Feb 07 04:21:37 PM PST 24 |
| Peak memory | 556560 kb |
| Host | smart-366288bb-36e2-4156-8a4d-05a9281b4d0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259332527 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.3259332527 |
| Directory | /workspace/54.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.221548653 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 345232770 ps |
| CPU time | 123.66 seconds |
| Started | Feb 07 04:18:29 PM PST 24 |
| Finished | Feb 07 04:20:33 PM PST 24 |
| Peak memory | 556636 kb |
| Host | smart-5e424d33-8719-47d0-8365-cd361028bab5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221548653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_ with_rand_reset.221548653 |
| Directory | /workspace/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.1539273951 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 581938948 ps |
| CPU time | 188.41 seconds |
| Started | Feb 07 04:18:25 PM PST 24 |
| Finished | Feb 07 04:21:34 PM PST 24 |
| Peak memory | 559348 kb |
| Host | smart-7051f9b8-8ef1-4d13-b900-9936f1e07632 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539273951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_al l_with_reset_error.1539273951 |
| Directory | /workspace/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.768293323 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 259349636 ps |
| CPU time | 29.97 seconds |
| Started | Feb 07 04:18:29 PM PST 24 |
| Finished | Feb 07 04:19:00 PM PST 24 |
| Peak memory | 555424 kb |
| Host | smart-d2b1eaa8-383f-428e-9972-bf663f827937 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768293323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.768293323 |
| Directory | /workspace/54.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device.581418554 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 555436643 ps |
| CPU time | 22.62 seconds |
| Started | Feb 07 04:18:36 PM PST 24 |
| Finished | Feb 07 04:18:59 PM PST 24 |
| Peak memory | 554616 kb |
| Host | smart-b0e91ee2-504a-49b5-adad-3083db85c2f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581418554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device. 581418554 |
| Directory | /workspace/55.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.1662228074 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 72998886087 ps |
| CPU time | 1306.14 seconds |
| Started | Feb 07 04:18:37 PM PST 24 |
| Finished | Feb 07 04:40:23 PM PST 24 |
| Peak memory | 555192 kb |
| Host | smart-56229bd8-94cd-454b-b61e-05e59c979b46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662228074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_ device_slow_rsp.1662228074 |
| Directory | /workspace/55.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.1659186953 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 758705273 ps |
| CPU time | 29.63 seconds |
| Started | Feb 07 04:18:30 PM PST 24 |
| Finished | Feb 07 04:19:00 PM PST 24 |
| Peak memory | 555592 kb |
| Host | smart-f11d9821-cbcb-4eab-b527-c9f213430e66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659186953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_add r.1659186953 |
| Directory | /workspace/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_random.1062329508 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 2030192858 ps |
| CPU time | 61.8 seconds |
| Started | Feb 07 04:18:30 PM PST 24 |
| Finished | Feb 07 04:19:33 PM PST 24 |
| Peak memory | 555408 kb |
| Host | smart-6472d28b-4d20-4c27-b633-0d96082491f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062329508 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.1062329508 |
| Directory | /workspace/55.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random.3992287067 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 720553189 ps |
| CPU time | 28.38 seconds |
| Started | Feb 07 04:18:32 PM PST 24 |
| Finished | Feb 07 04:19:00 PM PST 24 |
| Peak memory | 555376 kb |
| Host | smart-88abfc6b-35bd-4185-80f2-bd0076126b1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992287067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.3992287067 |
| Directory | /workspace/55.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.242718385 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 97868388419 ps |
| CPU time | 1101.09 seconds |
| Started | Feb 07 04:18:35 PM PST 24 |
| Finished | Feb 07 04:36:57 PM PST 24 |
| Peak memory | 555388 kb |
| Host | smart-b0c4184b-f4b6-48ea-b2ee-d408d3e8f587 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242718385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.242718385 |
| Directory | /workspace/55.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.2272378522 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 7914424656 ps |
| CPU time | 141.48 seconds |
| Started | Feb 07 04:18:33 PM PST 24 |
| Finished | Feb 07 04:20:55 PM PST 24 |
| Peak memory | 554708 kb |
| Host | smart-b67f2153-b979-40d1-9784-6c111ff1be2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272378522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.2272378522 |
| Directory | /workspace/55.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.3306880442 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 486610521 ps |
| CPU time | 40.76 seconds |
| Started | Feb 07 04:18:32 PM PST 24 |
| Finished | Feb 07 04:19:13 PM PST 24 |
| Peak memory | 559172 kb |
| Host | smart-7034a26b-9225-4bbc-b3f0-3efc6e41c4db |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306880442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_del ays.3306880442 |
| Directory | /workspace/55.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_same_source.1644478637 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 280545528 ps |
| CPU time | 21.49 seconds |
| Started | Feb 07 04:18:31 PM PST 24 |
| Finished | Feb 07 04:18:53 PM PST 24 |
| Peak memory | 555116 kb |
| Host | smart-a12cd5f3-58e9-4ce3-8ef8-fbb65001db3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644478637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.1644478637 |
| Directory | /workspace/55.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke.17195446 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 36513377 ps |
| CPU time | 6.19 seconds |
| Started | Feb 07 04:18:25 PM PST 24 |
| Finished | Feb 07 04:18:32 PM PST 24 |
| Peak memory | 553284 kb |
| Host | smart-2df69593-fdd2-4b9d-b610-359274bb783f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17195446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.17195446 |
| Directory | /workspace/55.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.568191840 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 9097340357 ps |
| CPU time | 97.61 seconds |
| Started | Feb 07 04:18:34 PM PST 24 |
| Finished | Feb 07 04:20:12 PM PST 24 |
| Peak memory | 553336 kb |
| Host | smart-baa909a5-47e0-43c1-9a69-bb2ae29de262 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568191840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.568191840 |
| Directory | /workspace/55.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.4017877672 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 5512331257 ps |
| CPU time | 95.75 seconds |
| Started | Feb 07 04:18:24 PM PST 24 |
| Finished | Feb 07 04:20:00 PM PST 24 |
| Peak memory | 553704 kb |
| Host | smart-a8ca44a9-713d-4442-9da1-35e997b449a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017877672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.4017877672 |
| Directory | /workspace/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.2063134924 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 40432804 ps |
| CPU time | 5.89 seconds |
| Started | Feb 07 04:18:29 PM PST 24 |
| Finished | Feb 07 04:18:36 PM PST 24 |
| Peak memory | 553276 kb |
| Host | smart-136abcfc-d4fa-422a-bf00-004404e5ebce |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063134924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delay s.2063134924 |
| Directory | /workspace/55.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all.2828449416 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 2394082639 ps |
| CPU time | 221.08 seconds |
| Started | Feb 07 04:18:33 PM PST 24 |
| Finished | Feb 07 04:22:15 PM PST 24 |
| Peak memory | 556284 kb |
| Host | smart-aa543f0e-3967-4d56-8dce-a89ae9315f27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828449416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.2828449416 |
| Directory | /workspace/55.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.4063519457 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 399516868 ps |
| CPU time | 202.16 seconds |
| Started | Feb 07 04:18:31 PM PST 24 |
| Finished | Feb 07 04:21:54 PM PST 24 |
| Peak memory | 556880 kb |
| Host | smart-60b199f8-e09e-4eae-8894-7a46452e5302 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063519457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_rand_reset.4063519457 |
| Directory | /workspace/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.34674536 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 322306734 ps |
| CPU time | 39.33 seconds |
| Started | Feb 07 04:18:31 PM PST 24 |
| Finished | Feb 07 04:19:11 PM PST 24 |
| Peak memory | 555416 kb |
| Host | smart-3c7af501-495f-4128-b6da-b0809ade967f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34674536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.34674536 |
| Directory | /workspace/55.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device.2235632760 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 883941919 ps |
| CPU time | 43.61 seconds |
| Started | Feb 07 04:18:40 PM PST 24 |
| Finished | Feb 07 04:19:24 PM PST 24 |
| Peak memory | 555332 kb |
| Host | smart-4828d68f-d6f8-4840-97c0-fc29837561ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235632760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device .2235632760 |
| Directory | /workspace/56.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.1978135632 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 140598496115 ps |
| CPU time | 2355.44 seconds |
| Started | Feb 07 04:18:42 PM PST 24 |
| Finished | Feb 07 04:57:59 PM PST 24 |
| Peak memory | 555204 kb |
| Host | smart-4dadc31a-a0a0-4b72-b561-e33761c11671 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978135632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_ device_slow_rsp.1978135632 |
| Directory | /workspace/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.4241262280 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 1061101301 ps |
| CPU time | 44.68 seconds |
| Started | Feb 07 04:18:39 PM PST 24 |
| Finished | Feb 07 04:19:24 PM PST 24 |
| Peak memory | 555108 kb |
| Host | smart-1da1148c-3cb1-4375-b4a1-a5311721fa70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241262280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_add r.4241262280 |
| Directory | /workspace/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_random.3710546896 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 312433763 ps |
| CPU time | 28.19 seconds |
| Started | Feb 07 04:18:42 PM PST 24 |
| Finished | Feb 07 04:19:11 PM PST 24 |
| Peak memory | 555636 kb |
| Host | smart-0cbb7005-b66d-4785-9680-acb3320be98e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710546896 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.3710546896 |
| Directory | /workspace/56.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random.2569391009 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 601125139 ps |
| CPU time | 55.39 seconds |
| Started | Feb 07 04:18:41 PM PST 24 |
| Finished | Feb 07 04:19:37 PM PST 24 |
| Peak memory | 555392 kb |
| Host | smart-03ddd3df-1eb9-49c5-9240-f84acd0e1ccb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569391009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.2569391009 |
| Directory | /workspace/56.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.3460063611 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 64809434216 ps |
| CPU time | 709.6 seconds |
| Started | Feb 07 04:18:42 PM PST 24 |
| Finished | Feb 07 04:30:32 PM PST 24 |
| Peak memory | 555184 kb |
| Host | smart-a7141288-e078-4f26-bfe8-346548489f32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460063611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.3460063611 |
| Directory | /workspace/56.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.3131027723 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 24232927313 ps |
| CPU time | 433.31 seconds |
| Started | Feb 07 04:18:40 PM PST 24 |
| Finished | Feb 07 04:25:54 PM PST 24 |
| Peak memory | 555036 kb |
| Host | smart-23cde24b-456b-4ab5-ad21-54e938d3fefc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131027723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.3131027723 |
| Directory | /workspace/56.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.3805743255 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 287756051 ps |
| CPU time | 29.35 seconds |
| Started | Feb 07 04:18:40 PM PST 24 |
| Finished | Feb 07 04:19:10 PM PST 24 |
| Peak memory | 555688 kb |
| Host | smart-b10df596-af5a-4ced-80c6-ba36c722a23d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805743255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_del ays.3805743255 |
| Directory | /workspace/56.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_same_source.3377826720 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 1352393891 ps |
| CPU time | 38.98 seconds |
| Started | Feb 07 04:18:47 PM PST 24 |
| Finished | Feb 07 04:19:26 PM PST 24 |
| Peak memory | 555124 kb |
| Host | smart-d4a9ac50-2b24-4af9-b304-6ecfe3400e29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377826720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.3377826720 |
| Directory | /workspace/56.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke.2870558028 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 52996535 ps |
| CPU time | 6.65 seconds |
| Started | Feb 07 04:18:42 PM PST 24 |
| Finished | Feb 07 04:18:49 PM PST 24 |
| Peak memory | 553280 kb |
| Host | smart-dea0602f-a822-44a1-a11d-e8ab52080ad4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870558028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.2870558028 |
| Directory | /workspace/56.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.663457001 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 9265714602 ps |
| CPU time | 97.6 seconds |
| Started | Feb 07 04:18:42 PM PST 24 |
| Finished | Feb 07 04:20:21 PM PST 24 |
| Peak memory | 553336 kb |
| Host | smart-66cd045f-f83f-43e7-8e4d-cba50724c885 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663457001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.663457001 |
| Directory | /workspace/56.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.2554340191 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 4121550831 ps |
| CPU time | 74.97 seconds |
| Started | Feb 07 04:18:34 PM PST 24 |
| Finished | Feb 07 04:19:50 PM PST 24 |
| Peak memory | 553364 kb |
| Host | smart-59974994-cf90-483c-b8b9-e2327ff6ba02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554340191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.2554340191 |
| Directory | /workspace/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.4053429035 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 43055461 ps |
| CPU time | 6.06 seconds |
| Started | Feb 07 04:18:37 PM PST 24 |
| Finished | Feb 07 04:18:44 PM PST 24 |
| Peak memory | 553280 kb |
| Host | smart-81858787-adba-4418-b383-f21f70f918bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053429035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delay s.4053429035 |
| Directory | /workspace/56.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all.2911131475 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 296179314 ps |
| CPU time | 15.06 seconds |
| Started | Feb 07 04:18:38 PM PST 24 |
| Finished | Feb 07 04:18:53 PM PST 24 |
| Peak memory | 555624 kb |
| Host | smart-2bb5ed42-acfe-4780-a4de-1276447fce02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911131475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.2911131475 |
| Directory | /workspace/56.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.3633827630 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 6398525762 ps |
| CPU time | 270.74 seconds |
| Started | Feb 07 04:18:48 PM PST 24 |
| Finished | Feb 07 04:23:19 PM PST 24 |
| Peak memory | 556488 kb |
| Host | smart-97a69d3f-3706-45b1-bc1a-efc69b554e2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633827630 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.3633827630 |
| Directory | /workspace/56.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.1364522277 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 221104355 ps |
| CPU time | 148.48 seconds |
| Started | Feb 07 04:18:42 PM PST 24 |
| Finished | Feb 07 04:21:11 PM PST 24 |
| Peak memory | 556372 kb |
| Host | smart-f9540894-a804-4cbb-ab5e-b3ac27661fdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364522277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all _with_rand_reset.1364522277 |
| Directory | /workspace/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.4288436553 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 569813211 ps |
| CPU time | 214.88 seconds |
| Started | Feb 07 04:18:50 PM PST 24 |
| Finished | Feb 07 04:22:25 PM PST 24 |
| Peak memory | 559332 kb |
| Host | smart-b87249c3-93e6-42c7-b9b3-e734212d15b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288436553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_al l_with_reset_error.4288436553 |
| Directory | /workspace/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.3389299073 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 867117576 ps |
| CPU time | 36.2 seconds |
| Started | Feb 07 04:18:41 PM PST 24 |
| Finished | Feb 07 04:19:17 PM PST 24 |
| Peak memory | 555324 kb |
| Host | smart-e1e02c10-1155-491b-96b8-92b8426d97e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389299073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.3389299073 |
| Directory | /workspace/56.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device.3006610595 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 107579201 ps |
| CPU time | 9.86 seconds |
| Started | Feb 07 04:19:07 PM PST 24 |
| Finished | Feb 07 04:19:17 PM PST 24 |
| Peak memory | 553076 kb |
| Host | smart-2426f7b4-b7f7-4e06-b720-23c91ba3b1ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006610595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device .3006610595 |
| Directory | /workspace/57.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.3041076398 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 10543358584 ps |
| CPU time | 171.09 seconds |
| Started | Feb 07 04:18:55 PM PST 24 |
| Finished | Feb 07 04:21:47 PM PST 24 |
| Peak memory | 553104 kb |
| Host | smart-3d9f55c0-a0ae-48ea-8512-7caff76d482d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041076398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_ device_slow_rsp.3041076398 |
| Directory | /workspace/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.3915344169 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 70336630 ps |
| CPU time | 5.88 seconds |
| Started | Feb 07 04:18:55 PM PST 24 |
| Finished | Feb 07 04:19:02 PM PST 24 |
| Peak memory | 553532 kb |
| Host | smart-0c31fe5d-8dcc-4da4-aa05-8efeba652ed1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915344169 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_add r.3915344169 |
| Directory | /workspace/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_random.2165635977 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 296199318 ps |
| CPU time | 25.57 seconds |
| Started | Feb 07 04:18:52 PM PST 24 |
| Finished | Feb 07 04:19:18 PM PST 24 |
| Peak memory | 555580 kb |
| Host | smart-edd5884d-3821-4bce-bc01-c3f1eac07e57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165635977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.2165635977 |
| Directory | /workspace/57.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random.1114241055 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 82046239 ps |
| CPU time | 6.6 seconds |
| Started | Feb 07 04:19:07 PM PST 24 |
| Finished | Feb 07 04:19:15 PM PST 24 |
| Peak memory | 553464 kb |
| Host | smart-34bd9521-24b6-4bc7-95c1-ab20a5fcff28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114241055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.1114241055 |
| Directory | /workspace/57.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.2244281829 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 67040354268 ps |
| CPU time | 742.89 seconds |
| Started | Feb 07 04:18:51 PM PST 24 |
| Finished | Feb 07 04:31:14 PM PST 24 |
| Peak memory | 555708 kb |
| Host | smart-df848aa3-5288-4024-9ff0-f36984225217 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244281829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.2244281829 |
| Directory | /workspace/57.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.812884812 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 17132231115 ps |
| CPU time | 286.35 seconds |
| Started | Feb 07 04:18:55 PM PST 24 |
| Finished | Feb 07 04:23:42 PM PST 24 |
| Peak memory | 555392 kb |
| Host | smart-2d2321b1-0f52-4470-938c-7ed2de8552d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812884812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.812884812 |
| Directory | /workspace/57.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.3981164140 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 491865130 ps |
| CPU time | 40.32 seconds |
| Started | Feb 07 04:18:49 PM PST 24 |
| Finished | Feb 07 04:19:29 PM PST 24 |
| Peak memory | 555656 kb |
| Host | smart-75784f45-40a2-46b9-9138-bdf2e16f4571 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981164140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_del ays.3981164140 |
| Directory | /workspace/57.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_same_source.3324091551 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 2465997719 ps |
| CPU time | 75.71 seconds |
| Started | Feb 07 04:18:57 PM PST 24 |
| Finished | Feb 07 04:20:13 PM PST 24 |
| Peak memory | 555728 kb |
| Host | smart-cb98c6ab-39ee-4403-9b59-d39198136778 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324091551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.3324091551 |
| Directory | /workspace/57.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke.357306393 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 51592882 ps |
| CPU time | 6.49 seconds |
| Started | Feb 07 04:18:56 PM PST 24 |
| Finished | Feb 07 04:19:04 PM PST 24 |
| Peak memory | 553276 kb |
| Host | smart-331e353b-f299-40b5-9307-934ecd8dc19c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357306393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.357306393 |
| Directory | /workspace/57.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.150782893 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 8141641522 ps |
| CPU time | 88.58 seconds |
| Started | Feb 07 04:18:57 PM PST 24 |
| Finished | Feb 07 04:20:26 PM PST 24 |
| Peak memory | 553676 kb |
| Host | smart-5179145a-ca66-4c36-ab39-6f45a27e69d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150782893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.150782893 |
| Directory | /workspace/57.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.4021746935 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 4717360486 ps |
| CPU time | 77.48 seconds |
| Started | Feb 07 04:18:54 PM PST 24 |
| Finished | Feb 07 04:20:11 PM PST 24 |
| Peak memory | 553656 kb |
| Host | smart-6a7a0fb4-3be8-4190-bcd1-9227900933cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021746935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.4021746935 |
| Directory | /workspace/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.305032409 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 42720774 ps |
| CPU time | 5.95 seconds |
| Started | Feb 07 04:18:56 PM PST 24 |
| Finished | Feb 07 04:19:03 PM PST 24 |
| Peak memory | 553256 kb |
| Host | smart-2dc986cb-4cdf-47da-ae9f-e50f6febebde |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305032409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delays .305032409 |
| Directory | /workspace/57.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all.3063665739 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 2558133568 ps |
| CPU time | 217.94 seconds |
| Started | Feb 07 04:18:49 PM PST 24 |
| Finished | Feb 07 04:22:28 PM PST 24 |
| Peak memory | 556600 kb |
| Host | smart-9a85bbc0-87aa-4776-9646-7d4b984f7788 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063665739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.3063665739 |
| Directory | /workspace/57.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.2225317628 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 6920844709 ps |
| CPU time | 288.86 seconds |
| Started | Feb 07 04:18:50 PM PST 24 |
| Finished | Feb 07 04:23:39 PM PST 24 |
| Peak memory | 557588 kb |
| Host | smart-88a0dc13-6973-40ff-bff5-b62c1bc9a429 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225317628 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.2225317628 |
| Directory | /workspace/57.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.1223571448 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 2380771541 ps |
| CPU time | 419.99 seconds |
| Started | Feb 07 04:18:52 PM PST 24 |
| Finished | Feb 07 04:25:52 PM PST 24 |
| Peak memory | 559336 kb |
| Host | smart-66bd153a-c938-4ff2-907f-f293fc8d7336 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223571448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_rand_reset.1223571448 |
| Directory | /workspace/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.4176255064 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 3665254659 ps |
| CPU time | 360.4 seconds |
| Started | Feb 07 04:18:53 PM PST 24 |
| Finished | Feb 07 04:24:54 PM PST 24 |
| Peak memory | 567620 kb |
| Host | smart-7ced00d3-d6ab-4220-820a-e2993d108176 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176255064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_al l_with_reset_error.4176255064 |
| Directory | /workspace/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.960857556 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 322292587 ps |
| CPU time | 38.43 seconds |
| Started | Feb 07 04:18:44 PM PST 24 |
| Finished | Feb 07 04:19:23 PM PST 24 |
| Peak memory | 555680 kb |
| Host | smart-0c2f5cf2-170b-40f2-ab57-a80ae37e76e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960857556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.960857556 |
| Directory | /workspace/57.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device.1134777901 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 1745171459 ps |
| CPU time | 74.92 seconds |
| Started | Feb 07 04:19:07 PM PST 24 |
| Finished | Feb 07 04:20:22 PM PST 24 |
| Peak memory | 555344 kb |
| Host | smart-a116c615-4612-4e91-8723-7d5ad69d3b38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134777901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device .1134777901 |
| Directory | /workspace/58.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.3179843286 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 106370444107 ps |
| CPU time | 1836.99 seconds |
| Started | Feb 07 04:19:07 PM PST 24 |
| Finished | Feb 07 04:49:45 PM PST 24 |
| Peak memory | 556724 kb |
| Host | smart-67164650-d20b-4efc-bc80-779a2d653681 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179843286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_ device_slow_rsp.3179843286 |
| Directory | /workspace/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.1423350904 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 1164904926 ps |
| CPU time | 49.46 seconds |
| Started | Feb 07 04:18:59 PM PST 24 |
| Finished | Feb 07 04:19:49 PM PST 24 |
| Peak memory | 555644 kb |
| Host | smart-aa7ce52c-3721-4b8c-9e9d-1e72f78394c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423350904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_add r.1423350904 |
| Directory | /workspace/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_random.4130586389 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 439771182 ps |
| CPU time | 18.43 seconds |
| Started | Feb 07 04:19:00 PM PST 24 |
| Finished | Feb 07 04:19:19 PM PST 24 |
| Peak memory | 555648 kb |
| Host | smart-c573fb31-0f53-41dd-a07f-4a3d1b8ffc15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130586389 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.4130586389 |
| Directory | /workspace/58.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random.2351667381 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 228691167 ps |
| CPU time | 22.09 seconds |
| Started | Feb 07 04:18:54 PM PST 24 |
| Finished | Feb 07 04:19:18 PM PST 24 |
| Peak memory | 555456 kb |
| Host | smart-6744e357-bd9e-4d9a-923c-582e1f9b0364 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351667381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.2351667381 |
| Directory | /workspace/58.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.3868186786 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 22285228999 ps |
| CPU time | 256.08 seconds |
| Started | Feb 07 04:18:55 PM PST 24 |
| Finished | Feb 07 04:23:12 PM PST 24 |
| Peak memory | 555712 kb |
| Host | smart-0ce0eae0-9aa7-47eb-8e25-5a04f99b6ce6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868186786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.3868186786 |
| Directory | /workspace/58.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.2479631300 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 5625750578 ps |
| CPU time | 87.23 seconds |
| Started | Feb 07 04:20:15 PM PST 24 |
| Finished | Feb 07 04:21:44 PM PST 24 |
| Peak memory | 552468 kb |
| Host | smart-0537798f-e271-4a81-be7d-27d8b192c86d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479631300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.2479631300 |
| Directory | /workspace/58.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.2286471180 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 452035927 ps |
| CPU time | 36.32 seconds |
| Started | Feb 07 04:18:57 PM PST 24 |
| Finished | Feb 07 04:19:34 PM PST 24 |
| Peak memory | 555636 kb |
| Host | smart-5c86ca71-6817-4558-bfea-cdec2c8dcfcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286471180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_del ays.2286471180 |
| Directory | /workspace/58.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_same_source.2529915542 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 203179309 ps |
| CPU time | 18.57 seconds |
| Started | Feb 07 04:19:03 PM PST 24 |
| Finished | Feb 07 04:19:22 PM PST 24 |
| Peak memory | 555348 kb |
| Host | smart-c0f5a86f-d61f-4652-9771-718a81e24254 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529915542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.2529915542 |
| Directory | /workspace/58.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke.3878513295 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 208003061 ps |
| CPU time | 8.48 seconds |
| Started | Feb 07 04:18:57 PM PST 24 |
| Finished | Feb 07 04:19:06 PM PST 24 |
| Peak memory | 553580 kb |
| Host | smart-5f1ee94e-22ac-4af9-b72e-05df85c7c35c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878513295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.3878513295 |
| Directory | /workspace/58.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.573550331 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 4491395986 ps |
| CPU time | 46.87 seconds |
| Started | Feb 07 04:18:51 PM PST 24 |
| Finished | Feb 07 04:19:38 PM PST 24 |
| Peak memory | 553668 kb |
| Host | smart-9e21eab4-5e1f-4ddf-9ad2-a2bbc77f5cec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573550331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.573550331 |
| Directory | /workspace/58.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.694199129 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 5557617172 ps |
| CPU time | 93.41 seconds |
| Started | Feb 07 04:18:55 PM PST 24 |
| Finished | Feb 07 04:20:29 PM PST 24 |
| Peak memory | 553680 kb |
| Host | smart-893edff0-dc8d-4efb-a873-e6d144ee2a08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694199129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.694199129 |
| Directory | /workspace/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.1081881579 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 54957658 ps |
| CPU time | 7.22 seconds |
| Started | Feb 07 04:18:57 PM PST 24 |
| Finished | Feb 07 04:19:05 PM PST 24 |
| Peak memory | 553008 kb |
| Host | smart-d7967137-56f8-4fc9-ab02-eb741783f634 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081881579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delay s.1081881579 |
| Directory | /workspace/58.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all.1784817405 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 1234473230 ps |
| CPU time | 101.22 seconds |
| Started | Feb 07 04:19:01 PM PST 24 |
| Finished | Feb 07 04:20:42 PM PST 24 |
| Peak memory | 556540 kb |
| Host | smart-e67e89db-36a3-4059-be6d-68b578a27d22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784817405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.1784817405 |
| Directory | /workspace/58.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.925344936 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 1067524013 ps |
| CPU time | 469.9 seconds |
| Started | Feb 07 04:19:02 PM PST 24 |
| Finished | Feb 07 04:26:52 PM PST 24 |
| Peak memory | 559352 kb |
| Host | smart-0ed8fd47-49e9-42bb-827f-063cf813208e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925344936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_ with_rand_reset.925344936 |
| Directory | /workspace/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.1668413578 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 837242122 ps |
| CPU time | 241.55 seconds |
| Started | Feb 07 04:18:51 PM PST 24 |
| Finished | Feb 07 04:22:53 PM PST 24 |
| Peak memory | 559360 kb |
| Host | smart-d9d01b9b-19fa-41fe-8987-02f6686036ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668413578 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_al l_with_reset_error.1668413578 |
| Directory | /workspace/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.2629436050 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 1263474192 ps |
| CPU time | 56.06 seconds |
| Started | Feb 07 04:19:01 PM PST 24 |
| Finished | Feb 07 04:19:57 PM PST 24 |
| Peak memory | 555700 kb |
| Host | smart-93ecf4a2-1cf5-4976-b88b-91b39bad79fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629436050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.2629436050 |
| Directory | /workspace/58.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device.2289168551 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 2412009025 ps |
| CPU time | 103.31 seconds |
| Started | Feb 07 04:19:06 PM PST 24 |
| Finished | Feb 07 04:20:50 PM PST 24 |
| Peak memory | 555176 kb |
| Host | smart-2434c443-6a99-49c2-8585-4476f5fdc164 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289168551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device .2289168551 |
| Directory | /workspace/59.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.1838617959 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 390098073 ps |
| CPU time | 17.91 seconds |
| Started | Feb 07 04:19:07 PM PST 24 |
| Finished | Feb 07 04:19:26 PM PST 24 |
| Peak memory | 555344 kb |
| Host | smart-3595c2e7-78fa-4654-9652-f43ae2bbcf1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838617959 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_add r.1838617959 |
| Directory | /workspace/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_random.4229646459 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 323748627 ps |
| CPU time | 24.54 seconds |
| Started | Feb 07 04:19:11 PM PST 24 |
| Finished | Feb 07 04:19:36 PM PST 24 |
| Peak memory | 555584 kb |
| Host | smart-518b98d2-f268-445d-9cb6-4e773456b950 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229646459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.4229646459 |
| Directory | /workspace/59.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random.3389982195 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 2026248389 ps |
| CPU time | 79.74 seconds |
| Started | Feb 07 04:19:13 PM PST 24 |
| Finished | Feb 07 04:20:33 PM PST 24 |
| Peak memory | 555360 kb |
| Host | smart-93fcfdbd-ef1b-4de7-805d-eb519b3d3f52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389982195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.3389982195 |
| Directory | /workspace/59.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.4235629330 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 116340880411 ps |
| CPU time | 1361.62 seconds |
| Started | Feb 07 04:19:10 PM PST 24 |
| Finished | Feb 07 04:41:52 PM PST 24 |
| Peak memory | 555136 kb |
| Host | smart-8eef1589-fccb-493f-aeaa-2b8b31a6a487 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235629330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.4235629330 |
| Directory | /workspace/59.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.1901271669 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 6700687946 ps |
| CPU time | 129.43 seconds |
| Started | Feb 07 04:19:11 PM PST 24 |
| Finished | Feb 07 04:21:21 PM PST 24 |
| Peak memory | 559200 kb |
| Host | smart-b07dfb9f-9bcf-483e-a874-00edf3dceda3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901271669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.1901271669 |
| Directory | /workspace/59.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.3303302848 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 578284642 ps |
| CPU time | 51.15 seconds |
| Started | Feb 07 04:19:05 PM PST 24 |
| Finished | Feb 07 04:19:57 PM PST 24 |
| Peak memory | 555572 kb |
| Host | smart-711b89e7-5252-4f3d-93a4-af9be588c1ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303302848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_del ays.3303302848 |
| Directory | /workspace/59.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_same_source.3241590035 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 118500376 ps |
| CPU time | 10.74 seconds |
| Started | Feb 07 04:19:06 PM PST 24 |
| Finished | Feb 07 04:19:17 PM PST 24 |
| Peak memory | 555340 kb |
| Host | smart-670f1b14-c77b-465e-94b5-858cfb6315d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241590035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.3241590035 |
| Directory | /workspace/59.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke.976057131 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 40928646 ps |
| CPU time | 5.81 seconds |
| Started | Feb 07 04:19:06 PM PST 24 |
| Finished | Feb 07 04:19:12 PM PST 24 |
| Peak memory | 553588 kb |
| Host | smart-cc4b0b1d-a475-47b4-86c4-c05694fad9d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976057131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.976057131 |
| Directory | /workspace/59.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.3116562354 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 7863096071 ps |
| CPU time | 87.89 seconds |
| Started | Feb 07 04:19:08 PM PST 24 |
| Finished | Feb 07 04:20:36 PM PST 24 |
| Peak memory | 553068 kb |
| Host | smart-46701da9-fa1d-4a50-ae86-f8ee50995573 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116562354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.3116562354 |
| Directory | /workspace/59.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.1751619388 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 4216683384 ps |
| CPU time | 76.06 seconds |
| Started | Feb 07 04:19:08 PM PST 24 |
| Finished | Feb 07 04:20:24 PM PST 24 |
| Peak memory | 553672 kb |
| Host | smart-d49d93fd-0246-4608-9103-8b03cc85bccf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751619388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.1751619388 |
| Directory | /workspace/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.2707804832 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 55812727 ps |
| CPU time | 6.53 seconds |
| Started | Feb 07 04:19:05 PM PST 24 |
| Finished | Feb 07 04:19:12 PM PST 24 |
| Peak memory | 553280 kb |
| Host | smart-7b71b565-b129-4d11-a27b-0ddce223668c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707804832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay s.2707804832 |
| Directory | /workspace/59.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all.1753772228 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 3372594281 ps |
| CPU time | 313.44 seconds |
| Started | Feb 07 04:19:09 PM PST 24 |
| Finished | Feb 07 04:24:23 PM PST 24 |
| Peak memory | 556556 kb |
| Host | smart-01f532e0-1fe6-47ad-ac9c-dbd158437337 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753772228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.1753772228 |
| Directory | /workspace/59.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.2604780849 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 1761462027 ps |
| CPU time | 47.1 seconds |
| Started | Feb 07 04:19:06 PM PST 24 |
| Finished | Feb 07 04:19:53 PM PST 24 |
| Peak memory | 555320 kb |
| Host | smart-6bcfa233-343f-433b-b78a-af32cacc87f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604780849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.2604780849 |
| Directory | /workspace/59.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.178007639 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 27390592874 ps |
| CPU time | 1266.87 seconds |
| Started | Feb 07 04:19:08 PM PST 24 |
| Finished | Feb 07 04:40:16 PM PST 24 |
| Peak memory | 557956 kb |
| Host | smart-f81d6fc8-c68b-49a8-8f44-71828ed6c5fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178007639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_ with_rand_reset.178007639 |
| Directory | /workspace/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.2188401358 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 6192031397 ps |
| CPU time | 403.07 seconds |
| Started | Feb 07 04:19:15 PM PST 24 |
| Finished | Feb 07 04:25:59 PM PST 24 |
| Peak memory | 559440 kb |
| Host | smart-c9b04345-948d-4222-b0d2-4ee7463a290b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188401358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_al l_with_reset_error.2188401358 |
| Directory | /workspace/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.45563803 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 18562663 ps |
| CPU time | 5 seconds |
| Started | Feb 07 04:19:08 PM PST 24 |
| Finished | Feb 07 04:19:14 PM PST 24 |
| Peak memory | 559160 kb |
| Host | smart-00a08882-2f49-4629-8ace-5efa7bd456ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45563803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.45563803 |
| Directory | /workspace/59.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.2892803656 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 8624068820 ps |
| CPU time | 388.28 seconds |
| Started | Feb 07 04:11:52 PM PST 24 |
| Finished | Feb 07 04:18:21 PM PST 24 |
| Peak memory | 624308 kb |
| Host | smart-dfb2c145-7e78-415c-ad4e-33bd1a693a8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892803656 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 6.chip_csr_mem_rw_with_rand_reset.2892803656 |
| Directory | /workspace/6.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_rw.2544230152 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 5351838730 ps |
| CPU time | 552.99 seconds |
| Started | Feb 07 04:11:51 PM PST 24 |
| Finished | Feb 07 04:21:04 PM PST 24 |
| Peak memory | 580392 kb |
| Host | smart-0a9bd57c-9595-4b19-ae0f-64f07ceebe6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544230152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.2544230152 |
| Directory | /workspace/6.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.3516067681 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 15333052192 ps |
| CPU time | 2255.31 seconds |
| Started | Feb 07 04:11:45 PM PST 24 |
| Finished | Feb 07 04:49:21 PM PST 24 |
| Peak memory | 575508 kb |
| Host | smart-c8cce4f9-009e-40e0-8467-77a946e689ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516067681 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.chip_same_csr_outstanding.3516067681 |
| Directory | /workspace/6.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device.2207835640 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 921333155 ps |
| CPU time | 63.16 seconds |
| Started | Feb 07 04:11:54 PM PST 24 |
| Finished | Feb 07 04:12:57 PM PST 24 |
| Peak memory | 555496 kb |
| Host | smart-cded1e0f-b2e3-4d94-9199-db90f0051478 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207835640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device. 2207835640 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.747005192 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 109020640287 ps |
| CPU time | 1881.89 seconds |
| Started | Feb 07 04:11:54 PM PST 24 |
| Finished | Feb 07 04:43:17 PM PST 24 |
| Peak memory | 556876 kb |
| Host | smart-9f8af96e-d096-4f25-ad3e-fa10a6d48a95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747005192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_de vice_slow_rsp.747005192 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.86235183 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 385285404 ps |
| CPU time | 16.47 seconds |
| Started | Feb 07 04:11:53 PM PST 24 |
| Finished | Feb 07 04:12:10 PM PST 24 |
| Peak memory | 555596 kb |
| Host | smart-0bda3631-9018-4cd4-892f-572cc0603f53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86235183 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.86235183 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_random.1050815498 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 2769509056 ps |
| CPU time | 93.69 seconds |
| Started | Feb 07 04:11:51 PM PST 24 |
| Finished | Feb 07 04:13:26 PM PST 24 |
| Peak memory | 555412 kb |
| Host | smart-d57d223a-c499-45d4-bcae-ea517a019b8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050815498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1050815498 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random.979896710 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 387199555 ps |
| CPU time | 33.77 seconds |
| Started | Feb 07 04:11:53 PM PST 24 |
| Finished | Feb 07 04:12:27 PM PST 24 |
| Peak memory | 555340 kb |
| Host | smart-5845edef-629b-4681-b54c-8ad363478f6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979896710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.979896710 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.487510312 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 51128260555 ps |
| CPU time | 472.1 seconds |
| Started | Feb 07 04:11:53 PM PST 24 |
| Finished | Feb 07 04:19:46 PM PST 24 |
| Peak memory | 555716 kb |
| Host | smart-a9da5276-d722-451d-b4e7-ac113fe87889 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487510312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.487510312 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.3276724605 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 36309953412 ps |
| CPU time | 557.85 seconds |
| Started | Feb 07 04:11:50 PM PST 24 |
| Finished | Feb 07 04:21:08 PM PST 24 |
| Peak memory | 555600 kb |
| Host | smart-516e312a-f9cb-4261-a308-e4b8944e0864 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276724605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.3276724605 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.1526953060 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 41621181 ps |
| CPU time | 6.5 seconds |
| Started | Feb 07 04:11:47 PM PST 24 |
| Finished | Feb 07 04:11:54 PM PST 24 |
| Peak memory | 553300 kb |
| Host | smart-72e60e1f-ecca-4839-9f90-b1a3fa042879 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526953060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_dela ys.1526953060 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_same_source.3008493505 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 371862896 ps |
| CPU time | 26.79 seconds |
| Started | Feb 07 04:11:53 PM PST 24 |
| Finished | Feb 07 04:12:20 PM PST 24 |
| Peak memory | 555324 kb |
| Host | smart-f74d91ac-051b-495e-990c-36f99b9ff671 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008493505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3008493505 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke.4247521286 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 203838884 ps |
| CPU time | 8.13 seconds |
| Started | Feb 07 04:11:48 PM PST 24 |
| Finished | Feb 07 04:11:57 PM PST 24 |
| Peak memory | 553316 kb |
| Host | smart-578382a3-1dd3-4f9c-ae8d-75a3dca4f025 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247521286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.4247521286 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.3015698778 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 8637809658 ps |
| CPU time | 89.45 seconds |
| Started | Feb 07 04:11:51 PM PST 24 |
| Finished | Feb 07 04:13:21 PM PST 24 |
| Peak memory | 553416 kb |
| Host | smart-d54d8639-b608-4a2c-b7f7-a34c84831d51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015698778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3015698778 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.1507177935 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 4244870610 ps |
| CPU time | 66.29 seconds |
| Started | Feb 07 04:11:53 PM PST 24 |
| Finished | Feb 07 04:13:00 PM PST 24 |
| Peak memory | 553100 kb |
| Host | smart-997292de-6e4e-41e8-b997-7447932e29ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507177935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1507177935 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.1011111256 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 40465588 ps |
| CPU time | 5.8 seconds |
| Started | Feb 07 04:11:47 PM PST 24 |
| Finished | Feb 07 04:11:54 PM PST 24 |
| Peak memory | 553264 kb |
| Host | smart-d526294f-445b-4ee7-a709-0bbc594e8cc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011111256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays .1011111256 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all.2860360331 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 2415577342 ps |
| CPU time | 184.18 seconds |
| Started | Feb 07 04:11:54 PM PST 24 |
| Finished | Feb 07 04:14:59 PM PST 24 |
| Peak memory | 556636 kb |
| Host | smart-c234976a-9f87-4c84-bead-896cc2d7e27a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860360331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2860360331 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.3167433059 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 3608007992 ps |
| CPU time | 132.06 seconds |
| Started | Feb 07 04:11:51 PM PST 24 |
| Finished | Feb 07 04:14:03 PM PST 24 |
| Peak memory | 556316 kb |
| Host | smart-799821ac-e8c0-4d17-a3bc-c384a03950fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167433059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3167433059 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.3605543331 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 280122726 ps |
| CPU time | 77.8 seconds |
| Started | Feb 07 04:11:50 PM PST 24 |
| Finished | Feb 07 04:13:08 PM PST 24 |
| Peak memory | 556576 kb |
| Host | smart-186dfe63-9b50-44ab-90eb-5a39b6534a29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605543331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_ with_rand_reset.3605543331 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.1021032733 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 9188718666 ps |
| CPU time | 516.16 seconds |
| Started | Feb 07 04:11:51 PM PST 24 |
| Finished | Feb 07 04:20:28 PM PST 24 |
| Peak memory | 567636 kb |
| Host | smart-01261883-48be-49ae-aa81-1ffa336f892f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021032733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all _with_reset_error.1021032733 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.3116855781 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 289936374 ps |
| CPU time | 30.69 seconds |
| Started | Feb 07 04:11:53 PM PST 24 |
| Finished | Feb 07 04:12:25 PM PST 24 |
| Peak memory | 555424 kb |
| Host | smart-670dc55c-e412-4a89-b363-08b85f18ad3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116855781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3116855781 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.3015151079 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 491906135 ps |
| CPU time | 38.48 seconds |
| Started | Feb 07 04:19:17 PM PST 24 |
| Finished | Feb 07 04:19:56 PM PST 24 |
| Peak memory | 555672 kb |
| Host | smart-0ec6258c-96eb-4922-97b4-690b892648cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015151079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device .3015151079 |
| Directory | /workspace/60.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.1138460214 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 113384120 ps |
| CPU time | 12.72 seconds |
| Started | Feb 07 04:20:23 PM PST 24 |
| Finished | Feb 07 04:20:36 PM PST 24 |
| Peak memory | 555240 kb |
| Host | smart-1cef31ab-1a37-4423-bb47-855f642890a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138460214 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_add r.1138460214 |
| Directory | /workspace/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_random.3959767460 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 1802256496 ps |
| CPU time | 55.4 seconds |
| Started | Feb 07 04:20:23 PM PST 24 |
| Finished | Feb 07 04:21:19 PM PST 24 |
| Peak memory | 554980 kb |
| Host | smart-a8cee4bf-39e1-4479-a375-0c33736082b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959767460 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.3959767460 |
| Directory | /workspace/60.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random.3755154073 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 2485982249 ps |
| CPU time | 94.26 seconds |
| Started | Feb 07 04:19:16 PM PST 24 |
| Finished | Feb 07 04:20:51 PM PST 24 |
| Peak memory | 555672 kb |
| Host | smart-498c1ece-c55b-4ffe-be45-8919d93153a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755154073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.3755154073 |
| Directory | /workspace/60.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.3245232870 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 55765363926 ps |
| CPU time | 643.55 seconds |
| Started | Feb 07 04:19:18 PM PST 24 |
| Finished | Feb 07 04:30:03 PM PST 24 |
| Peak memory | 555420 kb |
| Host | smart-c72ed25f-d240-468b-aaef-0cdf86522590 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245232870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.3245232870 |
| Directory | /workspace/60.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.1773393812 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 65592859421 ps |
| CPU time | 1245.17 seconds |
| Started | Feb 07 04:19:23 PM PST 24 |
| Finished | Feb 07 04:40:09 PM PST 24 |
| Peak memory | 555748 kb |
| Host | smart-e1d9322a-ecd3-466b-a7c4-dca1362aae64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773393812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.1773393812 |
| Directory | /workspace/60.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.2372437286 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 440223098 ps |
| CPU time | 42.95 seconds |
| Started | Feb 07 04:19:16 PM PST 24 |
| Finished | Feb 07 04:19:59 PM PST 24 |
| Peak memory | 555632 kb |
| Host | smart-77203f98-06f1-450c-85d7-d1f3b51caf76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372437286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_del ays.2372437286 |
| Directory | /workspace/60.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_same_source.1843873863 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 487389365 ps |
| CPU time | 41.89 seconds |
| Started | Feb 07 04:19:13 PM PST 24 |
| Finished | Feb 07 04:19:56 PM PST 24 |
| Peak memory | 559168 kb |
| Host | smart-985c933d-979e-4c9e-af6f-199e1712d1b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843873863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.1843873863 |
| Directory | /workspace/60.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke.3315630049 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 41993177 ps |
| CPU time | 6.22 seconds |
| Started | Feb 07 04:19:16 PM PST 24 |
| Finished | Feb 07 04:19:22 PM PST 24 |
| Peak memory | 553300 kb |
| Host | smart-e999090a-222b-4d28-b857-d523ad0b8d29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315630049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.3315630049 |
| Directory | /workspace/60.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.3074508914 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 7020927575 ps |
| CPU time | 74.19 seconds |
| Started | Feb 07 04:19:16 PM PST 24 |
| Finished | Feb 07 04:20:31 PM PST 24 |
| Peak memory | 553308 kb |
| Host | smart-71d7f7ed-3082-4cca-a26b-83cebf81166f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074508914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.3074508914 |
| Directory | /workspace/60.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.3134683104 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 4918658199 ps |
| CPU time | 90.69 seconds |
| Started | Feb 07 04:19:14 PM PST 24 |
| Finished | Feb 07 04:20:46 PM PST 24 |
| Peak memory | 553392 kb |
| Host | smart-57849108-f86e-43ac-933b-12a7e2132be6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134683104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.3134683104 |
| Directory | /workspace/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.1710017794 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 49064535 ps |
| CPU time | 6.13 seconds |
| Started | Feb 07 04:19:14 PM PST 24 |
| Finished | Feb 07 04:19:20 PM PST 24 |
| Peak memory | 553592 kb |
| Host | smart-eec5b11f-f117-4068-9760-52bf6e3dc3e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710017794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay s.1710017794 |
| Directory | /workspace/60.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all.1129022820 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 449960937 ps |
| CPU time | 39.71 seconds |
| Started | Feb 07 04:19:28 PM PST 24 |
| Finished | Feb 07 04:20:11 PM PST 24 |
| Peak memory | 556524 kb |
| Host | smart-717de2e3-c0e0-4b9e-84d6-68986e355492 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129022820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.1129022820 |
| Directory | /workspace/60.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.1045555290 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 10950391352 ps |
| CPU time | 431.02 seconds |
| Started | Feb 07 04:19:17 PM PST 24 |
| Finished | Feb 07 04:26:29 PM PST 24 |
| Peak memory | 556896 kb |
| Host | smart-40fcf92a-ab95-4139-8c43-513595ae5578 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045555290 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.1045555290 |
| Directory | /workspace/60.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.128763673 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 4258160041 ps |
| CPU time | 654.15 seconds |
| Started | Feb 07 04:19:23 PM PST 24 |
| Finished | Feb 07 04:30:18 PM PST 24 |
| Peak memory | 559444 kb |
| Host | smart-478edca4-cd8f-4a56-94c6-2c24e3022be2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128763673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_ with_rand_reset.128763673 |
| Directory | /workspace/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.3219127076 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 192613528 ps |
| CPU time | 33.17 seconds |
| Started | Feb 07 04:19:17 PM PST 24 |
| Finished | Feb 07 04:19:51 PM PST 24 |
| Peak memory | 556648 kb |
| Host | smart-bf754b61-388c-452f-8966-6fa5209aa3b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219127076 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_al l_with_reset_error.3219127076 |
| Directory | /workspace/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.1842226550 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 42768846 ps |
| CPU time | 7.86 seconds |
| Started | Feb 07 04:19:15 PM PST 24 |
| Finished | Feb 07 04:19:23 PM PST 24 |
| Peak memory | 553088 kb |
| Host | smart-3861ecce-dc6c-4ca7-bbb3-9bb8021068e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842226550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.1842226550 |
| Directory | /workspace/60.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device.2230905788 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 509116256 ps |
| CPU time | 22.73 seconds |
| Started | Feb 07 04:19:21 PM PST 24 |
| Finished | Feb 07 04:19:44 PM PST 24 |
| Peak memory | 554608 kb |
| Host | smart-165a2a29-03c1-44d1-8aa8-dd6dd861d397 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230905788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device .2230905788 |
| Directory | /workspace/61.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.57115811 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 22775132802 ps |
| CPU time | 443.97 seconds |
| Started | Feb 07 04:19:15 PM PST 24 |
| Finished | Feb 07 04:26:40 PM PST 24 |
| Peak memory | 555800 kb |
| Host | smart-36cabb1a-b2f6-4efe-8f8b-70174a2ac3c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57115811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_de vice_slow_rsp.57115811 |
| Directory | /workspace/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.3333450173 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 150968077 ps |
| CPU time | 15.64 seconds |
| Started | Feb 07 04:19:16 PM PST 24 |
| Finished | Feb 07 04:19:33 PM PST 24 |
| Peak memory | 559128 kb |
| Host | smart-c86bf169-7ab4-4b22-9809-5a66b860b364 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333450173 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_add r.3333450173 |
| Directory | /workspace/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_random.323252621 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 273550137 ps |
| CPU time | 22.99 seconds |
| Started | Feb 07 04:19:17 PM PST 24 |
| Finished | Feb 07 04:19:41 PM PST 24 |
| Peak memory | 555608 kb |
| Host | smart-baf72fca-e5ac-47f7-b0e9-548220793478 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323252621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.323252621 |
| Directory | /workspace/61.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random.3941224102 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 456502941 ps |
| CPU time | 38.61 seconds |
| Started | Feb 07 04:20:22 PM PST 24 |
| Finished | Feb 07 04:21:02 PM PST 24 |
| Peak memory | 554996 kb |
| Host | smart-fcdae112-671b-441c-955c-5a2808edfdab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941224102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.3941224102 |
| Directory | /workspace/61.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.1614425249 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 12276977300 ps |
| CPU time | 135.56 seconds |
| Started | Feb 07 04:19:19 PM PST 24 |
| Finished | Feb 07 04:21:35 PM PST 24 |
| Peak memory | 554704 kb |
| Host | smart-89fd149b-8804-4881-bbbf-3a7a1d860ce3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614425249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.1614425249 |
| Directory | /workspace/61.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.723012765 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 16202973975 ps |
| CPU time | 296.67 seconds |
| Started | Feb 07 04:19:29 PM PST 24 |
| Finished | Feb 07 04:24:28 PM PST 24 |
| Peak memory | 555404 kb |
| Host | smart-561586e3-7950-4500-8de8-17ec7d6f975e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723012765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.723012765 |
| Directory | /workspace/61.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.1420664169 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 486903509 ps |
| CPU time | 43.42 seconds |
| Started | Feb 07 04:19:16 PM PST 24 |
| Finished | Feb 07 04:20:00 PM PST 24 |
| Peak memory | 555664 kb |
| Host | smart-e6b25bfa-7bf6-4d20-bef0-5b18e914203e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420664169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_del ays.1420664169 |
| Directory | /workspace/61.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_same_source.3239710785 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 746502187 ps |
| CPU time | 23.69 seconds |
| Started | Feb 07 04:19:17 PM PST 24 |
| Finished | Feb 07 04:19:41 PM PST 24 |
| Peak memory | 555344 kb |
| Host | smart-816d554b-6262-4d24-b38b-5b5c0ab71f4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239710785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.3239710785 |
| Directory | /workspace/61.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke.3693252853 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 219762384 ps |
| CPU time | 9.55 seconds |
| Started | Feb 07 04:19:28 PM PST 24 |
| Finished | Feb 07 04:19:41 PM PST 24 |
| Peak memory | 553268 kb |
| Host | smart-57a996aa-8521-4d9e-8b97-8b19cc9becd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693252853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.3693252853 |
| Directory | /workspace/61.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.2275897503 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 8889328955 ps |
| CPU time | 96.37 seconds |
| Started | Feb 07 04:19:15 PM PST 24 |
| Finished | Feb 07 04:20:52 PM PST 24 |
| Peak memory | 553404 kb |
| Host | smart-80b04ca5-8e06-4057-912f-54d46454e7cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275897503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.2275897503 |
| Directory | /workspace/61.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.2635987155 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 6520172175 ps |
| CPU time | 106.72 seconds |
| Started | Feb 07 04:19:18 PM PST 24 |
| Finished | Feb 07 04:21:06 PM PST 24 |
| Peak memory | 553680 kb |
| Host | smart-5bc97b75-3446-4d75-8c33-f9ed7f9896ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635987155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.2635987155 |
| Directory | /workspace/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.2817096841 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 51467291 ps |
| CPU time | 6.29 seconds |
| Started | Feb 07 04:19:18 PM PST 24 |
| Finished | Feb 07 04:19:25 PM PST 24 |
| Peak memory | 553288 kb |
| Host | smart-fadb4349-20bd-4910-b76b-be829e8bc6da |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817096841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delay s.2817096841 |
| Directory | /workspace/61.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all.2799313808 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 4119023429 ps |
| CPU time | 138.64 seconds |
| Started | Feb 07 04:20:22 PM PST 24 |
| Finished | Feb 07 04:22:42 PM PST 24 |
| Peak memory | 556264 kb |
| Host | smart-04caa374-746d-45fc-8d2a-25d1bdf9740f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799313808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.2799313808 |
| Directory | /workspace/61.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.1413737607 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 3466148931 ps |
| CPU time | 246.89 seconds |
| Started | Feb 07 04:19:34 PM PST 24 |
| Finished | Feb 07 04:23:43 PM PST 24 |
| Peak memory | 556848 kb |
| Host | smart-5b1abb4f-7144-4b61-8c54-8bcb0369cd4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413737607 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.1413737607 |
| Directory | /workspace/61.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.1987403151 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 2359298843 ps |
| CPU time | 220.62 seconds |
| Started | Feb 07 04:19:22 PM PST 24 |
| Finished | Feb 07 04:23:03 PM PST 24 |
| Peak memory | 556980 kb |
| Host | smart-3d9a25ba-1799-4083-b39a-9018cf846c51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987403151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all _with_rand_reset.1987403151 |
| Directory | /workspace/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.1176093739 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 196867770 ps |
| CPU time | 42.04 seconds |
| Started | Feb 07 04:19:32 PM PST 24 |
| Finished | Feb 07 04:20:17 PM PST 24 |
| Peak memory | 556640 kb |
| Host | smart-5939d758-9487-4d39-b6db-dc64a7373de8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176093739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_al l_with_reset_error.1176093739 |
| Directory | /workspace/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.3943553340 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 1250743952 ps |
| CPU time | 48.15 seconds |
| Started | Feb 07 04:19:18 PM PST 24 |
| Finished | Feb 07 04:20:07 PM PST 24 |
| Peak memory | 555708 kb |
| Host | smart-4f23aedb-4d1f-467b-9917-268ddb5993dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943553340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.3943553340 |
| Directory | /workspace/61.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device.2022115893 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 574492915 ps |
| CPU time | 36.31 seconds |
| Started | Feb 07 04:19:32 PM PST 24 |
| Finished | Feb 07 04:20:11 PM PST 24 |
| Peak memory | 555104 kb |
| Host | smart-a6f19e77-8d63-4cc4-8333-f1456cda4d2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022115893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device .2022115893 |
| Directory | /workspace/62.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.2453697654 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 109432617770 ps |
| CPU time | 2178.23 seconds |
| Started | Feb 07 04:19:42 PM PST 24 |
| Finished | Feb 07 04:56:03 PM PST 24 |
| Peak memory | 556808 kb |
| Host | smart-8ecdf6b8-0bca-4df0-bd1d-f4c13105d048 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453697654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_ device_slow_rsp.2453697654 |
| Directory | /workspace/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.4105513131 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 1376468992 ps |
| CPU time | 58.17 seconds |
| Started | Feb 07 04:19:36 PM PST 24 |
| Finished | Feb 07 04:20:38 PM PST 24 |
| Peak memory | 555380 kb |
| Host | smart-34ff8a56-162f-4f49-b837-ab98eb4c6a23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105513131 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_add r.4105513131 |
| Directory | /workspace/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_random.3137178039 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 241658717 ps |
| CPU time | 12.1 seconds |
| Started | Feb 07 04:19:32 PM PST 24 |
| Finished | Feb 07 04:19:47 PM PST 24 |
| Peak memory | 553240 kb |
| Host | smart-fee3084d-b774-40eb-beb1-cadeef63d61b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137178039 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.3137178039 |
| Directory | /workspace/62.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random.2252183943 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 457509592 ps |
| CPU time | 18.25 seconds |
| Started | Feb 07 04:19:29 PM PST 24 |
| Finished | Feb 07 04:19:50 PM PST 24 |
| Peak memory | 555376 kb |
| Host | smart-23ca0b06-f20c-461d-8540-f986c8a9a728 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252183943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.2252183943 |
| Directory | /workspace/62.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.3503323678 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 6389145072 ps |
| CPU time | 70.15 seconds |
| Started | Feb 07 04:19:29 PM PST 24 |
| Finished | Feb 07 04:20:42 PM PST 24 |
| Peak memory | 553196 kb |
| Host | smart-f6c805a2-f278-4b67-a4b3-ada8a36ba7be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503323678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.3503323678 |
| Directory | /workspace/62.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.531628379 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 21834817246 ps |
| CPU time | 386.17 seconds |
| Started | Feb 07 04:19:28 PM PST 24 |
| Finished | Feb 07 04:25:58 PM PST 24 |
| Peak memory | 555432 kb |
| Host | smart-482d4c26-97a0-493c-9ab4-9bb07db96e1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531628379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.531628379 |
| Directory | /workspace/62.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.386620896 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 50888783 ps |
| CPU time | 7.2 seconds |
| Started | Feb 07 04:19:36 PM PST 24 |
| Finished | Feb 07 04:19:48 PM PST 24 |
| Peak memory | 553340 kb |
| Host | smart-a96bbb3a-286d-4e6f-b9cb-9463efd58977 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386620896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_dela ys.386620896 |
| Directory | /workspace/62.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_same_source.1181098409 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 1240953240 ps |
| CPU time | 38.25 seconds |
| Started | Feb 07 04:19:31 PM PST 24 |
| Finished | Feb 07 04:20:10 PM PST 24 |
| Peak memory | 555648 kb |
| Host | smart-9218809e-bc39-49f7-a461-7192e0176a96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181098409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.1181098409 |
| Directory | /workspace/62.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke.1461140425 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 224480914 ps |
| CPU time | 9.69 seconds |
| Started | Feb 07 04:19:31 PM PST 24 |
| Finished | Feb 07 04:19:42 PM PST 24 |
| Peak memory | 553600 kb |
| Host | smart-60298e50-8f4c-42ee-b7e4-7bcc99652779 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461140425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.1461140425 |
| Directory | /workspace/62.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.3703930777 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 9823766910 ps |
| CPU time | 102.8 seconds |
| Started | Feb 07 04:19:29 PM PST 24 |
| Finished | Feb 07 04:21:15 PM PST 24 |
| Peak memory | 553688 kb |
| Host | smart-a06700b2-2e21-437e-b7d2-269627275e85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703930777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.3703930777 |
| Directory | /workspace/62.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.3396547768 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 5236019467 ps |
| CPU time | 87.43 seconds |
| Started | Feb 07 04:19:32 PM PST 24 |
| Finished | Feb 07 04:21:02 PM PST 24 |
| Peak memory | 553340 kb |
| Host | smart-221836e4-d386-4162-9643-cc54df51264c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396547768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.3396547768 |
| Directory | /workspace/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.829484404 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 49352785 ps |
| CPU time | 6.45 seconds |
| Started | Feb 07 04:19:30 PM PST 24 |
| Finished | Feb 07 04:19:38 PM PST 24 |
| Peak memory | 553340 kb |
| Host | smart-2d61fd80-2b88-493e-b881-4b980b21e189 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829484404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delays .829484404 |
| Directory | /workspace/62.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all.2344161971 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 2748277624 ps |
| CPU time | 229.73 seconds |
| Started | Feb 07 04:19:31 PM PST 24 |
| Finished | Feb 07 04:23:22 PM PST 24 |
| Peak memory | 559404 kb |
| Host | smart-e810cd02-ca29-43bd-a016-21982fc78a5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344161971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.2344161971 |
| Directory | /workspace/62.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.1617159253 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 12067890859 ps |
| CPU time | 387.98 seconds |
| Started | Feb 07 04:19:32 PM PST 24 |
| Finished | Feb 07 04:26:03 PM PST 24 |
| Peak memory | 556364 kb |
| Host | smart-52cdbf14-d0d2-4254-ab1c-9a998bdc3983 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617159253 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.1617159253 |
| Directory | /workspace/62.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.920236202 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 46308431 ps |
| CPU time | 15.83 seconds |
| Started | Feb 07 04:19:33 PM PST 24 |
| Finished | Feb 07 04:19:51 PM PST 24 |
| Peak memory | 555620 kb |
| Host | smart-e4a4840a-19fc-41e5-8bed-8842ac4ae849 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920236202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_ with_rand_reset.920236202 |
| Directory | /workspace/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.1898348428 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 220263044 ps |
| CPU time | 61.5 seconds |
| Started | Feb 07 04:19:31 PM PST 24 |
| Finished | Feb 07 04:20:34 PM PST 24 |
| Peak memory | 556504 kb |
| Host | smart-b4429eb0-68b3-484d-9055-a9f73aa841f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898348428 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_al l_with_reset_error.1898348428 |
| Directory | /workspace/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.1512245141 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 1190246163 ps |
| CPU time | 48.46 seconds |
| Started | Feb 07 04:19:29 PM PST 24 |
| Finished | Feb 07 04:20:20 PM PST 24 |
| Peak memory | 555116 kb |
| Host | smart-9f4fc697-8462-42c0-8b0d-36bebf9cdf1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512245141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.1512245141 |
| Directory | /workspace/62.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device.2255837635 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 771000228 ps |
| CPU time | 35.34 seconds |
| Started | Feb 07 04:19:35 PM PST 24 |
| Finished | Feb 07 04:20:15 PM PST 24 |
| Peak memory | 556388 kb |
| Host | smart-6aca6361-ec64-40bf-b371-56e40f8a7325 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255837635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device .2255837635 |
| Directory | /workspace/63.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.3543635972 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 24989174413 ps |
| CPU time | 442.45 seconds |
| Started | Feb 07 04:19:30 PM PST 24 |
| Finished | Feb 07 04:26:54 PM PST 24 |
| Peak memory | 555432 kb |
| Host | smart-ea0d508d-00b3-4313-97d2-64fe869220ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543635972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_ device_slow_rsp.3543635972 |
| Directory | /workspace/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.2988420741 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 1246728345 ps |
| CPU time | 50.27 seconds |
| Started | Feb 07 04:19:36 PM PST 24 |
| Finished | Feb 07 04:20:31 PM PST 24 |
| Peak memory | 559180 kb |
| Host | smart-013c758c-b9e9-4821-98ab-12293e1c6397 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988420741 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_add r.2988420741 |
| Directory | /workspace/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_random.1229779450 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 358068325 ps |
| CPU time | 33.57 seconds |
| Started | Feb 07 04:19:38 PM PST 24 |
| Finished | Feb 07 04:20:15 PM PST 24 |
| Peak memory | 555352 kb |
| Host | smart-f9f80c28-7bbe-47c0-8000-c7c9d73eac68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229779450 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.1229779450 |
| Directory | /workspace/63.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random.2549789224 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 2225586489 ps |
| CPU time | 80.52 seconds |
| Started | Feb 07 04:19:35 PM PST 24 |
| Finished | Feb 07 04:20:56 PM PST 24 |
| Peak memory | 555436 kb |
| Host | smart-787aedc5-d19a-462c-8373-0068c8cf08ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549789224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.2549789224 |
| Directory | /workspace/63.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.2782175703 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 31241020969 ps |
| CPU time | 355.81 seconds |
| Started | Feb 07 04:19:37 PM PST 24 |
| Finished | Feb 07 04:25:37 PM PST 24 |
| Peak memory | 555384 kb |
| Host | smart-a460cc59-2e5e-42eb-bf45-ad16dacec8fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782175703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.2782175703 |
| Directory | /workspace/63.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.1976724404 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 63065324407 ps |
| CPU time | 1187.51 seconds |
| Started | Feb 07 04:19:37 PM PST 24 |
| Finished | Feb 07 04:39:29 PM PST 24 |
| Peak memory | 555708 kb |
| Host | smart-a7946865-1b90-4222-8b09-e25331943fd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976724404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.1976724404 |
| Directory | /workspace/63.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.3224220897 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 218747274 ps |
| CPU time | 18.87 seconds |
| Started | Feb 07 04:19:35 PM PST 24 |
| Finished | Feb 07 04:19:58 PM PST 24 |
| Peak memory | 555648 kb |
| Host | smart-04d987ec-239a-44e5-8ff5-fbd13c847b64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224220897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_del ays.3224220897 |
| Directory | /workspace/63.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_same_source.1949462436 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 470410828 ps |
| CPU time | 33.18 seconds |
| Started | Feb 07 04:19:41 PM PST 24 |
| Finished | Feb 07 04:20:16 PM PST 24 |
| Peak memory | 555096 kb |
| Host | smart-cab49869-bfdf-45a8-8c8a-ad9c7a48ba3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949462436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.1949462436 |
| Directory | /workspace/63.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke.1575211007 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 178721250 ps |
| CPU time | 8.51 seconds |
| Started | Feb 07 04:19:39 PM PST 24 |
| Finished | Feb 07 04:19:50 PM PST 24 |
| Peak memory | 553264 kb |
| Host | smart-344044e1-1989-4d9e-b762-45f04bcc2e89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575211007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.1575211007 |
| Directory | /workspace/63.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.2894218337 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 9060674683 ps |
| CPU time | 95.62 seconds |
| Started | Feb 07 04:19:37 PM PST 24 |
| Finished | Feb 07 04:21:17 PM PST 24 |
| Peak memory | 553396 kb |
| Host | smart-f83dcbbc-a455-40af-9084-40cc5cb7fe55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894218337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.2894218337 |
| Directory | /workspace/63.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.1428356404 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 5324176189 ps |
| CPU time | 89.47 seconds |
| Started | Feb 07 04:19:36 PM PST 24 |
| Finished | Feb 07 04:21:11 PM PST 24 |
| Peak memory | 553664 kb |
| Host | smart-b2515849-2948-4e74-821d-c2ac70af4fa5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428356404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.1428356404 |
| Directory | /workspace/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.734484876 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 42191410 ps |
| CPU time | 5.73 seconds |
| Started | Feb 07 04:19:40 PM PST 24 |
| Finished | Feb 07 04:19:48 PM PST 24 |
| Peak memory | 553568 kb |
| Host | smart-42080d96-c40f-4a9d-80ae-2f11582cefcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734484876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delays .734484876 |
| Directory | /workspace/63.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all.7850043 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 2344346836 ps |
| CPU time | 220.41 seconds |
| Started | Feb 07 04:19:37 PM PST 24 |
| Finished | Feb 07 04:23:22 PM PST 24 |
| Peak memory | 556304 kb |
| Host | smart-9f3ce408-ca53-4258-a636-fce6e63c7cd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7850043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.7850043 |
| Directory | /workspace/63.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.3869017832 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 16816640882 ps |
| CPU time | 633.54 seconds |
| Started | Feb 07 04:19:39 PM PST 24 |
| Finished | Feb 07 04:30:15 PM PST 24 |
| Peak memory | 559364 kb |
| Host | smart-a2ef49d4-99f6-432d-94ce-86bd755adee6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869017832 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.3869017832 |
| Directory | /workspace/63.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.681365837 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 11496643228 ps |
| CPU time | 670.68 seconds |
| Started | Feb 07 04:19:33 PM PST 24 |
| Finished | Feb 07 04:30:46 PM PST 24 |
| Peak memory | 559452 kb |
| Host | smart-c6df05c2-c0c8-4df7-94a4-8f94d070f2bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681365837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_ with_rand_reset.681365837 |
| Directory | /workspace/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.2107496680 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 60434372 ps |
| CPU time | 19.86 seconds |
| Started | Feb 07 04:19:34 PM PST 24 |
| Finished | Feb 07 04:19:56 PM PST 24 |
| Peak memory | 555720 kb |
| Host | smart-bb580815-23ce-4871-83b7-6147c8f9a795 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107496680 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_al l_with_reset_error.2107496680 |
| Directory | /workspace/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.2864818622 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 546624372 ps |
| CPU time | 22.96 seconds |
| Started | Feb 07 04:19:35 PM PST 24 |
| Finished | Feb 07 04:20:02 PM PST 24 |
| Peak memory | 555388 kb |
| Host | smart-baa5c254-1df5-4dbc-9f96-4643aac7b748 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864818622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.2864818622 |
| Directory | /workspace/63.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device.95979842 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 1907064637 ps |
| CPU time | 89.85 seconds |
| Started | Feb 07 04:19:39 PM PST 24 |
| Finished | Feb 07 04:21:12 PM PST 24 |
| Peak memory | 555380 kb |
| Host | smart-5d6cc7b6-c2cb-4a92-8eeb-f34efa821189 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95979842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device.95979842 |
| Directory | /workspace/64.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.1756119683 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 29781593688 ps |
| CPU time | 549.98 seconds |
| Started | Feb 07 04:19:40 PM PST 24 |
| Finished | Feb 07 04:28:52 PM PST 24 |
| Peak memory | 555732 kb |
| Host | smart-573a909d-b271-49c0-84f3-773460e3012a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756119683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_ device_slow_rsp.1756119683 |
| Directory | /workspace/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.3138749177 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 281075043 ps |
| CPU time | 30.29 seconds |
| Started | Feb 07 04:19:44 PM PST 24 |
| Finished | Feb 07 04:20:15 PM PST 24 |
| Peak memory | 555400 kb |
| Host | smart-d47b324d-6879-4d71-a937-593d127abfb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138749177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_add r.3138749177 |
| Directory | /workspace/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_random.2292702424 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 500414736 ps |
| CPU time | 36.08 seconds |
| Started | Feb 07 04:19:40 PM PST 24 |
| Finished | Feb 07 04:20:18 PM PST 24 |
| Peak memory | 555032 kb |
| Host | smart-3a12e32d-57d0-4fc5-b8ce-88383ad359c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292702424 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.2292702424 |
| Directory | /workspace/64.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random.1877415642 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 226615572 ps |
| CPU time | 23.01 seconds |
| Started | Feb 07 04:19:39 PM PST 24 |
| Finished | Feb 07 04:20:05 PM PST 24 |
| Peak memory | 555444 kb |
| Host | smart-c7fa2736-8ba1-476b-91ea-4f9057c26833 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877415642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.1877415642 |
| Directory | /workspace/64.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.1983997696 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 101755879354 ps |
| CPU time | 1094.94 seconds |
| Started | Feb 07 04:19:40 PM PST 24 |
| Finished | Feb 07 04:37:57 PM PST 24 |
| Peak memory | 555208 kb |
| Host | smart-5ab8d766-f164-406d-8df0-ab4acd106f57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983997696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.1983997696 |
| Directory | /workspace/64.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.1975257962 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 27030667613 ps |
| CPU time | 468.58 seconds |
| Started | Feb 07 04:19:44 PM PST 24 |
| Finished | Feb 07 04:27:34 PM PST 24 |
| Peak memory | 555484 kb |
| Host | smart-4e503086-ebd9-42ee-8977-ac3ed22fda51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975257962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.1975257962 |
| Directory | /workspace/64.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.2386234009 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 109483926 ps |
| CPU time | 11.43 seconds |
| Started | Feb 07 04:19:45 PM PST 24 |
| Finished | Feb 07 04:19:57 PM PST 24 |
| Peak memory | 559184 kb |
| Host | smart-c077e1cd-68c9-4710-8a29-bb7affaa600d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386234009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_del ays.2386234009 |
| Directory | /workspace/64.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_same_source.778265641 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 109634843 ps |
| CPU time | 9.8 seconds |
| Started | Feb 07 04:19:44 PM PST 24 |
| Finished | Feb 07 04:19:55 PM PST 24 |
| Peak memory | 555492 kb |
| Host | smart-d2252dc4-949d-45ae-8e95-4d6fcc153a80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778265641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.778265641 |
| Directory | /workspace/64.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke.1947805106 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 230734961 ps |
| CPU time | 10.29 seconds |
| Started | Feb 07 04:19:35 PM PST 24 |
| Finished | Feb 07 04:19:46 PM PST 24 |
| Peak memory | 553572 kb |
| Host | smart-4f147a17-6648-4142-b125-71c17256129e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947805106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.1947805106 |
| Directory | /workspace/64.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.2982266081 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 7502409973 ps |
| CPU time | 83.35 seconds |
| Started | Feb 07 04:19:38 PM PST 24 |
| Finished | Feb 07 04:21:05 PM PST 24 |
| Peak memory | 553664 kb |
| Host | smart-68cc5d74-3d6a-41c6-aa2d-fa990155ad44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982266081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.2982266081 |
| Directory | /workspace/64.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.2687483580 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 4765018523 ps |
| CPU time | 89.77 seconds |
| Started | Feb 07 04:19:40 PM PST 24 |
| Finished | Feb 07 04:21:11 PM PST 24 |
| Peak memory | 553672 kb |
| Host | smart-b801254d-6d17-448a-82cb-e07c81ff64c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687483580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.2687483580 |
| Directory | /workspace/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.1075878077 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 44803176 ps |
| CPU time | 5.97 seconds |
| Started | Feb 07 04:19:34 PM PST 24 |
| Finished | Feb 07 04:19:42 PM PST 24 |
| Peak memory | 553292 kb |
| Host | smart-366afd1b-bb97-4180-85d9-6c52a414bf25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075878077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delay s.1075878077 |
| Directory | /workspace/64.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all.3365455910 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 5887229765 ps |
| CPU time | 214.78 seconds |
| Started | Feb 07 04:19:43 PM PST 24 |
| Finished | Feb 07 04:23:20 PM PST 24 |
| Peak memory | 556416 kb |
| Host | smart-962ab530-7786-452b-882e-cb6dbad0bc72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365455910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.3365455910 |
| Directory | /workspace/64.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.1542294307 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 1993935898 ps |
| CPU time | 118.15 seconds |
| Started | Feb 07 04:19:44 PM PST 24 |
| Finished | Feb 07 04:21:43 PM PST 24 |
| Peak memory | 556496 kb |
| Host | smart-3a43a0b6-5852-4ed6-98de-54384f5071fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542294307 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.1542294307 |
| Directory | /workspace/64.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.744381767 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 38338559 ps |
| CPU time | 17.66 seconds |
| Started | Feb 07 04:19:40 PM PST 24 |
| Finished | Feb 07 04:19:59 PM PST 24 |
| Peak memory | 554784 kb |
| Host | smart-69520c68-6826-478b-8036-1024363fd364 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744381767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_ with_rand_reset.744381767 |
| Directory | /workspace/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.3051447247 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 462184084 ps |
| CPU time | 64.09 seconds |
| Started | Feb 07 04:19:57 PM PST 24 |
| Finished | Feb 07 04:21:02 PM PST 24 |
| Peak memory | 556576 kb |
| Host | smart-018e60d8-fe1f-4ac8-90f8-6f9aef22a153 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051447247 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_al l_with_reset_error.3051447247 |
| Directory | /workspace/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.1972948437 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 1373317576 ps |
| CPU time | 56.71 seconds |
| Started | Feb 07 04:19:41 PM PST 24 |
| Finished | Feb 07 04:20:39 PM PST 24 |
| Peak memory | 555660 kb |
| Host | smart-8e5079df-e8ab-4594-8404-aedc7d198c5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972948437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.1972948437 |
| Directory | /workspace/64.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device.2337067051 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 2377213347 ps |
| CPU time | 97 seconds |
| Started | Feb 07 04:19:52 PM PST 24 |
| Finished | Feb 07 04:21:30 PM PST 24 |
| Peak memory | 556252 kb |
| Host | smart-3bfd3dc5-d1aa-480d-a40e-18e13b75d165 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337067051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device .2337067051 |
| Directory | /workspace/65.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.300212822 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 77503164855 ps |
| CPU time | 1508.88 seconds |
| Started | Feb 07 04:19:52 PM PST 24 |
| Finished | Feb 07 04:45:03 PM PST 24 |
| Peak memory | 556752 kb |
| Host | smart-3bd0f199-3435-4cac-a1ba-1e4a8027b83f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300212822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_d evice_slow_rsp.300212822 |
| Directory | /workspace/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.381028981 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 743964031 ps |
| CPU time | 30.53 seconds |
| Started | Feb 07 04:19:55 PM PST 24 |
| Finished | Feb 07 04:20:29 PM PST 24 |
| Peak memory | 555632 kb |
| Host | smart-6f89551e-5324-4760-b742-f2eac1f01195 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381028981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_addr .381028981 |
| Directory | /workspace/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_random.3805551057 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 229003117 ps |
| CPU time | 11.64 seconds |
| Started | Feb 07 04:19:50 PM PST 24 |
| Finished | Feb 07 04:20:03 PM PST 24 |
| Peak memory | 554620 kb |
| Host | smart-8b662b47-0b80-492f-8f5a-ab9cd03fd98e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805551057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.3805551057 |
| Directory | /workspace/65.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random.2285510972 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 451349782 ps |
| CPU time | 18 seconds |
| Started | Feb 07 04:19:53 PM PST 24 |
| Finished | Feb 07 04:20:15 PM PST 24 |
| Peak memory | 555376 kb |
| Host | smart-292a8278-3ac1-4cd3-9aa1-3a6db112e62a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285510972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.2285510972 |
| Directory | /workspace/65.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.1851098241 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 104298077042 ps |
| CPU time | 1230.58 seconds |
| Started | Feb 07 04:19:59 PM PST 24 |
| Finished | Feb 07 04:40:31 PM PST 24 |
| Peak memory | 555468 kb |
| Host | smart-529e38c5-5ddc-4d1a-84a5-0744748e32bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851098241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.1851098241 |
| Directory | /workspace/65.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.787548139 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 61279886234 ps |
| CPU time | 1234 seconds |
| Started | Feb 07 04:19:51 PM PST 24 |
| Finished | Feb 07 04:40:26 PM PST 24 |
| Peak memory | 555452 kb |
| Host | smart-8bdc508d-5a53-4c78-bb3f-377b87ff6fd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787548139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.787548139 |
| Directory | /workspace/65.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.4230389033 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 233404005 ps |
| CPU time | 25.26 seconds |
| Started | Feb 07 04:19:51 PM PST 24 |
| Finished | Feb 07 04:20:17 PM PST 24 |
| Peak memory | 555404 kb |
| Host | smart-33944fa7-886c-4778-a3cf-477a57d0c8fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230389033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_del ays.4230389033 |
| Directory | /workspace/65.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_same_source.3914844860 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 405431500 ps |
| CPU time | 28.39 seconds |
| Started | Feb 07 04:19:53 PM PST 24 |
| Finished | Feb 07 04:20:26 PM PST 24 |
| Peak memory | 555360 kb |
| Host | smart-7f2d474a-2de5-422e-bdae-366044075ea1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914844860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.3914844860 |
| Directory | /workspace/65.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke.1347509344 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 187344495 ps |
| CPU time | 8.9 seconds |
| Started | Feb 07 04:19:58 PM PST 24 |
| Finished | Feb 07 04:20:08 PM PST 24 |
| Peak memory | 553384 kb |
| Host | smart-e47e7108-a776-4cdb-88cf-b88a9ff9409c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347509344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.1347509344 |
| Directory | /workspace/65.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.1074095619 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 8128141042 ps |
| CPU time | 89.18 seconds |
| Started | Feb 07 04:19:54 PM PST 24 |
| Finished | Feb 07 04:21:27 PM PST 24 |
| Peak memory | 553432 kb |
| Host | smart-48fa2296-b1d6-4b65-ab64-7d66c6842775 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074095619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.1074095619 |
| Directory | /workspace/65.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.3635597672 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 4664095349 ps |
| CPU time | 78.91 seconds |
| Started | Feb 07 04:19:50 PM PST 24 |
| Finished | Feb 07 04:21:10 PM PST 24 |
| Peak memory | 553352 kb |
| Host | smart-f5f35ecb-b98f-478a-a60b-b77517e0654e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635597672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.3635597672 |
| Directory | /workspace/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.2313635051 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 52816673 ps |
| CPU time | 6.37 seconds |
| Started | Feb 07 04:19:51 PM PST 24 |
| Finished | Feb 07 04:19:59 PM PST 24 |
| Peak memory | 553256 kb |
| Host | smart-586e9b2b-821e-4ed5-8adb-119c366b7835 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313635051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delay s.2313635051 |
| Directory | /workspace/65.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all.513876930 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 1650024867 ps |
| CPU time | 157.49 seconds |
| Started | Feb 07 04:19:53 PM PST 24 |
| Finished | Feb 07 04:22:31 PM PST 24 |
| Peak memory | 556840 kb |
| Host | smart-b002a60e-e569-4623-ace0-f9c53ece385b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513876930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.513876930 |
| Directory | /workspace/65.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.3434730386 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 480597600 ps |
| CPU time | 42.17 seconds |
| Started | Feb 07 04:20:03 PM PST 24 |
| Finished | Feb 07 04:20:45 PM PST 24 |
| Peak memory | 555672 kb |
| Host | smart-5142aaeb-b6c8-4f72-8e9b-c84c6b5cbebf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434730386 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.3434730386 |
| Directory | /workspace/65.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.1711645462 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 806199148 ps |
| CPU time | 142.81 seconds |
| Started | Feb 07 04:19:50 PM PST 24 |
| Finished | Feb 07 04:22:13 PM PST 24 |
| Peak memory | 556836 kb |
| Host | smart-83250a7c-6603-4306-b362-28160391c870 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711645462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all _with_rand_reset.1711645462 |
| Directory | /workspace/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.2752652211 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 5746583059 ps |
| CPU time | 341.93 seconds |
| Started | Feb 07 04:20:00 PM PST 24 |
| Finished | Feb 07 04:25:44 PM PST 24 |
| Peak memory | 558828 kb |
| Host | smart-b8f08468-b080-40ed-a73c-66927b115935 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752652211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_al l_with_reset_error.2752652211 |
| Directory | /workspace/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.2066946852 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 381511443 ps |
| CPU time | 18.27 seconds |
| Started | Feb 07 04:19:54 PM PST 24 |
| Finished | Feb 07 04:20:16 PM PST 24 |
| Peak memory | 555124 kb |
| Host | smart-e8035e6b-b181-4ac1-821c-4515974cc679 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066946852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.2066946852 |
| Directory | /workspace/65.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device.2730996842 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 906584030 ps |
| CPU time | 72.79 seconds |
| Started | Feb 07 04:20:04 PM PST 24 |
| Finished | Feb 07 04:21:18 PM PST 24 |
| Peak memory | 555364 kb |
| Host | smart-95d4f17c-39fe-4673-a11f-037a3768acb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730996842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device .2730996842 |
| Directory | /workspace/66.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.65043137 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 50738694146 ps |
| CPU time | 922.34 seconds |
| Started | Feb 07 04:20:17 PM PST 24 |
| Finished | Feb 07 04:35:40 PM PST 24 |
| Peak memory | 555464 kb |
| Host | smart-c8829567-d735-421d-aa20-9db518a869ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65043137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_de vice_slow_rsp.65043137 |
| Directory | /workspace/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.2785696122 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 145641320 ps |
| CPU time | 16.77 seconds |
| Started | Feb 07 04:20:02 PM PST 24 |
| Finished | Feb 07 04:20:20 PM PST 24 |
| Peak memory | 555344 kb |
| Host | smart-0e161be3-cd18-4901-9365-35e2ba300970 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785696122 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_add r.2785696122 |
| Directory | /workspace/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_random.821925719 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 462260419 ps |
| CPU time | 17.83 seconds |
| Started | Feb 07 04:20:07 PM PST 24 |
| Finished | Feb 07 04:20:25 PM PST 24 |
| Peak memory | 555628 kb |
| Host | smart-ea40dc7d-b440-463e-84d1-14b8e7c1d786 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821925719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.821925719 |
| Directory | /workspace/66.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random.1070277294 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 2059607526 ps |
| CPU time | 69.73 seconds |
| Started | Feb 07 04:19:56 PM PST 24 |
| Finished | Feb 07 04:21:08 PM PST 24 |
| Peak memory | 555412 kb |
| Host | smart-7536082b-db50-406b-9cf3-1fdea255bcab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070277294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.1070277294 |
| Directory | /workspace/66.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.2860992853 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 85546058408 ps |
| CPU time | 952.3 seconds |
| Started | Feb 07 04:20:01 PM PST 24 |
| Finished | Feb 07 04:35:54 PM PST 24 |
| Peak memory | 555712 kb |
| Host | smart-2d583ca8-1f82-4e05-96de-2bae59f99deb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860992853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.2860992853 |
| Directory | /workspace/66.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.1508465735 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 54450096176 ps |
| CPU time | 1087.88 seconds |
| Started | Feb 07 04:20:02 PM PST 24 |
| Finished | Feb 07 04:38:11 PM PST 24 |
| Peak memory | 555444 kb |
| Host | smart-9d8750de-338a-49bf-8a30-db92f13cae7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508465735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.1508465735 |
| Directory | /workspace/66.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.286642312 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 219883607 ps |
| CPU time | 22.45 seconds |
| Started | Feb 07 04:19:59 PM PST 24 |
| Finished | Feb 07 04:20:24 PM PST 24 |
| Peak memory | 555360 kb |
| Host | smart-27bf77ba-4144-4542-bb9b-eaf94951365d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286642312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_dela ys.286642312 |
| Directory | /workspace/66.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_same_source.3312658004 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 2467817661 ps |
| CPU time | 77.01 seconds |
| Started | Feb 07 04:20:02 PM PST 24 |
| Finished | Feb 07 04:21:20 PM PST 24 |
| Peak memory | 555388 kb |
| Host | smart-745e37ee-cc31-4145-b5ca-7bd3a1b19ab0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312658004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.3312658004 |
| Directory | /workspace/66.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke.3312371283 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 219569922 ps |
| CPU time | 10.13 seconds |
| Started | Feb 07 04:20:00 PM PST 24 |
| Finished | Feb 07 04:20:12 PM PST 24 |
| Peak memory | 553008 kb |
| Host | smart-55eb9e5a-937e-4263-bd0b-7b71040bf621 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312371283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.3312371283 |
| Directory | /workspace/66.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.3812765965 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 6926963603 ps |
| CPU time | 78.28 seconds |
| Started | Feb 07 04:20:00 PM PST 24 |
| Finished | Feb 07 04:21:20 PM PST 24 |
| Peak memory | 553708 kb |
| Host | smart-cb902a4f-fdbd-4b40-aa11-c1227dde2798 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812765965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.3812765965 |
| Directory | /workspace/66.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.858577953 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 5343041332 ps |
| CPU time | 91.44 seconds |
| Started | Feb 07 04:19:57 PM PST 24 |
| Finished | Feb 07 04:21:30 PM PST 24 |
| Peak memory | 553400 kb |
| Host | smart-4e4d1a7b-f3e2-46ca-8ae0-cc322bae9b44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858577953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.858577953 |
| Directory | /workspace/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.1138312836 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 55344990 ps |
| CPU time | 6.52 seconds |
| Started | Feb 07 04:19:57 PM PST 24 |
| Finished | Feb 07 04:20:05 PM PST 24 |
| Peak memory | 553012 kb |
| Host | smart-8394775f-fc3f-4683-a1e0-26334726277b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138312836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delay s.1138312836 |
| Directory | /workspace/66.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all.1038487002 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 657208981 ps |
| CPU time | 65.21 seconds |
| Started | Feb 07 04:20:04 PM PST 24 |
| Finished | Feb 07 04:21:10 PM PST 24 |
| Peak memory | 555780 kb |
| Host | smart-52a909a5-9d8d-481c-9a95-d19b4d38e33f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038487002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.1038487002 |
| Directory | /workspace/66.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.4057039744 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 9858105052 ps |
| CPU time | 354.96 seconds |
| Started | Feb 07 04:20:04 PM PST 24 |
| Finished | Feb 07 04:25:59 PM PST 24 |
| Peak memory | 559372 kb |
| Host | smart-c72c9076-6697-4c34-b049-c4a1c88ab522 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057039744 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.4057039744 |
| Directory | /workspace/66.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.389744519 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 5402099117 ps |
| CPU time | 316.23 seconds |
| Started | Feb 07 04:20:18 PM PST 24 |
| Finished | Feb 07 04:25:34 PM PST 24 |
| Peak memory | 557212 kb |
| Host | smart-bd8ddbb3-25de-46f7-8505-49969b939498 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389744519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_ with_rand_reset.389744519 |
| Directory | /workspace/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.1439209492 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 4217937911 ps |
| CPU time | 482.93 seconds |
| Started | Feb 07 04:20:01 PM PST 24 |
| Finished | Feb 07 04:28:05 PM PST 24 |
| Peak memory | 559356 kb |
| Host | smart-cf232e39-33f7-4ba6-8aa6-36ab9b795e94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439209492 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_al l_with_reset_error.1439209492 |
| Directory | /workspace/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.3636742485 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 323080084 ps |
| CPU time | 37.72 seconds |
| Started | Feb 07 04:20:02 PM PST 24 |
| Finished | Feb 07 04:20:40 PM PST 24 |
| Peak memory | 555704 kb |
| Host | smart-1742237e-7d01-40f5-a75f-8ee97c1d664f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636742485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.3636742485 |
| Directory | /workspace/66.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device.1459572828 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 838703321 ps |
| CPU time | 32.05 seconds |
| Started | Feb 07 04:20:03 PM PST 24 |
| Finished | Feb 07 04:20:36 PM PST 24 |
| Peak memory | 554320 kb |
| Host | smart-843d409e-ac5e-41bb-88f0-f657eb2934ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459572828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device .1459572828 |
| Directory | /workspace/67.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.239504541 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 84902025258 ps |
| CPU time | 1486.92 seconds |
| Started | Feb 07 04:20:18 PM PST 24 |
| Finished | Feb 07 04:45:05 PM PST 24 |
| Peak memory | 555740 kb |
| Host | smart-5de9dde9-e3e0-4657-98e1-1c0f82a3ad14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239504541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_d evice_slow_rsp.239504541 |
| Directory | /workspace/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.1721708846 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 127072187 ps |
| CPU time | 15.42 seconds |
| Started | Feb 07 04:20:12 PM PST 24 |
| Finished | Feb 07 04:20:28 PM PST 24 |
| Peak memory | 555400 kb |
| Host | smart-132ce1d9-7246-45ab-8d35-0101ad201563 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721708846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_add r.1721708846 |
| Directory | /workspace/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_random.2232064058 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 614356205 ps |
| CPU time | 44.28 seconds |
| Started | Feb 07 04:20:07 PM PST 24 |
| Finished | Feb 07 04:20:52 PM PST 24 |
| Peak memory | 555608 kb |
| Host | smart-e5e67160-be3c-453e-9503-9ad1f21e1b64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232064058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.2232064058 |
| Directory | /workspace/67.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random.1416025324 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 371125105 ps |
| CPU time | 28.36 seconds |
| Started | Feb 07 04:20:18 PM PST 24 |
| Finished | Feb 07 04:20:47 PM PST 24 |
| Peak memory | 555132 kb |
| Host | smart-70471810-dd11-4ef9-b89a-3c8dec4ece00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416025324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.1416025324 |
| Directory | /workspace/67.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.1778562308 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 93933674538 ps |
| CPU time | 1196.81 seconds |
| Started | Feb 07 04:20:06 PM PST 24 |
| Finished | Feb 07 04:40:03 PM PST 24 |
| Peak memory | 555420 kb |
| Host | smart-ce59d6d8-9945-4c75-802d-4571eee75024 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778562308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.1778562308 |
| Directory | /workspace/67.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.3252557450 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 61751810171 ps |
| CPU time | 1140.14 seconds |
| Started | Feb 07 04:20:04 PM PST 24 |
| Finished | Feb 07 04:39:05 PM PST 24 |
| Peak memory | 555736 kb |
| Host | smart-874c2cdd-a787-4162-8e72-f962a330acb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252557450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.3252557450 |
| Directory | /workspace/67.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.702458627 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 492457747 ps |
| CPU time | 43.97 seconds |
| Started | Feb 07 04:20:04 PM PST 24 |
| Finished | Feb 07 04:20:49 PM PST 24 |
| Peak memory | 555620 kb |
| Host | smart-b2e2b0a1-5b63-4214-adc0-96d248cc5eed |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702458627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_dela ys.702458627 |
| Directory | /workspace/67.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_same_source.3985044719 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 1003086036 ps |
| CPU time | 28.8 seconds |
| Started | Feb 07 04:20:02 PM PST 24 |
| Finished | Feb 07 04:20:32 PM PST 24 |
| Peak memory | 555204 kb |
| Host | smart-af7ac1c4-152f-4b2c-9b8f-ac8dcdac2c1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985044719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.3985044719 |
| Directory | /workspace/67.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke.731025931 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 44594097 ps |
| CPU time | 6.09 seconds |
| Started | Feb 07 04:20:05 PM PST 24 |
| Finished | Feb 07 04:20:11 PM PST 24 |
| Peak memory | 553628 kb |
| Host | smart-e7c9475e-6213-4f22-8047-f615f36793d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731025931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.731025931 |
| Directory | /workspace/67.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.1492919427 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 9292299389 ps |
| CPU time | 99.88 seconds |
| Started | Feb 07 04:20:18 PM PST 24 |
| Finished | Feb 07 04:21:58 PM PST 24 |
| Peak memory | 553448 kb |
| Host | smart-5f157dee-a44e-4565-995a-e2d748d8f9c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492919427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.1492919427 |
| Directory | /workspace/67.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.404064406 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 3727764255 ps |
| CPU time | 66.34 seconds |
| Started | Feb 07 04:20:04 PM PST 24 |
| Finished | Feb 07 04:21:11 PM PST 24 |
| Peak memory | 553680 kb |
| Host | smart-f9cba5d9-ddc0-4cc8-834e-f95c67932c28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404064406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.404064406 |
| Directory | /workspace/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.2798982203 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 52876642 ps |
| CPU time | 6.45 seconds |
| Started | Feb 07 04:20:07 PM PST 24 |
| Finished | Feb 07 04:20:14 PM PST 24 |
| Peak memory | 553020 kb |
| Host | smart-22348099-4cfa-4618-aae8-467748e17ee2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798982203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delay s.2798982203 |
| Directory | /workspace/67.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all.4206732729 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 7480022080 ps |
| CPU time | 291.21 seconds |
| Started | Feb 07 04:20:12 PM PST 24 |
| Finished | Feb 07 04:25:04 PM PST 24 |
| Peak memory | 556832 kb |
| Host | smart-28f89c56-b4fc-4de9-9726-88fcc9e8840d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206732729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.4206732729 |
| Directory | /workspace/67.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.696917724 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 2210831645 ps |
| CPU time | 161.61 seconds |
| Started | Feb 07 04:20:12 PM PST 24 |
| Finished | Feb 07 04:22:55 PM PST 24 |
| Peak memory | 556488 kb |
| Host | smart-229a030d-de2f-4a8b-a935-a03697bc54a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696917724 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.696917724 |
| Directory | /workspace/67.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.3162328433 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 71892424 ps |
| CPU time | 30.12 seconds |
| Started | Feb 07 04:20:14 PM PST 24 |
| Finished | Feb 07 04:20:45 PM PST 24 |
| Peak memory | 554504 kb |
| Host | smart-3b3923b2-4cb1-4020-a875-9a12a8ac6e5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162328433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all _with_rand_reset.3162328433 |
| Directory | /workspace/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.3922989816 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 470624560 ps |
| CPU time | 169.23 seconds |
| Started | Feb 07 04:20:11 PM PST 24 |
| Finished | Feb 07 04:23:01 PM PST 24 |
| Peak memory | 559224 kb |
| Host | smart-2d631aea-8d43-4ead-b2c5-bb5c8d865645 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922989816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_al l_with_reset_error.3922989816 |
| Directory | /workspace/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.104364536 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 133807994 ps |
| CPU time | 17.18 seconds |
| Started | Feb 07 04:20:11 PM PST 24 |
| Finished | Feb 07 04:20:29 PM PST 24 |
| Peak memory | 555368 kb |
| Host | smart-2d03a8ab-3107-4f16-b024-969a32b49a80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104364536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.104364536 |
| Directory | /workspace/67.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device.146000688 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 1228256621 ps |
| CPU time | 43.76 seconds |
| Started | Feb 07 04:20:15 PM PST 24 |
| Finished | Feb 07 04:21:00 PM PST 24 |
| Peak memory | 559164 kb |
| Host | smart-7d3d43c0-cda6-4ea3-a07b-794dcd01b8b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146000688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device. 146000688 |
| Directory | /workspace/68.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.4168740509 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 46616261189 ps |
| CPU time | 879.82 seconds |
| Started | Feb 07 04:20:14 PM PST 24 |
| Finished | Feb 07 04:34:54 PM PST 24 |
| Peak memory | 555492 kb |
| Host | smart-dc08f951-0ba2-4a1c-b84a-a3201b48fbc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168740509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_ device_slow_rsp.4168740509 |
| Directory | /workspace/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.2456142826 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 993036031 ps |
| CPU time | 36.53 seconds |
| Started | Feb 07 04:20:19 PM PST 24 |
| Finished | Feb 07 04:20:56 PM PST 24 |
| Peak memory | 555596 kb |
| Host | smart-70fa24df-d9ba-45e0-ad7e-be1528672021 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456142826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_add r.2456142826 |
| Directory | /workspace/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_random.999040501 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 203714639 ps |
| CPU time | 9.58 seconds |
| Started | Feb 07 04:20:11 PM PST 24 |
| Finished | Feb 07 04:20:21 PM PST 24 |
| Peak memory | 553592 kb |
| Host | smart-45494f56-203c-4deb-be60-4ae295ca117b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999040501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.999040501 |
| Directory | /workspace/68.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random.506041028 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 2483004150 ps |
| CPU time | 86.47 seconds |
| Started | Feb 07 04:20:16 PM PST 24 |
| Finished | Feb 07 04:21:44 PM PST 24 |
| Peak memory | 559256 kb |
| Host | smart-db26e3d7-f974-453f-b8fc-9a333e45eb5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506041028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.506041028 |
| Directory | /workspace/68.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.3121002638 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 15520457891 ps |
| CPU time | 186.12 seconds |
| Started | Feb 07 04:20:15 PM PST 24 |
| Finished | Feb 07 04:23:22 PM PST 24 |
| Peak memory | 555724 kb |
| Host | smart-c6bfbbf0-9a24-4b06-a3a5-e908210ff585 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121002638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.3121002638 |
| Directory | /workspace/68.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.4078617357 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 14791322696 ps |
| CPU time | 250.19 seconds |
| Started | Feb 07 04:20:12 PM PST 24 |
| Finished | Feb 07 04:24:23 PM PST 24 |
| Peak memory | 555064 kb |
| Host | smart-d16c956a-947c-4251-b554-6e896fb79105 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078617357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.4078617357 |
| Directory | /workspace/68.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.3723015117 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 329491502 ps |
| CPU time | 31.23 seconds |
| Started | Feb 07 04:20:13 PM PST 24 |
| Finished | Feb 07 04:20:45 PM PST 24 |
| Peak memory | 555676 kb |
| Host | smart-96c09669-f32d-4d0c-92bc-6e53e996c9ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723015117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_del ays.3723015117 |
| Directory | /workspace/68.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_same_source.93978377 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 553889496 ps |
| CPU time | 44.57 seconds |
| Started | Feb 07 04:20:11 PM PST 24 |
| Finished | Feb 07 04:20:56 PM PST 24 |
| Peak memory | 555356 kb |
| Host | smart-8426c42c-8150-455f-b7eb-7537650e44e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93978377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.93978377 |
| Directory | /workspace/68.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke.2633656910 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 42722674 ps |
| CPU time | 6 seconds |
| Started | Feb 07 04:20:12 PM PST 24 |
| Finished | Feb 07 04:20:19 PM PST 24 |
| Peak memory | 553552 kb |
| Host | smart-476649f1-636d-4287-9fe3-fbb10ff6215a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633656910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.2633656910 |
| Directory | /workspace/68.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.2496328524 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 8829542312 ps |
| CPU time | 90.14 seconds |
| Started | Feb 07 04:20:16 PM PST 24 |
| Finished | Feb 07 04:21:47 PM PST 24 |
| Peak memory | 553428 kb |
| Host | smart-b5095df6-9c22-4056-ab46-7e1290ba9faf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496328524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.2496328524 |
| Directory | /workspace/68.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.332612857 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 6770813616 ps |
| CPU time | 112.52 seconds |
| Started | Feb 07 04:20:14 PM PST 24 |
| Finished | Feb 07 04:22:07 PM PST 24 |
| Peak memory | 559192 kb |
| Host | smart-48793d3f-5992-495e-8e7f-0aef20d2aec2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332612857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.332612857 |
| Directory | /workspace/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.619386333 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 43261137 ps |
| CPU time | 6.22 seconds |
| Started | Feb 07 04:20:12 PM PST 24 |
| Finished | Feb 07 04:20:19 PM PST 24 |
| Peak memory | 553236 kb |
| Host | smart-7b3cfb6e-f4fc-4c05-a729-c719341060f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619386333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delays .619386333 |
| Directory | /workspace/68.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all.214248531 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 3548838030 ps |
| CPU time | 326.62 seconds |
| Started | Feb 07 04:20:20 PM PST 24 |
| Finished | Feb 07 04:25:47 PM PST 24 |
| Peak memory | 557732 kb |
| Host | smart-92229928-f1f9-4ac1-940a-f4a00e9272fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214248531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.214248531 |
| Directory | /workspace/68.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.2750288224 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 11959506094 ps |
| CPU time | 395.11 seconds |
| Started | Feb 07 04:20:20 PM PST 24 |
| Finished | Feb 07 04:26:56 PM PST 24 |
| Peak memory | 556880 kb |
| Host | smart-a4bdf646-127c-438c-a304-f008c249df63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750288224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.2750288224 |
| Directory | /workspace/68.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.1721632636 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 63549597 ps |
| CPU time | 18.05 seconds |
| Started | Feb 07 04:20:19 PM PST 24 |
| Finished | Feb 07 04:20:38 PM PST 24 |
| Peak memory | 555308 kb |
| Host | smart-a80a96f3-e38b-4c81-93ce-b68a97cba2f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721632636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all _with_rand_reset.1721632636 |
| Directory | /workspace/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.4174909120 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 452966760 ps |
| CPU time | 99.87 seconds |
| Started | Feb 07 04:20:27 PM PST 24 |
| Finished | Feb 07 04:22:08 PM PST 24 |
| Peak memory | 556492 kb |
| Host | smart-855dafa7-7ab4-4c5a-a9bf-d00a1a545e62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174909120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_al l_with_reset_error.4174909120 |
| Directory | /workspace/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.4292892428 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 1022847848 ps |
| CPU time | 41.18 seconds |
| Started | Feb 07 04:20:23 PM PST 24 |
| Finished | Feb 07 04:21:05 PM PST 24 |
| Peak memory | 555100 kb |
| Host | smart-9f480021-89d9-498d-91a8-dc5b2040ecd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292892428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.4292892428 |
| Directory | /workspace/68.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device.807147566 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 2454075552 ps |
| CPU time | 97.18 seconds |
| Started | Feb 07 04:20:19 PM PST 24 |
| Finished | Feb 07 04:21:56 PM PST 24 |
| Peak memory | 555728 kb |
| Host | smart-9bdc9179-01c1-4e0d-8fcf-c25c6a90bf3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807147566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device. 807147566 |
| Directory | /workspace/69.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.2261781470 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 108634874915 ps |
| CPU time | 1921.63 seconds |
| Started | Feb 07 04:20:22 PM PST 24 |
| Finished | Feb 07 04:52:25 PM PST 24 |
| Peak memory | 556588 kb |
| Host | smart-fd6878e0-2dd6-4a4f-8872-d8a4dfc6758a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261781470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_ device_slow_rsp.2261781470 |
| Directory | /workspace/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.1663056680 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 90943988 ps |
| CPU time | 12.58 seconds |
| Started | Feb 07 04:20:23 PM PST 24 |
| Finished | Feb 07 04:20:36 PM PST 24 |
| Peak memory | 555344 kb |
| Host | smart-2114b46e-7265-48a8-80c8-ab0660c0365d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663056680 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_add r.1663056680 |
| Directory | /workspace/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_random.1383929541 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 518400159 ps |
| CPU time | 41.79 seconds |
| Started | Feb 07 04:20:21 PM PST 24 |
| Finished | Feb 07 04:21:03 PM PST 24 |
| Peak memory | 555680 kb |
| Host | smart-726b9ec3-4af8-467e-bfc5-b404713d450f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383929541 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.1383929541 |
| Directory | /workspace/69.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random.3371994013 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 92209308 ps |
| CPU time | 9.38 seconds |
| Started | Feb 07 04:20:23 PM PST 24 |
| Finished | Feb 07 04:20:33 PM PST 24 |
| Peak memory | 555364 kb |
| Host | smart-fdad2c38-d08c-4a66-91a2-abae1fa44049 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371994013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.3371994013 |
| Directory | /workspace/69.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.2406490553 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 75434782793 ps |
| CPU time | 837.39 seconds |
| Started | Feb 07 04:20:20 PM PST 24 |
| Finished | Feb 07 04:34:19 PM PST 24 |
| Peak memory | 555464 kb |
| Host | smart-27bfa8c2-75c8-4062-9946-5a59a483823e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406490553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.2406490553 |
| Directory | /workspace/69.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.2107031946 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 34003175984 ps |
| CPU time | 565.49 seconds |
| Started | Feb 07 04:20:20 PM PST 24 |
| Finished | Feb 07 04:29:46 PM PST 24 |
| Peak memory | 555300 kb |
| Host | smart-324817a3-72d6-4aea-8d0d-0cd66f209bd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107031946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.2107031946 |
| Directory | /workspace/69.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.4164027999 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 72889149 ps |
| CPU time | 7.85 seconds |
| Started | Feb 07 04:20:23 PM PST 24 |
| Finished | Feb 07 04:20:31 PM PST 24 |
| Peak memory | 554324 kb |
| Host | smart-5a265976-5998-4793-ae78-587a5ab5ec37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164027999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_del ays.4164027999 |
| Directory | /workspace/69.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_same_source.4008842423 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 506528564 ps |
| CPU time | 37.06 seconds |
| Started | Feb 07 04:20:21 PM PST 24 |
| Finished | Feb 07 04:20:59 PM PST 24 |
| Peak memory | 555596 kb |
| Host | smart-ac80fac4-3947-47a8-8425-ea80e116d08f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008842423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.4008842423 |
| Directory | /workspace/69.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke.2599780126 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 186144916 ps |
| CPU time | 8.43 seconds |
| Started | Feb 07 04:20:18 PM PST 24 |
| Finished | Feb 07 04:20:27 PM PST 24 |
| Peak memory | 553452 kb |
| Host | smart-f0a2f9b5-e79d-4e01-b717-b3434e449b87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599780126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.2599780126 |
| Directory | /workspace/69.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.2528182421 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 5429976797 ps |
| CPU time | 57.82 seconds |
| Started | Feb 07 04:20:20 PM PST 24 |
| Finished | Feb 07 04:21:18 PM PST 24 |
| Peak memory | 553688 kb |
| Host | smart-ab7199af-4f9e-497b-bf3b-53056237ac40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528182421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.2528182421 |
| Directory | /workspace/69.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.3499250731 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 5805118856 ps |
| CPU time | 101.95 seconds |
| Started | Feb 07 04:20:21 PM PST 24 |
| Finished | Feb 07 04:22:03 PM PST 24 |
| Peak memory | 559224 kb |
| Host | smart-7fa2597b-67af-4e25-8e48-f208e3e93c47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499250731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.3499250731 |
| Directory | /workspace/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.2610209236 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 49665464 ps |
| CPU time | 6.01 seconds |
| Started | Feb 07 04:20:21 PM PST 24 |
| Finished | Feb 07 04:20:27 PM PST 24 |
| Peak memory | 553336 kb |
| Host | smart-4c6d547a-1632-48cc-8ed7-19bab119ea64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610209236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delay s.2610209236 |
| Directory | /workspace/69.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all.2241539871 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 5156182528 ps |
| CPU time | 420.04 seconds |
| Started | Feb 07 04:20:36 PM PST 24 |
| Finished | Feb 07 04:27:36 PM PST 24 |
| Peak memory | 557292 kb |
| Host | smart-780a363e-829c-4cb7-9629-50f56454a3de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241539871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.2241539871 |
| Directory | /workspace/69.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.593951120 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 15016552116 ps |
| CPU time | 551.74 seconds |
| Started | Feb 07 04:20:34 PM PST 24 |
| Finished | Feb 07 04:29:47 PM PST 24 |
| Peak memory | 556588 kb |
| Host | smart-6bce8903-939e-4531-b55f-a865894672d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593951120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.593951120 |
| Directory | /workspace/69.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.3705330491 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 679430093 ps |
| CPU time | 271.74 seconds |
| Started | Feb 07 04:20:33 PM PST 24 |
| Finished | Feb 07 04:25:05 PM PST 24 |
| Peak memory | 557624 kb |
| Host | smart-725078da-c060-4fe9-b7f3-101b49a9434d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705330491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_rand_reset.3705330491 |
| Directory | /workspace/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.4233975927 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 1180901053 ps |
| CPU time | 107.1 seconds |
| Started | Feb 07 04:20:36 PM PST 24 |
| Finished | Feb 07 04:22:24 PM PST 24 |
| Peak memory | 556352 kb |
| Host | smart-152795ca-231a-442c-bc64-a8503aed11f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233975927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_al l_with_reset_error.4233975927 |
| Directory | /workspace/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.1899202432 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 554186287 ps |
| CPU time | 25.38 seconds |
| Started | Feb 07 04:20:28 PM PST 24 |
| Finished | Feb 07 04:20:53 PM PST 24 |
| Peak memory | 559192 kb |
| Host | smart-2e4c33dd-e76d-4fc2-ab88-6b8ddd2b8401 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899202432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.1899202432 |
| Directory | /workspace/69.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.2341665164 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 5393662003 ps |
| CPU time | 206.14 seconds |
| Started | Feb 07 04:12:12 PM PST 24 |
| Finished | Feb 07 04:15:38 PM PST 24 |
| Peak memory | 613532 kb |
| Host | smart-5d4fb8d3-c57e-4771-9478-c2acbb6a6158 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341665164 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 7.chip_csr_mem_rw_with_rand_reset.2341665164 |
| Directory | /workspace/7.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_rw.2685543447 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 4991772440 ps |
| CPU time | 344.42 seconds |
| Started | Feb 07 04:11:56 PM PST 24 |
| Finished | Feb 07 04:17:41 PM PST 24 |
| Peak memory | 580272 kb |
| Host | smart-bab26d33-e029-475a-8c80-d51bd66ddf99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685543447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.2685543447 |
| Directory | /workspace/7.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.4125735999 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 31862408657 ps |
| CPU time | 3555.32 seconds |
| Started | Feb 07 04:11:57 PM PST 24 |
| Finished | Feb 07 05:11:13 PM PST 24 |
| Peak memory | 580300 kb |
| Host | smart-6fc196b4-88ec-4b1f-abbd-81f9f8c53cf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125735999 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.4125735999 |
| Directory | /workspace/7.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_tl_errors.605142396 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 2567030663 ps |
| CPU time | 77.34 seconds |
| Started | Feb 07 04:11:57 PM PST 24 |
| Finished | Feb 07 04:13:15 PM PST 24 |
| Peak memory | 580320 kb |
| Host | smart-c917c919-a6f5-46cf-994b-a2dad3de7809 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605142396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.605142396 |
| Directory | /workspace/7.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device.1414914731 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 592649905 ps |
| CPU time | 38.84 seconds |
| Started | Feb 07 04:12:05 PM PST 24 |
| Finished | Feb 07 04:12:45 PM PST 24 |
| Peak memory | 555668 kb |
| Host | smart-e498f408-38e4-4761-bef5-535738c26611 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414914731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device. 1414914731 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.4192999994 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 34700853534 ps |
| CPU time | 576.94 seconds |
| Started | Feb 07 04:12:06 PM PST 24 |
| Finished | Feb 07 04:21:43 PM PST 24 |
| Peak memory | 555416 kb |
| Host | smart-8441512d-8276-4795-9ee1-4dd356215c55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192999994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_d evice_slow_rsp.4192999994 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.2186085454 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 63665197 ps |
| CPU time | 5.69 seconds |
| Started | Feb 07 04:11:57 PM PST 24 |
| Finished | Feb 07 04:12:03 PM PST 24 |
| Peak memory | 553568 kb |
| Host | smart-1b2d035b-acb0-4e87-8a03-7a615bc8f6ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186085454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr .2186085454 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_random.1616620472 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 24531540 ps |
| CPU time | 4.94 seconds |
| Started | Feb 07 04:11:52 PM PST 24 |
| Finished | Feb 07 04:11:57 PM PST 24 |
| Peak memory | 553176 kb |
| Host | smart-be175c6c-20e8-4069-bfe7-2bc3581fb723 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616620472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.1616620472 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random.2374603059 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 180065071 ps |
| CPU time | 9.02 seconds |
| Started | Feb 07 04:12:02 PM PST 24 |
| Finished | Feb 07 04:12:11 PM PST 24 |
| Peak memory | 553512 kb |
| Host | smart-9768be27-6c8c-4c2b-b718-0ffa126c00d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374603059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.2374603059 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.3097208637 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 105836046923 ps |
| CPU time | 1073.37 seconds |
| Started | Feb 07 04:11:56 PM PST 24 |
| Finished | Feb 07 04:29:50 PM PST 24 |
| Peak memory | 555704 kb |
| Host | smart-2935891a-f7c5-4da7-aa88-ee06334d5149 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097208637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3097208637 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.2248659502 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 55902716071 ps |
| CPU time | 972.13 seconds |
| Started | Feb 07 04:11:58 PM PST 24 |
| Finished | Feb 07 04:28:11 PM PST 24 |
| Peak memory | 555700 kb |
| Host | smart-b19ad586-a551-48b3-b9f7-efcf1888f078 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248659502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.2248659502 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.4236306730 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 495239887 ps |
| CPU time | 47.99 seconds |
| Started | Feb 07 04:11:59 PM PST 24 |
| Finished | Feb 07 04:12:47 PM PST 24 |
| Peak memory | 555696 kb |
| Host | smart-dda6ee56-7f11-413f-a72a-7697d7d6b2b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236306730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_dela ys.4236306730 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_same_source.2585905184 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 974595201 ps |
| CPU time | 31.17 seconds |
| Started | Feb 07 04:12:00 PM PST 24 |
| Finished | Feb 07 04:12:32 PM PST 24 |
| Peak memory | 555264 kb |
| Host | smart-65cb2b6c-756c-494c-88a8-9fefafb7de30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585905184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2585905184 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke.3277399816 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 205271056 ps |
| CPU time | 9.33 seconds |
| Started | Feb 07 04:12:01 PM PST 24 |
| Finished | Feb 07 04:12:11 PM PST 24 |
| Peak memory | 553320 kb |
| Host | smart-f8c25774-4b4a-4c72-9364-db740a0171b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277399816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.3277399816 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.3973248670 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 10108146314 ps |
| CPU time | 110.26 seconds |
| Started | Feb 07 04:11:53 PM PST 24 |
| Finished | Feb 07 04:13:44 PM PST 24 |
| Peak memory | 553696 kb |
| Host | smart-a21b932c-89d0-4f9f-a63d-f43a010ebb9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973248670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.3973248670 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.1618568869 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 5901081830 ps |
| CPU time | 102.48 seconds |
| Started | Feb 07 04:11:59 PM PST 24 |
| Finished | Feb 07 04:13:42 PM PST 24 |
| Peak memory | 553676 kb |
| Host | smart-c4a5baad-095e-4a10-b143-fb06e293d514 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618568869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.1618568869 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.2845063901 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 50388739 ps |
| CPU time | 5.99 seconds |
| Started | Feb 07 04:11:55 PM PST 24 |
| Finished | Feb 07 04:12:01 PM PST 24 |
| Peak memory | 553044 kb |
| Host | smart-4f57d132-3e80-42da-bfe9-c032f3b8078e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845063901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays .2845063901 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all.1431771782 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 1298223884 ps |
| CPU time | 93.34 seconds |
| Started | Feb 07 04:12:02 PM PST 24 |
| Finished | Feb 07 04:13:35 PM PST 24 |
| Peak memory | 557832 kb |
| Host | smart-7606e319-0d59-47cd-8f67-f151b17bbf0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431771782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.1431771782 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.2265482884 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 14059701790 ps |
| CPU time | 480.45 seconds |
| Started | Feb 07 04:11:56 PM PST 24 |
| Finished | Feb 07 04:19:57 PM PST 24 |
| Peak memory | 556648 kb |
| Host | smart-815a4f7c-9335-4cc0-b18d-f84fe31ca9d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265482884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2265482884 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.1838329452 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 799800848 ps |
| CPU time | 112.95 seconds |
| Started | Feb 07 04:12:00 PM PST 24 |
| Finished | Feb 07 04:13:54 PM PST 24 |
| Peak memory | 556856 kb |
| Host | smart-709cbe0a-526d-4df8-8cf8-c6b1c856c802 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838329452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_ with_rand_reset.1838329452 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.1846075759 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 512531252 ps |
| CPU time | 23.33 seconds |
| Started | Feb 07 04:11:58 PM PST 24 |
| Finished | Feb 07 04:12:22 PM PST 24 |
| Peak memory | 555512 kb |
| Host | smart-c848e45e-e6a0-4094-8190-ac0a5b35a809 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846075759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.1846075759 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.1375599505 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 1374218067 ps |
| CPU time | 47.25 seconds |
| Started | Feb 07 04:20:33 PM PST 24 |
| Finished | Feb 07 04:21:20 PM PST 24 |
| Peak memory | 554576 kb |
| Host | smart-7872fdff-5f83-4bc7-8a6b-1ce4bacf3577 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375599505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device .1375599505 |
| Directory | /workspace/70.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.1902389605 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 57160316445 ps |
| CPU time | 999.61 seconds |
| Started | Feb 07 04:20:34 PM PST 24 |
| Finished | Feb 07 04:37:14 PM PST 24 |
| Peak memory | 556812 kb |
| Host | smart-11a3c467-30f2-4d28-8775-ebbf4982e9f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902389605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_ device_slow_rsp.1902389605 |
| Directory | /workspace/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.2296383422 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 19977108 ps |
| CPU time | 5.37 seconds |
| Started | Feb 07 04:20:39 PM PST 24 |
| Finished | Feb 07 04:20:45 PM PST 24 |
| Peak memory | 553252 kb |
| Host | smart-be741c72-ff9f-48dc-a01a-a150dc88ff2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296383422 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_add r.2296383422 |
| Directory | /workspace/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_random.2711490773 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 453940185 ps |
| CPU time | 37.79 seconds |
| Started | Feb 07 04:20:35 PM PST 24 |
| Finished | Feb 07 04:21:13 PM PST 24 |
| Peak memory | 555352 kb |
| Host | smart-574e9e2b-97fe-4b24-97a4-d96c97fd5e59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711490773 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.2711490773 |
| Directory | /workspace/70.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random.963214735 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 1633338231 ps |
| CPU time | 55.14 seconds |
| Started | Feb 07 04:20:33 PM PST 24 |
| Finished | Feb 07 04:21:28 PM PST 24 |
| Peak memory | 555388 kb |
| Host | smart-79f2f87c-eaae-4401-bb95-002ff454a80d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963214735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.963214735 |
| Directory | /workspace/70.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.3752500072 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 4191544613 ps |
| CPU time | 48.61 seconds |
| Started | Feb 07 04:20:34 PM PST 24 |
| Finished | Feb 07 04:21:23 PM PST 24 |
| Peak memory | 553672 kb |
| Host | smart-897c8506-022f-4d2d-8563-403b00c4b784 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752500072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.3752500072 |
| Directory | /workspace/70.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.1028055784 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 63464441436 ps |
| CPU time | 1205.44 seconds |
| Started | Feb 07 04:20:35 PM PST 24 |
| Finished | Feb 07 04:40:41 PM PST 24 |
| Peak memory | 555720 kb |
| Host | smart-006fa2e3-a8ac-4115-afe9-bde929bfd5e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028055784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.1028055784 |
| Directory | /workspace/70.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.1557860680 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 444940551 ps |
| CPU time | 39.97 seconds |
| Started | Feb 07 04:20:35 PM PST 24 |
| Finished | Feb 07 04:21:15 PM PST 24 |
| Peak memory | 555640 kb |
| Host | smart-17e9fda9-5377-4028-9e36-8c8afb1079cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557860680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_del ays.1557860680 |
| Directory | /workspace/70.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_same_source.740487797 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 344421784 ps |
| CPU time | 29.21 seconds |
| Started | Feb 07 04:20:38 PM PST 24 |
| Finished | Feb 07 04:21:08 PM PST 24 |
| Peak memory | 555344 kb |
| Host | smart-b6405bfc-927d-4350-84d8-af067e76343c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740487797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.740487797 |
| Directory | /workspace/70.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke.3598305163 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 168556816 ps |
| CPU time | 8.27 seconds |
| Started | Feb 07 04:20:34 PM PST 24 |
| Finished | Feb 07 04:20:42 PM PST 24 |
| Peak memory | 559064 kb |
| Host | smart-a016e9bf-fea1-4a87-aa9d-addef2499460 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598305163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.3598305163 |
| Directory | /workspace/70.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.2490207644 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 9657498955 ps |
| CPU time | 105.29 seconds |
| Started | Feb 07 04:20:31 PM PST 24 |
| Finished | Feb 07 04:22:17 PM PST 24 |
| Peak memory | 553676 kb |
| Host | smart-420ded29-b22c-492c-a931-8d148cc71a96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490207644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.2490207644 |
| Directory | /workspace/70.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.400314627 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 4656709944 ps |
| CPU time | 79.94 seconds |
| Started | Feb 07 04:20:33 PM PST 24 |
| Finished | Feb 07 04:21:53 PM PST 24 |
| Peak memory | 553332 kb |
| Host | smart-6176bd53-4317-41c2-b108-aeff0c4e71e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400314627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.400314627 |
| Directory | /workspace/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.742377945 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 56252744 ps |
| CPU time | 6.51 seconds |
| Started | Feb 07 04:20:32 PM PST 24 |
| Finished | Feb 07 04:20:39 PM PST 24 |
| Peak memory | 553600 kb |
| Host | smart-a2f05025-217f-4902-a73c-44deee160ec9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742377945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delays .742377945 |
| Directory | /workspace/70.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all.2157220214 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 8706352696 ps |
| CPU time | 355.86 seconds |
| Started | Feb 07 04:20:38 PM PST 24 |
| Finished | Feb 07 04:26:34 PM PST 24 |
| Peak memory | 556800 kb |
| Host | smart-045f7b99-0126-4d17-b10b-a186e9f7b9e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157220214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.2157220214 |
| Directory | /workspace/70.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.3778798448 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 2932250264 ps |
| CPU time | 113.65 seconds |
| Started | Feb 07 04:20:43 PM PST 24 |
| Finished | Feb 07 04:22:37 PM PST 24 |
| Peak memory | 555360 kb |
| Host | smart-75a56330-036f-43e1-8474-406af209988d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778798448 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.3778798448 |
| Directory | /workspace/70.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.2280268810 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 645408233 ps |
| CPU time | 250.04 seconds |
| Started | Feb 07 04:20:39 PM PST 24 |
| Finished | Feb 07 04:24:49 PM PST 24 |
| Peak memory | 557860 kb |
| Host | smart-8111ee0a-9ebe-4625-8d3c-45d34051065a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280268810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_rand_reset.2280268810 |
| Directory | /workspace/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.2228248452 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 278461891 ps |
| CPU time | 88.67 seconds |
| Started | Feb 07 04:20:36 PM PST 24 |
| Finished | Feb 07 04:22:05 PM PST 24 |
| Peak memory | 556868 kb |
| Host | smart-1f9b1dff-00c7-4a19-8952-b0e33b64128a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228248452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_al l_with_reset_error.2228248452 |
| Directory | /workspace/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.3559270457 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 1055737430 ps |
| CPU time | 40.52 seconds |
| Started | Feb 07 04:20:40 PM PST 24 |
| Finished | Feb 07 04:21:21 PM PST 24 |
| Peak memory | 555652 kb |
| Host | smart-e1c9b3b9-083d-4621-b9c4-b00655c6b42c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559270457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.3559270457 |
| Directory | /workspace/70.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device.3391326759 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 1807208551 ps |
| CPU time | 70.87 seconds |
| Started | Feb 07 04:20:46 PM PST 24 |
| Finished | Feb 07 04:21:57 PM PST 24 |
| Peak memory | 555336 kb |
| Host | smart-39d73b7b-5e32-4345-87d1-918e94adb8b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391326759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device .3391326759 |
| Directory | /workspace/71.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.3050983345 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 90887281258 ps |
| CPU time | 1771.5 seconds |
| Started | Feb 07 04:20:52 PM PST 24 |
| Finished | Feb 07 04:50:24 PM PST 24 |
| Peak memory | 555352 kb |
| Host | smart-2083c8db-a58c-4bcb-aaba-abca21c70963 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050983345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_ device_slow_rsp.3050983345 |
| Directory | /workspace/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.163628398 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 83037621 ps |
| CPU time | 12.49 seconds |
| Started | Feb 07 04:20:53 PM PST 24 |
| Finished | Feb 07 04:21:06 PM PST 24 |
| Peak memory | 555628 kb |
| Host | smart-232f3108-18c0-4e42-9c4d-ae89e12ba867 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163628398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_addr .163628398 |
| Directory | /workspace/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_random.4058561853 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 674166137 ps |
| CPU time | 25.47 seconds |
| Started | Feb 07 04:20:44 PM PST 24 |
| Finished | Feb 07 04:21:10 PM PST 24 |
| Peak memory | 555600 kb |
| Host | smart-2c48911b-ec8a-4c0c-b207-2503b1169b63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058561853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.4058561853 |
| Directory | /workspace/71.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random.4267809339 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 386676164 ps |
| CPU time | 16.85 seconds |
| Started | Feb 07 04:20:40 PM PST 24 |
| Finished | Feb 07 04:20:57 PM PST 24 |
| Peak memory | 555636 kb |
| Host | smart-7a5d9b39-71c8-4c5d-b8ef-2bb1d07e8c4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267809339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.4267809339 |
| Directory | /workspace/71.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.573432927 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 79543355398 ps |
| CPU time | 935.09 seconds |
| Started | Feb 07 04:20:42 PM PST 24 |
| Finished | Feb 07 04:36:17 PM PST 24 |
| Peak memory | 555440 kb |
| Host | smart-27724308-85b9-4fa9-9948-827ff2e2e0bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573432927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.573432927 |
| Directory | /workspace/71.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.3624089513 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 62171360811 ps |
| CPU time | 1142.72 seconds |
| Started | Feb 07 04:20:51 PM PST 24 |
| Finished | Feb 07 04:39:54 PM PST 24 |
| Peak memory | 555756 kb |
| Host | smart-0dea0aca-ac21-43c2-bb2c-56d551cdf1d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624089513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.3624089513 |
| Directory | /workspace/71.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.2967708830 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 218860494 ps |
| CPU time | 21.7 seconds |
| Started | Feb 07 04:20:41 PM PST 24 |
| Finished | Feb 07 04:21:04 PM PST 24 |
| Peak memory | 555416 kb |
| Host | smart-11e8cffb-f650-44f0-ba6f-9bbf4f6c3811 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967708830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_del ays.2967708830 |
| Directory | /workspace/71.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_same_source.3819569705 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 202070889 ps |
| CPU time | 15.25 seconds |
| Started | Feb 07 04:20:50 PM PST 24 |
| Finished | Feb 07 04:21:06 PM PST 24 |
| Peak memory | 555404 kb |
| Host | smart-716a94dc-1b32-4d1b-afb1-2fef721a850d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819569705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.3819569705 |
| Directory | /workspace/71.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke.1612717591 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 212939722 ps |
| CPU time | 8.47 seconds |
| Started | Feb 07 04:20:37 PM PST 24 |
| Finished | Feb 07 04:20:46 PM PST 24 |
| Peak memory | 552984 kb |
| Host | smart-28d36a79-f419-49fc-8344-02f247c01bef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612717591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.1612717591 |
| Directory | /workspace/71.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.2256439800 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 7254692069 ps |
| CPU time | 78.9 seconds |
| Started | Feb 07 04:20:36 PM PST 24 |
| Finished | Feb 07 04:21:55 PM PST 24 |
| Peak memory | 553408 kb |
| Host | smart-aaea6635-1593-40c5-a630-0949079ec638 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256439800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.2256439800 |
| Directory | /workspace/71.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.3887248872 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 5459960254 ps |
| CPU time | 98.55 seconds |
| Started | Feb 07 04:20:39 PM PST 24 |
| Finished | Feb 07 04:22:18 PM PST 24 |
| Peak memory | 553376 kb |
| Host | smart-22b4115b-f49c-49f7-b568-8e21167a519a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887248872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.3887248872 |
| Directory | /workspace/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.2243503525 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 53090519 ps |
| CPU time | 6.89 seconds |
| Started | Feb 07 04:20:35 PM PST 24 |
| Finished | Feb 07 04:20:42 PM PST 24 |
| Peak memory | 553592 kb |
| Host | smart-60992fc8-065a-4313-a35e-25daf1b3a518 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243503525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delay s.2243503525 |
| Directory | /workspace/71.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all.502413193 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 1364699628 ps |
| CPU time | 109.41 seconds |
| Started | Feb 07 04:20:53 PM PST 24 |
| Finished | Feb 07 04:22:43 PM PST 24 |
| Peak memory | 559264 kb |
| Host | smart-2f35a657-8eaf-4c35-940e-a6a2ee18f754 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502413193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.502413193 |
| Directory | /workspace/71.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.1570325878 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 1760185535 ps |
| CPU time | 167.89 seconds |
| Started | Feb 07 04:20:47 PM PST 24 |
| Finished | Feb 07 04:23:35 PM PST 24 |
| Peak memory | 556492 kb |
| Host | smart-254ddf5c-eaa2-49e9-8cf0-5b5606064918 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570325878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.1570325878 |
| Directory | /workspace/71.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.2319555130 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 230749543 ps |
| CPU time | 183.32 seconds |
| Started | Feb 07 04:20:54 PM PST 24 |
| Finished | Feb 07 04:23:57 PM PST 24 |
| Peak memory | 559340 kb |
| Host | smart-56706249-c65b-45cc-ac44-5a0baf9f68f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319555130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_rand_reset.2319555130 |
| Directory | /workspace/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.2237651994 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 716063764 ps |
| CPU time | 187.78 seconds |
| Started | Feb 07 04:20:46 PM PST 24 |
| Finished | Feb 07 04:23:54 PM PST 24 |
| Peak memory | 559348 kb |
| Host | smart-e1e8f8a1-ffb5-42a8-9726-7e4d80373529 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237651994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_al l_with_reset_error.2237651994 |
| Directory | /workspace/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.2024259302 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 122486594 ps |
| CPU time | 17.62 seconds |
| Started | Feb 07 04:20:47 PM PST 24 |
| Finished | Feb 07 04:21:05 PM PST 24 |
| Peak memory | 555452 kb |
| Host | smart-f60fb07c-e646-412a-9110-1ba71b0a887a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024259302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.2024259302 |
| Directory | /workspace/71.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device.1534847216 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 1597990249 ps |
| CPU time | 63.96 seconds |
| Started | Feb 07 04:20:54 PM PST 24 |
| Finished | Feb 07 04:21:58 PM PST 24 |
| Peak memory | 555620 kb |
| Host | smart-9bf355c7-ef5f-459b-9b8c-765a3981bd34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534847216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device .1534847216 |
| Directory | /workspace/72.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.2590103698 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 133433719176 ps |
| CPU time | 2651.95 seconds |
| Started | Feb 07 04:20:55 PM PST 24 |
| Finished | Feb 07 05:05:08 PM PST 24 |
| Peak memory | 556320 kb |
| Host | smart-37ca0be9-5e53-4bca-91ef-4a7f6dc192d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590103698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_ device_slow_rsp.2590103698 |
| Directory | /workspace/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.3647229066 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 194438107 ps |
| CPU time | 10.34 seconds |
| Started | Feb 07 04:20:54 PM PST 24 |
| Finished | Feb 07 04:21:05 PM PST 24 |
| Peak memory | 553324 kb |
| Host | smart-42a3c746-a510-443e-8f81-9205b3440185 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647229066 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add r.3647229066 |
| Directory | /workspace/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_random.1306986883 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 98212225 ps |
| CPU time | 10.64 seconds |
| Started | Feb 07 04:20:58 PM PST 24 |
| Finished | Feb 07 04:21:09 PM PST 24 |
| Peak memory | 555620 kb |
| Host | smart-146d47de-b596-4b1c-b12d-86fbbdcb4fda |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306986883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.1306986883 |
| Directory | /workspace/72.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random.1371378476 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 2107200594 ps |
| CPU time | 69.11 seconds |
| Started | Feb 07 04:20:46 PM PST 24 |
| Finished | Feb 07 04:21:55 PM PST 24 |
| Peak memory | 555428 kb |
| Host | smart-4ef804fd-f1e1-4aa0-b406-858cea923712 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371378476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.1371378476 |
| Directory | /workspace/72.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.745323171 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 29187902539 ps |
| CPU time | 321.34 seconds |
| Started | Feb 07 04:20:56 PM PST 24 |
| Finished | Feb 07 04:26:17 PM PST 24 |
| Peak memory | 555452 kb |
| Host | smart-4af0e31f-a6dc-4970-ba29-b84ad205136f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745323171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.745323171 |
| Directory | /workspace/72.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.912398068 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 38094724121 ps |
| CPU time | 638.37 seconds |
| Started | Feb 07 04:20:49 PM PST 24 |
| Finished | Feb 07 04:31:27 PM PST 24 |
| Peak memory | 555528 kb |
| Host | smart-a645dd86-5082-4cea-81f5-d229d114a881 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912398068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.912398068 |
| Directory | /workspace/72.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.1067041580 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 309913257 ps |
| CPU time | 29.53 seconds |
| Started | Feb 07 04:20:52 PM PST 24 |
| Finished | Feb 07 04:21:22 PM PST 24 |
| Peak memory | 555364 kb |
| Host | smart-d2856a76-a206-4695-af5a-c897fd58ab4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067041580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_del ays.1067041580 |
| Directory | /workspace/72.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_same_source.1720678604 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 272767160 ps |
| CPU time | 19.31 seconds |
| Started | Feb 07 04:20:53 PM PST 24 |
| Finished | Feb 07 04:21:12 PM PST 24 |
| Peak memory | 555360 kb |
| Host | smart-c530b2f5-e0f2-44ed-86d7-e9974059f4c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720678604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.1720678604 |
| Directory | /workspace/72.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke.2329341899 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 43140058 ps |
| CPU time | 5.9 seconds |
| Started | Feb 07 04:20:45 PM PST 24 |
| Finished | Feb 07 04:20:52 PM PST 24 |
| Peak memory | 559100 kb |
| Host | smart-eaa75b64-8a28-476f-a736-888dea60ee07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329341899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.2329341899 |
| Directory | /workspace/72.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.907553806 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 9223693901 ps |
| CPU time | 99.19 seconds |
| Started | Feb 07 04:20:47 PM PST 24 |
| Finished | Feb 07 04:22:27 PM PST 24 |
| Peak memory | 553684 kb |
| Host | smart-2620dcec-f4c5-4ef0-be22-bb9e53b3a5ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907553806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.907553806 |
| Directory | /workspace/72.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.1036253492 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 6004601141 ps |
| CPU time | 106.8 seconds |
| Started | Feb 07 04:20:48 PM PST 24 |
| Finished | Feb 07 04:22:35 PM PST 24 |
| Peak memory | 553392 kb |
| Host | smart-1d2bad9f-5b5e-4883-ac29-8b94892dc131 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036253492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.1036253492 |
| Directory | /workspace/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.3521620897 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 43212707 ps |
| CPU time | 6.43 seconds |
| Started | Feb 07 04:20:53 PM PST 24 |
| Finished | Feb 07 04:21:00 PM PST 24 |
| Peak memory | 553588 kb |
| Host | smart-e15a348f-4b24-49f2-b069-8fac2b0a185d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521620897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delay s.3521620897 |
| Directory | /workspace/72.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all.3276541981 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 12849522168 ps |
| CPU time | 514.4 seconds |
| Started | Feb 07 04:20:52 PM PST 24 |
| Finished | Feb 07 04:29:26 PM PST 24 |
| Peak memory | 558820 kb |
| Host | smart-05d3c903-5bae-4b2f-a2ee-156484137235 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276541981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.3276541981 |
| Directory | /workspace/72.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.3181632191 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 1027352589 ps |
| CPU time | 65.83 seconds |
| Started | Feb 07 04:21:13 PM PST 24 |
| Finished | Feb 07 04:22:20 PM PST 24 |
| Peak memory | 555496 kb |
| Host | smart-92ff4777-5028-4d49-8d06-eace36e63654 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181632191 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.3181632191 |
| Directory | /workspace/72.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.4175069247 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 799589958 ps |
| CPU time | 331.22 seconds |
| Started | Feb 07 04:20:56 PM PST 24 |
| Finished | Feb 07 04:26:28 PM PST 24 |
| Peak memory | 559016 kb |
| Host | smart-062f5289-54aa-4f7f-b53f-ebebcfa53d4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175069247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all _with_rand_reset.4175069247 |
| Directory | /workspace/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.298071713 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 4250226211 ps |
| CPU time | 421.35 seconds |
| Started | Feb 07 04:20:52 PM PST 24 |
| Finished | Feb 07 04:27:54 PM PST 24 |
| Peak memory | 558072 kb |
| Host | smart-0b159011-f058-4fe7-9752-2edace6b4442 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298071713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all _with_reset_error.298071713 |
| Directory | /workspace/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.1285220710 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 1148981811 ps |
| CPU time | 50.05 seconds |
| Started | Feb 07 04:20:54 PM PST 24 |
| Finished | Feb 07 04:21:45 PM PST 24 |
| Peak memory | 555352 kb |
| Host | smart-c14c7327-0c2e-4220-8ca0-8c3edd298f0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285220710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.1285220710 |
| Directory | /workspace/72.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device.70433801 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 493471313 ps |
| CPU time | 40.19 seconds |
| Started | Feb 07 04:21:00 PM PST 24 |
| Finished | Feb 07 04:21:41 PM PST 24 |
| Peak memory | 555628 kb |
| Host | smart-2bf1af67-96be-48ed-b3ea-579b49fa2442 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70433801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device.70433801 |
| Directory | /workspace/73.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.154185926 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 43459259702 ps |
| CPU time | 817.3 seconds |
| Started | Feb 07 04:21:01 PM PST 24 |
| Finished | Feb 07 04:34:39 PM PST 24 |
| Peak memory | 556744 kb |
| Host | smart-955896bd-e481-4e8b-abd6-f2862392eb0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154185926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_d evice_slow_rsp.154185926 |
| Directory | /workspace/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.1647988707 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 86377749 ps |
| CPU time | 11.15 seconds |
| Started | Feb 07 04:20:59 PM PST 24 |
| Finished | Feb 07 04:21:11 PM PST 24 |
| Peak memory | 555208 kb |
| Host | smart-4ecf0db9-71a3-4314-b6fd-d9abed7bb84f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647988707 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_add r.1647988707 |
| Directory | /workspace/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_random.2169759830 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 102469046 ps |
| CPU time | 10.2 seconds |
| Started | Feb 07 04:21:13 PM PST 24 |
| Finished | Feb 07 04:21:24 PM PST 24 |
| Peak memory | 555480 kb |
| Host | smart-08f83233-6091-4756-ac55-1c75c12bb19c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169759830 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.2169759830 |
| Directory | /workspace/73.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random.234280994 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 1852943512 ps |
| CPU time | 62.43 seconds |
| Started | Feb 07 04:20:52 PM PST 24 |
| Finished | Feb 07 04:21:55 PM PST 24 |
| Peak memory | 555400 kb |
| Host | smart-9a7997b1-d234-461c-9c06-76fc602f1fcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234280994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.234280994 |
| Directory | /workspace/73.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.1199371424 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 77973989909 ps |
| CPU time | 847.22 seconds |
| Started | Feb 07 04:20:59 PM PST 24 |
| Finished | Feb 07 04:35:06 PM PST 24 |
| Peak memory | 555728 kb |
| Host | smart-3e7f6cce-b837-42bf-94da-ad517d44aa49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199371424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.1199371424 |
| Directory | /workspace/73.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.1554711228 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 31428134321 ps |
| CPU time | 594.24 seconds |
| Started | Feb 07 04:20:58 PM PST 24 |
| Finished | Feb 07 04:30:52 PM PST 24 |
| Peak memory | 555448 kb |
| Host | smart-e1589e99-8aad-4928-a49a-c197df519edb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554711228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.1554711228 |
| Directory | /workspace/73.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.353144998 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 386743746 ps |
| CPU time | 37.24 seconds |
| Started | Feb 07 04:20:54 PM PST 24 |
| Finished | Feb 07 04:21:32 PM PST 24 |
| Peak memory | 555356 kb |
| Host | smart-74b37a19-2b7b-4834-a08f-2f4bf6abeb1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353144998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_dela ys.353144998 |
| Directory | /workspace/73.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_same_source.2480946990 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 970597252 ps |
| CPU time | 31.92 seconds |
| Started | Feb 07 04:20:59 PM PST 24 |
| Finished | Feb 07 04:21:31 PM PST 24 |
| Peak memory | 555656 kb |
| Host | smart-437440b7-2e8b-406b-bda3-f58ac2df2ea5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480946990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.2480946990 |
| Directory | /workspace/73.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke.348473311 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 49740745 ps |
| CPU time | 6.3 seconds |
| Started | Feb 07 04:20:53 PM PST 24 |
| Finished | Feb 07 04:20:59 PM PST 24 |
| Peak memory | 553200 kb |
| Host | smart-50f6ffc0-e799-476b-bc36-48cfe3b6503c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348473311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.348473311 |
| Directory | /workspace/73.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.191506323 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 9784689151 ps |
| CPU time | 108.75 seconds |
| Started | Feb 07 04:20:54 PM PST 24 |
| Finished | Feb 07 04:22:43 PM PST 24 |
| Peak memory | 553712 kb |
| Host | smart-a7cdcb50-6555-4654-ad7d-c6bc63946463 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191506323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.191506323 |
| Directory | /workspace/73.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.283051037 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 4107685814 ps |
| CPU time | 65.2 seconds |
| Started | Feb 07 04:21:13 PM PST 24 |
| Finished | Feb 07 04:22:19 PM PST 24 |
| Peak memory | 559060 kb |
| Host | smart-eb762e6e-c297-49fa-9e82-323132d3340c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283051037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.283051037 |
| Directory | /workspace/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.3216487966 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 46506060 ps |
| CPU time | 5.99 seconds |
| Started | Feb 07 04:21:13 PM PST 24 |
| Finished | Feb 07 04:21:20 PM PST 24 |
| Peak memory | 553140 kb |
| Host | smart-bb19b61c-f9e1-455d-b7f6-7f4c8e3014bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216487966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delay s.3216487966 |
| Directory | /workspace/73.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all.3904446336 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 3405714701 ps |
| CPU time | 259.04 seconds |
| Started | Feb 07 04:21:13 PM PST 24 |
| Finished | Feb 07 04:25:33 PM PST 24 |
| Peak memory | 557100 kb |
| Host | smart-8d085c2c-f970-4cfd-bccd-6bacd860422a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904446336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.3904446336 |
| Directory | /workspace/73.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.3523425555 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 10445367251 ps |
| CPU time | 355.48 seconds |
| Started | Feb 07 04:21:03 PM PST 24 |
| Finished | Feb 07 04:26:59 PM PST 24 |
| Peak memory | 557672 kb |
| Host | smart-e8315dea-11f7-4c45-aec1-6eb5d0b70698 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523425555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.3523425555 |
| Directory | /workspace/73.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.2599391343 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 201838674 ps |
| CPU time | 75.32 seconds |
| Started | Feb 07 04:21:04 PM PST 24 |
| Finished | Feb 07 04:22:20 PM PST 24 |
| Peak memory | 556880 kb |
| Host | smart-971d444d-3c20-47bb-a28f-fc43ecd3739d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599391343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all _with_rand_reset.2599391343 |
| Directory | /workspace/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.884216664 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 5033081713 ps |
| CPU time | 451.07 seconds |
| Started | Feb 07 04:21:00 PM PST 24 |
| Finished | Feb 07 04:28:31 PM PST 24 |
| Peak memory | 559396 kb |
| Host | smart-90de5fcc-269f-405e-a625-b0408e98ddce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884216664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all _with_reset_error.884216664 |
| Directory | /workspace/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.56211636 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 1216209145 ps |
| CPU time | 51.32 seconds |
| Started | Feb 07 04:21:03 PM PST 24 |
| Finished | Feb 07 04:21:54 PM PST 24 |
| Peak memory | 555400 kb |
| Host | smart-974244b8-443e-4d1b-8e2b-f7a042f31674 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56211636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.56211636 |
| Directory | /workspace/73.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device.3604425069 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 942619112 ps |
| CPU time | 74.61 seconds |
| Started | Feb 07 04:21:11 PM PST 24 |
| Finished | Feb 07 04:22:26 PM PST 24 |
| Peak memory | 555336 kb |
| Host | smart-9449a914-b6b5-48e2-aa57-253b20d1e015 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604425069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device .3604425069 |
| Directory | /workspace/74.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.4224964459 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 119978148426 ps |
| CPU time | 2413.67 seconds |
| Started | Feb 07 04:21:13 PM PST 24 |
| Finished | Feb 07 05:01:28 PM PST 24 |
| Peak memory | 555704 kb |
| Host | smart-1c95439a-ac05-4a52-9e31-f7d966bfbf72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224964459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_ device_slow_rsp.4224964459 |
| Directory | /workspace/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.726938268 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 644462508 ps |
| CPU time | 26.79 seconds |
| Started | Feb 07 04:21:12 PM PST 24 |
| Finished | Feb 07 04:21:39 PM PST 24 |
| Peak memory | 555388 kb |
| Host | smart-a46def8c-9a8e-4221-871c-7047ec48e8f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726938268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_addr .726938268 |
| Directory | /workspace/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_random.1930989247 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 177715125 ps |
| CPU time | 8.86 seconds |
| Started | Feb 07 04:21:11 PM PST 24 |
| Finished | Feb 07 04:21:20 PM PST 24 |
| Peak memory | 553576 kb |
| Host | smart-6b9eb27d-afe5-43f4-ae70-d93cad6f561d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930989247 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.1930989247 |
| Directory | /workspace/74.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random.1902535885 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 1737150635 ps |
| CPU time | 64.06 seconds |
| Started | Feb 07 04:21:00 PM PST 24 |
| Finished | Feb 07 04:22:04 PM PST 24 |
| Peak memory | 555376 kb |
| Host | smart-507ae46b-f5cd-48d5-82cd-2f5ba0dafe76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902535885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.1902535885 |
| Directory | /workspace/74.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.3779845712 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 85181673663 ps |
| CPU time | 1061.65 seconds |
| Started | Feb 07 04:21:13 PM PST 24 |
| Finished | Feb 07 04:38:55 PM PST 24 |
| Peak memory | 555164 kb |
| Host | smart-29aafc0b-3287-418a-b412-dc643a9cda45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779845712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.3779845712 |
| Directory | /workspace/74.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.2031098238 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 51042938855 ps |
| CPU time | 929.11 seconds |
| Started | Feb 07 04:21:14 PM PST 24 |
| Finished | Feb 07 04:36:43 PM PST 24 |
| Peak memory | 555432 kb |
| Host | smart-4a022f15-8664-43d2-8a40-64ad2e6c40d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031098238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.2031098238 |
| Directory | /workspace/74.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.1899859787 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 515147717 ps |
| CPU time | 45.4 seconds |
| Started | Feb 07 04:21:03 PM PST 24 |
| Finished | Feb 07 04:21:49 PM PST 24 |
| Peak memory | 555388 kb |
| Host | smart-e1751ab0-0ad4-4fe6-8ab8-4e9610791af9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899859787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_del ays.1899859787 |
| Directory | /workspace/74.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_same_source.1203633322 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 1847960257 ps |
| CPU time | 62.53 seconds |
| Started | Feb 07 04:21:11 PM PST 24 |
| Finished | Feb 07 04:22:14 PM PST 24 |
| Peak memory | 559196 kb |
| Host | smart-91c11282-7220-4a8f-be2a-c67dadafc065 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203633322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.1203633322 |
| Directory | /workspace/74.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke.3413266388 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 44061106 ps |
| CPU time | 6.31 seconds |
| Started | Feb 07 04:21:04 PM PST 24 |
| Finished | Feb 07 04:21:10 PM PST 24 |
| Peak memory | 559084 kb |
| Host | smart-db807497-05df-4623-951b-c0dd0d8e406b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413266388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.3413266388 |
| Directory | /workspace/74.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.283782003 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 11515213174 ps |
| CPU time | 115.69 seconds |
| Started | Feb 07 04:21:00 PM PST 24 |
| Finished | Feb 07 04:22:56 PM PST 24 |
| Peak memory | 553420 kb |
| Host | smart-a0b8bb8e-feca-4141-9e39-1a9f95750530 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283782003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.283782003 |
| Directory | /workspace/74.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.1231136661 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 6144741055 ps |
| CPU time | 104.26 seconds |
| Started | Feb 07 04:21:00 PM PST 24 |
| Finished | Feb 07 04:22:45 PM PST 24 |
| Peak memory | 553688 kb |
| Host | smart-a9093b60-e69a-452b-a906-207420af74eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231136661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.1231136661 |
| Directory | /workspace/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.224088953 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 39995858 ps |
| CPU time | 5.56 seconds |
| Started | Feb 07 04:21:01 PM PST 24 |
| Finished | Feb 07 04:21:07 PM PST 24 |
| Peak memory | 553572 kb |
| Host | smart-29b7adea-64d1-4256-83a1-17660f715318 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224088953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delays .224088953 |
| Directory | /workspace/74.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all.1346207034 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 1395378196 ps |
| CPU time | 131.13 seconds |
| Started | Feb 07 04:21:17 PM PST 24 |
| Finished | Feb 07 04:23:30 PM PST 24 |
| Peak memory | 556636 kb |
| Host | smart-7c0040dc-ea52-44d0-8004-551cb539bc6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346207034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.1346207034 |
| Directory | /workspace/74.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.1734556551 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 1717058765 ps |
| CPU time | 49.62 seconds |
| Started | Feb 07 04:21:21 PM PST 24 |
| Finished | Feb 07 04:22:12 PM PST 24 |
| Peak memory | 555588 kb |
| Host | smart-dd0d877e-0ec1-473f-8baf-245dff1a0f1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734556551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.1734556551 |
| Directory | /workspace/74.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.3863440561 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 5484356660 ps |
| CPU time | 710.31 seconds |
| Started | Feb 07 04:21:11 PM PST 24 |
| Finished | Feb 07 04:33:02 PM PST 24 |
| Peak memory | 557980 kb |
| Host | smart-59523546-d255-4425-8185-f03b4ef7939b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863440561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all _with_rand_reset.3863440561 |
| Directory | /workspace/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.2741767338 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 102257307 ps |
| CPU time | 89.55 seconds |
| Started | Feb 07 04:21:12 PM PST 24 |
| Finished | Feb 07 04:22:43 PM PST 24 |
| Peak memory | 556380 kb |
| Host | smart-43185b56-9876-42c3-bd83-025f0d4aa100 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741767338 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_al l_with_reset_error.2741767338 |
| Directory | /workspace/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.1327578402 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 229411469 ps |
| CPU time | 31.96 seconds |
| Started | Feb 07 04:21:10 PM PST 24 |
| Finished | Feb 07 04:21:43 PM PST 24 |
| Peak memory | 555340 kb |
| Host | smart-e01188ca-8323-41ac-8745-0c42c4e46e75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327578402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.1327578402 |
| Directory | /workspace/74.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device.141084418 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 2725863435 ps |
| CPU time | 107.36 seconds |
| Started | Feb 07 04:21:23 PM PST 24 |
| Finished | Feb 07 04:23:14 PM PST 24 |
| Peak memory | 555676 kb |
| Host | smart-f3c41b7a-ceb2-4cec-b79f-41500eb61186 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141084418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device. 141084418 |
| Directory | /workspace/75.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.935311879 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 63516179 ps |
| CPU time | 9.64 seconds |
| Started | Feb 07 04:21:13 PM PST 24 |
| Finished | Feb 07 04:21:24 PM PST 24 |
| Peak memory | 555612 kb |
| Host | smart-01d58d0f-bec5-44fa-a91d-a2e71bbb6427 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935311879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_addr .935311879 |
| Directory | /workspace/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_random.1196816767 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 2086828749 ps |
| CPU time | 76.3 seconds |
| Started | Feb 07 04:21:15 PM PST 24 |
| Finished | Feb 07 04:22:34 PM PST 24 |
| Peak memory | 555612 kb |
| Host | smart-c27a86c4-681c-43e7-84c3-9d578a615ab0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196816767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.1196816767 |
| Directory | /workspace/75.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random.3013449579 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 701972669 ps |
| CPU time | 26.99 seconds |
| Started | Feb 07 04:21:16 PM PST 24 |
| Finished | Feb 07 04:21:45 PM PST 24 |
| Peak memory | 555380 kb |
| Host | smart-816add4d-57b9-4605-94c2-87a81207d916 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013449579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.3013449579 |
| Directory | /workspace/75.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.1271210702 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 5777523196 ps |
| CPU time | 68.69 seconds |
| Started | Feb 07 04:21:18 PM PST 24 |
| Finished | Feb 07 04:22:27 PM PST 24 |
| Peak memory | 553692 kb |
| Host | smart-60983e21-de3a-4c2b-98bb-2a567d58defc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271210702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.1271210702 |
| Directory | /workspace/75.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.3394413717 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 37433203183 ps |
| CPU time | 692.34 seconds |
| Started | Feb 07 04:21:22 PM PST 24 |
| Finished | Feb 07 04:32:55 PM PST 24 |
| Peak memory | 555164 kb |
| Host | smart-18b9bd37-32e5-426b-ada9-f2bb12cd0221 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394413717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.3394413717 |
| Directory | /workspace/75.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.3652353204 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 557986440 ps |
| CPU time | 44.64 seconds |
| Started | Feb 07 04:21:15 PM PST 24 |
| Finished | Feb 07 04:22:03 PM PST 24 |
| Peak memory | 555176 kb |
| Host | smart-a5ba1675-4148-4e65-8736-5d2c7354d2aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652353204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_del ays.3652353204 |
| Directory | /workspace/75.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_same_source.719543531 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 1446670288 ps |
| CPU time | 40.06 seconds |
| Started | Feb 07 04:21:22 PM PST 24 |
| Finished | Feb 07 04:22:03 PM PST 24 |
| Peak memory | 555276 kb |
| Host | smart-8ddfd52b-2d78-4c4e-aaac-a0cec6c9beb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719543531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.719543531 |
| Directory | /workspace/75.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke.641147413 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 49535370 ps |
| CPU time | 6.29 seconds |
| Started | Feb 07 04:21:22 PM PST 24 |
| Finished | Feb 07 04:21:33 PM PST 24 |
| Peak memory | 553252 kb |
| Host | smart-464e8131-855b-4937-9c5b-1b6e7af3755e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641147413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.641147413 |
| Directory | /workspace/75.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.2406478412 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 9114010346 ps |
| CPU time | 90.58 seconds |
| Started | Feb 07 04:21:14 PM PST 24 |
| Finished | Feb 07 04:22:48 PM PST 24 |
| Peak memory | 553352 kb |
| Host | smart-251a70fd-d004-4606-af7c-ceb97fdb6953 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406478412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.2406478412 |
| Directory | /workspace/75.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.790286580 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 6416874720 ps |
| CPU time | 106.24 seconds |
| Started | Feb 07 04:21:18 PM PST 24 |
| Finished | Feb 07 04:23:05 PM PST 24 |
| Peak memory | 553400 kb |
| Host | smart-3a1d8265-c924-4500-94be-f13fd1b834ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790286580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.790286580 |
| Directory | /workspace/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.2367872175 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 46312639 ps |
| CPU time | 6.48 seconds |
| Started | Feb 07 04:21:15 PM PST 24 |
| Finished | Feb 07 04:21:25 PM PST 24 |
| Peak memory | 559180 kb |
| Host | smart-c43c0249-da2e-4a11-a43c-ef2a12da65b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367872175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delay s.2367872175 |
| Directory | /workspace/75.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all.3463924409 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 8809031084 ps |
| CPU time | 325.78 seconds |
| Started | Feb 07 04:21:34 PM PST 24 |
| Finished | Feb 07 04:27:01 PM PST 24 |
| Peak memory | 556984 kb |
| Host | smart-0c9822ab-2cc9-490e-ab77-d85e6ce84544 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463924409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.3463924409 |
| Directory | /workspace/75.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.2250586882 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 3075097248 ps |
| CPU time | 489.05 seconds |
| Started | Feb 07 04:21:23 PM PST 24 |
| Finished | Feb 07 04:29:36 PM PST 24 |
| Peak memory | 559364 kb |
| Host | smart-e9f065be-1182-487a-994f-b7febdea5509 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250586882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all _with_rand_reset.2250586882 |
| Directory | /workspace/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.3670996746 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 10136443365 ps |
| CPU time | 580.16 seconds |
| Started | Feb 07 04:21:29 PM PST 24 |
| Finished | Feb 07 04:31:11 PM PST 24 |
| Peak memory | 559376 kb |
| Host | smart-bdd6f2e8-9f43-4142-af5d-e3fe6d722242 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670996746 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al l_with_reset_error.3670996746 |
| Directory | /workspace/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.3651024473 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 1198158025 ps |
| CPU time | 49.7 seconds |
| Started | Feb 07 04:21:21 PM PST 24 |
| Finished | Feb 07 04:22:12 PM PST 24 |
| Peak memory | 555312 kb |
| Host | smart-04825646-432c-4722-a2c2-2d1f82214a42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651024473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.3651024473 |
| Directory | /workspace/75.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device.3791668745 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 749777630 ps |
| CPU time | 62.61 seconds |
| Started | Feb 07 04:21:34 PM PST 24 |
| Finished | Feb 07 04:22:38 PM PST 24 |
| Peak memory | 555384 kb |
| Host | smart-a9ac2d25-fe66-4860-b31f-8b32cec975a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791668745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device .3791668745 |
| Directory | /workspace/76.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.112919806 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 83327008609 ps |
| CPU time | 1686.43 seconds |
| Started | Feb 07 04:21:22 PM PST 24 |
| Finished | Feb 07 04:49:29 PM PST 24 |
| Peak memory | 556752 kb |
| Host | smart-0bdde580-303d-4536-8618-ce0e3cc129f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112919806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_d evice_slow_rsp.112919806 |
| Directory | /workspace/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.3148662754 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 268105755 ps |
| CPU time | 27.82 seconds |
| Started | Feb 07 04:21:31 PM PST 24 |
| Finished | Feb 07 04:21:59 PM PST 24 |
| Peak memory | 555224 kb |
| Host | smart-34638fed-2fc7-4cdd-baa8-a635cb5b66e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148662754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_add r.3148662754 |
| Directory | /workspace/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_random.170119947 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 1254461900 ps |
| CPU time | 41.41 seconds |
| Started | Feb 07 04:21:27 PM PST 24 |
| Finished | Feb 07 04:22:10 PM PST 24 |
| Peak memory | 555644 kb |
| Host | smart-dc3b8438-6b95-4dd0-ac0c-c6501d57dfcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170119947 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.170119947 |
| Directory | /workspace/76.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random.1507212017 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 1367023793 ps |
| CPU time | 54.79 seconds |
| Started | Feb 07 04:21:22 PM PST 24 |
| Finished | Feb 07 04:22:18 PM PST 24 |
| Peak memory | 555640 kb |
| Host | smart-99180499-39c0-4361-8d15-d0d2bdd78956 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507212017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.1507212017 |
| Directory | /workspace/76.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.585865177 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 4710886897 ps |
| CPU time | 51.46 seconds |
| Started | Feb 07 04:21:29 PM PST 24 |
| Finished | Feb 07 04:22:22 PM PST 24 |
| Peak memory | 553000 kb |
| Host | smart-0019bfc2-5e7b-420d-8145-e4f3b3be178e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585865177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.585865177 |
| Directory | /workspace/76.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.497797550 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 49033031141 ps |
| CPU time | 957.14 seconds |
| Started | Feb 07 04:21:22 PM PST 24 |
| Finished | Feb 07 04:37:20 PM PST 24 |
| Peak memory | 555460 kb |
| Host | smart-1773a15c-7a12-43af-b3f6-1966ae8509f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497797550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.497797550 |
| Directory | /workspace/76.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.1287394006 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 398257549 ps |
| CPU time | 34.72 seconds |
| Started | Feb 07 04:21:28 PM PST 24 |
| Finished | Feb 07 04:22:05 PM PST 24 |
| Peak memory | 555376 kb |
| Host | smart-cc2739b8-4367-43c0-b1bd-5860e6abf150 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287394006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_del ays.1287394006 |
| Directory | /workspace/76.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_same_source.1317287005 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 46513114 ps |
| CPU time | 6.96 seconds |
| Started | Feb 07 04:21:23 PM PST 24 |
| Finished | Feb 07 04:21:34 PM PST 24 |
| Peak memory | 553548 kb |
| Host | smart-e7c00f88-731b-4b4a-9984-ed0866794bf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317287005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.1317287005 |
| Directory | /workspace/76.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke.1633930062 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 208614722 ps |
| CPU time | 8.89 seconds |
| Started | Feb 07 04:21:28 PM PST 24 |
| Finished | Feb 07 04:21:39 PM PST 24 |
| Peak memory | 553584 kb |
| Host | smart-57769c2a-dcb5-47bd-b094-a41866e9bd4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633930062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.1633930062 |
| Directory | /workspace/76.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.3760946334 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 7015042369 ps |
| CPU time | 74.59 seconds |
| Started | Feb 07 04:21:28 PM PST 24 |
| Finished | Feb 07 04:22:43 PM PST 24 |
| Peak memory | 553672 kb |
| Host | smart-981d9df6-36a4-4777-963a-cad89e9c75c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760946334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.3760946334 |
| Directory | /workspace/76.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.889712103 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 6820510902 ps |
| CPU time | 107 seconds |
| Started | Feb 07 04:21:27 PM PST 24 |
| Finished | Feb 07 04:23:15 PM PST 24 |
| Peak memory | 553076 kb |
| Host | smart-fcda03c8-cd00-447c-8cff-19f095b2e0ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889712103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.889712103 |
| Directory | /workspace/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.753986353 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 51641806 ps |
| CPU time | 6.93 seconds |
| Started | Feb 07 04:21:28 PM PST 24 |
| Finished | Feb 07 04:21:37 PM PST 24 |
| Peak memory | 553280 kb |
| Host | smart-3ddfbb7f-afa8-4722-86b8-53c030853884 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753986353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delays .753986353 |
| Directory | /workspace/76.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.1783378595 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 4848008782 ps |
| CPU time | 181.17 seconds |
| Started | Feb 07 04:21:33 PM PST 24 |
| Finished | Feb 07 04:24:35 PM PST 24 |
| Peak memory | 556656 kb |
| Host | smart-5e168af0-1529-4de3-9c87-ae81667f42cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783378595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.1783378595 |
| Directory | /workspace/76.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.4114419889 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 219174818 ps |
| CPU time | 56.03 seconds |
| Started | Feb 07 04:21:30 PM PST 24 |
| Finished | Feb 07 04:22:27 PM PST 24 |
| Peak memory | 556332 kb |
| Host | smart-6a8aa642-2e7c-4661-9bf2-b6b17de49304 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114419889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all _with_rand_reset.4114419889 |
| Directory | /workspace/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.1947540006 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 3351641959 ps |
| CPU time | 327.27 seconds |
| Started | Feb 07 04:21:39 PM PST 24 |
| Finished | Feb 07 04:27:08 PM PST 24 |
| Peak memory | 575152 kb |
| Host | smart-1fe9b363-6c58-4028-b2ad-77bc4da9ab00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947540006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al l_with_reset_error.1947540006 |
| Directory | /workspace/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.1885015201 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 220177598 ps |
| CPU time | 28.73 seconds |
| Started | Feb 07 04:21:27 PM PST 24 |
| Finished | Feb 07 04:21:57 PM PST 24 |
| Peak memory | 555384 kb |
| Host | smart-6aec8c37-a12c-44ce-8c9c-989ee179ac67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885015201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.1885015201 |
| Directory | /workspace/76.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device.1402831400 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 104766061 ps |
| CPU time | 9.68 seconds |
| Started | Feb 07 04:21:36 PM PST 24 |
| Finished | Feb 07 04:21:46 PM PST 24 |
| Peak memory | 553600 kb |
| Host | smart-1fa318c0-2c37-4fcd-a2f8-b7b928d9d8cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402831400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device .1402831400 |
| Directory | /workspace/77.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.1131237991 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 71284606278 ps |
| CPU time | 1213.13 seconds |
| Started | Feb 07 04:21:37 PM PST 24 |
| Finished | Feb 07 04:41:54 PM PST 24 |
| Peak memory | 559272 kb |
| Host | smart-871be192-b8bc-4f07-a24f-be1b8e10278a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131237991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_ device_slow_rsp.1131237991 |
| Directory | /workspace/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.2772909439 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 52993694 ps |
| CPU time | 8.43 seconds |
| Started | Feb 07 04:21:40 PM PST 24 |
| Finished | Feb 07 04:21:49 PM PST 24 |
| Peak memory | 554232 kb |
| Host | smart-2ae9ac98-11f7-4a1d-b3c6-8e3640089bb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772909439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_add r.2772909439 |
| Directory | /workspace/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_random.1246855665 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 522801114 ps |
| CPU time | 36.72 seconds |
| Started | Feb 07 04:21:34 PM PST 24 |
| Finished | Feb 07 04:22:11 PM PST 24 |
| Peak memory | 555380 kb |
| Host | smart-8ccfa353-c0c1-4f37-ba69-e7a670c0fc99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246855665 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.1246855665 |
| Directory | /workspace/77.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random.1382422521 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 1081507043 ps |
| CPU time | 35.07 seconds |
| Started | Feb 07 04:21:36 PM PST 24 |
| Finished | Feb 07 04:22:15 PM PST 24 |
| Peak memory | 555480 kb |
| Host | smart-f5c8f820-d242-4f1a-9b74-ad38164d7b34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382422521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.1382422521 |
| Directory | /workspace/77.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.1785927000 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 5471829667 ps |
| CPU time | 59.88 seconds |
| Started | Feb 07 04:21:38 PM PST 24 |
| Finished | Feb 07 04:22:40 PM PST 24 |
| Peak memory | 553616 kb |
| Host | smart-64119539-d778-4da3-9f1a-529950b01922 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785927000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.1785927000 |
| Directory | /workspace/77.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.3816808891 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 53496882120 ps |
| CPU time | 989 seconds |
| Started | Feb 07 04:21:36 PM PST 24 |
| Finished | Feb 07 04:38:05 PM PST 24 |
| Peak memory | 555704 kb |
| Host | smart-4445b425-286d-4ebe-a3e8-bee449a30600 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816808891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.3816808891 |
| Directory | /workspace/77.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.3710117511 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 519846656 ps |
| CPU time | 45.67 seconds |
| Started | Feb 07 04:21:38 PM PST 24 |
| Finished | Feb 07 04:22:26 PM PST 24 |
| Peak memory | 555648 kb |
| Host | smart-04024921-5330-48b7-86fc-ae7461757ddb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710117511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_del ays.3710117511 |
| Directory | /workspace/77.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_same_source.1682498272 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 519808814 ps |
| CPU time | 35.91 seconds |
| Started | Feb 07 04:21:34 PM PST 24 |
| Finished | Feb 07 04:22:11 PM PST 24 |
| Peak memory | 555668 kb |
| Host | smart-948d3eff-feac-4b15-a1cd-a7f3764d991b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682498272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.1682498272 |
| Directory | /workspace/77.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke.55458988 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 41135465 ps |
| CPU time | 6.46 seconds |
| Started | Feb 07 04:21:37 PM PST 24 |
| Finished | Feb 07 04:21:47 PM PST 24 |
| Peak memory | 553328 kb |
| Host | smart-a0a83007-0074-4b88-b9ed-c8968a07bcff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55458988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.55458988 |
| Directory | /workspace/77.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.728036408 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 7688661918 ps |
| CPU time | 80.07 seconds |
| Started | Feb 07 04:21:33 PM PST 24 |
| Finished | Feb 07 04:22:54 PM PST 24 |
| Peak memory | 553364 kb |
| Host | smart-2ab481a2-cbbd-47ad-a609-b58e4579ae8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728036408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.728036408 |
| Directory | /workspace/77.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.2481539188 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 4840547152 ps |
| CPU time | 86.56 seconds |
| Started | Feb 07 04:21:38 PM PST 24 |
| Finished | Feb 07 04:23:07 PM PST 24 |
| Peak memory | 553068 kb |
| Host | smart-1b2d1bc5-fe3a-498f-91d2-47754407a2b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481539188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.2481539188 |
| Directory | /workspace/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.4239750782 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 41978784 ps |
| CPU time | 6.05 seconds |
| Started | Feb 07 04:21:37 PM PST 24 |
| Finished | Feb 07 04:21:47 PM PST 24 |
| Peak memory | 553260 kb |
| Host | smart-3bd60908-2964-4eab-872b-dbb2007ad300 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239750782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delay s.4239750782 |
| Directory | /workspace/77.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all.1551136403 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 1687647306 ps |
| CPU time | 126.47 seconds |
| Started | Feb 07 04:21:39 PM PST 24 |
| Finished | Feb 07 04:23:47 PM PST 24 |
| Peak memory | 556672 kb |
| Host | smart-bd2ce64a-0d19-4781-8fff-e2a8f3f19874 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551136403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.1551136403 |
| Directory | /workspace/77.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.3297700795 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 2788180947 ps |
| CPU time | 289.4 seconds |
| Started | Feb 07 04:21:36 PM PST 24 |
| Finished | Feb 07 04:26:30 PM PST 24 |
| Peak memory | 559388 kb |
| Host | smart-944425da-bab2-4cb9-b7ed-9e94c6c755ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297700795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all _with_rand_reset.3297700795 |
| Directory | /workspace/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.1218849495 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 583441610 ps |
| CPU time | 156.13 seconds |
| Started | Feb 07 04:21:45 PM PST 24 |
| Finished | Feb 07 04:24:22 PM PST 24 |
| Peak memory | 558180 kb |
| Host | smart-06c126f2-6e63-4cee-8503-8fee378dd50f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218849495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_al l_with_reset_error.1218849495 |
| Directory | /workspace/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.2577478573 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 232897724 ps |
| CPU time | 11.77 seconds |
| Started | Feb 07 04:21:36 PM PST 24 |
| Finished | Feb 07 04:21:51 PM PST 24 |
| Peak memory | 554352 kb |
| Host | smart-db5059ad-3fc5-4136-b521-81520c998089 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577478573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.2577478573 |
| Directory | /workspace/77.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device.616600209 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 767075142 ps |
| CPU time | 60.19 seconds |
| Started | Feb 07 04:21:40 PM PST 24 |
| Finished | Feb 07 04:22:42 PM PST 24 |
| Peak memory | 555344 kb |
| Host | smart-664e0dc3-aaf7-4a07-9c6f-d43c35a67762 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616600209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device. 616600209 |
| Directory | /workspace/78.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.1628718807 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 290843672 ps |
| CPU time | 31.11 seconds |
| Started | Feb 07 04:21:41 PM PST 24 |
| Finished | Feb 07 04:22:15 PM PST 24 |
| Peak memory | 555628 kb |
| Host | smart-36359c8c-ff05-4330-960d-bbcb24bf565a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628718807 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_add r.1628718807 |
| Directory | /workspace/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_random.2568929366 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 221260455 ps |
| CPU time | 18.97 seconds |
| Started | Feb 07 04:21:40 PM PST 24 |
| Finished | Feb 07 04:22:00 PM PST 24 |
| Peak memory | 559172 kb |
| Host | smart-311a532c-4256-4d91-ac70-c0967e6425f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568929366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.2568929366 |
| Directory | /workspace/78.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random.2381006287 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 625228835 ps |
| CPU time | 24.01 seconds |
| Started | Feb 07 04:21:45 PM PST 24 |
| Finished | Feb 07 04:22:10 PM PST 24 |
| Peak memory | 555632 kb |
| Host | smart-2c31422d-2a6d-4843-bf5c-261217a9e159 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381006287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.2381006287 |
| Directory | /workspace/78.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.1365173509 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 5777828612 ps |
| CPU time | 57.89 seconds |
| Started | Feb 07 04:21:44 PM PST 24 |
| Finished | Feb 07 04:22:43 PM PST 24 |
| Peak memory | 553384 kb |
| Host | smart-6a6cface-1e84-4386-ae32-2a928387f24c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365173509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.1365173509 |
| Directory | /workspace/78.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.4010406982 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 45770399755 ps |
| CPU time | 942.16 seconds |
| Started | Feb 07 04:21:39 PM PST 24 |
| Finished | Feb 07 04:37:23 PM PST 24 |
| Peak memory | 555708 kb |
| Host | smart-d5d17c62-1259-4802-b470-d0984e656665 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010406982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.4010406982 |
| Directory | /workspace/78.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.2349148828 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 106995244 ps |
| CPU time | 11.21 seconds |
| Started | Feb 07 04:21:37 PM PST 24 |
| Finished | Feb 07 04:21:52 PM PST 24 |
| Peak memory | 555624 kb |
| Host | smart-ce50d5e5-aa26-444e-916e-35c050074b5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349148828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_del ays.2349148828 |
| Directory | /workspace/78.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_same_source.3529477600 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 375191800 ps |
| CPU time | 26.22 seconds |
| Started | Feb 07 04:21:39 PM PST 24 |
| Finished | Feb 07 04:22:07 PM PST 24 |
| Peak memory | 555244 kb |
| Host | smart-ef8d1b55-5395-4cdb-bc8c-d7b1a157808a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529477600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.3529477600 |
| Directory | /workspace/78.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke.513208104 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 235109564 ps |
| CPU time | 9.47 seconds |
| Started | Feb 07 04:21:42 PM PST 24 |
| Finished | Feb 07 04:21:54 PM PST 24 |
| Peak memory | 553560 kb |
| Host | smart-c5d0cfcf-c4ec-4920-8f73-32ea56a378b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513208104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.513208104 |
| Directory | /workspace/78.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.1730991616 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 9725908304 ps |
| CPU time | 97 seconds |
| Started | Feb 07 04:21:40 PM PST 24 |
| Finished | Feb 07 04:23:18 PM PST 24 |
| Peak memory | 553636 kb |
| Host | smart-2f21e4e0-6add-4a95-8ddc-74f9895c3086 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730991616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.1730991616 |
| Directory | /workspace/78.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.2856987501 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 4324381397 ps |
| CPU time | 75.31 seconds |
| Started | Feb 07 04:21:43 PM PST 24 |
| Finished | Feb 07 04:23:00 PM PST 24 |
| Peak memory | 553360 kb |
| Host | smart-77ca3f3a-d989-4774-87bd-718039ffe255 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856987501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.2856987501 |
| Directory | /workspace/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.1724839488 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 43670385 ps |
| CPU time | 6.07 seconds |
| Started | Feb 07 04:21:41 PM PST 24 |
| Finished | Feb 07 04:21:48 PM PST 24 |
| Peak memory | 553000 kb |
| Host | smart-b65341f8-4888-4e51-816c-9eec6b365f51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724839488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delay s.1724839488 |
| Directory | /workspace/78.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all.3286473476 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 2198056423 ps |
| CPU time | 186.55 seconds |
| Started | Feb 07 04:21:42 PM PST 24 |
| Finished | Feb 07 04:24:51 PM PST 24 |
| Peak memory | 556340 kb |
| Host | smart-ebe0852d-61c7-4efe-8032-8af7e4df0dd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286473476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.3286473476 |
| Directory | /workspace/78.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.1898844495 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 5750013548 ps |
| CPU time | 219.31 seconds |
| Started | Feb 07 04:21:40 PM PST 24 |
| Finished | Feb 07 04:25:21 PM PST 24 |
| Peak memory | 556592 kb |
| Host | smart-5aade1cf-41d5-48a8-a824-5b08bcc4b323 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898844495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.1898844495 |
| Directory | /workspace/78.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.3268044091 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 4900633469 ps |
| CPU time | 715.5 seconds |
| Started | Feb 07 04:21:41 PM PST 24 |
| Finished | Feb 07 04:33:39 PM PST 24 |
| Peak memory | 567632 kb |
| Host | smart-5cd85284-613b-48cf-aaad-4e0efe083423 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268044091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_rand_reset.3268044091 |
| Directory | /workspace/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.1731660044 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 26647686317 ps |
| CPU time | 1044.72 seconds |
| Started | Feb 07 04:21:58 PM PST 24 |
| Finished | Feb 07 04:39:23 PM PST 24 |
| Peak memory | 558304 kb |
| Host | smart-917afa52-0a06-46dc-9280-0321382f5dc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731660044 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_al l_with_reset_error.1731660044 |
| Directory | /workspace/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.2269174769 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 278566019 ps |
| CPU time | 33.25 seconds |
| Started | Feb 07 04:21:41 PM PST 24 |
| Finished | Feb 07 04:22:15 PM PST 24 |
| Peak memory | 555504 kb |
| Host | smart-ed05999b-1b65-4ec1-9d1b-ec2e0a2c2299 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269174769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.2269174769 |
| Directory | /workspace/78.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device.3628104654 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 259329320 ps |
| CPU time | 19.15 seconds |
| Started | Feb 07 04:21:52 PM PST 24 |
| Finished | Feb 07 04:22:12 PM PST 24 |
| Peak memory | 554240 kb |
| Host | smart-6215d7ae-97a6-48fc-a3a6-8e686d564f2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628104654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device .3628104654 |
| Directory | /workspace/79.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.1581178710 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 44372516122 ps |
| CPU time | 792.13 seconds |
| Started | Feb 07 04:22:00 PM PST 24 |
| Finished | Feb 07 04:35:13 PM PST 24 |
| Peak memory | 556572 kb |
| Host | smart-8fe72d45-738c-485b-b3fa-d7171ffb939b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581178710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_ device_slow_rsp.1581178710 |
| Directory | /workspace/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.3664682843 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 274928527 ps |
| CPU time | 28.78 seconds |
| Started | Feb 07 04:21:52 PM PST 24 |
| Finished | Feb 07 04:22:21 PM PST 24 |
| Peak memory | 555604 kb |
| Host | smart-9989c63e-4826-4e62-bee2-9d36c6d67284 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664682843 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_add r.3664682843 |
| Directory | /workspace/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_random.1140268291 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 2207702515 ps |
| CPU time | 81.56 seconds |
| Started | Feb 07 04:21:59 PM PST 24 |
| Finished | Feb 07 04:23:21 PM PST 24 |
| Peak memory | 554980 kb |
| Host | smart-38e00b5f-5ba3-4f75-aa76-3afa6facec69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140268291 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.1140268291 |
| Directory | /workspace/79.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random.14241295 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 651818792 ps |
| CPU time | 54.84 seconds |
| Started | Feb 07 04:21:51 PM PST 24 |
| Finished | Feb 07 04:22:47 PM PST 24 |
| Peak memory | 555616 kb |
| Host | smart-58b486e7-32ff-45b5-bbd2-bc149977d485 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14241295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.14241295 |
| Directory | /workspace/79.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.1075957021 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 56097293503 ps |
| CPU time | 625.15 seconds |
| Started | Feb 07 04:21:50 PM PST 24 |
| Finished | Feb 07 04:32:15 PM PST 24 |
| Peak memory | 555744 kb |
| Host | smart-d973484a-7b42-42f8-9597-99b2f7506431 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075957021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.1075957021 |
| Directory | /workspace/79.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.3605074313 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 8098723467 ps |
| CPU time | 133.56 seconds |
| Started | Feb 07 04:21:51 PM PST 24 |
| Finished | Feb 07 04:24:06 PM PST 24 |
| Peak memory | 555144 kb |
| Host | smart-224abd32-7d09-4f7a-9474-6edf5d5ec5b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605074313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.3605074313 |
| Directory | /workspace/79.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.3554685007 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 530462349 ps |
| CPU time | 51.32 seconds |
| Started | Feb 07 04:21:52 PM PST 24 |
| Finished | Feb 07 04:22:44 PM PST 24 |
| Peak memory | 555396 kb |
| Host | smart-05644a45-bf1b-49ce-86c9-45cd48f489c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554685007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_del ays.3554685007 |
| Directory | /workspace/79.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_same_source.890650084 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 855608271 ps |
| CPU time | 27.95 seconds |
| Started | Feb 07 04:21:58 PM PST 24 |
| Finished | Feb 07 04:22:26 PM PST 24 |
| Peak memory | 555324 kb |
| Host | smart-e5bb743d-a05b-46ec-bb78-ee1064630b78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890650084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.890650084 |
| Directory | /workspace/79.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke.1419143293 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 188998004 ps |
| CPU time | 8.8 seconds |
| Started | Feb 07 04:21:53 PM PST 24 |
| Finished | Feb 07 04:22:02 PM PST 24 |
| Peak memory | 553284 kb |
| Host | smart-5eab9045-f9c2-40a7-9a51-1b0912d014c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419143293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.1419143293 |
| Directory | /workspace/79.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.1545032609 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 6472802962 ps |
| CPU time | 65.61 seconds |
| Started | Feb 07 04:21:51 PM PST 24 |
| Finished | Feb 07 04:22:58 PM PST 24 |
| Peak memory | 553380 kb |
| Host | smart-9a26a1b7-cc00-4ac7-8b09-586111e70dfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545032609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.1545032609 |
| Directory | /workspace/79.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.1077596426 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 4021373296 ps |
| CPU time | 71.19 seconds |
| Started | Feb 07 04:21:52 PM PST 24 |
| Finished | Feb 07 04:23:04 PM PST 24 |
| Peak memory | 553652 kb |
| Host | smart-c68df061-e4d1-454c-bb09-097071cb2b55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077596426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.1077596426 |
| Directory | /workspace/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.1970646241 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 51625338 ps |
| CPU time | 5.88 seconds |
| Started | Feb 07 04:21:54 PM PST 24 |
| Finished | Feb 07 04:22:00 PM PST 24 |
| Peak memory | 553600 kb |
| Host | smart-61aeef14-4553-4104-8096-c1936035f15b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970646241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delay s.1970646241 |
| Directory | /workspace/79.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all.3074992451 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 881198650 ps |
| CPU time | 35.07 seconds |
| Started | Feb 07 04:21:54 PM PST 24 |
| Finished | Feb 07 04:22:30 PM PST 24 |
| Peak memory | 556636 kb |
| Host | smart-4d454bfd-1fac-4891-9a6c-47c7b5d05aee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074992451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.3074992451 |
| Directory | /workspace/79.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.3586943393 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 2005985260 ps |
| CPU time | 72.81 seconds |
| Started | Feb 07 04:21:52 PM PST 24 |
| Finished | Feb 07 04:23:05 PM PST 24 |
| Peak memory | 556368 kb |
| Host | smart-7e3ad8b8-0434-470a-88f4-87ae1990cd62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586943393 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.3586943393 |
| Directory | /workspace/79.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.62827634 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 402387467 ps |
| CPU time | 258.18 seconds |
| Started | Feb 07 04:21:50 PM PST 24 |
| Finished | Feb 07 04:26:09 PM PST 24 |
| Peak memory | 559300 kb |
| Host | smart-26d32203-0101-4a3c-9e6f-29749c9f24e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62827634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_w ith_rand_reset.62827634 |
| Directory | /workspace/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.2451077462 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 10948994312 ps |
| CPU time | 478.92 seconds |
| Started | Feb 07 04:21:59 PM PST 24 |
| Finished | Feb 07 04:29:59 PM PST 24 |
| Peak memory | 559404 kb |
| Host | smart-f29dc14d-4b73-457b-9fab-701bb764bdf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451077462 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_al l_with_reset_error.2451077462 |
| Directory | /workspace/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.3632992376 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 319576173 ps |
| CPU time | 36.16 seconds |
| Started | Feb 07 04:21:54 PM PST 24 |
| Finished | Feb 07 04:22:31 PM PST 24 |
| Peak memory | 555704 kb |
| Host | smart-b380137b-b8c9-4818-9435-90e3794fee0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632992376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.3632992376 |
| Directory | /workspace/79.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.4251824610 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 3849626112 ps |
| CPU time | 199.91 seconds |
| Started | Feb 07 04:12:02 PM PST 24 |
| Finished | Feb 07 04:15:22 PM PST 24 |
| Peak memory | 622080 kb |
| Host | smart-eadeae54-a345-4b57-9c1b-48247d4de2f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251824610 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 8.chip_csr_mem_rw_with_rand_reset.4251824610 |
| Directory | /workspace/8.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_rw.303157624 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 3872213918 ps |
| CPU time | 362.76 seconds |
| Started | Feb 07 04:12:08 PM PST 24 |
| Finished | Feb 07 04:18:11 PM PST 24 |
| Peak memory | 580188 kb |
| Host | smart-ee1552bd-4679-4ea7-b5ae-a8992b11ab2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303157624 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.303157624 |
| Directory | /workspace/8.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.3510419622 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 32430485358 ps |
| CPU time | 4081.79 seconds |
| Started | Feb 07 04:11:59 PM PST 24 |
| Finished | Feb 07 05:20:01 PM PST 24 |
| Peak memory | 575852 kb |
| Host | smart-bb068f4f-3ee4-483c-978f-504d0768b6a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510419622 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 8.chip_same_csr_outstanding.3510419622 |
| Directory | /workspace/8.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_tl_errors.3917855849 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 3409558758 ps |
| CPU time | 150.95 seconds |
| Started | Feb 07 04:12:06 PM PST 24 |
| Finished | Feb 07 04:14:37 PM PST 24 |
| Peak memory | 580404 kb |
| Host | smart-b2cafbda-e68f-4fb9-9cd4-01bb0327a577 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917855849 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.3917855849 |
| Directory | /workspace/8.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device.1963614779 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 290119215 ps |
| CPU time | 16.02 seconds |
| Started | Feb 07 04:12:12 PM PST 24 |
| Finished | Feb 07 04:12:28 PM PST 24 |
| Peak memory | 554056 kb |
| Host | smart-d7d85150-a455-45c0-a169-a5bbc304f709 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963614779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device. 1963614779 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.4033882190 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 11502396848 ps |
| CPU time | 191.37 seconds |
| Started | Feb 07 04:12:12 PM PST 24 |
| Finished | Feb 07 04:15:24 PM PST 24 |
| Peak memory | 559216 kb |
| Host | smart-6d3d9381-1df6-426c-9976-7052f045575d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033882190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_d evice_slow_rsp.4033882190 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.2910403386 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 143489496 ps |
| CPU time | 8.46 seconds |
| Started | Feb 07 04:12:07 PM PST 24 |
| Finished | Feb 07 04:12:16 PM PST 24 |
| Peak memory | 553560 kb |
| Host | smart-bb53b7a3-5e04-4617-bb55-c05dbda7f250 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910403386 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr .2910403386 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_random.584328502 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 411036080 ps |
| CPU time | 29.24 seconds |
| Started | Feb 07 04:12:02 PM PST 24 |
| Finished | Feb 07 04:12:32 PM PST 24 |
| Peak memory | 555304 kb |
| Host | smart-66e7a543-47ec-4736-bb7e-190efa81efca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584328502 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.584328502 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random.4169609250 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 2142909498 ps |
| CPU time | 70.7 seconds |
| Started | Feb 07 04:12:06 PM PST 24 |
| Finished | Feb 07 04:13:17 PM PST 24 |
| Peak memory | 555644 kb |
| Host | smart-2ba13ad1-b73a-421e-baf1-4cc5138d0fc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169609250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.4169609250 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.1974724028 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 17601030880 ps |
| CPU time | 189.17 seconds |
| Started | Feb 07 04:12:06 PM PST 24 |
| Finished | Feb 07 04:15:16 PM PST 24 |
| Peak memory | 554668 kb |
| Host | smart-d1736f8b-4faa-4afa-9dfe-0310d1b742d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974724028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1974724028 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.489337064 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 34099397820 ps |
| CPU time | 646.68 seconds |
| Started | Feb 07 04:12:02 PM PST 24 |
| Finished | Feb 07 04:22:49 PM PST 24 |
| Peak memory | 555472 kb |
| Host | smart-ad68e0a6-7683-4c44-b1c0-f4631b654237 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489337064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.489337064 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.1516724080 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 519934952 ps |
| CPU time | 42.87 seconds |
| Started | Feb 07 04:12:06 PM PST 24 |
| Finished | Feb 07 04:12:49 PM PST 24 |
| Peak memory | 554844 kb |
| Host | smart-43a8ce41-258c-4a2a-bc11-578ed4c5b104 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516724080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_dela ys.1516724080 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_same_source.1285505558 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 1790256775 ps |
| CPU time | 55.45 seconds |
| Started | Feb 07 04:12:01 PM PST 24 |
| Finished | Feb 07 04:12:57 PM PST 24 |
| Peak memory | 559188 kb |
| Host | smart-860335e5-bd4f-4e6e-98e9-c443eebc0a69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285505558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.1285505558 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke.2652081839 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 40331436 ps |
| CPU time | 5.4 seconds |
| Started | Feb 07 04:11:54 PM PST 24 |
| Finished | Feb 07 04:12:00 PM PST 24 |
| Peak memory | 553604 kb |
| Host | smart-e6e971ae-9f4a-4079-9de5-dfcdb6602960 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652081839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.2652081839 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.3798248311 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 6474869092 ps |
| CPU time | 65.75 seconds |
| Started | Feb 07 04:12:05 PM PST 24 |
| Finished | Feb 07 04:13:11 PM PST 24 |
| Peak memory | 553608 kb |
| Host | smart-1f49b01e-2d19-4f05-8745-ccccb80221f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798248311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3798248311 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.1204169527 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 4337889778 ps |
| CPU time | 69.39 seconds |
| Started | Feb 07 04:12:06 PM PST 24 |
| Finished | Feb 07 04:13:16 PM PST 24 |
| Peak memory | 553688 kb |
| Host | smart-2388e384-557f-478a-b9d3-fe6d6aa5c8fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204169527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.1204169527 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.488422334 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 36445041 ps |
| CPU time | 5.66 seconds |
| Started | Feb 07 04:11:59 PM PST 24 |
| Finished | Feb 07 04:12:05 PM PST 24 |
| Peak memory | 553284 kb |
| Host | smart-5f4d0d28-c647-4295-98b2-0553b7b37233 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488422334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays. 488422334 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all.2061466204 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 6790636303 ps |
| CPU time | 233.47 seconds |
| Started | Feb 07 04:12:09 PM PST 24 |
| Finished | Feb 07 04:16:03 PM PST 24 |
| Peak memory | 556600 kb |
| Host | smart-265f11c1-82f0-4119-ab3a-5ba2ea4be63e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061466204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.2061466204 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.2065707266 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 1294102354 ps |
| CPU time | 110.11 seconds |
| Started | Feb 07 04:12:07 PM PST 24 |
| Finished | Feb 07 04:13:58 PM PST 24 |
| Peak memory | 555464 kb |
| Host | smart-0bbc7073-7e1c-4bfc-9807-7e6970aa5dba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065707266 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.2065707266 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.2004192645 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 2676089355 ps |
| CPU time | 148.11 seconds |
| Started | Feb 07 04:12:06 PM PST 24 |
| Finished | Feb 07 04:14:34 PM PST 24 |
| Peak memory | 556592 kb |
| Host | smart-aa7b204c-4034-406e-9668-4b27951e6791 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004192645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_ with_rand_reset.2004192645 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.2627125846 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 169042679 ps |
| CPU time | 48.79 seconds |
| Started | Feb 07 04:12:08 PM PST 24 |
| Finished | Feb 07 04:12:57 PM PST 24 |
| Peak memory | 556868 kb |
| Host | smart-bdea58a2-dbce-45c5-9c4b-8f0f17a30a6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627125846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all _with_reset_error.2627125846 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.1619977295 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 1328336511 ps |
| CPU time | 54.69 seconds |
| Started | Feb 07 04:12:00 PM PST 24 |
| Finished | Feb 07 04:12:55 PM PST 24 |
| Peak memory | 555580 kb |
| Host | smart-872a39c8-ef25-47e6-a96c-22d548d792f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619977295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1619977295 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device.1809557320 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 2983148944 ps |
| CPU time | 110.14 seconds |
| Started | Feb 07 04:22:02 PM PST 24 |
| Finished | Feb 07 04:23:52 PM PST 24 |
| Peak memory | 555432 kb |
| Host | smart-1fd25e98-1273-428b-a95a-796ba448034e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809557320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device .1809557320 |
| Directory | /workspace/80.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.3419038064 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 38467682597 ps |
| CPU time | 716.88 seconds |
| Started | Feb 07 04:22:02 PM PST 24 |
| Finished | Feb 07 04:34:00 PM PST 24 |
| Peak memory | 555436 kb |
| Host | smart-1a9b5aab-775c-48d6-9f3a-7b7856255888 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419038064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_ device_slow_rsp.3419038064 |
| Directory | /workspace/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.954313596 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 931282818 ps |
| CPU time | 37.4 seconds |
| Started | Feb 07 04:22:02 PM PST 24 |
| Finished | Feb 07 04:22:40 PM PST 24 |
| Peak memory | 555264 kb |
| Host | smart-525cf66e-b8a3-4b27-91ce-57c1bc25eb6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954313596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_addr .954313596 |
| Directory | /workspace/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_random.45801157 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 465294943 ps |
| CPU time | 43.12 seconds |
| Started | Feb 07 04:22:05 PM PST 24 |
| Finished | Feb 07 04:22:48 PM PST 24 |
| Peak memory | 555072 kb |
| Host | smart-13323100-62f8-4fe4-95c8-7c09353dc85d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45801157 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.45801157 |
| Directory | /workspace/80.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random.459774732 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 1895119835 ps |
| CPU time | 70.17 seconds |
| Started | Feb 07 04:22:00 PM PST 24 |
| Finished | Feb 07 04:23:11 PM PST 24 |
| Peak memory | 555380 kb |
| Host | smart-32a01e76-bb84-42fb-9cac-911e57cfe554 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459774732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.459774732 |
| Directory | /workspace/80.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.3929400805 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 86057545117 ps |
| CPU time | 942.79 seconds |
| Started | Feb 07 04:22:00 PM PST 24 |
| Finished | Feb 07 04:37:44 PM PST 24 |
| Peak memory | 555460 kb |
| Host | smart-f8a0d8a2-9c34-4602-a453-5b70377fe546 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929400805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.3929400805 |
| Directory | /workspace/80.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.3503830330 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 53403845444 ps |
| CPU time | 1040.54 seconds |
| Started | Feb 07 04:22:03 PM PST 24 |
| Finished | Feb 07 04:39:24 PM PST 24 |
| Peak memory | 555724 kb |
| Host | smart-3cbc9520-eac3-4bd1-8c90-3978d4c1d5d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503830330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.3503830330 |
| Directory | /workspace/80.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.3574318903 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 572252741 ps |
| CPU time | 42.58 seconds |
| Started | Feb 07 04:22:01 PM PST 24 |
| Finished | Feb 07 04:22:44 PM PST 24 |
| Peak memory | 555664 kb |
| Host | smart-3fe55f31-540a-4475-b36d-a06ea613abb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574318903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_del ays.3574318903 |
| Directory | /workspace/80.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_same_source.419803558 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 2248860487 ps |
| CPU time | 64.11 seconds |
| Started | Feb 07 04:22:02 PM PST 24 |
| Finished | Feb 07 04:23:07 PM PST 24 |
| Peak memory | 555700 kb |
| Host | smart-09948e26-0797-4b2d-8620-1969d825c0ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419803558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.419803558 |
| Directory | /workspace/80.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke.2263548882 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 173628178 ps |
| CPU time | 8.26 seconds |
| Started | Feb 07 04:21:58 PM PST 24 |
| Finished | Feb 07 04:22:07 PM PST 24 |
| Peak memory | 553436 kb |
| Host | smart-c264ceb0-4d01-4907-a1ff-f47290c7e15e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263548882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.2263548882 |
| Directory | /workspace/80.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.2299785706 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 9426478761 ps |
| CPU time | 103.03 seconds |
| Started | Feb 07 04:22:04 PM PST 24 |
| Finished | Feb 07 04:23:48 PM PST 24 |
| Peak memory | 559228 kb |
| Host | smart-e59e45de-9dcd-4233-ab50-05bada792119 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299785706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.2299785706 |
| Directory | /workspace/80.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.1810318991 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 5423853883 ps |
| CPU time | 90.43 seconds |
| Started | Feb 07 04:22:03 PM PST 24 |
| Finished | Feb 07 04:23:34 PM PST 24 |
| Peak memory | 553340 kb |
| Host | smart-04688ad7-9d47-4316-a1fd-104e1e4c99b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810318991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.1810318991 |
| Directory | /workspace/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.2328956259 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 52392027 ps |
| CPU time | 6.64 seconds |
| Started | Feb 07 04:22:05 PM PST 24 |
| Finished | Feb 07 04:22:12 PM PST 24 |
| Peak memory | 553284 kb |
| Host | smart-21dffa4e-c613-418e-93fc-7e83b40b45d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328956259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delay s.2328956259 |
| Directory | /workspace/80.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all.4025222690 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 3376393550 ps |
| CPU time | 132.42 seconds |
| Started | Feb 07 04:22:00 PM PST 24 |
| Finished | Feb 07 04:24:13 PM PST 24 |
| Peak memory | 556340 kb |
| Host | smart-5f946a02-4ec2-43dc-a1cf-68df16e3b97b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025222690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.4025222690 |
| Directory | /workspace/80.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.113053929 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 1665990147 ps |
| CPU time | 133.43 seconds |
| Started | Feb 07 04:22:07 PM PST 24 |
| Finished | Feb 07 04:24:21 PM PST 24 |
| Peak memory | 556816 kb |
| Host | smart-2a468270-790f-465f-981a-e33030e94871 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113053929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.113053929 |
| Directory | /workspace/80.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.1506349893 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 560255879 ps |
| CPU time | 170.82 seconds |
| Started | Feb 07 04:22:08 PM PST 24 |
| Finished | Feb 07 04:24:59 PM PST 24 |
| Peak memory | 558356 kb |
| Host | smart-d509a179-d198-4681-9954-1eb9133fe48f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506349893 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_al l_with_reset_error.1506349893 |
| Directory | /workspace/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.236725571 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 909846074 ps |
| CPU time | 38.8 seconds |
| Started | Feb 07 04:22:01 PM PST 24 |
| Finished | Feb 07 04:22:41 PM PST 24 |
| Peak memory | 555624 kb |
| Host | smart-3319dde8-7f59-4578-a58c-3314b8202c0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236725571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.236725571 |
| Directory | /workspace/80.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device.1095392107 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 890142562 ps |
| CPU time | 35.32 seconds |
| Started | Feb 07 04:22:08 PM PST 24 |
| Finished | Feb 07 04:22:44 PM PST 24 |
| Peak memory | 555644 kb |
| Host | smart-108d4c83-8627-4718-9434-d552fd90d57f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095392107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device .1095392107 |
| Directory | /workspace/81.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.1450921440 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 106257894185 ps |
| CPU time | 2050.98 seconds |
| Started | Feb 07 04:22:11 PM PST 24 |
| Finished | Feb 07 04:56:23 PM PST 24 |
| Peak memory | 556876 kb |
| Host | smart-a75596ac-5cb8-4b60-b915-9a04125b7bb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450921440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_ device_slow_rsp.1450921440 |
| Directory | /workspace/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.1128358884 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 101553350 ps |
| CPU time | 12.42 seconds |
| Started | Feb 07 04:22:17 PM PST 24 |
| Finished | Feb 07 04:22:30 PM PST 24 |
| Peak memory | 555048 kb |
| Host | smart-0fa74f1c-e183-4cd6-9f3b-d931211357f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128358884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_add r.1128358884 |
| Directory | /workspace/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_random.2550058087 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 490068928 ps |
| CPU time | 40.29 seconds |
| Started | Feb 07 04:22:19 PM PST 24 |
| Finished | Feb 07 04:23:00 PM PST 24 |
| Peak memory | 555636 kb |
| Host | smart-5ee5f212-3cce-48c2-b8d7-b628d9526f8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550058087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.2550058087 |
| Directory | /workspace/81.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random.1761369968 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 387293124 ps |
| CPU time | 36.2 seconds |
| Started | Feb 07 04:22:09 PM PST 24 |
| Finished | Feb 07 04:22:45 PM PST 24 |
| Peak memory | 555420 kb |
| Host | smart-708fb897-a8e2-4b69-b366-a3a544377ab3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761369968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.1761369968 |
| Directory | /workspace/81.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.971132107 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 71777083678 ps |
| CPU time | 829.6 seconds |
| Started | Feb 07 04:22:08 PM PST 24 |
| Finished | Feb 07 04:35:58 PM PST 24 |
| Peak memory | 555720 kb |
| Host | smart-642382e5-1738-4ad8-9f0b-0b69ab382501 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971132107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.971132107 |
| Directory | /workspace/81.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.1600853104 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 26007120652 ps |
| CPU time | 442.65 seconds |
| Started | Feb 07 04:22:09 PM PST 24 |
| Finished | Feb 07 04:29:32 PM PST 24 |
| Peak memory | 555440 kb |
| Host | smart-18163a1d-5d78-46fd-832c-b57be0a829b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600853104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.1600853104 |
| Directory | /workspace/81.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.239624742 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 396759259 ps |
| CPU time | 31.85 seconds |
| Started | Feb 07 04:22:09 PM PST 24 |
| Finished | Feb 07 04:22:41 PM PST 24 |
| Peak memory | 555388 kb |
| Host | smart-3ff4d889-18ce-484b-93ec-c8300cd628a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239624742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_dela ys.239624742 |
| Directory | /workspace/81.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_same_source.4082069833 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 218621373 ps |
| CPU time | 17.55 seconds |
| Started | Feb 07 04:22:08 PM PST 24 |
| Finished | Feb 07 04:22:26 PM PST 24 |
| Peak memory | 555684 kb |
| Host | smart-b9e9b291-5cc9-4e99-b3ae-d16132c5c767 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082069833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.4082069833 |
| Directory | /workspace/81.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke.4042682163 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 223749976 ps |
| CPU time | 10.09 seconds |
| Started | Feb 07 04:22:09 PM PST 24 |
| Finished | Feb 07 04:22:20 PM PST 24 |
| Peak memory | 553280 kb |
| Host | smart-b6bd4767-e3aa-4ddc-8384-2ca44352c89a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042682163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.4042682163 |
| Directory | /workspace/81.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.1837258622 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 7934468136 ps |
| CPU time | 86.85 seconds |
| Started | Feb 07 04:22:08 PM PST 24 |
| Finished | Feb 07 04:23:36 PM PST 24 |
| Peak memory | 553680 kb |
| Host | smart-cf53bc36-f3bc-4cb5-91c0-cd8afd0a9ca2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837258622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.1837258622 |
| Directory | /workspace/81.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.126641002 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 6098565590 ps |
| CPU time | 102.18 seconds |
| Started | Feb 07 04:22:09 PM PST 24 |
| Finished | Feb 07 04:23:51 PM PST 24 |
| Peak memory | 553672 kb |
| Host | smart-f3732d75-5137-461e-be11-ed25d256a2b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126641002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.126641002 |
| Directory | /workspace/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.4136137489 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 48775742 ps |
| CPU time | 6.37 seconds |
| Started | Feb 07 04:22:11 PM PST 24 |
| Finished | Feb 07 04:22:18 PM PST 24 |
| Peak memory | 553324 kb |
| Host | smart-721a8233-393f-4475-8007-4381900555d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136137489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delay s.4136137489 |
| Directory | /workspace/81.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all.2031199484 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 908967777 ps |
| CPU time | 68.08 seconds |
| Started | Feb 07 04:22:23 PM PST 24 |
| Finished | Feb 07 04:23:32 PM PST 24 |
| Peak memory | 556840 kb |
| Host | smart-12e9b8f2-fc5b-4fbb-ad4c-839450222f88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031199484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.2031199484 |
| Directory | /workspace/81.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.3486774263 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 9180877386 ps |
| CPU time | 352.76 seconds |
| Started | Feb 07 04:22:18 PM PST 24 |
| Finished | Feb 07 04:28:12 PM PST 24 |
| Peak memory | 556600 kb |
| Host | smart-43babf38-f2e7-4e10-ba3a-47a60d601eaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486774263 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.3486774263 |
| Directory | /workspace/81.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.65817083 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 4573583162 ps |
| CPU time | 599.41 seconds |
| Started | Feb 07 04:22:15 PM PST 24 |
| Finished | Feb 07 04:32:15 PM PST 24 |
| Peak memory | 558056 kb |
| Host | smart-695087d9-fabb-4085-9bd9-05764e85d63f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65817083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_w ith_rand_reset.65817083 |
| Directory | /workspace/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.499300227 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 55147489 ps |
| CPU time | 9.25 seconds |
| Started | Feb 07 04:22:19 PM PST 24 |
| Finished | Feb 07 04:22:29 PM PST 24 |
| Peak memory | 554348 kb |
| Host | smart-c305bf5f-bad7-4f9b-b6fc-be44fd63814c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499300227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.499300227 |
| Directory | /workspace/81.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device.3194809416 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 1404250260 ps |
| CPU time | 110.08 seconds |
| Started | Feb 07 04:22:16 PM PST 24 |
| Finished | Feb 07 04:24:07 PM PST 24 |
| Peak memory | 555684 kb |
| Host | smart-2281751b-4922-40d8-9a1b-07b414493320 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194809416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device .3194809416 |
| Directory | /workspace/82.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.1935041667 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 127981376407 ps |
| CPU time | 2457.16 seconds |
| Started | Feb 07 04:22:19 PM PST 24 |
| Finished | Feb 07 05:03:17 PM PST 24 |
| Peak memory | 556828 kb |
| Host | smart-eff2e24b-987e-418f-87b5-f891792146d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935041667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_ device_slow_rsp.1935041667 |
| Directory | /workspace/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.4142908159 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 23535022 ps |
| CPU time | 4.84 seconds |
| Started | Feb 07 04:22:24 PM PST 24 |
| Finished | Feb 07 04:22:29 PM PST 24 |
| Peak memory | 553564 kb |
| Host | smart-6ec9cf9a-58ad-473f-a509-e644b9a70f3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142908159 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_add r.4142908159 |
| Directory | /workspace/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_random.1361948021 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 852329006 ps |
| CPU time | 28.45 seconds |
| Started | Feb 07 04:22:24 PM PST 24 |
| Finished | Feb 07 04:22:53 PM PST 24 |
| Peak memory | 555628 kb |
| Host | smart-a07acf05-0d01-41b9-93f3-c29a781ca2e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361948021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.1361948021 |
| Directory | /workspace/82.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random.717781490 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 626082689 ps |
| CPU time | 54.46 seconds |
| Started | Feb 07 04:22:15 PM PST 24 |
| Finished | Feb 07 04:23:10 PM PST 24 |
| Peak memory | 555084 kb |
| Host | smart-20a0c702-d168-4c6a-968d-5dcde418f56c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717781490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.717781490 |
| Directory | /workspace/82.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.3668842235 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 30921078771 ps |
| CPU time | 366.55 seconds |
| Started | Feb 07 04:22:19 PM PST 24 |
| Finished | Feb 07 04:28:26 PM PST 24 |
| Peak memory | 555712 kb |
| Host | smart-50843b65-9f08-43ef-8eda-175371899119 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668842235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.3668842235 |
| Directory | /workspace/82.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.4066984099 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 7678800979 ps |
| CPU time | 133.58 seconds |
| Started | Feb 07 04:22:18 PM PST 24 |
| Finished | Feb 07 04:24:32 PM PST 24 |
| Peak memory | 554648 kb |
| Host | smart-8cb2fe95-24ed-4e58-a433-17eafb73ca0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066984099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.4066984099 |
| Directory | /workspace/82.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.1301132070 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 141608905 ps |
| CPU time | 14.55 seconds |
| Started | Feb 07 04:22:19 PM PST 24 |
| Finished | Feb 07 04:22:35 PM PST 24 |
| Peak memory | 555660 kb |
| Host | smart-642bbbc7-0f96-40bb-9ac9-d4540fd2f858 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301132070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_del ays.1301132070 |
| Directory | /workspace/82.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_same_source.1806856707 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 2745072527 ps |
| CPU time | 86.77 seconds |
| Started | Feb 07 04:22:17 PM PST 24 |
| Finished | Feb 07 04:23:45 PM PST 24 |
| Peak memory | 555032 kb |
| Host | smart-36da298a-9e58-4162-ac37-45de805047dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806856707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.1806856707 |
| Directory | /workspace/82.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke.3432918909 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 240681754 ps |
| CPU time | 9.82 seconds |
| Started | Feb 07 04:22:23 PM PST 24 |
| Finished | Feb 07 04:22:34 PM PST 24 |
| Peak memory | 553200 kb |
| Host | smart-e0e2e77a-7f99-4302-9e7f-a646f5d33697 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432918909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.3432918909 |
| Directory | /workspace/82.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.891076387 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 7331529846 ps |
| CPU time | 77.92 seconds |
| Started | Feb 07 04:22:19 PM PST 24 |
| Finished | Feb 07 04:23:38 PM PST 24 |
| Peak memory | 553364 kb |
| Host | smart-6cfb9643-fa9d-40fc-a96c-8c840a425935 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891076387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.891076387 |
| Directory | /workspace/82.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.1766936608 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 3596151595 ps |
| CPU time | 62.74 seconds |
| Started | Feb 07 04:22:16 PM PST 24 |
| Finished | Feb 07 04:23:19 PM PST 24 |
| Peak memory | 552952 kb |
| Host | smart-44db0294-9975-4e55-9ac4-6acb18d5d587 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766936608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.1766936608 |
| Directory | /workspace/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.2221607761 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 41637695 ps |
| CPU time | 6 seconds |
| Started | Feb 07 04:22:22 PM PST 24 |
| Finished | Feb 07 04:22:30 PM PST 24 |
| Peak memory | 553316 kb |
| Host | smart-fb24b87b-5ae9-40a8-9944-e357b200533c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221607761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delay s.2221607761 |
| Directory | /workspace/82.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all.1217248141 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 1439231225 ps |
| CPU time | 45.64 seconds |
| Started | Feb 07 04:22:24 PM PST 24 |
| Finished | Feb 07 04:23:10 PM PST 24 |
| Peak memory | 555796 kb |
| Host | smart-311624b5-a664-41fd-bfb2-faf8c1f787df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217248141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.1217248141 |
| Directory | /workspace/82.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.600483369 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 5215711110 ps |
| CPU time | 559.26 seconds |
| Started | Feb 07 04:22:19 PM PST 24 |
| Finished | Feb 07 04:31:39 PM PST 24 |
| Peak memory | 559212 kb |
| Host | smart-0a86657e-9a85-43cd-822e-6cd21c9226fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600483369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_ with_rand_reset.600483369 |
| Directory | /workspace/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.3868840228 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 2767903698 ps |
| CPU time | 252.45 seconds |
| Started | Feb 07 04:22:23 PM PST 24 |
| Finished | Feb 07 04:26:36 PM PST 24 |
| Peak memory | 559360 kb |
| Host | smart-da935964-6954-400a-b4d1-ad750afff9dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868840228 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_al l_with_reset_error.3868840228 |
| Directory | /workspace/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.4042086391 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 129633240 ps |
| CPU time | 16.18 seconds |
| Started | Feb 07 04:22:18 PM PST 24 |
| Finished | Feb 07 04:22:34 PM PST 24 |
| Peak memory | 555688 kb |
| Host | smart-33270c82-a11d-4af9-a416-1a8798def3c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042086391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.4042086391 |
| Directory | /workspace/82.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device.951713419 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 51281505 ps |
| CPU time | 9.31 seconds |
| Started | Feb 07 04:22:33 PM PST 24 |
| Finished | Feb 07 04:22:43 PM PST 24 |
| Peak memory | 554324 kb |
| Host | smart-750abe8b-6460-4472-ae01-afee76bc8940 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951713419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device. 951713419 |
| Directory | /workspace/83.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.1788805541 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 11079936367 ps |
| CPU time | 187.6 seconds |
| Started | Feb 07 04:22:33 PM PST 24 |
| Finished | Feb 07 04:25:41 PM PST 24 |
| Peak memory | 553644 kb |
| Host | smart-e93395bc-171b-4167-8cb2-1bd472ed86a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788805541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_ device_slow_rsp.1788805541 |
| Directory | /workspace/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.1248526589 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 295987082 ps |
| CPU time | 30.5 seconds |
| Started | Feb 07 04:22:26 PM PST 24 |
| Finished | Feb 07 04:22:56 PM PST 24 |
| Peak memory | 555376 kb |
| Host | smart-8c837d87-6cee-4785-abf5-dbf355f87bb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248526589 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_add r.1248526589 |
| Directory | /workspace/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_random.3936901646 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 2535764222 ps |
| CPU time | 77.37 seconds |
| Started | Feb 07 04:22:36 PM PST 24 |
| Finished | Feb 07 04:23:54 PM PST 24 |
| Peak memory | 555252 kb |
| Host | smart-d0728e96-049a-4132-982c-bad7937fdffb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936901646 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.3936901646 |
| Directory | /workspace/83.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random.4170497288 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 2287818431 ps |
| CPU time | 83.45 seconds |
| Started | Feb 07 04:22:27 PM PST 24 |
| Finished | Feb 07 04:23:51 PM PST 24 |
| Peak memory | 555436 kb |
| Host | smart-3d9b681d-d70a-4659-8a13-accfebe9dfdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170497288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.4170497288 |
| Directory | /workspace/83.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.4018306094 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 71115680958 ps |
| CPU time | 898.85 seconds |
| Started | Feb 07 04:22:29 PM PST 24 |
| Finished | Feb 07 04:37:28 PM PST 24 |
| Peak memory | 555704 kb |
| Host | smart-ed727ec1-4aa4-4c4f-b6dc-4f4f0b93010b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018306094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.4018306094 |
| Directory | /workspace/83.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.3492896629 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 29589193111 ps |
| CPU time | 512.43 seconds |
| Started | Feb 07 04:22:26 PM PST 24 |
| Finished | Feb 07 04:30:59 PM PST 24 |
| Peak memory | 555196 kb |
| Host | smart-97af3e0d-623b-467e-a0d6-c11964474e32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492896629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.3492896629 |
| Directory | /workspace/83.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.80333469 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 585296345 ps |
| CPU time | 50.99 seconds |
| Started | Feb 07 04:22:28 PM PST 24 |
| Finished | Feb 07 04:23:19 PM PST 24 |
| Peak memory | 555128 kb |
| Host | smart-7b17135d-4d82-4b74-b810-1e65695eec28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80333469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_delay s.80333469 |
| Directory | /workspace/83.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_same_source.1958261440 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 1591902150 ps |
| CPU time | 44.18 seconds |
| Started | Feb 07 04:22:31 PM PST 24 |
| Finished | Feb 07 04:23:15 PM PST 24 |
| Peak memory | 554944 kb |
| Host | smart-463636bb-694f-4874-b0e4-5b2eb797a08d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958261440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.1958261440 |
| Directory | /workspace/83.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke.1775295301 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 169992605 ps |
| CPU time | 8.26 seconds |
| Started | Feb 07 04:22:14 PM PST 24 |
| Finished | Feb 07 04:22:23 PM PST 24 |
| Peak memory | 552980 kb |
| Host | smart-b99d76cc-74e0-4766-b4ec-ce179db9d071 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775295301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.1775295301 |
| Directory | /workspace/83.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.1644727872 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 8592403897 ps |
| CPU time | 101.02 seconds |
| Started | Feb 07 04:22:19 PM PST 24 |
| Finished | Feb 07 04:24:01 PM PST 24 |
| Peak memory | 553408 kb |
| Host | smart-e52dfbef-6707-48ed-84d3-0495cb9fab76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644727872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.1644727872 |
| Directory | /workspace/83.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.2992078832 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 5445690002 ps |
| CPU time | 93.54 seconds |
| Started | Feb 07 04:22:33 PM PST 24 |
| Finished | Feb 07 04:24:07 PM PST 24 |
| Peak memory | 553356 kb |
| Host | smart-128f2da8-05a5-4f8f-9b75-e7d5c018eb3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992078832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.2992078832 |
| Directory | /workspace/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.3391268751 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 52582511 ps |
| CPU time | 6.88 seconds |
| Started | Feb 07 04:22:15 PM PST 24 |
| Finished | Feb 07 04:22:22 PM PST 24 |
| Peak memory | 553248 kb |
| Host | smart-d14f7974-f171-4919-b867-366651e0c969 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391268751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delay s.3391268751 |
| Directory | /workspace/83.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all.3006093395 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 11376022448 ps |
| CPU time | 404.34 seconds |
| Started | Feb 07 04:22:27 PM PST 24 |
| Finished | Feb 07 04:29:12 PM PST 24 |
| Peak memory | 556876 kb |
| Host | smart-4a36b468-d4eb-497b-adeb-c49c2a555320 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006093395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.3006093395 |
| Directory | /workspace/83.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.2729889864 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 11479689595 ps |
| CPU time | 457.12 seconds |
| Started | Feb 07 04:22:29 PM PST 24 |
| Finished | Feb 07 04:30:07 PM PST 24 |
| Peak memory | 556680 kb |
| Host | smart-32e908a5-3391-40b2-88d6-8d232faf841b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729889864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.2729889864 |
| Directory | /workspace/83.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.527008501 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 360232900 ps |
| CPU time | 118.62 seconds |
| Started | Feb 07 04:22:26 PM PST 24 |
| Finished | Feb 07 04:24:25 PM PST 24 |
| Peak memory | 557812 kb |
| Host | smart-7b4a78fa-e25c-4343-bb33-7823c648bb36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527008501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_ with_rand_reset.527008501 |
| Directory | /workspace/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.1019408653 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 315972176 ps |
| CPU time | 72.67 seconds |
| Started | Feb 07 04:22:27 PM PST 24 |
| Finished | Feb 07 04:23:40 PM PST 24 |
| Peak memory | 556856 kb |
| Host | smart-bc8df4d9-89d7-4c92-a09c-2434f51a7799 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019408653 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_al l_with_reset_error.1019408653 |
| Directory | /workspace/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.1538213630 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 297865933 ps |
| CPU time | 31.13 seconds |
| Started | Feb 07 04:22:36 PM PST 24 |
| Finished | Feb 07 04:23:08 PM PST 24 |
| Peak memory | 555076 kb |
| Host | smart-e710295f-e854-4a56-9bc1-0521c38fba4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538213630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.1538213630 |
| Directory | /workspace/83.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device.608725630 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 1060041089 ps |
| CPU time | 95.39 seconds |
| Started | Feb 07 04:22:38 PM PST 24 |
| Finished | Feb 07 04:24:14 PM PST 24 |
| Peak memory | 555444 kb |
| Host | smart-123dea0a-8eeb-469b-90a2-8b52d5a828d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608725630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device. 608725630 |
| Directory | /workspace/84.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.316446559 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 92512705364 ps |
| CPU time | 1644.17 seconds |
| Started | Feb 07 04:22:35 PM PST 24 |
| Finished | Feb 07 04:50:00 PM PST 24 |
| Peak memory | 556544 kb |
| Host | smart-46b3e82c-1f7f-4cec-962e-b6830e1a0a22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316446559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_d evice_slow_rsp.316446559 |
| Directory | /workspace/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.2898196585 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 755961274 ps |
| CPU time | 31.76 seconds |
| Started | Feb 07 04:22:45 PM PST 24 |
| Finished | Feb 07 04:23:17 PM PST 24 |
| Peak memory | 555340 kb |
| Host | smart-afb76fd5-dc71-475b-9685-b280d74609c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898196585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_add r.2898196585 |
| Directory | /workspace/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_random.1228994205 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 1231275318 ps |
| CPU time | 44.66 seconds |
| Started | Feb 07 04:22:34 PM PST 24 |
| Finished | Feb 07 04:23:19 PM PST 24 |
| Peak memory | 555636 kb |
| Host | smart-f7103758-c74a-46b6-a0be-395c720762d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228994205 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.1228994205 |
| Directory | /workspace/84.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random.2138149029 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 135132868 ps |
| CPU time | 7.74 seconds |
| Started | Feb 07 04:22:34 PM PST 24 |
| Finished | Feb 07 04:22:42 PM PST 24 |
| Peak memory | 553556 kb |
| Host | smart-b6d4269a-751f-4f34-bc7d-de3f3fa7eb8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138149029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.2138149029 |
| Directory | /workspace/84.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.473083086 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 93859365462 ps |
| CPU time | 1129.5 seconds |
| Started | Feb 07 04:22:36 PM PST 24 |
| Finished | Feb 07 04:41:27 PM PST 24 |
| Peak memory | 555224 kb |
| Host | smart-836b42fa-b1c0-4052-baa0-b2046693d1d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473083086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.473083086 |
| Directory | /workspace/84.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.2569803638 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 23494067529 ps |
| CPU time | 445.1 seconds |
| Started | Feb 07 04:22:35 PM PST 24 |
| Finished | Feb 07 04:30:01 PM PST 24 |
| Peak memory | 555740 kb |
| Host | smart-f4e52a25-c034-43d0-af6e-011dad7f031e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569803638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.2569803638 |
| Directory | /workspace/84.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.189036916 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 231971904 ps |
| CPU time | 24.1 seconds |
| Started | Feb 07 04:22:35 PM PST 24 |
| Finished | Feb 07 04:23:00 PM PST 24 |
| Peak memory | 555420 kb |
| Host | smart-8845006b-9876-49ed-9d7a-87283217a5fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189036916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_dela ys.189036916 |
| Directory | /workspace/84.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_same_source.2404463050 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 269736340 ps |
| CPU time | 19 seconds |
| Started | Feb 07 04:22:42 PM PST 24 |
| Finished | Feb 07 04:23:01 PM PST 24 |
| Peak memory | 555184 kb |
| Host | smart-2daae4bd-8c8c-44cd-8276-bcd442230619 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404463050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.2404463050 |
| Directory | /workspace/84.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke.208614435 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 50604933 ps |
| CPU time | 6.44 seconds |
| Started | Feb 07 04:22:29 PM PST 24 |
| Finished | Feb 07 04:22:36 PM PST 24 |
| Peak memory | 553528 kb |
| Host | smart-f51e8349-046b-494c-91f3-ca4ba1fd79b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208614435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.208614435 |
| Directory | /workspace/84.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.2416650401 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 9481413309 ps |
| CPU time | 93.2 seconds |
| Started | Feb 07 04:22:37 PM PST 24 |
| Finished | Feb 07 04:24:10 PM PST 24 |
| Peak memory | 553400 kb |
| Host | smart-9b06423f-3df4-40c1-8160-9c2636c56ca3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416650401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.2416650401 |
| Directory | /workspace/84.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.1580259966 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 3968013311 ps |
| CPU time | 70.23 seconds |
| Started | Feb 07 04:22:35 PM PST 24 |
| Finished | Feb 07 04:23:45 PM PST 24 |
| Peak memory | 553652 kb |
| Host | smart-00b61a03-2452-4505-a038-f4d64fc6fe02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580259966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.1580259966 |
| Directory | /workspace/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.1751035751 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 34952094 ps |
| CPU time | 5.83 seconds |
| Started | Feb 07 04:22:42 PM PST 24 |
| Finished | Feb 07 04:22:48 PM PST 24 |
| Peak memory | 553600 kb |
| Host | smart-db83742f-ae03-4839-8ce3-8eadd614a6fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751035751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delay s.1751035751 |
| Directory | /workspace/84.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all.639142633 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 8137167012 ps |
| CPU time | 296.71 seconds |
| Started | Feb 07 04:22:44 PM PST 24 |
| Finished | Feb 07 04:27:42 PM PST 24 |
| Peak memory | 556864 kb |
| Host | smart-510bef38-f826-415b-aa87-5e427aeed8cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639142633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.639142633 |
| Directory | /workspace/84.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.3723067131 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 12298081550 ps |
| CPU time | 445.11 seconds |
| Started | Feb 07 04:22:47 PM PST 24 |
| Finished | Feb 07 04:30:12 PM PST 24 |
| Peak memory | 557108 kb |
| Host | smart-800b7df5-0051-4dcc-9cb4-75aee5e91864 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723067131 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.3723067131 |
| Directory | /workspace/84.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.97975512 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 6876287905 ps |
| CPU time | 509.15 seconds |
| Started | Feb 07 04:22:44 PM PST 24 |
| Finished | Feb 07 04:31:14 PM PST 24 |
| Peak memory | 557672 kb |
| Host | smart-1c0927a3-cd78-4508-993d-d04c7de64c9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97975512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_w ith_rand_reset.97975512 |
| Directory | /workspace/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.1527567276 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 5459122034 ps |
| CPU time | 645.92 seconds |
| Started | Feb 07 04:22:44 PM PST 24 |
| Finished | Feb 07 04:33:30 PM PST 24 |
| Peak memory | 567588 kb |
| Host | smart-d09748ba-fcca-485a-9337-54f352cdbe86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527567276 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_al l_with_reset_error.1527567276 |
| Directory | /workspace/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.3574813825 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 431926500 ps |
| CPU time | 20.32 seconds |
| Started | Feb 07 04:22:36 PM PST 24 |
| Finished | Feb 07 04:22:57 PM PST 24 |
| Peak memory | 555720 kb |
| Host | smart-bcfcfea9-9e82-48a5-92f0-8ef3e85b6bdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574813825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.3574813825 |
| Directory | /workspace/84.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device.2774191575 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 2537674035 ps |
| CPU time | 94.14 seconds |
| Started | Feb 07 04:23:02 PM PST 24 |
| Finished | Feb 07 04:24:38 PM PST 24 |
| Peak memory | 555456 kb |
| Host | smart-4d8ab44c-a847-4361-9e45-3952b467d7b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774191575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device .2774191575 |
| Directory | /workspace/85.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.1623933943 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 130500258164 ps |
| CPU time | 2425.23 seconds |
| Started | Feb 07 04:22:59 PM PST 24 |
| Finished | Feb 07 05:03:26 PM PST 24 |
| Peak memory | 555448 kb |
| Host | smart-d088b9a8-de9d-4776-beb0-16864358e984 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623933943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_ device_slow_rsp.1623933943 |
| Directory | /workspace/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.1079982698 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 191782298 ps |
| CPU time | 22 seconds |
| Started | Feb 07 04:22:58 PM PST 24 |
| Finished | Feb 07 04:23:22 PM PST 24 |
| Peak memory | 555324 kb |
| Host | smart-259d8d53-29ae-4702-8928-dad39d4705ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079982698 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_add r.1079982698 |
| Directory | /workspace/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_random.3998511129 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 2012267974 ps |
| CPU time | 76.92 seconds |
| Started | Feb 07 04:22:56 PM PST 24 |
| Finished | Feb 07 04:24:17 PM PST 24 |
| Peak memory | 555304 kb |
| Host | smart-b528589b-6bb0-4455-bb82-b0bc7d755546 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998511129 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.3998511129 |
| Directory | /workspace/85.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random.2632823855 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 563061740 ps |
| CPU time | 49.59 seconds |
| Started | Feb 07 04:22:48 PM PST 24 |
| Finished | Feb 07 04:23:38 PM PST 24 |
| Peak memory | 555664 kb |
| Host | smart-5afb4f1e-354a-4f1e-80a4-003eaa5e80e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632823855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.2632823855 |
| Directory | /workspace/85.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.4166854209 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 21321230191 ps |
| CPU time | 237.85 seconds |
| Started | Feb 07 04:23:01 PM PST 24 |
| Finished | Feb 07 04:27:00 PM PST 24 |
| Peak memory | 555712 kb |
| Host | smart-6df4bd2b-dd16-4b25-9a49-20c0034e814f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166854209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.4166854209 |
| Directory | /workspace/85.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.4249456733 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 50622197366 ps |
| CPU time | 997.79 seconds |
| Started | Feb 07 04:22:57 PM PST 24 |
| Finished | Feb 07 04:39:38 PM PST 24 |
| Peak memory | 555436 kb |
| Host | smart-7b2c9923-64f3-4630-9ccc-070bbec40ecb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249456733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.4249456733 |
| Directory | /workspace/85.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.3192609162 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 327236350 ps |
| CPU time | 32.08 seconds |
| Started | Feb 07 04:22:45 PM PST 24 |
| Finished | Feb 07 04:23:17 PM PST 24 |
| Peak memory | 555360 kb |
| Host | smart-7ff7b45a-eb84-4d42-88b5-f8d42d3ea4ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192609162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_del ays.3192609162 |
| Directory | /workspace/85.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_same_source.4100364747 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 158527683 ps |
| CPU time | 7.35 seconds |
| Started | Feb 07 04:23:02 PM PST 24 |
| Finished | Feb 07 04:23:11 PM PST 24 |
| Peak memory | 553036 kb |
| Host | smart-cb55a8c2-e57d-47a0-a119-5686ee31deef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100364747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.4100364747 |
| Directory | /workspace/85.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke.3976321845 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 138414524 ps |
| CPU time | 8.01 seconds |
| Started | Feb 07 04:22:44 PM PST 24 |
| Finished | Feb 07 04:22:53 PM PST 24 |
| Peak memory | 553532 kb |
| Host | smart-415cdfdd-4a1e-4854-a9b2-1eaa829e7174 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976321845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.3976321845 |
| Directory | /workspace/85.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.4261614241 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 5738371104 ps |
| CPU time | 63.21 seconds |
| Started | Feb 07 04:22:46 PM PST 24 |
| Finished | Feb 07 04:23:50 PM PST 24 |
| Peak memory | 553408 kb |
| Host | smart-6b5305f8-74aa-4d58-a9cf-297c7e604fcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261614241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.4261614241 |
| Directory | /workspace/85.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.3066458161 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 5375629209 ps |
| CPU time | 100.8 seconds |
| Started | Feb 07 04:22:47 PM PST 24 |
| Finished | Feb 07 04:24:28 PM PST 24 |
| Peak memory | 553640 kb |
| Host | smart-ca4b90f8-ea1e-40f8-be49-76228bd1a1a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066458161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.3066458161 |
| Directory | /workspace/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.1041151353 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 53365189 ps |
| CPU time | 6.18 seconds |
| Started | Feb 07 04:22:43 PM PST 24 |
| Finished | Feb 07 04:22:50 PM PST 24 |
| Peak memory | 553304 kb |
| Host | smart-296e3b8c-88bd-4a13-814f-178bc8bea399 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041151353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delay s.1041151353 |
| Directory | /workspace/85.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all.1048021051 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 3733813020 ps |
| CPU time | 125.95 seconds |
| Started | Feb 07 04:22:59 PM PST 24 |
| Finished | Feb 07 04:25:06 PM PST 24 |
| Peak memory | 559376 kb |
| Host | smart-2c07ad0c-35f5-425f-ac40-b4ce74d78174 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048021051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.1048021051 |
| Directory | /workspace/85.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.2344814041 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 11617782032 ps |
| CPU time | 493.1 seconds |
| Started | Feb 07 04:23:00 PM PST 24 |
| Finished | Feb 07 04:31:14 PM PST 24 |
| Peak memory | 556676 kb |
| Host | smart-614bc3b2-68c6-49e2-bb2e-eaa89c6a9462 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344814041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.2344814041 |
| Directory | /workspace/85.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.215285106 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 245656925 ps |
| CPU time | 102.94 seconds |
| Started | Feb 07 04:22:59 PM PST 24 |
| Finished | Feb 07 04:24:43 PM PST 24 |
| Peak memory | 556560 kb |
| Host | smart-f097f852-a1ef-4173-8d62-094d37c9f263 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215285106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_ with_rand_reset.215285106 |
| Directory | /workspace/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.3174481141 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 921300383 ps |
| CPU time | 129.41 seconds |
| Started | Feb 07 04:23:00 PM PST 24 |
| Finished | Feb 07 04:25:11 PM PST 24 |
| Peak memory | 556848 kb |
| Host | smart-0f84bcfa-0f48-457e-b3a6-08209448b2ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174481141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_al l_with_reset_error.3174481141 |
| Directory | /workspace/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.3653842802 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 1140825991 ps |
| CPU time | 50.17 seconds |
| Started | Feb 07 04:22:58 PM PST 24 |
| Finished | Feb 07 04:23:51 PM PST 24 |
| Peak memory | 555580 kb |
| Host | smart-0580dfd6-8aaf-4f38-8ce9-7444c96df6b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653842802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.3653842802 |
| Directory | /workspace/85.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device.452970686 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 778135022 ps |
| CPU time | 62.94 seconds |
| Started | Feb 07 04:23:14 PM PST 24 |
| Finished | Feb 07 04:24:18 PM PST 24 |
| Peak memory | 555364 kb |
| Host | smart-103e0ad1-cc8f-4e70-8b38-53d50ba0a1c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452970686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device. 452970686 |
| Directory | /workspace/86.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.1974455218 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 126727911718 ps |
| CPU time | 2602.45 seconds |
| Started | Feb 07 04:23:16 PM PST 24 |
| Finished | Feb 07 05:06:41 PM PST 24 |
| Peak memory | 556760 kb |
| Host | smart-cd881965-41de-496c-b98a-9b1ce5a21a15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974455218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_ device_slow_rsp.1974455218 |
| Directory | /workspace/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.1072964599 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 590169639 ps |
| CPU time | 26.08 seconds |
| Started | Feb 07 04:23:07 PM PST 24 |
| Finished | Feb 07 04:23:33 PM PST 24 |
| Peak memory | 555376 kb |
| Host | smart-183b8dd5-b351-4cf7-b5aa-1b163a19e57d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072964599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_add r.1072964599 |
| Directory | /workspace/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_random.569392413 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 2595226321 ps |
| CPU time | 91.67 seconds |
| Started | Feb 07 04:23:15 PM PST 24 |
| Finished | Feb 07 04:24:47 PM PST 24 |
| Peak memory | 555688 kb |
| Host | smart-5eb9db75-01a5-4c8e-9bb7-6ead9d9f2cb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569392413 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.569392413 |
| Directory | /workspace/86.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random.269271307 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 1198083315 ps |
| CPU time | 44.81 seconds |
| Started | Feb 07 04:22:56 PM PST 24 |
| Finished | Feb 07 04:23:44 PM PST 24 |
| Peak memory | 555636 kb |
| Host | smart-9491c419-d1a7-4461-8f6d-12b20c31168b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269271307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.269271307 |
| Directory | /workspace/86.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.284045583 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 27175106419 ps |
| CPU time | 303.42 seconds |
| Started | Feb 07 04:23:01 PM PST 24 |
| Finished | Feb 07 04:28:06 PM PST 24 |
| Peak memory | 555508 kb |
| Host | smart-2a8e78d2-ffc1-437c-9a1f-b8b6b2413f4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284045583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.284045583 |
| Directory | /workspace/86.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.3808067967 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 31008140789 ps |
| CPU time | 587.33 seconds |
| Started | Feb 07 04:23:06 PM PST 24 |
| Finished | Feb 07 04:32:54 PM PST 24 |
| Peak memory | 555440 kb |
| Host | smart-24e40787-81f8-4f60-84c1-7a665b9b49c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808067967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.3808067967 |
| Directory | /workspace/86.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.2228299240 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 106286056 ps |
| CPU time | 10.93 seconds |
| Started | Feb 07 04:23:01 PM PST 24 |
| Finished | Feb 07 04:23:14 PM PST 24 |
| Peak memory | 555388 kb |
| Host | smart-331748e0-efa2-4f83-ba63-c22873ce1e0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228299240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_del ays.2228299240 |
| Directory | /workspace/86.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_same_source.3127944647 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 1417792852 ps |
| CPU time | 46.52 seconds |
| Started | Feb 07 04:23:10 PM PST 24 |
| Finished | Feb 07 04:23:57 PM PST 24 |
| Peak memory | 555216 kb |
| Host | smart-ff7e78d3-740d-4163-bee2-b038888b5064 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127944647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.3127944647 |
| Directory | /workspace/86.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke.3328645800 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 46561069 ps |
| CPU time | 6.33 seconds |
| Started | Feb 07 04:22:59 PM PST 24 |
| Finished | Feb 07 04:23:07 PM PST 24 |
| Peak memory | 553616 kb |
| Host | smart-0601cebf-7e37-41f1-a6cc-ec6d19037051 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328645800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.3328645800 |
| Directory | /workspace/86.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.2056333595 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 8739379794 ps |
| CPU time | 96.57 seconds |
| Started | Feb 07 04:23:01 PM PST 24 |
| Finished | Feb 07 04:24:38 PM PST 24 |
| Peak memory | 553108 kb |
| Host | smart-6515ea7e-36aa-4343-8850-2e9a4666e1c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056333595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.2056333595 |
| Directory | /workspace/86.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.392582151 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 6236253438 ps |
| CPU time | 104.91 seconds |
| Started | Feb 07 04:22:58 PM PST 24 |
| Finished | Feb 07 04:24:45 PM PST 24 |
| Peak memory | 553704 kb |
| Host | smart-7ee310a2-8e4a-4081-adbf-3deb78294650 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392582151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.392582151 |
| Directory | /workspace/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.1475886920 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 43197830 ps |
| CPU time | 5.96 seconds |
| Started | Feb 07 04:22:58 PM PST 24 |
| Finished | Feb 07 04:23:06 PM PST 24 |
| Peak memory | 553444 kb |
| Host | smart-0049254f-c747-4843-9fe3-6786b6c708a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475886920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delay s.1475886920 |
| Directory | /workspace/86.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all.1590940509 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 7734053634 ps |
| CPU time | 323.22 seconds |
| Started | Feb 07 04:23:14 PM PST 24 |
| Finished | Feb 07 04:28:38 PM PST 24 |
| Peak memory | 556308 kb |
| Host | smart-c4ae9677-c112-4a96-a259-a8f7c2b0d165 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590940509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.1590940509 |
| Directory | /workspace/86.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.2412483445 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 6754311091 ps |
| CPU time | 303.97 seconds |
| Started | Feb 07 04:23:13 PM PST 24 |
| Finished | Feb 07 04:28:19 PM PST 24 |
| Peak memory | 556844 kb |
| Host | smart-992fdbdb-eb55-4400-a7ad-38aeaa6ad186 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412483445 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.2412483445 |
| Directory | /workspace/86.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.1075635539 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 40253840 ps |
| CPU time | 14.28 seconds |
| Started | Feb 07 04:23:16 PM PST 24 |
| Finished | Feb 07 04:23:32 PM PST 24 |
| Peak memory | 554516 kb |
| Host | smart-ffc8488d-d90c-43cc-85ca-0b14b66f83fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075635539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all _with_rand_reset.1075635539 |
| Directory | /workspace/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.2060360713 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 4378967727 ps |
| CPU time | 242.2 seconds |
| Started | Feb 07 04:23:12 PM PST 24 |
| Finished | Feb 07 04:27:17 PM PST 24 |
| Peak memory | 559384 kb |
| Host | smart-c0f51b98-1b91-415b-99b5-2c0809163d9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060360713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_al l_with_reset_error.2060360713 |
| Directory | /workspace/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.280310961 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 1297265775 ps |
| CPU time | 58.46 seconds |
| Started | Feb 07 04:23:11 PM PST 24 |
| Finished | Feb 07 04:24:13 PM PST 24 |
| Peak memory | 555204 kb |
| Host | smart-5533067b-d72f-41ca-b8e0-15701546064c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280310961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.280310961 |
| Directory | /workspace/86.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device.716757578 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 101874279 ps |
| CPU time | 11.08 seconds |
| Started | Feb 07 04:23:15 PM PST 24 |
| Finished | Feb 07 04:23:27 PM PST 24 |
| Peak memory | 554116 kb |
| Host | smart-a7dc8407-ab1c-4a38-b738-178b2c91c899 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716757578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device. 716757578 |
| Directory | /workspace/87.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.171207076 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 102384645543 ps |
| CPU time | 1950.26 seconds |
| Started | Feb 07 04:23:14 PM PST 24 |
| Finished | Feb 07 04:55:46 PM PST 24 |
| Peak memory | 556668 kb |
| Host | smart-9a276df3-3827-4e54-97cd-4653669688f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171207076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_d evice_slow_rsp.171207076 |
| Directory | /workspace/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.762590126 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 538890580 ps |
| CPU time | 26.81 seconds |
| Started | Feb 07 04:23:16 PM PST 24 |
| Finished | Feb 07 04:23:44 PM PST 24 |
| Peak memory | 555636 kb |
| Host | smart-ab9871e8-1e86-4c05-b578-c87ba99a0001 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762590126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_addr .762590126 |
| Directory | /workspace/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_random.1290115070 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 311724796 ps |
| CPU time | 26.74 seconds |
| Started | Feb 07 04:23:13 PM PST 24 |
| Finished | Feb 07 04:23:42 PM PST 24 |
| Peak memory | 555624 kb |
| Host | smart-9d5dc16b-2bfc-4251-9868-5bc7521e25ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290115070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.1290115070 |
| Directory | /workspace/87.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random.4154750226 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 350001913 ps |
| CPU time | 31.54 seconds |
| Started | Feb 07 04:23:16 PM PST 24 |
| Finished | Feb 07 04:23:49 PM PST 24 |
| Peak memory | 555352 kb |
| Host | smart-a99fed3d-fabe-4a77-8a0e-4cbabe70c16d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154750226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.4154750226 |
| Directory | /workspace/87.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.723331603 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 90579963647 ps |
| CPU time | 1123.94 seconds |
| Started | Feb 07 04:23:14 PM PST 24 |
| Finished | Feb 07 04:41:59 PM PST 24 |
| Peak memory | 555208 kb |
| Host | smart-cec5fddc-320d-4f65-b24e-03274f493983 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723331603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.723331603 |
| Directory | /workspace/87.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.3886603347 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 46925562908 ps |
| CPU time | 953.88 seconds |
| Started | Feb 07 04:23:26 PM PST 24 |
| Finished | Feb 07 04:39:23 PM PST 24 |
| Peak memory | 555664 kb |
| Host | smart-0633ace7-d589-4322-bb4e-50b1093fbb4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886603347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.3886603347 |
| Directory | /workspace/87.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.2102804019 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 308305959 ps |
| CPU time | 25.13 seconds |
| Started | Feb 07 04:23:09 PM PST 24 |
| Finished | Feb 07 04:23:36 PM PST 24 |
| Peak memory | 555668 kb |
| Host | smart-4478e7f6-7c1d-4323-a809-29ca5cc8c192 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102804019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_del ays.2102804019 |
| Directory | /workspace/87.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_same_source.3691642880 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 1946097141 ps |
| CPU time | 62.3 seconds |
| Started | Feb 07 04:23:14 PM PST 24 |
| Finished | Feb 07 04:24:17 PM PST 24 |
| Peak memory | 555592 kb |
| Host | smart-903040a4-30dc-435e-a3fa-d3e0076d52b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691642880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.3691642880 |
| Directory | /workspace/87.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke.1019223284 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 43279780 ps |
| CPU time | 5.59 seconds |
| Started | Feb 07 04:23:15 PM PST 24 |
| Finished | Feb 07 04:23:21 PM PST 24 |
| Peak memory | 553584 kb |
| Host | smart-9d3efeea-2776-4a1c-93aa-7274ecb98171 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019223284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.1019223284 |
| Directory | /workspace/87.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.2879167156 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 8221333745 ps |
| CPU time | 88.49 seconds |
| Started | Feb 07 04:23:10 PM PST 24 |
| Finished | Feb 07 04:24:42 PM PST 24 |
| Peak memory | 553648 kb |
| Host | smart-25b43c77-c444-4fe0-9916-fff903686b3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879167156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.2879167156 |
| Directory | /workspace/87.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.520524968 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 7361083372 ps |
| CPU time | 138.54 seconds |
| Started | Feb 07 04:23:06 PM PST 24 |
| Finished | Feb 07 04:25:25 PM PST 24 |
| Peak memory | 553680 kb |
| Host | smart-08592f1b-ff87-4f2c-9b01-7931cb5e4892 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520524968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.520524968 |
| Directory | /workspace/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.3576499264 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 47029083 ps |
| CPU time | 6.46 seconds |
| Started | Feb 07 04:23:16 PM PST 24 |
| Finished | Feb 07 04:23:25 PM PST 24 |
| Peak memory | 553032 kb |
| Host | smart-618f8a68-9036-44ae-a153-411b1f84f443 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576499264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delay s.3576499264 |
| Directory | /workspace/87.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all.2298664871 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 2494926204 ps |
| CPU time | 166.4 seconds |
| Started | Feb 07 04:23:14 PM PST 24 |
| Finished | Feb 07 04:26:01 PM PST 24 |
| Peak memory | 556844 kb |
| Host | smart-f6ffd40f-ba90-4a8c-a110-3b14192eed6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298664871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.2298664871 |
| Directory | /workspace/87.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.27780197 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 11570478841 ps |
| CPU time | 404.51 seconds |
| Started | Feb 07 04:23:13 PM PST 24 |
| Finished | Feb 07 04:30:00 PM PST 24 |
| Peak memory | 556712 kb |
| Host | smart-118e9c9a-f13b-4d2e-87fa-e579bd6f8334 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27780197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.27780197 |
| Directory | /workspace/87.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.34727894 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 3593722989 ps |
| CPU time | 232.11 seconds |
| Started | Feb 07 04:23:32 PM PST 24 |
| Finished | Feb 07 04:27:25 PM PST 24 |
| Peak memory | 557428 kb |
| Host | smart-f5a5556c-e6fd-4cfd-94e5-d70c94ef3d8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34727894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_w ith_rand_reset.34727894 |
| Directory | /workspace/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.1032707311 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 110414708 ps |
| CPU time | 22.63 seconds |
| Started | Feb 07 04:23:14 PM PST 24 |
| Finished | Feb 07 04:23:38 PM PST 24 |
| Peak memory | 555520 kb |
| Host | smart-280577d6-df81-46db-94cf-73245ff49b15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032707311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_al l_with_reset_error.1032707311 |
| Directory | /workspace/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.2988204555 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 49251088 ps |
| CPU time | 7.74 seconds |
| Started | Feb 07 04:23:24 PM PST 24 |
| Finished | Feb 07 04:23:34 PM PST 24 |
| Peak memory | 554120 kb |
| Host | smart-f1463151-1b49-4cd6-89bf-8d26833390f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988204555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.2988204555 |
| Directory | /workspace/87.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device.591072881 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 1585660142 ps |
| CPU time | 68.72 seconds |
| Started | Feb 07 04:23:28 PM PST 24 |
| Finished | Feb 07 04:24:38 PM PST 24 |
| Peak memory | 555684 kb |
| Host | smart-72facb9f-f032-43cc-b377-68bea5dde3a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591072881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device. 591072881 |
| Directory | /workspace/88.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.3842424687 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 41499199708 ps |
| CPU time | 706.76 seconds |
| Started | Feb 07 04:23:21 PM PST 24 |
| Finished | Feb 07 04:35:12 PM PST 24 |
| Peak memory | 555168 kb |
| Host | smart-adc3550a-eb5b-429d-9432-3ea3f25b8b62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842424687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_ device_slow_rsp.3842424687 |
| Directory | /workspace/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.2744249799 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 120775846 ps |
| CPU time | 15.05 seconds |
| Started | Feb 07 04:23:36 PM PST 24 |
| Finished | Feb 07 04:23:52 PM PST 24 |
| Peak memory | 555340 kb |
| Host | smart-138372de-6fc7-4643-a63d-37cc0a2f6962 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744249799 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_add r.2744249799 |
| Directory | /workspace/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_random.1417376802 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 401337288 ps |
| CPU time | 15.39 seconds |
| Started | Feb 07 04:23:20 PM PST 24 |
| Finished | Feb 07 04:23:36 PM PST 24 |
| Peak memory | 555320 kb |
| Host | smart-e94d1ac3-3fe2-49d1-9617-62c3ce3f683e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417376802 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.1417376802 |
| Directory | /workspace/88.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random.2938385153 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 2464433150 ps |
| CPU time | 85.5 seconds |
| Started | Feb 07 04:23:35 PM PST 24 |
| Finished | Feb 07 04:25:02 PM PST 24 |
| Peak memory | 555724 kb |
| Host | smart-134d9ed3-ebf7-4083-95ba-139a48e23d81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938385153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.2938385153 |
| Directory | /workspace/88.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.258423399 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 59369561685 ps |
| CPU time | 735.97 seconds |
| Started | Feb 07 04:23:24 PM PST 24 |
| Finished | Feb 07 04:35:42 PM PST 24 |
| Peak memory | 555724 kb |
| Host | smart-ab2acee2-2ea6-4e6b-b613-ef807908b822 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258423399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.258423399 |
| Directory | /workspace/88.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.863473566 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 14884299432 ps |
| CPU time | 266.41 seconds |
| Started | Feb 07 04:23:19 PM PST 24 |
| Finished | Feb 07 04:27:46 PM PST 24 |
| Peak memory | 555708 kb |
| Host | smart-ca521c2b-e860-4765-abb7-8fdc857357f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863473566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.863473566 |
| Directory | /workspace/88.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.682220698 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 156730373 ps |
| CPU time | 14.23 seconds |
| Started | Feb 07 04:23:36 PM PST 24 |
| Finished | Feb 07 04:23:51 PM PST 24 |
| Peak memory | 555376 kb |
| Host | smart-ac0eca3f-56db-4e22-a95b-2a0b51b8f9d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682220698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_dela ys.682220698 |
| Directory | /workspace/88.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_same_source.1293665290 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 351494962 ps |
| CPU time | 30.03 seconds |
| Started | Feb 07 04:23:27 PM PST 24 |
| Finished | Feb 07 04:23:59 PM PST 24 |
| Peak memory | 555356 kb |
| Host | smart-29257f84-66ff-46ac-8f4c-0492c0546af0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293665290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.1293665290 |
| Directory | /workspace/88.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke.782045527 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 205990858 ps |
| CPU time | 9.31 seconds |
| Started | Feb 07 04:23:36 PM PST 24 |
| Finished | Feb 07 04:23:46 PM PST 24 |
| Peak memory | 553280 kb |
| Host | smart-0e13aa7f-a0a9-40ba-ae7d-d858a9756f9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782045527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.782045527 |
| Directory | /workspace/88.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.3964497132 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 7168924944 ps |
| CPU time | 70.85 seconds |
| Started | Feb 07 04:23:19 PM PST 24 |
| Finished | Feb 07 04:24:31 PM PST 24 |
| Peak memory | 553240 kb |
| Host | smart-f6ae281e-d8bc-4e89-81f2-92e4851de987 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964497132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.3964497132 |
| Directory | /workspace/88.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.3758937639 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 5074078108 ps |
| CPU time | 89.46 seconds |
| Started | Feb 07 04:23:27 PM PST 24 |
| Finished | Feb 07 04:24:58 PM PST 24 |
| Peak memory | 559192 kb |
| Host | smart-c1051a79-be05-4206-a7a4-ea182a70de2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758937639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.3758937639 |
| Directory | /workspace/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.2460887717 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 48483490 ps |
| CPU time | 6.55 seconds |
| Started | Feb 07 04:23:26 PM PST 24 |
| Finished | Feb 07 04:23:34 PM PST 24 |
| Peak memory | 553584 kb |
| Host | smart-d694ecb6-3095-4fe8-a4ac-49e00e91c843 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460887717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delay s.2460887717 |
| Directory | /workspace/88.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all.1984078507 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 3555207779 ps |
| CPU time | 284.78 seconds |
| Started | Feb 07 04:23:36 PM PST 24 |
| Finished | Feb 07 04:28:22 PM PST 24 |
| Peak memory | 557024 kb |
| Host | smart-a3442fca-2c4f-43c3-a13d-a58c4e5567df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984078507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.1984078507 |
| Directory | /workspace/88.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.1456630164 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 7045177511 ps |
| CPU time | 231.62 seconds |
| Started | Feb 07 04:23:38 PM PST 24 |
| Finished | Feb 07 04:27:30 PM PST 24 |
| Peak memory | 556640 kb |
| Host | smart-c1fad163-a330-481d-9506-7fabe14c8cfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456630164 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.1456630164 |
| Directory | /workspace/88.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.3806891442 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 5031974286 ps |
| CPU time | 507.08 seconds |
| Started | Feb 07 04:23:26 PM PST 24 |
| Finished | Feb 07 04:31:56 PM PST 24 |
| Peak memory | 559380 kb |
| Host | smart-9be54643-34fb-46d2-9a4d-48d360f88599 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806891442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all _with_rand_reset.3806891442 |
| Directory | /workspace/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.2778708922 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 7064440928 ps |
| CPU time | 345.18 seconds |
| Started | Feb 07 04:23:31 PM PST 24 |
| Finished | Feb 07 04:29:16 PM PST 24 |
| Peak memory | 558552 kb |
| Host | smart-46c69e15-0286-4449-83c7-ea806c3ab483 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778708922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_al l_with_reset_error.2778708922 |
| Directory | /workspace/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.3387527901 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 985031445 ps |
| CPU time | 41.77 seconds |
| Started | Feb 07 04:23:25 PM PST 24 |
| Finished | Feb 07 04:24:08 PM PST 24 |
| Peak memory | 555176 kb |
| Host | smart-5838c47a-9870-4df3-b3aa-a02138601d10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387527901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.3387527901 |
| Directory | /workspace/88.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device.856145280 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 1922388885 ps |
| CPU time | 75.79 seconds |
| Started | Feb 07 04:23:33 PM PST 24 |
| Finished | Feb 07 04:24:49 PM PST 24 |
| Peak memory | 556456 kb |
| Host | smart-2c68d48c-d7aa-4972-b9f5-f98a68d40ddd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856145280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device. 856145280 |
| Directory | /workspace/89.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.3496728031 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 42186545441 ps |
| CPU time | 792.24 seconds |
| Started | Feb 07 04:23:31 PM PST 24 |
| Finished | Feb 07 04:36:44 PM PST 24 |
| Peak memory | 555448 kb |
| Host | smart-3b5931c3-4884-4523-b08d-2e66a35ab1d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496728031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_ device_slow_rsp.3496728031 |
| Directory | /workspace/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.462212585 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 196291562 ps |
| CPU time | 22.24 seconds |
| Started | Feb 07 04:23:36 PM PST 24 |
| Finished | Feb 07 04:23:59 PM PST 24 |
| Peak memory | 555636 kb |
| Host | smart-0996646b-dc7f-40f2-9d32-3fa2302cd683 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462212585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_addr .462212585 |
| Directory | /workspace/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_random.1267285310 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 92677920 ps |
| CPU time | 9.84 seconds |
| Started | Feb 07 04:23:34 PM PST 24 |
| Finished | Feb 07 04:23:45 PM PST 24 |
| Peak memory | 555316 kb |
| Host | smart-c252b4e7-8713-4631-8e58-8cf117c6ace6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267285310 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.1267285310 |
| Directory | /workspace/89.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random.3549393471 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 322412945 ps |
| CPU time | 14.45 seconds |
| Started | Feb 07 04:23:32 PM PST 24 |
| Finished | Feb 07 04:23:47 PM PST 24 |
| Peak memory | 555632 kb |
| Host | smart-276a5935-5c5c-48d3-930a-54c2b4e7aa17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549393471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.3549393471 |
| Directory | /workspace/89.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.1622162944 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 99447435032 ps |
| CPU time | 1163.1 seconds |
| Started | Feb 07 04:23:30 PM PST 24 |
| Finished | Feb 07 04:42:53 PM PST 24 |
| Peak memory | 555396 kb |
| Host | smart-129e6916-2dcc-49a7-93b5-8ffc58b09a9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622162944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.1622162944 |
| Directory | /workspace/89.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.2057371808 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 38786870769 ps |
| CPU time | 750.11 seconds |
| Started | Feb 07 04:23:29 PM PST 24 |
| Finished | Feb 07 04:36:00 PM PST 24 |
| Peak memory | 555412 kb |
| Host | smart-e3761137-1f55-46ca-8ad3-71a2661f9ecb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057371808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.2057371808 |
| Directory | /workspace/89.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.59152272 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 215388868 ps |
| CPU time | 22.12 seconds |
| Started | Feb 07 04:23:29 PM PST 24 |
| Finished | Feb 07 04:23:52 PM PST 24 |
| Peak memory | 555664 kb |
| Host | smart-8364106c-4882-4698-94e7-0b72d0d5c87d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59152272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_delay s.59152272 |
| Directory | /workspace/89.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_same_source.355026315 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 1156989156 ps |
| CPU time | 34.23 seconds |
| Started | Feb 07 04:23:35 PM PST 24 |
| Finished | Feb 07 04:24:10 PM PST 24 |
| Peak memory | 555624 kb |
| Host | smart-354a8e45-2146-4fa3-89c4-3f53e0beebce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355026315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.355026315 |
| Directory | /workspace/89.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke.3807408348 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 57924549 ps |
| CPU time | 6.78 seconds |
| Started | Feb 07 04:23:32 PM PST 24 |
| Finished | Feb 07 04:23:39 PM PST 24 |
| Peak memory | 553628 kb |
| Host | smart-30796ab2-d0a5-4677-852b-8850a0cebe15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807408348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.3807408348 |
| Directory | /workspace/89.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.713096994 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 9153926214 ps |
| CPU time | 93.24 seconds |
| Started | Feb 07 04:23:32 PM PST 24 |
| Finished | Feb 07 04:25:06 PM PST 24 |
| Peak memory | 553368 kb |
| Host | smart-8e030dd6-1525-4361-8c96-5f300dbdbbcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713096994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.713096994 |
| Directory | /workspace/89.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.1661174788 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 5206230866 ps |
| CPU time | 91.16 seconds |
| Started | Feb 07 04:23:30 PM PST 24 |
| Finished | Feb 07 04:25:02 PM PST 24 |
| Peak memory | 553668 kb |
| Host | smart-1ca63aff-706a-438c-9e7e-26a7d28f42c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661174788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.1661174788 |
| Directory | /workspace/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.1914784186 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 45972443 ps |
| CPU time | 6.09 seconds |
| Started | Feb 07 04:23:36 PM PST 24 |
| Finished | Feb 07 04:23:43 PM PST 24 |
| Peak memory | 553288 kb |
| Host | smart-fa9063ce-a8c1-4025-bc9a-b2bc4adea389 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914784186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delay s.1914784186 |
| Directory | /workspace/89.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all.1526723341 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 2303120557 ps |
| CPU time | 188.87 seconds |
| Started | Feb 07 04:23:32 PM PST 24 |
| Finished | Feb 07 04:26:41 PM PST 24 |
| Peak memory | 556804 kb |
| Host | smart-d7d0dcf0-0449-4758-89e1-61bcddb5f543 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526723341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.1526723341 |
| Directory | /workspace/89.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.764959589 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 521708954 ps |
| CPU time | 48.54 seconds |
| Started | Feb 07 04:23:38 PM PST 24 |
| Finished | Feb 07 04:24:27 PM PST 24 |
| Peak memory | 555328 kb |
| Host | smart-a06f84e9-b9f6-4048-97e7-814e0cf2a179 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764959589 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.764959589 |
| Directory | /workspace/89.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.2143319271 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 8622255286 ps |
| CPU time | 538.61 seconds |
| Started | Feb 07 04:23:38 PM PST 24 |
| Finished | Feb 07 04:32:37 PM PST 24 |
| Peak memory | 558692 kb |
| Host | smart-ba43cb64-50e2-4eeb-9dee-47c139548a08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143319271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_rand_reset.2143319271 |
| Directory | /workspace/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.3761057609 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 6400371056 ps |
| CPU time | 356.38 seconds |
| Started | Feb 07 04:24:00 PM PST 24 |
| Finished | Feb 07 04:29:57 PM PST 24 |
| Peak memory | 559424 kb |
| Host | smart-392fed85-61f2-476d-b86c-673f4ca6b064 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761057609 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_al l_with_reset_error.3761057609 |
| Directory | /workspace/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.1226518603 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 338236670 ps |
| CPU time | 32.19 seconds |
| Started | Feb 07 04:23:35 PM PST 24 |
| Finished | Feb 07 04:24:08 PM PST 24 |
| Peak memory | 555392 kb |
| Host | smart-38088b61-fab2-48a0-a1ea-542db99c4c1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226518603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.1226518603 |
| Directory | /workspace/89.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_rw.2757196909 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 3555724520 ps |
| CPU time | 248.47 seconds |
| Started | Feb 07 04:12:12 PM PST 24 |
| Finished | Feb 07 04:16:21 PM PST 24 |
| Peak memory | 580404 kb |
| Host | smart-7c0559ac-0a58-4886-92c9-2d2491d706d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757196909 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.2757196909 |
| Directory | /workspace/9.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_tl_errors.3041486947 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 2848890054 ps |
| CPU time | 156.51 seconds |
| Started | Feb 07 04:12:07 PM PST 24 |
| Finished | Feb 07 04:14:44 PM PST 24 |
| Peak memory | 580308 kb |
| Host | smart-94f40362-9f5d-4ca9-8d16-3a3f840ce00a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041486947 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.3041486947 |
| Directory | /workspace/9.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device.509931645 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 80587204 ps |
| CPU time | 10.89 seconds |
| Started | Feb 07 04:12:01 PM PST 24 |
| Finished | Feb 07 04:12:12 PM PST 24 |
| Peak memory | 554580 kb |
| Host | smart-24da721f-06bd-42eb-9471-c12b68eaa673 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509931645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.509931645 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.2337866719 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 69767443692 ps |
| CPU time | 1191.19 seconds |
| Started | Feb 07 04:12:06 PM PST 24 |
| Finished | Feb 07 04:31:58 PM PST 24 |
| Peak memory | 556472 kb |
| Host | smart-adbfe686-22fd-4dbb-9b85-3971adc79ebf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337866719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_d evice_slow_rsp.2337866719 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.2927710340 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 37786781 ps |
| CPU time | 6.85 seconds |
| Started | Feb 07 04:12:00 PM PST 24 |
| Finished | Feb 07 04:12:08 PM PST 24 |
| Peak memory | 553036 kb |
| Host | smart-5e9fd252-c458-4f9f-947a-5af310ac8a96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927710340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr .2927710340 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_random.4292508552 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 83754016 ps |
| CPU time | 9.52 seconds |
| Started | Feb 07 04:12:00 PM PST 24 |
| Finished | Feb 07 04:12:10 PM PST 24 |
| Peak memory | 555324 kb |
| Host | smart-67818bd0-1880-4f4a-98da-1316157658ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292508552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.4292508552 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random.385326235 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 85175374 ps |
| CPU time | 6.52 seconds |
| Started | Feb 07 04:12:12 PM PST 24 |
| Finished | Feb 07 04:12:19 PM PST 24 |
| Peak memory | 553304 kb |
| Host | smart-390d6f25-dce2-43a5-983b-6f1fe3a68581 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385326235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.385326235 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.2259279321 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 54042289417 ps |
| CPU time | 623.99 seconds |
| Started | Feb 07 04:12:06 PM PST 24 |
| Finished | Feb 07 04:22:30 PM PST 24 |
| Peak memory | 555456 kb |
| Host | smart-03113a9b-558b-4208-a8e2-996494cd9a28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259279321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.2259279321 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.1503708197 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 10628517606 ps |
| CPU time | 179.01 seconds |
| Started | Feb 07 04:12:04 PM PST 24 |
| Finished | Feb 07 04:15:03 PM PST 24 |
| Peak memory | 555428 kb |
| Host | smart-f23c7129-cc39-42cb-8f91-b00ef3c18974 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503708197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1503708197 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.729566407 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 559395907 ps |
| CPU time | 45.38 seconds |
| Started | Feb 07 04:12:09 PM PST 24 |
| Finished | Feb 07 04:12:54 PM PST 24 |
| Peak memory | 555356 kb |
| Host | smart-681805a1-f949-476f-96d5-aa4863622182 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729566407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delay s.729566407 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_same_source.1390887655 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 186290392 ps |
| CPU time | 8.43 seconds |
| Started | Feb 07 04:12:11 PM PST 24 |
| Finished | Feb 07 04:12:20 PM PST 24 |
| Peak memory | 553280 kb |
| Host | smart-8970831a-9ea1-4a94-93cd-7952bac45e3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390887655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.1390887655 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke.35721208 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 192865722 ps |
| CPU time | 8.27 seconds |
| Started | Feb 07 04:12:08 PM PST 24 |
| Finished | Feb 07 04:12:17 PM PST 24 |
| Peak memory | 553024 kb |
| Host | smart-89f1deac-1b7e-4c28-b8d8-b5404a46f066 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35721208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.35721208 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.4216209469 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 8449458983 ps |
| CPU time | 88.18 seconds |
| Started | Feb 07 04:12:10 PM PST 24 |
| Finished | Feb 07 04:13:39 PM PST 24 |
| Peak memory | 553368 kb |
| Host | smart-285c3d1a-da16-4eea-a8a1-814758420c7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216209469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.4216209469 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.3297920056 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 4605872193 ps |
| CPU time | 80.23 seconds |
| Started | Feb 07 04:12:09 PM PST 24 |
| Finished | Feb 07 04:13:29 PM PST 24 |
| Peak memory | 553088 kb |
| Host | smart-28596e03-eb77-4378-964c-e45ef44f20f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297920056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.3297920056 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.851261651 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 46543303 ps |
| CPU time | 6.04 seconds |
| Started | Feb 07 04:12:04 PM PST 24 |
| Finished | Feb 07 04:12:10 PM PST 24 |
| Peak memory | 553304 kb |
| Host | smart-3230b5fb-38f2-464c-af1a-5d29b7af37b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851261651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays. 851261651 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all.1786922159 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 98467264 ps |
| CPU time | 8.21 seconds |
| Started | Feb 07 04:12:03 PM PST 24 |
| Finished | Feb 07 04:12:12 PM PST 24 |
| Peak memory | 553188 kb |
| Host | smart-4adece7c-f01e-44f7-8bcb-5231586d4ae9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786922159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.1786922159 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.2919269959 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 2860381737 ps |
| CPU time | 107.69 seconds |
| Started | Feb 07 04:12:04 PM PST 24 |
| Finished | Feb 07 04:13:52 PM PST 24 |
| Peak memory | 556468 kb |
| Host | smart-6c41f393-ed19-422f-9496-f3b5bc22d185 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919269959 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.2919269959 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.958347637 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 14152437266 ps |
| CPU time | 725.24 seconds |
| Started | Feb 07 04:12:03 PM PST 24 |
| Finished | Feb 07 04:24:09 PM PST 24 |
| Peak memory | 558688 kb |
| Host | smart-7e562fd1-3bc1-44ed-8cbb-11bb971c3730 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958347637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_w ith_rand_reset.958347637 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.2141712244 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 959176641 ps |
| CPU time | 163.02 seconds |
| Started | Feb 07 04:12:04 PM PST 24 |
| Finished | Feb 07 04:14:47 PM PST 24 |
| Peak memory | 559032 kb |
| Host | smart-03f5f2e6-37bc-48b3-a280-efb88f861d7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141712244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all _with_reset_error.2141712244 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.248670632 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 786195792 ps |
| CPU time | 29.05 seconds |
| Started | Feb 07 04:11:55 PM PST 24 |
| Finished | Feb 07 04:12:24 PM PST 24 |
| Peak memory | 555124 kb |
| Host | smart-0a6658f6-55e9-40a7-8f93-a77a1a9310c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248670632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.248670632 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device.95283172 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 563282518 ps |
| CPU time | 41.83 seconds |
| Started | Feb 07 04:23:38 PM PST 24 |
| Finished | Feb 07 04:24:21 PM PST 24 |
| Peak memory | 555616 kb |
| Host | smart-9d687cc4-05c6-4ea3-8832-55a8ee2083f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95283172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device.95283172 |
| Directory | /workspace/90.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.234311540 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 40436428155 ps |
| CPU time | 723.39 seconds |
| Started | Feb 07 04:23:39 PM PST 24 |
| Finished | Feb 07 04:35:44 PM PST 24 |
| Peak memory | 556800 kb |
| Host | smart-8b1c5c2c-b040-4a72-a650-db6595076fca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234311540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_d evice_slow_rsp.234311540 |
| Directory | /workspace/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.164089102 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 949698455 ps |
| CPU time | 36.42 seconds |
| Started | Feb 07 04:23:59 PM PST 24 |
| Finished | Feb 07 04:24:36 PM PST 24 |
| Peak memory | 555388 kb |
| Host | smart-fbe4056c-92c0-4708-9b33-c3b9dfaff88b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164089102 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_addr .164089102 |
| Directory | /workspace/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_random.2612435006 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 167891844 ps |
| CPU time | 16.08 seconds |
| Started | Feb 07 04:23:38 PM PST 24 |
| Finished | Feb 07 04:23:55 PM PST 24 |
| Peak memory | 555304 kb |
| Host | smart-d3131ca5-e5b3-4c45-af9b-8696b7dd51a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612435006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.2612435006 |
| Directory | /workspace/90.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random.963561561 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 72425437 ps |
| CPU time | 9.52 seconds |
| Started | Feb 07 04:23:58 PM PST 24 |
| Finished | Feb 07 04:24:09 PM PST 24 |
| Peak memory | 554628 kb |
| Host | smart-b594b0ec-73e2-4f0a-b2b3-9104ad86246d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963561561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.963561561 |
| Directory | /workspace/90.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.4238611733 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 59892155544 ps |
| CPU time | 702.67 seconds |
| Started | Feb 07 04:24:00 PM PST 24 |
| Finished | Feb 07 04:35:43 PM PST 24 |
| Peak memory | 555728 kb |
| Host | smart-a66fe47a-28e5-440a-bc4b-ca7207c8c583 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238611733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.4238611733 |
| Directory | /workspace/90.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.641821575 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 41272368601 ps |
| CPU time | 716.02 seconds |
| Started | Feb 07 04:23:40 PM PST 24 |
| Finished | Feb 07 04:35:37 PM PST 24 |
| Peak memory | 555204 kb |
| Host | smart-d03c2803-9709-4a04-ac3f-29298b36c8a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641821575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.641821575 |
| Directory | /workspace/90.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.2179720107 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 30612661 ps |
| CPU time | 5.33 seconds |
| Started | Feb 07 04:23:38 PM PST 24 |
| Finished | Feb 07 04:23:44 PM PST 24 |
| Peak memory | 553580 kb |
| Host | smart-c06f5f44-f5bb-445c-9316-36a5e3cd82cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179720107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_del ays.2179720107 |
| Directory | /workspace/90.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_same_source.45467521 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 385402574 ps |
| CPU time | 29.53 seconds |
| Started | Feb 07 04:23:36 PM PST 24 |
| Finished | Feb 07 04:24:06 PM PST 24 |
| Peak memory | 555600 kb |
| Host | smart-b8ec24d9-b1b3-41ef-be6b-96286e547054 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45467521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.45467521 |
| Directory | /workspace/90.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke.1326478794 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 218695499 ps |
| CPU time | 9.25 seconds |
| Started | Feb 07 04:23:39 PM PST 24 |
| Finished | Feb 07 04:23:49 PM PST 24 |
| Peak memory | 553616 kb |
| Host | smart-729e0ce3-4b4f-4943-ab6b-0364b48f178f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326478794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.1326478794 |
| Directory | /workspace/90.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.753632692 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 8066570881 ps |
| CPU time | 87.15 seconds |
| Started | Feb 07 04:23:36 PM PST 24 |
| Finished | Feb 07 04:25:04 PM PST 24 |
| Peak memory | 553640 kb |
| Host | smart-85668ae7-ead5-4e27-8e17-a79cbd680223 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753632692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.753632692 |
| Directory | /workspace/90.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.1711837651 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 4692293477 ps |
| CPU time | 84.3 seconds |
| Started | Feb 07 04:23:41 PM PST 24 |
| Finished | Feb 07 04:25:06 PM PST 24 |
| Peak memory | 553384 kb |
| Host | smart-b41869b0-1c02-434c-95b5-48aa2adb9dc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711837651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.1711837651 |
| Directory | /workspace/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.2555026908 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 47091121 ps |
| CPU time | 5.75 seconds |
| Started | Feb 07 04:23:38 PM PST 24 |
| Finished | Feb 07 04:23:44 PM PST 24 |
| Peak memory | 553612 kb |
| Host | smart-5b4c79b0-a140-4a64-b997-ed11762603d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555026908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delay s.2555026908 |
| Directory | /workspace/90.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all.931063107 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 5641665273 ps |
| CPU time | 221.81 seconds |
| Started | Feb 07 04:23:37 PM PST 24 |
| Finished | Feb 07 04:27:20 PM PST 24 |
| Peak memory | 556616 kb |
| Host | smart-5785e2cc-7fdf-405a-af18-0219b05ce57c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931063107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.931063107 |
| Directory | /workspace/90.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.3671606358 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 387952544 ps |
| CPU time | 33.06 seconds |
| Started | Feb 07 04:23:59 PM PST 24 |
| Finished | Feb 07 04:24:32 PM PST 24 |
| Peak memory | 556700 kb |
| Host | smart-985d6f2d-8caf-4fc8-a0ec-ead24eb240df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671606358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.3671606358 |
| Directory | /workspace/90.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.2878053208 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 360365637 ps |
| CPU time | 123.64 seconds |
| Started | Feb 07 04:23:42 PM PST 24 |
| Finished | Feb 07 04:25:47 PM PST 24 |
| Peak memory | 556620 kb |
| Host | smart-3ad6753d-35f0-4ea0-9bb5-fbae8ceb8e12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878053208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all _with_rand_reset.2878053208 |
| Directory | /workspace/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.428899679 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 880443373 ps |
| CPU time | 203.74 seconds |
| Started | Feb 07 04:23:59 PM PST 24 |
| Finished | Feb 07 04:27:23 PM PST 24 |
| Peak memory | 559360 kb |
| Host | smart-d08a96d8-1bd1-487a-b0ec-dcef30e21e9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428899679 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all _with_reset_error.428899679 |
| Directory | /workspace/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.3072026182 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 74423212 ps |
| CPU time | 10.99 seconds |
| Started | Feb 07 04:23:41 PM PST 24 |
| Finished | Feb 07 04:23:53 PM PST 24 |
| Peak memory | 555340 kb |
| Host | smart-98d2459d-9556-4f57-b213-ce9d04e77a66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072026182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.3072026182 |
| Directory | /workspace/90.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device.3883567110 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 2313424966 ps |
| CPU time | 86.45 seconds |
| Started | Feb 07 04:23:48 PM PST 24 |
| Finished | Feb 07 04:25:15 PM PST 24 |
| Peak memory | 555736 kb |
| Host | smart-ef6b12b9-5961-4df5-812d-5b522a5f22e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883567110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device .3883567110 |
| Directory | /workspace/91.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.227850 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 1400011501 ps |
| CPU time | 58.71 seconds |
| Started | Feb 07 04:23:45 PM PST 24 |
| Finished | Feb 07 04:24:45 PM PST 24 |
| Peak memory | 555388 kb |
| Host | smart-42932ed3-03a5-4d6f-ab31-0aa4c2a205bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_addr.227850 |
| Directory | /workspace/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_random.1064924209 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 430446128 ps |
| CPU time | 32.94 seconds |
| Started | Feb 07 04:23:45 PM PST 24 |
| Finished | Feb 07 04:24:19 PM PST 24 |
| Peak memory | 555640 kb |
| Host | smart-3a9ffbf1-35e5-4ec7-a53b-c5c1e4acb796 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064924209 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.1064924209 |
| Directory | /workspace/91.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random.2503447924 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 2072970818 ps |
| CPU time | 79.18 seconds |
| Started | Feb 07 04:23:43 PM PST 24 |
| Finished | Feb 07 04:25:03 PM PST 24 |
| Peak memory | 555624 kb |
| Host | smart-f0b6c1ab-5ff0-4460-905a-a4f7b24b3bfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503447924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.2503447924 |
| Directory | /workspace/91.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.3947102797 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 22283752716 ps |
| CPU time | 226.67 seconds |
| Started | Feb 07 04:23:51 PM PST 24 |
| Finished | Feb 07 04:27:39 PM PST 24 |
| Peak memory | 555396 kb |
| Host | smart-39ba716d-d457-4e9b-9b06-24916ad6622b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947102797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.3947102797 |
| Directory | /workspace/91.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.1673529987 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 22965851251 ps |
| CPU time | 420.23 seconds |
| Started | Feb 07 04:23:51 PM PST 24 |
| Finished | Feb 07 04:30:52 PM PST 24 |
| Peak memory | 555384 kb |
| Host | smart-1ef9ef4f-54e5-4b68-b9d1-7db9ebe5ebf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673529987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.1673529987 |
| Directory | /workspace/91.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.3219388190 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 415482091 ps |
| CPU time | 31.55 seconds |
| Started | Feb 07 04:23:59 PM PST 24 |
| Finished | Feb 07 04:24:32 PM PST 24 |
| Peak memory | 555472 kb |
| Host | smart-b0ea5e80-0367-4c0c-8b61-9be4793276dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219388190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_del ays.3219388190 |
| Directory | /workspace/91.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_same_source.3869960175 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 553439839 ps |
| CPU time | 17.38 seconds |
| Started | Feb 07 04:23:45 PM PST 24 |
| Finished | Feb 07 04:24:03 PM PST 24 |
| Peak memory | 555376 kb |
| Host | smart-e82a4f53-e140-43df-9f89-5f347ac0d124 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869960175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.3869960175 |
| Directory | /workspace/91.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke.4122320658 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 235405326 ps |
| CPU time | 10.26 seconds |
| Started | Feb 07 04:23:41 PM PST 24 |
| Finished | Feb 07 04:23:52 PM PST 24 |
| Peak memory | 553320 kb |
| Host | smart-4731fafd-13d9-454e-897f-85f8d1773226 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122320658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.4122320658 |
| Directory | /workspace/91.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.634889426 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 8415483089 ps |
| CPU time | 94.03 seconds |
| Started | Feb 07 04:23:59 PM PST 24 |
| Finished | Feb 07 04:25:34 PM PST 24 |
| Peak memory | 553692 kb |
| Host | smart-587b0911-7011-44c8-9d1b-53c2491f0b97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634889426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.634889426 |
| Directory | /workspace/91.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.3805590802 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 4660560543 ps |
| CPU time | 85.84 seconds |
| Started | Feb 07 04:23:40 PM PST 24 |
| Finished | Feb 07 04:25:06 PM PST 24 |
| Peak memory | 553200 kb |
| Host | smart-efd8d9ea-2ad8-4a7c-9a07-54e0e5992ef4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805590802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.3805590802 |
| Directory | /workspace/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.60734543 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 56775116 ps |
| CPU time | 6.96 seconds |
| Started | Feb 07 04:23:59 PM PST 24 |
| Finished | Feb 07 04:24:06 PM PST 24 |
| Peak memory | 553600 kb |
| Host | smart-efdd95b8-ed6c-4160-b721-02d7e7d6f01d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60734543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delays.60734543 |
| Directory | /workspace/91.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all.3370940609 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 14657804702 ps |
| CPU time | 609.73 seconds |
| Started | Feb 07 04:23:46 PM PST 24 |
| Finished | Feb 07 04:33:57 PM PST 24 |
| Peak memory | 559372 kb |
| Host | smart-aa414d64-760d-4005-913d-7bb98c264d2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370940609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.3370940609 |
| Directory | /workspace/91.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.4062862512 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 14071944957 ps |
| CPU time | 539.98 seconds |
| Started | Feb 07 04:23:47 PM PST 24 |
| Finished | Feb 07 04:32:48 PM PST 24 |
| Peak memory | 556624 kb |
| Host | smart-a02c27bb-4349-40c7-8af1-3c51e7fc44ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062862512 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.4062862512 |
| Directory | /workspace/91.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.3749212017 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 877033102 ps |
| CPU time | 191.51 seconds |
| Started | Feb 07 04:23:46 PM PST 24 |
| Finished | Feb 07 04:26:59 PM PST 24 |
| Peak memory | 556680 kb |
| Host | smart-e4be2522-f90d-4e34-819c-ecabed4884ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749212017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all _with_rand_reset.3749212017 |
| Directory | /workspace/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.1785861574 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 2117228445 ps |
| CPU time | 284.3 seconds |
| Started | Feb 07 04:23:45 PM PST 24 |
| Finished | Feb 07 04:28:30 PM PST 24 |
| Peak memory | 558736 kb |
| Host | smart-7aab42a9-8aea-4e1b-863f-b94bc62094db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785861574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_al l_with_reset_error.1785861574 |
| Directory | /workspace/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.408703222 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 594983104 ps |
| CPU time | 27.83 seconds |
| Started | Feb 07 04:23:46 PM PST 24 |
| Finished | Feb 07 04:24:15 PM PST 24 |
| Peak memory | 555444 kb |
| Host | smart-3d943ed0-85a3-48c8-9434-6f08a8d03f41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408703222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.408703222 |
| Directory | /workspace/91.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device.1028188501 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 3024435600 ps |
| CPU time | 114.29 seconds |
| Started | Feb 07 04:23:58 PM PST 24 |
| Finished | Feb 07 04:25:53 PM PST 24 |
| Peak memory | 555304 kb |
| Host | smart-e5c8f1d9-4372-41ba-8b28-6db131f8b402 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028188501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device .1028188501 |
| Directory | /workspace/92.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.1025702254 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 122247603386 ps |
| CPU time | 2416.1 seconds |
| Started | Feb 07 04:23:53 PM PST 24 |
| Finished | Feb 07 05:04:10 PM PST 24 |
| Peak memory | 555800 kb |
| Host | smart-89322b50-7c34-469f-b0bb-c7a93b97fd42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025702254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_ device_slow_rsp.1025702254 |
| Directory | /workspace/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.1812643638 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 851765840 ps |
| CPU time | 32.02 seconds |
| Started | Feb 07 04:24:00 PM PST 24 |
| Finished | Feb 07 04:24:32 PM PST 24 |
| Peak memory | 555608 kb |
| Host | smart-b8758e7b-438b-48fa-91c4-5ec16a42cbb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812643638 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_add r.1812643638 |
| Directory | /workspace/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_random.1603093672 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 2295825772 ps |
| CPU time | 82.63 seconds |
| Started | Feb 07 04:23:55 PM PST 24 |
| Finished | Feb 07 04:25:18 PM PST 24 |
| Peak memory | 555416 kb |
| Host | smart-afd0d857-f3af-4444-a9e5-7bf98b81f81d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603093672 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.1603093672 |
| Directory | /workspace/92.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random.245718781 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 585419245 ps |
| CPU time | 46.13 seconds |
| Started | Feb 07 04:23:45 PM PST 24 |
| Finished | Feb 07 04:24:32 PM PST 24 |
| Peak memory | 555400 kb |
| Host | smart-42587f25-def8-41b2-8518-321a4385cce3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245718781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.245718781 |
| Directory | /workspace/92.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.177902052 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 75570541283 ps |
| CPU time | 978.65 seconds |
| Started | Feb 07 04:23:47 PM PST 24 |
| Finished | Feb 07 04:40:07 PM PST 24 |
| Peak memory | 555672 kb |
| Host | smart-c7020e7b-d388-4baa-bb9c-57f9d93938cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177902052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.177902052 |
| Directory | /workspace/92.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.482130976 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 66019037871 ps |
| CPU time | 1194.8 seconds |
| Started | Feb 07 04:23:58 PM PST 24 |
| Finished | Feb 07 04:43:54 PM PST 24 |
| Peak memory | 555616 kb |
| Host | smart-67f6e1d5-0afa-419d-853e-9b774a0444d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482130976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.482130976 |
| Directory | /workspace/92.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.3804794046 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 589721545 ps |
| CPU time | 42.46 seconds |
| Started | Feb 07 04:23:47 PM PST 24 |
| Finished | Feb 07 04:24:30 PM PST 24 |
| Peak memory | 555644 kb |
| Host | smart-bbd51236-1847-4b9f-9b66-107584b88e9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804794046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_del ays.3804794046 |
| Directory | /workspace/92.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_same_source.2947669064 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 960132151 ps |
| CPU time | 31.28 seconds |
| Started | Feb 07 04:23:57 PM PST 24 |
| Finished | Feb 07 04:24:28 PM PST 24 |
| Peak memory | 555040 kb |
| Host | smart-befc8817-8ca0-450b-9f6a-7217005dcb7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947669064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.2947669064 |
| Directory | /workspace/92.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke.207024020 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 211693265 ps |
| CPU time | 9.08 seconds |
| Started | Feb 07 04:23:47 PM PST 24 |
| Finished | Feb 07 04:23:57 PM PST 24 |
| Peak memory | 553320 kb |
| Host | smart-d2a2cb23-1a78-404b-8df2-761ac5d20ef8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207024020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.207024020 |
| Directory | /workspace/92.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.40513466 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 9335031683 ps |
| CPU time | 103.71 seconds |
| Started | Feb 07 04:23:50 PM PST 24 |
| Finished | Feb 07 04:25:35 PM PST 24 |
| Peak memory | 553624 kb |
| Host | smart-1239d9c3-7baa-4e66-8b0e-a1607e01112c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40513466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.40513466 |
| Directory | /workspace/92.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.365552059 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 5085811151 ps |
| CPU time | 87.9 seconds |
| Started | Feb 07 04:23:45 PM PST 24 |
| Finished | Feb 07 04:25:13 PM PST 24 |
| Peak memory | 559220 kb |
| Host | smart-780d5651-2628-4502-86a6-d493cda06ef7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365552059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.365552059 |
| Directory | /workspace/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.2683255863 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 39759475 ps |
| CPU time | 5.45 seconds |
| Started | Feb 07 04:23:48 PM PST 24 |
| Finished | Feb 07 04:23:54 PM PST 24 |
| Peak memory | 553612 kb |
| Host | smart-dfd4345d-b162-4962-b1e3-6774297d3001 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683255863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delay s.2683255863 |
| Directory | /workspace/92.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all.3262335308 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 11097741908 ps |
| CPU time | 433.37 seconds |
| Started | Feb 07 04:23:55 PM PST 24 |
| Finished | Feb 07 04:31:09 PM PST 24 |
| Peak memory | 556600 kb |
| Host | smart-30de04c3-a6b4-4e09-ab98-b7e30417c38e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262335308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.3262335308 |
| Directory | /workspace/92.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.3384952910 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 2772520439 ps |
| CPU time | 201.82 seconds |
| Started | Feb 07 04:23:59 PM PST 24 |
| Finished | Feb 07 04:27:21 PM PST 24 |
| Peak memory | 556848 kb |
| Host | smart-0ff0b1e6-a727-43e6-aafb-8f8bfb339fe7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384952910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.3384952910 |
| Directory | /workspace/92.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.4150153815 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 5040281113 ps |
| CPU time | 777.04 seconds |
| Started | Feb 07 04:23:59 PM PST 24 |
| Finished | Feb 07 04:36:57 PM PST 24 |
| Peak memory | 567612 kb |
| Host | smart-b160e97d-993d-45d9-b3fc-860af1bf9c6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150153815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all _with_rand_reset.4150153815 |
| Directory | /workspace/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.3990329619 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 1218473439 ps |
| CPU time | 54.39 seconds |
| Started | Feb 07 04:23:59 PM PST 24 |
| Finished | Feb 07 04:24:54 PM PST 24 |
| Peak memory | 555244 kb |
| Host | smart-539699d6-9071-4ee9-9c61-4e09005f33af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990329619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.3990329619 |
| Directory | /workspace/92.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device.3019224842 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 14813767 ps |
| CPU time | 5.85 seconds |
| Started | Feb 07 04:24:05 PM PST 24 |
| Finished | Feb 07 04:24:12 PM PST 24 |
| Peak memory | 553616 kb |
| Host | smart-e5c980e5-fa7c-485e-bd31-baff9dcf24c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019224842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device .3019224842 |
| Directory | /workspace/93.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.2570375261 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 100434796587 ps |
| CPU time | 1907.62 seconds |
| Started | Feb 07 04:24:06 PM PST 24 |
| Finished | Feb 07 04:55:55 PM PST 24 |
| Peak memory | 556812 kb |
| Host | smart-da950126-5e66-4a78-8863-d610ffda6f48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570375261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_ device_slow_rsp.2570375261 |
| Directory | /workspace/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.3432392236 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 550004813 ps |
| CPU time | 23.86 seconds |
| Started | Feb 07 04:24:07 PM PST 24 |
| Finished | Feb 07 04:24:32 PM PST 24 |
| Peak memory | 555312 kb |
| Host | smart-65ea2bb4-9515-4189-81c5-2d6ad8b3503d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432392236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_add r.3432392236 |
| Directory | /workspace/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_random.1703571842 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 306079112 ps |
| CPU time | 13.15 seconds |
| Started | Feb 07 04:24:07 PM PST 24 |
| Finished | Feb 07 04:24:21 PM PST 24 |
| Peak memory | 554628 kb |
| Host | smart-9566d89e-e950-4ffa-a330-390eb5a40e4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703571842 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.1703571842 |
| Directory | /workspace/93.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random.3137600754 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 1161649440 ps |
| CPU time | 39.59 seconds |
| Started | Feb 07 04:23:54 PM PST 24 |
| Finished | Feb 07 04:24:34 PM PST 24 |
| Peak memory | 555636 kb |
| Host | smart-99f3fd28-3f32-481c-b19f-d7a6dbe579c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137600754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.3137600754 |
| Directory | /workspace/93.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.1278600372 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 102194941125 ps |
| CPU time | 1143.79 seconds |
| Started | Feb 07 04:23:58 PM PST 24 |
| Finished | Feb 07 04:43:03 PM PST 24 |
| Peak memory | 555564 kb |
| Host | smart-79f0aceb-7a18-4003-86f4-43e5172da651 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278600372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.1278600372 |
| Directory | /workspace/93.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.101176538 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 14480643244 ps |
| CPU time | 252.61 seconds |
| Started | Feb 07 04:23:59 PM PST 24 |
| Finished | Feb 07 04:28:13 PM PST 24 |
| Peak memory | 555492 kb |
| Host | smart-44e66640-9672-4da8-8aca-cadabd75f819 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101176538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.101176538 |
| Directory | /workspace/93.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.323956844 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 224950263 ps |
| CPU time | 20.69 seconds |
| Started | Feb 07 04:24:00 PM PST 24 |
| Finished | Feb 07 04:24:21 PM PST 24 |
| Peak memory | 555684 kb |
| Host | smart-14c597ac-28e0-4df0-b4a1-9b0988baba4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323956844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_dela ys.323956844 |
| Directory | /workspace/93.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_same_source.873815144 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 414902993 ps |
| CPU time | 27.88 seconds |
| Started | Feb 07 04:24:05 PM PST 24 |
| Finished | Feb 07 04:24:33 PM PST 24 |
| Peak memory | 555392 kb |
| Host | smart-8361700c-19c9-4a2a-a3e9-3018cf2cbe1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873815144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.873815144 |
| Directory | /workspace/93.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke.2601994296 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 57542591 ps |
| CPU time | 6.49 seconds |
| Started | Feb 07 04:23:55 PM PST 24 |
| Finished | Feb 07 04:24:02 PM PST 24 |
| Peak memory | 553568 kb |
| Host | smart-ecd5d984-14a3-496b-aef5-9ec4c3323394 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601994296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.2601994296 |
| Directory | /workspace/93.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.1374603279 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 10686595909 ps |
| CPU time | 109.21 seconds |
| Started | Feb 07 04:23:54 PM PST 24 |
| Finished | Feb 07 04:25:44 PM PST 24 |
| Peak memory | 553688 kb |
| Host | smart-0e4a6705-41af-4ef1-bdc0-31a2030d00fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374603279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.1374603279 |
| Directory | /workspace/93.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.48918143 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 6262499085 ps |
| CPU time | 110.38 seconds |
| Started | Feb 07 04:23:54 PM PST 24 |
| Finished | Feb 07 04:25:45 PM PST 24 |
| Peak memory | 553668 kb |
| Host | smart-f38235d6-645f-42b3-90fb-d411bc71f092 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48918143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.48918143 |
| Directory | /workspace/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.2656354302 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 50332871 ps |
| CPU time | 6.48 seconds |
| Started | Feb 07 04:23:59 PM PST 24 |
| Finished | Feb 07 04:24:06 PM PST 24 |
| Peak memory | 553248 kb |
| Host | smart-522fb5e8-cec0-491b-9226-25919f1da94d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656354302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delay s.2656354302 |
| Directory | /workspace/93.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all.2364846253 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 1485373322 ps |
| CPU time | 56.57 seconds |
| Started | Feb 07 04:24:08 PM PST 24 |
| Finished | Feb 07 04:25:05 PM PST 24 |
| Peak memory | 556148 kb |
| Host | smart-93cab350-531e-4270-b47c-742102442540 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364846253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.2364846253 |
| Directory | /workspace/93.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.2883616526 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 11576839630 ps |
| CPU time | 538.13 seconds |
| Started | Feb 07 04:24:10 PM PST 24 |
| Finished | Feb 07 04:33:09 PM PST 24 |
| Peak memory | 556544 kb |
| Host | smart-1ad651f1-10ad-4d02-9081-1e119b3ddf5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883616526 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.2883616526 |
| Directory | /workspace/93.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.3211487022 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 3867416169 ps |
| CPU time | 259.77 seconds |
| Started | Feb 07 04:24:11 PM PST 24 |
| Finished | Feb 07 04:28:32 PM PST 24 |
| Peak memory | 557512 kb |
| Host | smart-a36e7285-823e-4172-8f65-1b1759fa49df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211487022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all _with_rand_reset.3211487022 |
| Directory | /workspace/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.2573523474 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 5998749943 ps |
| CPU time | 315.01 seconds |
| Started | Feb 07 04:24:07 PM PST 24 |
| Finished | Feb 07 04:29:22 PM PST 24 |
| Peak memory | 559368 kb |
| Host | smart-b03257be-5857-47f7-b809-383367c31e3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573523474 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_al l_with_reset_error.2573523474 |
| Directory | /workspace/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.3133338613 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 312148970 ps |
| CPU time | 16.69 seconds |
| Started | Feb 07 04:24:06 PM PST 24 |
| Finished | Feb 07 04:24:24 PM PST 24 |
| Peak memory | 555708 kb |
| Host | smart-76fd1011-2e4c-4432-b66d-1ad5c6721670 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133338613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.3133338613 |
| Directory | /workspace/93.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device.3204345198 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 2482918513 ps |
| CPU time | 102.07 seconds |
| Started | Feb 07 04:24:17 PM PST 24 |
| Finished | Feb 07 04:25:59 PM PST 24 |
| Peak memory | 555212 kb |
| Host | smart-dfb21f53-00af-444c-b627-d6a73469ca6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204345198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device .3204345198 |
| Directory | /workspace/94.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.1971275868 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 68007274992 ps |
| CPU time | 1173.03 seconds |
| Started | Feb 07 04:24:13 PM PST 24 |
| Finished | Feb 07 04:43:47 PM PST 24 |
| Peak memory | 555784 kb |
| Host | smart-cca18060-a341-4f25-8910-316f4abde0f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971275868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_ device_slow_rsp.1971275868 |
| Directory | /workspace/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.1365747095 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 125331111 ps |
| CPU time | 8.37 seconds |
| Started | Feb 07 04:24:17 PM PST 24 |
| Finished | Feb 07 04:24:26 PM PST 24 |
| Peak memory | 553248 kb |
| Host | smart-46ab2e7c-c5be-404d-85c5-cd6c854ef5e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365747095 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_add r.1365747095 |
| Directory | /workspace/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_random.3950144146 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 2449916297 ps |
| CPU time | 83.35 seconds |
| Started | Feb 07 04:24:17 PM PST 24 |
| Finished | Feb 07 04:25:40 PM PST 24 |
| Peak memory | 555496 kb |
| Host | smart-0b3ac908-0b3a-4440-a918-059d86d60c6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950144146 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.3950144146 |
| Directory | /workspace/94.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random.3899667006 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 724659351 ps |
| CPU time | 29.67 seconds |
| Started | Feb 07 04:24:16 PM PST 24 |
| Finished | Feb 07 04:24:46 PM PST 24 |
| Peak memory | 555340 kb |
| Host | smart-05da6ded-b108-4d6d-8d12-e6868e588b36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899667006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.3899667006 |
| Directory | /workspace/94.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.833199431 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 66453570757 ps |
| CPU time | 784.48 seconds |
| Started | Feb 07 04:24:17 PM PST 24 |
| Finished | Feb 07 04:37:22 PM PST 24 |
| Peak memory | 555744 kb |
| Host | smart-0a64ad91-601f-49eb-b44c-c797133dfd59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833199431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.833199431 |
| Directory | /workspace/94.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.1885520055 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 11177846756 ps |
| CPU time | 204.97 seconds |
| Started | Feb 07 04:24:11 PM PST 24 |
| Finished | Feb 07 04:27:36 PM PST 24 |
| Peak memory | 555440 kb |
| Host | smart-4ba4cd61-4b87-4b00-9c7d-27b8e352ff99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885520055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.1885520055 |
| Directory | /workspace/94.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.3249601626 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 132694529 ps |
| CPU time | 13.65 seconds |
| Started | Feb 07 04:24:14 PM PST 24 |
| Finished | Feb 07 04:24:28 PM PST 24 |
| Peak memory | 555400 kb |
| Host | smart-e66ec836-ed87-4a0f-ad4b-0882ef274c53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249601626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_del ays.3249601626 |
| Directory | /workspace/94.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_same_source.4201795148 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 127584964 ps |
| CPU time | 11.54 seconds |
| Started | Feb 07 04:24:11 PM PST 24 |
| Finished | Feb 07 04:24:23 PM PST 24 |
| Peak memory | 555452 kb |
| Host | smart-9f480751-cdc3-435f-ad2c-10cbf9eb3cea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201795148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.4201795148 |
| Directory | /workspace/94.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke.1000693229 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 177374715 ps |
| CPU time | 7.98 seconds |
| Started | Feb 07 04:24:09 PM PST 24 |
| Finished | Feb 07 04:24:17 PM PST 24 |
| Peak memory | 553312 kb |
| Host | smart-f23d9e21-3d21-4e94-ba9e-08b46b5a0fec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000693229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.1000693229 |
| Directory | /workspace/94.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.2328474447 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 7719831790 ps |
| CPU time | 85.24 seconds |
| Started | Feb 07 04:24:06 PM PST 24 |
| Finished | Feb 07 04:25:32 PM PST 24 |
| Peak memory | 553440 kb |
| Host | smart-a7bfd314-7494-4cbd-9d3f-71856edfecb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328474447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.2328474447 |
| Directory | /workspace/94.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.494046087 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 5575433522 ps |
| CPU time | 93.21 seconds |
| Started | Feb 07 04:24:07 PM PST 24 |
| Finished | Feb 07 04:25:40 PM PST 24 |
| Peak memory | 553700 kb |
| Host | smart-1f95e72b-aeba-4768-93b8-d31d055a0f61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494046087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.494046087 |
| Directory | /workspace/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.868083489 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 51915481 ps |
| CPU time | 6.54 seconds |
| Started | Feb 07 04:24:06 PM PST 24 |
| Finished | Feb 07 04:24:13 PM PST 24 |
| Peak memory | 553268 kb |
| Host | smart-65887c76-939a-4478-b884-92f558d267f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868083489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delays .868083489 |
| Directory | /workspace/94.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all.1243271283 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 9433490901 ps |
| CPU time | 358.68 seconds |
| Started | Feb 07 04:24:17 PM PST 24 |
| Finished | Feb 07 04:30:16 PM PST 24 |
| Peak memory | 556700 kb |
| Host | smart-b2ecd3fa-06c8-46d7-b753-dd7776925a0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243271283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.1243271283 |
| Directory | /workspace/94.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.2288620515 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 1800836980 ps |
| CPU time | 56.71 seconds |
| Started | Feb 07 04:24:13 PM PST 24 |
| Finished | Feb 07 04:25:10 PM PST 24 |
| Peak memory | 555388 kb |
| Host | smart-49d07ef5-f4b2-42ae-9075-d0d8156c1271 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288620515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.2288620515 |
| Directory | /workspace/94.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.3792101750 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 996553785 ps |
| CPU time | 221.13 seconds |
| Started | Feb 07 04:24:12 PM PST 24 |
| Finished | Feb 07 04:27:53 PM PST 24 |
| Peak memory | 557632 kb |
| Host | smart-641f1228-c86e-46ad-b581-79e21f84fa97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792101750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all _with_rand_reset.3792101750 |
| Directory | /workspace/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.2858684974 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 3509313902 ps |
| CPU time | 348.77 seconds |
| Started | Feb 07 04:24:11 PM PST 24 |
| Finished | Feb 07 04:30:01 PM PST 24 |
| Peak memory | 559256 kb |
| Host | smart-8d7ee834-8bfa-4840-a579-b4731ea713b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858684974 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_al l_with_reset_error.2858684974 |
| Directory | /workspace/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.2019601880 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 208195263 ps |
| CPU time | 13.34 seconds |
| Started | Feb 07 04:24:11 PM PST 24 |
| Finished | Feb 07 04:24:25 PM PST 24 |
| Peak memory | 554456 kb |
| Host | smart-fec1dce3-c153-4862-9517-b7cbda48fb6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019601880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.2019601880 |
| Directory | /workspace/94.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device.607589519 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 410001532 ps |
| CPU time | 39.36 seconds |
| Started | Feb 07 04:24:20 PM PST 24 |
| Finished | Feb 07 04:25:00 PM PST 24 |
| Peak memory | 555392 kb |
| Host | smart-877d3632-6a1b-4a71-aa6f-2e250b33d8ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607589519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device. 607589519 |
| Directory | /workspace/95.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.1929026289 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 45305176212 ps |
| CPU time | 806.99 seconds |
| Started | Feb 07 04:24:19 PM PST 24 |
| Finished | Feb 07 04:37:47 PM PST 24 |
| Peak memory | 555680 kb |
| Host | smart-71178c17-2959-404c-b3b9-67b1c52f4ec2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929026289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_ device_slow_rsp.1929026289 |
| Directory | /workspace/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.1998313913 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 259745311 ps |
| CPU time | 27.89 seconds |
| Started | Feb 07 04:24:19 PM PST 24 |
| Finished | Feb 07 04:24:47 PM PST 24 |
| Peak memory | 555656 kb |
| Host | smart-39087793-ee72-44a0-b69f-5b5d9bcb351a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998313913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_add r.1998313913 |
| Directory | /workspace/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_random.691675309 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 200409030 ps |
| CPU time | 17.66 seconds |
| Started | Feb 07 04:24:21 PM PST 24 |
| Finished | Feb 07 04:24:39 PM PST 24 |
| Peak memory | 555340 kb |
| Host | smart-932042de-c8b9-40cb-b930-e5f84753e6da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691675309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.691675309 |
| Directory | /workspace/95.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random.205385746 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 303710668 ps |
| CPU time | 14.73 seconds |
| Started | Feb 07 04:24:21 PM PST 24 |
| Finished | Feb 07 04:24:36 PM PST 24 |
| Peak memory | 555316 kb |
| Host | smart-51cc0192-e27d-41c2-a164-c47a3287090d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205385746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.205385746 |
| Directory | /workspace/95.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.2062432426 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 110654049474 ps |
| CPU time | 1104.53 seconds |
| Started | Feb 07 04:24:20 PM PST 24 |
| Finished | Feb 07 04:42:45 PM PST 24 |
| Peak memory | 555708 kb |
| Host | smart-07a1b3f6-8117-421b-9755-dcf45c8adbed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062432426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.2062432426 |
| Directory | /workspace/95.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.4290838790 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 22446394237 ps |
| CPU time | 402.86 seconds |
| Started | Feb 07 04:24:21 PM PST 24 |
| Finished | Feb 07 04:31:05 PM PST 24 |
| Peak memory | 555728 kb |
| Host | smart-dfaa3de2-ea77-49b6-9165-193fe93a45a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290838790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.4290838790 |
| Directory | /workspace/95.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.3400363238 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 404507071 ps |
| CPU time | 33.9 seconds |
| Started | Feb 07 04:24:18 PM PST 24 |
| Finished | Feb 07 04:24:52 PM PST 24 |
| Peak memory | 555324 kb |
| Host | smart-ac701d43-4554-439c-a5f3-c76d3987e2da |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400363238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_del ays.3400363238 |
| Directory | /workspace/95.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_same_source.1912629339 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 73564241 ps |
| CPU time | 8.13 seconds |
| Started | Feb 07 04:24:22 PM PST 24 |
| Finished | Feb 07 04:24:30 PM PST 24 |
| Peak memory | 555144 kb |
| Host | smart-fd2862d5-2b2e-43ed-8fc1-f9f33398dab7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912629339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.1912629339 |
| Directory | /workspace/95.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke.104981512 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 158374930 ps |
| CPU time | 7.61 seconds |
| Started | Feb 07 04:24:10 PM PST 24 |
| Finished | Feb 07 04:24:18 PM PST 24 |
| Peak memory | 553580 kb |
| Host | smart-c7788c0b-0c75-4bc9-9a2d-2f7c44ccbdc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104981512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.104981512 |
| Directory | /workspace/95.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.1076178745 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 9055383065 ps |
| CPU time | 92.42 seconds |
| Started | Feb 07 04:24:20 PM PST 24 |
| Finished | Feb 07 04:25:53 PM PST 24 |
| Peak memory | 553376 kb |
| Host | smart-6d53a7be-3752-4be2-8ecb-5e70c87375fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076178745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.1076178745 |
| Directory | /workspace/95.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.88947815 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 6621299895 ps |
| CPU time | 111.1 seconds |
| Started | Feb 07 04:24:19 PM PST 24 |
| Finished | Feb 07 04:26:10 PM PST 24 |
| Peak memory | 553556 kb |
| Host | smart-0530085a-0d3a-494a-861e-dc217f3468c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88947815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.88947815 |
| Directory | /workspace/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.1441366507 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 49058820 ps |
| CPU time | 5.94 seconds |
| Started | Feb 07 04:24:18 PM PST 24 |
| Finished | Feb 07 04:24:24 PM PST 24 |
| Peak memory | 553564 kb |
| Host | smart-96803b40-a7e3-4ab4-ad5b-00592a2a25e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441366507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delay s.1441366507 |
| Directory | /workspace/95.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all.1642133725 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 3174431339 ps |
| CPU time | 267.1 seconds |
| Started | Feb 07 04:24:19 PM PST 24 |
| Finished | Feb 07 04:28:47 PM PST 24 |
| Peak memory | 556892 kb |
| Host | smart-8603666f-2f7f-4026-be5e-c3295c11fe16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642133725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.1642133725 |
| Directory | /workspace/95.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.943434612 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 3124196495 ps |
| CPU time | 103.98 seconds |
| Started | Feb 07 04:24:27 PM PST 24 |
| Finished | Feb 07 04:26:12 PM PST 24 |
| Peak memory | 556788 kb |
| Host | smart-d14aa49b-d938-42e4-ac04-ec232efb1f32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943434612 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.943434612 |
| Directory | /workspace/95.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.3375804029 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 196647135 ps |
| CPU time | 100.82 seconds |
| Started | Feb 07 04:24:21 PM PST 24 |
| Finished | Feb 07 04:26:02 PM PST 24 |
| Peak memory | 556584 kb |
| Host | smart-dfd23fef-6f98-480e-ba99-968112f60d4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375804029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all _with_rand_reset.3375804029 |
| Directory | /workspace/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.2816102586 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 485928288 ps |
| CPU time | 109.02 seconds |
| Started | Feb 07 04:24:28 PM PST 24 |
| Finished | Feb 07 04:26:18 PM PST 24 |
| Peak memory | 558428 kb |
| Host | smart-90c6c2f8-dbff-4f52-bc5e-04d58bbd2f73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816102586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_al l_with_reset_error.2816102586 |
| Directory | /workspace/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.1675269368 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 970356495 ps |
| CPU time | 38 seconds |
| Started | Feb 07 04:24:21 PM PST 24 |
| Finished | Feb 07 04:25:00 PM PST 24 |
| Peak memory | 555636 kb |
| Host | smart-080e73d1-9ae6-4a02-a6d2-011891d9ff8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675269368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.1675269368 |
| Directory | /workspace/95.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device.2302354437 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 677185261 ps |
| CPU time | 50.41 seconds |
| Started | Feb 07 04:24:30 PM PST 24 |
| Finished | Feb 07 04:25:21 PM PST 24 |
| Peak memory | 556400 kb |
| Host | smart-d0ce7e90-a67d-422f-a2fb-fbc64255377c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302354437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device .2302354437 |
| Directory | /workspace/96.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.2825283011 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 107292324484 ps |
| CPU time | 1956.31 seconds |
| Started | Feb 07 04:24:27 PM PST 24 |
| Finished | Feb 07 04:57:04 PM PST 24 |
| Peak memory | 555548 kb |
| Host | smart-2ae7dcf2-a878-42a2-aa2c-8295d0a6018e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825283011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_ device_slow_rsp.2825283011 |
| Directory | /workspace/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.1018007238 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 538545023 ps |
| CPU time | 26.32 seconds |
| Started | Feb 07 04:24:43 PM PST 24 |
| Finished | Feb 07 04:25:11 PM PST 24 |
| Peak memory | 555116 kb |
| Host | smart-ae7a16c7-0592-4de8-ab8a-251694177a26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018007238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_add r.1018007238 |
| Directory | /workspace/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_random.2730064347 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 589669274 ps |
| CPU time | 42.07 seconds |
| Started | Feb 07 04:24:44 PM PST 24 |
| Finished | Feb 07 04:25:27 PM PST 24 |
| Peak memory | 555648 kb |
| Host | smart-7bd8ac9a-a5eb-4050-9a56-91deb7509b31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730064347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.2730064347 |
| Directory | /workspace/96.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random.1327317480 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 2609998011 ps |
| CPU time | 94.47 seconds |
| Started | Feb 07 04:24:29 PM PST 24 |
| Finished | Feb 07 04:26:04 PM PST 24 |
| Peak memory | 555468 kb |
| Host | smart-9381b560-2de0-4dcd-ad01-9a7b9ce83e7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327317480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.1327317480 |
| Directory | /workspace/96.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.1106083927 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 104128421755 ps |
| CPU time | 1116.49 seconds |
| Started | Feb 07 04:24:31 PM PST 24 |
| Finished | Feb 07 04:43:08 PM PST 24 |
| Peak memory | 555748 kb |
| Host | smart-6d612c61-3736-4355-8d4f-cf6d106d9408 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106083927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.1106083927 |
| Directory | /workspace/96.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.1832146157 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 63490260214 ps |
| CPU time | 1228.06 seconds |
| Started | Feb 07 04:24:29 PM PST 24 |
| Finished | Feb 07 04:44:57 PM PST 24 |
| Peak memory | 555164 kb |
| Host | smart-cecac313-a8b3-476f-8609-5c875a517758 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832146157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.1832146157 |
| Directory | /workspace/96.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.412538922 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 434739279 ps |
| CPU time | 36.82 seconds |
| Started | Feb 07 04:24:31 PM PST 24 |
| Finished | Feb 07 04:25:08 PM PST 24 |
| Peak memory | 555256 kb |
| Host | smart-b9fb5550-e4bf-4ea0-b917-34fb6258d41f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412538922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_dela ys.412538922 |
| Directory | /workspace/96.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_same_source.2911183350 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 380635833 ps |
| CPU time | 29.32 seconds |
| Started | Feb 07 04:24:27 PM PST 24 |
| Finished | Feb 07 04:24:57 PM PST 24 |
| Peak memory | 555644 kb |
| Host | smart-ed6fbdd8-94d8-415a-815d-7cfedd20190d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911183350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.2911183350 |
| Directory | /workspace/96.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke.3782583865 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 164506980 ps |
| CPU time | 8.25 seconds |
| Started | Feb 07 04:24:28 PM PST 24 |
| Finished | Feb 07 04:24:37 PM PST 24 |
| Peak memory | 553292 kb |
| Host | smart-ceb14c5b-6e53-4eb8-92db-2c125e401c0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782583865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.3782583865 |
| Directory | /workspace/96.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.3869307049 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 7778389400 ps |
| CPU time | 76.37 seconds |
| Started | Feb 07 04:24:28 PM PST 24 |
| Finished | Feb 07 04:25:45 PM PST 24 |
| Peak memory | 553412 kb |
| Host | smart-9c3b77a1-9429-4c66-b938-57eb9c6ea84e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869307049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.3869307049 |
| Directory | /workspace/96.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.783115734 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 5227898835 ps |
| CPU time | 90.48 seconds |
| Started | Feb 07 04:24:30 PM PST 24 |
| Finished | Feb 07 04:26:01 PM PST 24 |
| Peak memory | 553076 kb |
| Host | smart-5a54cedc-b762-45fd-9b47-08da854f902a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783115734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.783115734 |
| Directory | /workspace/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.2275777373 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 39310424 ps |
| CPU time | 5.58 seconds |
| Started | Feb 07 04:24:34 PM PST 24 |
| Finished | Feb 07 04:24:41 PM PST 24 |
| Peak memory | 553532 kb |
| Host | smart-65f8dafb-6671-4c56-a42a-c0bae9728e6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275777373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay s.2275777373 |
| Directory | /workspace/96.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all.3210624612 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 289475937 ps |
| CPU time | 21.51 seconds |
| Started | Feb 07 04:24:43 PM PST 24 |
| Finished | Feb 07 04:25:05 PM PST 24 |
| Peak memory | 555752 kb |
| Host | smart-27f9ce1e-5834-4525-a9ef-ec53595def0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210624612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.3210624612 |
| Directory | /workspace/96.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.2527794042 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 6369070242 ps |
| CPU time | 231.91 seconds |
| Started | Feb 07 04:24:40 PM PST 24 |
| Finished | Feb 07 04:28:33 PM PST 24 |
| Peak memory | 556760 kb |
| Host | smart-a140dde3-3236-4329-9063-eec419bfc3ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527794042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.2527794042 |
| Directory | /workspace/96.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.2987350801 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 293523538 ps |
| CPU time | 77.46 seconds |
| Started | Feb 07 04:24:46 PM PST 24 |
| Finished | Feb 07 04:26:07 PM PST 24 |
| Peak memory | 559272 kb |
| Host | smart-a7075c53-655d-45e8-a451-4605b202b8e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987350801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all _with_rand_reset.2987350801 |
| Directory | /workspace/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.3978305064 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 14258253464 ps |
| CPU time | 667.3 seconds |
| Started | Feb 07 04:24:41 PM PST 24 |
| Finished | Feb 07 04:35:49 PM PST 24 |
| Peak memory | 559352 kb |
| Host | smart-4d395e45-e864-4a15-8f03-5b88240741ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978305064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_al l_with_reset_error.3978305064 |
| Directory | /workspace/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.970335374 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 392108506 ps |
| CPU time | 20.28 seconds |
| Started | Feb 07 04:24:41 PM PST 24 |
| Finished | Feb 07 04:25:02 PM PST 24 |
| Peak memory | 555388 kb |
| Host | smart-3ff9b408-bfc3-4b45-8653-b3cdd21cc48a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970335374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.970335374 |
| Directory | /workspace/96.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device.172685224 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 906825288 ps |
| CPU time | 73.76 seconds |
| Started | Feb 07 04:24:47 PM PST 24 |
| Finished | Feb 07 04:26:04 PM PST 24 |
| Peak memory | 555388 kb |
| Host | smart-a74b1d0b-b107-47d0-b66b-da5c681ef817 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172685224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device. 172685224 |
| Directory | /workspace/97.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.4086168475 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 102178285696 ps |
| CPU time | 2088.66 seconds |
| Started | Feb 07 04:24:48 PM PST 24 |
| Finished | Feb 07 04:59:39 PM PST 24 |
| Peak memory | 556840 kb |
| Host | smart-1faa504a-f1d4-4122-a023-13d9f0471242 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086168475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_ device_slow_rsp.4086168475 |
| Directory | /workspace/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.1382060674 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 1262288424 ps |
| CPU time | 49.89 seconds |
| Started | Feb 07 04:24:50 PM PST 24 |
| Finished | Feb 07 04:25:41 PM PST 24 |
| Peak memory | 555656 kb |
| Host | smart-0e60a812-9249-431d-aa76-d97a615d4dca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382060674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_add r.1382060674 |
| Directory | /workspace/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_random.4282158610 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 154706205 ps |
| CPU time | 8.6 seconds |
| Started | Feb 07 04:24:49 PM PST 24 |
| Finished | Feb 07 04:24:59 PM PST 24 |
| Peak memory | 553268 kb |
| Host | smart-34adc2d3-98bc-4b4a-8a54-12b6e145ff78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282158610 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.4282158610 |
| Directory | /workspace/97.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random.3785877144 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 120621971 ps |
| CPU time | 12.33 seconds |
| Started | Feb 07 04:24:48 PM PST 24 |
| Finished | Feb 07 04:25:03 PM PST 24 |
| Peak memory | 555412 kb |
| Host | smart-a98b50ae-6da3-49eb-96c1-69dbd0c8ceb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785877144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.3785877144 |
| Directory | /workspace/97.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.2226642401 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 14083521281 ps |
| CPU time | 162.35 seconds |
| Started | Feb 07 04:24:47 PM PST 24 |
| Finished | Feb 07 04:27:33 PM PST 24 |
| Peak memory | 555440 kb |
| Host | smart-ab06a140-ade5-41b3-a856-ea915d8b86a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226642401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.2226642401 |
| Directory | /workspace/97.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.2994848930 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 4034346061 ps |
| CPU time | 68.5 seconds |
| Started | Feb 07 04:24:52 PM PST 24 |
| Finished | Feb 07 04:26:02 PM PST 24 |
| Peak memory | 553412 kb |
| Host | smart-19fb9ce2-a4ef-4ee8-9620-97d169ce82ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994848930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.2994848930 |
| Directory | /workspace/97.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.3137896149 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 409648689 ps |
| CPU time | 39.35 seconds |
| Started | Feb 07 04:24:47 PM PST 24 |
| Finished | Feb 07 04:25:30 PM PST 24 |
| Peak memory | 559156 kb |
| Host | smart-c467203b-b30c-4eeb-b383-2822699f236f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137896149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_del ays.3137896149 |
| Directory | /workspace/97.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_same_source.2652740181 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 713107643 ps |
| CPU time | 24.08 seconds |
| Started | Feb 07 04:24:56 PM PST 24 |
| Finished | Feb 07 04:25:21 PM PST 24 |
| Peak memory | 555072 kb |
| Host | smart-4c9a1893-9e6d-492d-8a57-cb10be0e5434 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652740181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.2652740181 |
| Directory | /workspace/97.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke.906469014 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 51086366 ps |
| CPU time | 6.01 seconds |
| Started | Feb 07 04:24:46 PM PST 24 |
| Finished | Feb 07 04:24:56 PM PST 24 |
| Peak memory | 553576 kb |
| Host | smart-7ef96734-c5d5-4eda-bc90-cc80a0a7c54c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906469014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.906469014 |
| Directory | /workspace/97.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.2619790259 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 8170718246 ps |
| CPU time | 87.68 seconds |
| Started | Feb 07 04:24:42 PM PST 24 |
| Finished | Feb 07 04:26:10 PM PST 24 |
| Peak memory | 553636 kb |
| Host | smart-dff051b0-7b92-40b2-956b-287705a6acb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619790259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.2619790259 |
| Directory | /workspace/97.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.848473957 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 5945801137 ps |
| CPU time | 108.2 seconds |
| Started | Feb 07 04:24:49 PM PST 24 |
| Finished | Feb 07 04:26:39 PM PST 24 |
| Peak memory | 553232 kb |
| Host | smart-dd5ddfa1-df1e-4953-a2e2-3f39a1dfee4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848473957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.848473957 |
| Directory | /workspace/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.1187428001 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 50832500 ps |
| CPU time | 6.31 seconds |
| Started | Feb 07 04:24:41 PM PST 24 |
| Finished | Feb 07 04:24:48 PM PST 24 |
| Peak memory | 553584 kb |
| Host | smart-9f37f1b6-f827-4428-98c4-4bfd48db1b0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187428001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delay s.1187428001 |
| Directory | /workspace/97.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all.526670645 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 1748183003 ps |
| CPU time | 135.89 seconds |
| Started | Feb 07 04:24:49 PM PST 24 |
| Finished | Feb 07 04:27:06 PM PST 24 |
| Peak memory | 555548 kb |
| Host | smart-6ba50e7f-e561-4992-98f5-5aee20a2f15e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526670645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.526670645 |
| Directory | /workspace/97.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.3655173542 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 9374610075 ps |
| CPU time | 370.92 seconds |
| Started | Feb 07 04:24:53 PM PST 24 |
| Finished | Feb 07 04:31:05 PM PST 24 |
| Peak memory | 556584 kb |
| Host | smart-3e28eeb9-6d3c-4736-aa08-92a4d01a028a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655173542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.3655173542 |
| Directory | /workspace/97.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.26468839 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 286169115 ps |
| CPU time | 108.3 seconds |
| Started | Feb 07 04:24:52 PM PST 24 |
| Finished | Feb 07 04:26:42 PM PST 24 |
| Peak memory | 556636 kb |
| Host | smart-16303098-c120-43fa-8109-d5b92410bab6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26468839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_w ith_rand_reset.26468839 |
| Directory | /workspace/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.1722371072 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 278690850 ps |
| CPU time | 81.86 seconds |
| Started | Feb 07 04:24:51 PM PST 24 |
| Finished | Feb 07 04:26:15 PM PST 24 |
| Peak memory | 556728 kb |
| Host | smart-45c432ee-bf1f-4109-b8d6-30da5e14844b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722371072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_al l_with_reset_error.1722371072 |
| Directory | /workspace/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.2337771096 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 849983899 ps |
| CPU time | 37.76 seconds |
| Started | Feb 07 04:24:56 PM PST 24 |
| Finished | Feb 07 04:25:34 PM PST 24 |
| Peak memory | 555348 kb |
| Host | smart-40a8a34b-b5e7-4c4a-9040-52f8a3abb74a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337771096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.2337771096 |
| Directory | /workspace/97.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device.3420771747 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 2085007110 ps |
| CPU time | 88.91 seconds |
| Started | Feb 07 04:24:55 PM PST 24 |
| Finished | Feb 07 04:26:24 PM PST 24 |
| Peak memory | 555072 kb |
| Host | smart-6ad7f7bc-9283-4887-b265-bb7c896d795f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420771747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device .3420771747 |
| Directory | /workspace/98.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.46164162 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 124269454049 ps |
| CPU time | 2409.58 seconds |
| Started | Feb 07 04:24:56 PM PST 24 |
| Finished | Feb 07 05:05:07 PM PST 24 |
| Peak memory | 556876 kb |
| Host | smart-e6701bf8-feb4-4ab4-bf0e-0340ac88f68f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46164162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_de vice_slow_rsp.46164162 |
| Directory | /workspace/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.384134482 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 241151571 ps |
| CPU time | 29.24 seconds |
| Started | Feb 07 04:25:03 PM PST 24 |
| Finished | Feb 07 04:25:34 PM PST 24 |
| Peak memory | 555080 kb |
| Host | smart-13eeac63-bde2-47d7-87dd-e573c3579253 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384134482 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_addr .384134482 |
| Directory | /workspace/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_random.491048623 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 1250294525 ps |
| CPU time | 44.41 seconds |
| Started | Feb 07 04:24:58 PM PST 24 |
| Finished | Feb 07 04:25:44 PM PST 24 |
| Peak memory | 555332 kb |
| Host | smart-cdd2d0e1-21d7-4dcf-9324-6414c76edcae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491048623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.491048623 |
| Directory | /workspace/98.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random.2311650586 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 423562282 ps |
| CPU time | 43.09 seconds |
| Started | Feb 07 04:24:56 PM PST 24 |
| Finished | Feb 07 04:25:39 PM PST 24 |
| Peak memory | 555396 kb |
| Host | smart-71a8c9eb-d915-428d-829c-8aecf042aae6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311650586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.2311650586 |
| Directory | /workspace/98.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.43598834 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 14133119707 ps |
| CPU time | 166.98 seconds |
| Started | Feb 07 04:25:03 PM PST 24 |
| Finished | Feb 07 04:27:52 PM PST 24 |
| Peak memory | 553480 kb |
| Host | smart-ef1f5781-34eb-4239-9397-5665ce82fcc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43598834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.43598834 |
| Directory | /workspace/98.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.4033377441 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 29418522508 ps |
| CPU time | 563.81 seconds |
| Started | Feb 07 04:24:57 PM PST 24 |
| Finished | Feb 07 04:34:22 PM PST 24 |
| Peak memory | 555700 kb |
| Host | smart-d0628565-a80b-4ee8-8431-9f5712e12e7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033377441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.4033377441 |
| Directory | /workspace/98.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.3693781577 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 166908598 ps |
| CPU time | 17.16 seconds |
| Started | Feb 07 04:24:55 PM PST 24 |
| Finished | Feb 07 04:25:13 PM PST 24 |
| Peak memory | 555364 kb |
| Host | smart-b3af1da4-a63d-4483-b11e-fb01286e4fbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693781577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_del ays.3693781577 |
| Directory | /workspace/98.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_same_source.3757491562 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 1527193942 ps |
| CPU time | 47.3 seconds |
| Started | Feb 07 04:25:07 PM PST 24 |
| Finished | Feb 07 04:26:00 PM PST 24 |
| Peak memory | 555140 kb |
| Host | smart-fe7fbab4-3ca2-4274-a180-f136e4aa5528 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757491562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.3757491562 |
| Directory | /workspace/98.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke.152112615 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 49260465 ps |
| CPU time | 5.62 seconds |
| Started | Feb 07 04:24:52 PM PST 24 |
| Finished | Feb 07 04:24:59 PM PST 24 |
| Peak memory | 553112 kb |
| Host | smart-74534810-d255-4698-92d1-c11309e78ff7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152112615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.152112615 |
| Directory | /workspace/98.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.1617704970 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 6534693677 ps |
| CPU time | 68.38 seconds |
| Started | Feb 07 04:24:48 PM PST 24 |
| Finished | Feb 07 04:25:59 PM PST 24 |
| Peak memory | 553076 kb |
| Host | smart-8d890d97-d34d-48c5-a645-23c7d519fc87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617704970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.1617704970 |
| Directory | /workspace/98.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.2741335752 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 3925247368 ps |
| CPU time | 62.57 seconds |
| Started | Feb 07 04:24:52 PM PST 24 |
| Finished | Feb 07 04:25:56 PM PST 24 |
| Peak memory | 553500 kb |
| Host | smart-e8deb8d6-ad17-4f2a-b7cd-dc4926c21547 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741335752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.2741335752 |
| Directory | /workspace/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.1540081147 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 45113953 ps |
| CPU time | 5.91 seconds |
| Started | Feb 07 04:24:55 PM PST 24 |
| Finished | Feb 07 04:25:02 PM PST 24 |
| Peak memory | 553552 kb |
| Host | smart-36cb8472-c81e-4751-92b4-4cb328222201 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540081147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delay s.1540081147 |
| Directory | /workspace/98.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all.3994099826 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 3583090938 ps |
| CPU time | 133.56 seconds |
| Started | Feb 07 04:24:59 PM PST 24 |
| Finished | Feb 07 04:27:17 PM PST 24 |
| Peak memory | 556812 kb |
| Host | smart-d8a06e1b-dced-49ed-b838-fdc6cc3a0d3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994099826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.3994099826 |
| Directory | /workspace/98.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.2862326839 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 1198526347 ps |
| CPU time | 101.12 seconds |
| Started | Feb 07 04:25:02 PM PST 24 |
| Finished | Feb 07 04:26:46 PM PST 24 |
| Peak memory | 556484 kb |
| Host | smart-27cfaf5e-72d3-4422-96bd-92a379b22c63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862326839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.2862326839 |
| Directory | /workspace/98.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.1275582176 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 4962695110 ps |
| CPU time | 620.28 seconds |
| Started | Feb 07 04:25:07 PM PST 24 |
| Finished | Feb 07 04:35:33 PM PST 24 |
| Peak memory | 559448 kb |
| Host | smart-2cc8f6bc-e854-4cbf-a873-de73e7d6c7ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275582176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_rand_reset.1275582176 |
| Directory | /workspace/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.3282143649 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 1670239280 ps |
| CPU time | 145.37 seconds |
| Started | Feb 07 04:25:03 PM PST 24 |
| Finished | Feb 07 04:27:30 PM PST 24 |
| Peak memory | 559332 kb |
| Host | smart-e2300706-3703-4ffc-b80f-f3cbd1e7649e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282143649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_al l_with_reset_error.3282143649 |
| Directory | /workspace/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.1731423310 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 66488444 ps |
| CPU time | 10.91 seconds |
| Started | Feb 07 04:25:07 PM PST 24 |
| Finished | Feb 07 04:25:24 PM PST 24 |
| Peak memory | 555476 kb |
| Host | smart-f1f58337-7eb7-40fe-8504-e7a56e1916bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731423310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.1731423310 |
| Directory | /workspace/98.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device.1571546129 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 881962537 ps |
| CPU time | 38.76 seconds |
| Started | Feb 07 04:24:59 PM PST 24 |
| Finished | Feb 07 04:25:42 PM PST 24 |
| Peak memory | 555472 kb |
| Host | smart-657dc3a7-3acd-4dad-b06d-44eb35d831d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571546129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device .1571546129 |
| Directory | /workspace/99.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.1532424816 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 329615465 ps |
| CPU time | 39.28 seconds |
| Started | Feb 07 04:25:03 PM PST 24 |
| Finished | Feb 07 04:25:44 PM PST 24 |
| Peak memory | 555112 kb |
| Host | smart-a913204e-3df3-4378-bb1f-eb94e973746d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532424816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_add r.1532424816 |
| Directory | /workspace/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_random.2747174979 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 464050467 ps |
| CPU time | 17.61 seconds |
| Started | Feb 07 04:25:05 PM PST 24 |
| Finished | Feb 07 04:25:29 PM PST 24 |
| Peak memory | 555628 kb |
| Host | smart-c9fd785f-8081-4b87-b94a-a2b21122ad17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747174979 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.2747174979 |
| Directory | /workspace/99.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random.2577979123 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 72113284 ps |
| CPU time | 8.97 seconds |
| Started | Feb 07 04:24:59 PM PST 24 |
| Finished | Feb 07 04:25:13 PM PST 24 |
| Peak memory | 554560 kb |
| Host | smart-9ffae4e9-089d-4e49-a9e2-87c3d951359d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577979123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.2577979123 |
| Directory | /workspace/99.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.4043128401 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 87939932123 ps |
| CPU time | 1000.76 seconds |
| Started | Feb 07 04:24:55 PM PST 24 |
| Finished | Feb 07 04:41:36 PM PST 24 |
| Peak memory | 555700 kb |
| Host | smart-3cc20bcd-5e7e-4f4e-a410-a19b8bc07066 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043128401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.4043128401 |
| Directory | /workspace/99.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.2782912044 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 35021406904 ps |
| CPU time | 665.06 seconds |
| Started | Feb 07 04:24:58 PM PST 24 |
| Finished | Feb 07 04:36:05 PM PST 24 |
| Peak memory | 555432 kb |
| Host | smart-3f901383-0ec2-4ede-b1ca-b8cedc7cb606 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782912044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.2782912044 |
| Directory | /workspace/99.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.279730215 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 582216286 ps |
| CPU time | 48.3 seconds |
| Started | Feb 07 04:24:56 PM PST 24 |
| Finished | Feb 07 04:25:45 PM PST 24 |
| Peak memory | 555640 kb |
| Host | smart-de263d1f-4979-45c5-abd2-64317f87a68c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279730215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_dela ys.279730215 |
| Directory | /workspace/99.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_same_source.4162545366 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 572746127 ps |
| CPU time | 44.39 seconds |
| Started | Feb 07 04:25:06 PM PST 24 |
| Finished | Feb 07 04:25:56 PM PST 24 |
| Peak memory | 555356 kb |
| Host | smart-edea9944-bbbd-4a25-937f-05c267f5d3ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162545366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.4162545366 |
| Directory | /workspace/99.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke.1117397158 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 250401796 ps |
| CPU time | 10.5 seconds |
| Started | Feb 07 04:24:59 PM PST 24 |
| Finished | Feb 07 04:25:13 PM PST 24 |
| Peak memory | 559180 kb |
| Host | smart-988db355-496b-48ec-89c0-36e2178aff56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117397158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.1117397158 |
| Directory | /workspace/99.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.1187200900 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 8805338966 ps |
| CPU time | 98.18 seconds |
| Started | Feb 07 04:24:56 PM PST 24 |
| Finished | Feb 07 04:26:35 PM PST 24 |
| Peak memory | 559236 kb |
| Host | smart-c8d5da60-6001-4c0b-b53d-aa644bca379f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187200900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.1187200900 |
| Directory | /workspace/99.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.3022068570 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 5878909935 ps |
| CPU time | 113.52 seconds |
| Started | Feb 07 04:25:06 PM PST 24 |
| Finished | Feb 07 04:27:06 PM PST 24 |
| Peak memory | 553116 kb |
| Host | smart-d49d7d4a-1916-4bbe-bb4a-437ce145c7e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022068570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.3022068570 |
| Directory | /workspace/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.242361441 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 44570551 ps |
| CPU time | 6.52 seconds |
| Started | Feb 07 04:24:56 PM PST 24 |
| Finished | Feb 07 04:25:03 PM PST 24 |
| Peak memory | 552988 kb |
| Host | smart-1291237a-901f-45ad-bb6d-a91d91b57e52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242361441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delays .242361441 |
| Directory | /workspace/99.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all.4212329285 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 11639675980 ps |
| CPU time | 440.06 seconds |
| Started | Feb 07 04:25:03 PM PST 24 |
| Finished | Feb 07 04:32:25 PM PST 24 |
| Peak memory | 557712 kb |
| Host | smart-616f037c-d1c8-4759-a3b2-45ad436a9e90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212329285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.4212329285 |
| Directory | /workspace/99.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.1505064701 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 2769013143 ps |
| CPU time | 209.34 seconds |
| Started | Feb 07 04:25:08 PM PST 24 |
| Finished | Feb 07 04:28:42 PM PST 24 |
| Peak memory | 556564 kb |
| Host | smart-f480eaf8-580a-4bd7-b701-fca12e3cc18d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505064701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.1505064701 |
| Directory | /workspace/99.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.981300541 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 1910000405 ps |
| CPU time | 347.16 seconds |
| Started | Feb 07 04:25:06 PM PST 24 |
| Finished | Feb 07 04:30:59 PM PST 24 |
| Peak memory | 557996 kb |
| Host | smart-d96bd4f2-25bb-406b-94ed-019cbb4ea67b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981300541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_ with_rand_reset.981300541 |
| Directory | /workspace/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.3858333382 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 7320905039 ps |
| CPU time | 502.47 seconds |
| Started | Feb 07 04:25:06 PM PST 24 |
| Finished | Feb 07 04:33:35 PM PST 24 |
| Peak memory | 567612 kb |
| Host | smart-d88e9595-11c6-4318-b0ac-e386472c5e8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858333382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_al l_with_reset_error.3858333382 |
| Directory | /workspace/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.2869391568 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 41422804 ps |
| CPU time | 7.12 seconds |
| Started | Feb 07 04:25:05 PM PST 24 |
| Finished | Feb 07 04:25:19 PM PST 24 |
| Peak memory | 553620 kb |
| Host | smart-c5f63a58-b0f9-4f0a-a6c4-ca6b6be15234 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869391568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.2869391568 |
| Directory | /workspace/99.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_mem_access.2935785492 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 12705364790 ps |
| CPU time | 1528.59 seconds |
| Started | Feb 07 04:27:08 PM PST 24 |
| Finished | Feb 07 04:52:37 PM PST 24 |
| Peak memory | 593020 kb |
| Host | smart-93ae084a-0fa5-4045-89ed-11644976653e |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935785492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.2 935785492 |
| Directory | /workspace/0.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.396775089 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 4120692688 ps |
| CPU time | 464.2 seconds |
| Started | Feb 07 04:35:52 PM PST 24 |
| Finished | Feb 07 04:43:37 PM PST 24 |
| Peak memory | 617540 kb |
| Host | smart-b6a80e6f-ba27-4a48-893c-a30e008d72f0 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3 96775089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.396775089 |
| Directory | /workspace/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sival_flash_info_access.3641895719 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 3869774305 ps |
| CPU time | 477.95 seconds |
| Started | Feb 07 04:32:56 PM PST 24 |
| Finished | Feb 07 04:40:55 PM PST 24 |
| Peak memory | 600408 kb |
| Host | smart-abf41cff-4948-4c7b-86a3-d93231eedfb6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3641895719 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.3641895719 |
| Directory | /workspace/0.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc.1089615831 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 3037361000 ps |
| CPU time | 265.61 seconds |
| Started | Feb 07 04:34:03 PM PST 24 |
| Finished | Feb 07 04:38:29 PM PST 24 |
| Peak memory | 600496 kb |
| Host | smart-8fe8d9b2-7928-40ea-9c85-eab35a1390da |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089615831 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.1089615831 |
| Directory | /workspace/0.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.260719302 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 2638435899 ps |
| CPU time | 259.78 seconds |
| Started | Feb 07 04:33:48 PM PST 24 |
| Finished | Feb 07 04:38:09 PM PST 24 |
| Peak memory | 600456 kb |
| Host | smart-ec34e5fd-a4d4-4d05-a6b6-f2fa5670837d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607 19302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.260719302 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.4293358563 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 3112600638 ps |
| CPU time | 283.17 seconds |
| Started | Feb 07 04:35:50 PM PST 24 |
| Finished | Feb 07 04:40:34 PM PST 24 |
| Peak memory | 600532 kb |
| Host | smart-52bba635-050a-4ba0-ab26-f3562ccc2e65 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293358563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.4293358563 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_entropy.1283499021 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 2668190520 ps |
| CPU time | 200.12 seconds |
| Started | Feb 07 04:36:15 PM PST 24 |
| Finished | Feb 07 04:39:35 PM PST 24 |
| Peak memory | 600504 kb |
| Host | smart-9e8f28d2-df22-403d-8578-a63d6afe7eed |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283499021 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.1283499021 |
| Directory | /workspace/0.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_idle.3985507767 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 2102549672 ps |
| CPU time | 278.47 seconds |
| Started | Feb 07 04:33:43 PM PST 24 |
| Finished | Feb 07 04:38:22 PM PST 24 |
| Peak memory | 600384 kb |
| Host | smart-061c793f-4e2a-4f34-a9b8-0000c9c70709 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985507767 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.3985507767 |
| Directory | /workspace/0.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_masking_off.763801715 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 2941232579 ps |
| CPU time | 393.83 seconds |
| Started | Feb 07 04:32:59 PM PST 24 |
| Finished | Feb 07 04:39:33 PM PST 24 |
| Peak memory | 599664 kb |
| Host | smart-1fc1151b-57b2-4d51-b1d4-3585e2b83847 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763801715 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.763801715 |
| Directory | /workspace/0.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_smoketest.1884757961 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 2828183842 ps |
| CPU time | 244.76 seconds |
| Started | Feb 07 04:39:50 PM PST 24 |
| Finished | Feb 07 04:43:56 PM PST 24 |
| Peak memory | 600500 kb |
| Host | smart-b3b77a1a-2438-4192-93a9-26d5d68d0c2f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884757961 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.1884757961 |
| Directory | /workspace/0.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_entropy.3920142936 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 3368579306 ps |
| CPU time | 285.18 seconds |
| Started | Feb 07 04:33:27 PM PST 24 |
| Finished | Feb 07 04:38:13 PM PST 24 |
| Peak memory | 601336 kb |
| Host | smart-9cbba4c6-6c3b-4f0a-8639-877126ddfa78 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3920142936 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.3920142936 |
| Directory | /workspace/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_escalation.3718600233 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 4792553096 ps |
| CPU time | 478.93 seconds |
| Started | Feb 07 04:33:55 PM PST 24 |
| Finished | Feb 07 04:41:55 PM PST 24 |
| Peak memory | 605564 kb |
| Host | smart-0bde28d1-899b-4d6f-9266-8ec1cfe2f250 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3718600233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.3718600233 |
| Directory | /workspace/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2336177089 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 7762697094 ps |
| CPU time | 1866.34 seconds |
| Started | Feb 07 04:33:35 PM PST 24 |
| Finished | Feb 07 05:04:46 PM PST 24 |
| Peak memory | 601968 kb |
| Host | smart-5a78480b-5e48-4513-8d56-c4e990fa618f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2336177089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.2336177089 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.599311485 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 8631377320 ps |
| CPU time | 2215.59 seconds |
| Started | Feb 07 04:36:30 PM PST 24 |
| Finished | Feb 07 05:13:26 PM PST 24 |
| Peak memory | 599520 kb |
| Host | smart-95560269-98b5-4c4f-b09a-8eda0a96e013 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599311485 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_toggle.599311485 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.841093005 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 9130447852 ps |
| CPU time | 1281.22 seconds |
| Started | Feb 07 04:35:37 PM PST 24 |
| Finished | Feb 07 04:57:00 PM PST 24 |
| Peak memory | 602472 kb |
| Host | smart-5c740429-f425-4fef-aec1-6d895caf0aac |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841093005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_hand ler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.841093005 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.2101453643 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 4152053768 ps |
| CPU time | 410.91 seconds |
| Started | Feb 07 04:33:35 PM PST 24 |
| Finished | Feb 07 04:40:30 PM PST 24 |
| Peak memory | 601608 kb |
| Host | smart-c5468060-1767-4fc5-a7c2-f1531126c205 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2101453643 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.2101453643 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1997477001 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 254679674688 ps |
| CPU time | 11695.4 seconds |
| Started | Feb 07 04:33:41 PM PST 24 |
| Finished | Feb 07 07:48:39 PM PST 24 |
| Peak memory | 600200 kb |
| Host | smart-2e1f6703-23fa-412e-824c-4e98e05d453e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1997477001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1997477001 |
| Directory | /workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_irq.3135909942 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 4156337724 ps |
| CPU time | 541.34 seconds |
| Started | Feb 07 04:33:55 PM PST 24 |
| Finished | Feb 07 04:42:57 PM PST 24 |
| Peak memory | 599180 kb |
| Host | smart-ca73b6e2-d047-4b93-b078-f893c0843fd1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135909942 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.3135909942 |
| Directory | /workspace/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1778754737 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 6599077046 ps |
| CPU time | 302.44 seconds |
| Started | Feb 07 04:32:46 PM PST 24 |
| Finished | Feb 07 04:37:49 PM PST 24 |
| Peak memory | 601256 kb |
| Host | smart-968ca95d-69ef-47c7-b2cd-88a2d38e4b09 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1778754737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1778754737 |
| Directory | /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3478756113 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 3219471994 ps |
| CPU time | 417.04 seconds |
| Started | Feb 07 04:36:48 PM PST 24 |
| Finished | Feb 07 04:43:46 PM PST 24 |
| Peak memory | 600448 kb |
| Host | smart-3b322568-8bd8-4088-bd96-f8aacbf47d90 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478756113 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_aon_timer_smoketest.3478756113 |
| Directory | /workspace/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1427195800 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 8204352466 ps |
| CPU time | 874.8 seconds |
| Started | Feb 07 04:32:35 PM PST 24 |
| Finished | Feb 07 04:47:10 PM PST 24 |
| Peak memory | 601340 kb |
| Host | smart-0f88116e-8de0-44bf-970b-8c7c4d9ca576 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1427195800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.1427195800 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.208026449 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 6332884640 ps |
| CPU time | 914.73 seconds |
| Started | Feb 07 04:34:13 PM PST 24 |
| Finished | Feb 07 04:49:29 PM PST 24 |
| Peak memory | 601444 kb |
| Host | smart-fab3d1ec-4b28-4520-a3d6-bd1d1cf8ac4f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =208026449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.208026449 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_outputs.2082359347 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 7276935418 ps |
| CPU time | 1118.94 seconds |
| Started | Feb 07 04:34:46 PM PST 24 |
| Finished | Feb 07 04:53:26 PM PST 24 |
| Peak memory | 606540 kb |
| Host | smart-bc3fb0d3-5bc0-4d26-ad0e-f62c5b10ab29 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082359347 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.2082359347 |
| Directory | /workspace/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.716315708 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 7047000712 ps |
| CPU time | 551.18 seconds |
| Started | Feb 07 04:34:20 PM PST 24 |
| Finished | Feb 07 04:43:32 PM PST 24 |
| Peak memory | 603108 kb |
| Host | smart-22b6e78e-5b7b-4a58-8ed1-a339c56ed6eb |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=716315708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.716315708 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3299599995 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 4593555996 ps |
| CPU time | 700.74 seconds |
| Started | Feb 07 04:36:15 PM PST 24 |
| Finished | Feb 07 04:47:56 PM PST 24 |
| Peak memory | 594808 kb |
| Host | smart-07d957c4-daaa-4bea-86fe-f77d8c1ccedc |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299599995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.3299599995 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2551710868 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 4410457952 ps |
| CPU time | 626.7 seconds |
| Started | Feb 07 04:34:31 PM PST 24 |
| Finished | Feb 07 04:44:58 PM PST 24 |
| Peak memory | 594808 kb |
| Host | smart-86a56b20-5a28-4160-bd08-1d24851e36f3 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551710868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.2551710868 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.647418861 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 4191405680 ps |
| CPU time | 740.42 seconds |
| Started | Feb 07 04:34:30 PM PST 24 |
| Finished | Feb 07 04:46:51 PM PST 24 |
| Peak memory | 594884 kb |
| Host | smart-4ddc85fa-d890-41b9-a037-65dd41ef6feb |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647418861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.647418861 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1545205624 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 4772596440 ps |
| CPU time | 756.72 seconds |
| Started | Feb 07 04:34:30 PM PST 24 |
| Finished | Feb 07 04:47:08 PM PST 24 |
| Peak memory | 594620 kb |
| Host | smart-39f3e486-271f-47d7-adf3-5fa382eeee95 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545205624 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.1545205624 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3153511912 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 4936639360 ps |
| CPU time | 548.19 seconds |
| Started | Feb 07 04:35:44 PM PST 24 |
| Finished | Feb 07 04:44:53 PM PST 24 |
| Peak memory | 594892 kb |
| Host | smart-2c7bee30-7dde-4f91-8e04-6bca8b0c5b08 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153511912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3153511912 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter.2980731011 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 2980112119 ps |
| CPU time | 187.02 seconds |
| Started | Feb 07 04:36:48 PM PST 24 |
| Finished | Feb 07 04:39:55 PM PST 24 |
| Peak memory | 599116 kb |
| Host | smart-f7ab9e08-168b-4145-915e-3ea1d2711a42 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980731011 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_clkmgr_jitter.2980731011 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2744745034 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 3265816006 ps |
| CPU time | 388.55 seconds |
| Started | Feb 07 04:34:11 PM PST 24 |
| Finished | Feb 07 04:40:40 PM PST 24 |
| Peak memory | 600556 kb |
| Host | smart-ba730007-29fd-407a-8467-cdbff7b001b7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744745034 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.2744745034 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.2357872720 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 3162355064 ps |
| CPU time | 228.56 seconds |
| Started | Feb 07 04:36:05 PM PST 24 |
| Finished | Feb 07 04:39:54 PM PST 24 |
| Peak memory | 600524 kb |
| Host | smart-da2fc19f-a0b4-4540-a4a2-0060d6307e14 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357872720 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.2357872720 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.4034886680 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 3679507476 ps |
| CPU time | 536.28 seconds |
| Started | Feb 07 04:33:41 PM PST 24 |
| Finished | Feb 07 04:42:39 PM PST 24 |
| Peak memory | 600960 kb |
| Host | smart-840b5363-18f7-4c89-afab-ce65c118c156 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034886680 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.4034886680 |
| Directory | /workspace/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1724114048 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 5758521132 ps |
| CPU time | 531.92 seconds |
| Started | Feb 07 04:35:16 PM PST 24 |
| Finished | Feb 07 04:44:13 PM PST 24 |
| Peak memory | 601080 kb |
| Host | smart-0830a2fd-9957-445d-a630-648d0d8a2466 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724114048 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.1724114048 |
| Directory | /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2352076389 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 4640111140 ps |
| CPU time | 469.27 seconds |
| Started | Feb 07 04:35:08 PM PST 24 |
| Finished | Feb 07 04:43:01 PM PST 24 |
| Peak memory | 599932 kb |
| Host | smart-7b10052c-e7de-46f9-bff2-7f496edaeeb8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352076389 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.2352076389 |
| Directory | /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2521297063 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 4080579294 ps |
| CPU time | 477.61 seconds |
| Started | Feb 07 04:34:46 PM PST 24 |
| Finished | Feb 07 04:42:44 PM PST 24 |
| Peak memory | 600940 kb |
| Host | smart-93e2d8ec-368e-422c-81ce-421460e108b4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521297063 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.2521297063 |
| Directory | /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.4041666294 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 11316641840 ps |
| CPU time | 1226.6 seconds |
| Started | Feb 07 04:34:13 PM PST 24 |
| Finished | Feb 07 04:54:40 PM PST 24 |
| Peak memory | 601416 kb |
| Host | smart-cd45d47d-538e-477c-b16d-2cc43016e200 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041666294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.4041666294 |
| Directory | /workspace/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.675401684 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 3177862890 ps |
| CPU time | 469.85 seconds |
| Started | Feb 07 04:35:09 PM PST 24 |
| Finished | Feb 07 04:43:03 PM PST 24 |
| Peak memory | 599160 kb |
| Host | smart-dfd08313-a2d5-45cd-bef7-5b7d09ec4803 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675401684 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.675401684 |
| Directory | /workspace/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3904896101 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 3831638568 ps |
| CPU time | 533.17 seconds |
| Started | Feb 07 04:33:36 PM PST 24 |
| Finished | Feb 07 04:42:34 PM PST 24 |
| Peak memory | 600712 kb |
| Host | smart-deb1598c-e05f-4884-9aaa-88c5d5465340 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904896101 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.3904896101 |
| Directory | /workspace/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.2017596408 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 2738763066 ps |
| CPU time | 322.22 seconds |
| Started | Feb 07 04:37:14 PM PST 24 |
| Finished | Feb 07 04:42:37 PM PST 24 |
| Peak memory | 599104 kb |
| Host | smart-5d0841b2-8dce-4042-bf6e-b2ead670d2fc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017596408 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_clkmgr_smoketest.2017596408 |
| Directory | /workspace/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_coremark.4031565771 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 50243049196 ps |
| CPU time | 9864.25 seconds |
| Started | Feb 07 04:34:47 PM PST 24 |
| Finished | Feb 07 07:19:12 PM PST 24 |
| Peak memory | 602168 kb |
| Host | smart-d1e21a00-3d1d-42d9-81cf-fe26071665f0 |
| User | root |
| Command | /workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=4031565771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.4031565771 |
| Directory | /workspace/0.chip_sw_coremark/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2093055023 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 10106513200 ps |
| CPU time | 2584.28 seconds |
| Started | Feb 07 04:34:00 PM PST 24 |
| Finished | Feb 07 05:17:06 PM PST 24 |
| Peak memory | 601096 kb |
| Host | smart-2e664da5-86c9-45e1-a877-0177059e59e9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093055023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.2093055023 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.262539484 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 3366415240 ps |
| CPU time | 362.25 seconds |
| Started | Feb 07 04:33:04 PM PST 24 |
| Finished | Feb 07 04:39:07 PM PST 24 |
| Peak memory | 599944 kb |
| Host | smart-cd2864ac-3817-4cea-a7a0-14cd0c3c6c17 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26253 9484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.262539484 |
| Directory | /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_kat_test.1568700679 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 1957064440 ps |
| CPU time | 206.23 seconds |
| Started | Feb 07 04:36:03 PM PST 24 |
| Finished | Feb 07 04:39:30 PM PST 24 |
| Peak memory | 600408 kb |
| Host | smart-f8bfa429-9d56-4aa1-b4c5-349bb456dc4e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568700679 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.1568700679 |
| Directory | /workspace/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1903164018 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 10396237494 ps |
| CPU time | 743.79 seconds |
| Started | Feb 07 04:33:56 PM PST 24 |
| Finished | Feb 07 04:46:21 PM PST 24 |
| Peak memory | 602232 kb |
| Host | smart-8c26f6ae-f4cd-493b-aec0-23dc49eb1343 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903164018 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csr ng_lc_hw_debug_en_test.1903164018 |
| Directory | /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_smoketest.4132184732 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 2997007268 ps |
| CPU time | 159.32 seconds |
| Started | Feb 07 04:37:16 PM PST 24 |
| Finished | Feb 07 04:39:56 PM PST 24 |
| Peak memory | 600540 kb |
| Host | smart-c3e1618f-40a7-4dc9-8f75-0a6e9139ba87 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132184732 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_csrng_smoketest.4132184732 |
| Directory | /workspace/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_data_integrity_escalation.326526943 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 6606156930 ps |
| CPU time | 897.08 seconds |
| Started | Feb 07 04:33:50 PM PST 24 |
| Finished | Feb 07 04:48:48 PM PST 24 |
| Peak memory | 600652 kb |
| Host | smart-a78639ad-8049-4aff-aed2-2a2343cb1379 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=326526943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.326526943 |
| Directory | /workspace/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2257651695 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 5011990466 ps |
| CPU time | 1023.82 seconds |
| Started | Feb 07 04:34:01 PM PST 24 |
| Finished | Feb 07 04:51:05 PM PST 24 |
| Peak memory | 599728 kb |
| Host | smart-3f828a7f-4b36-4418-8259-e055b8e86db6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257651695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.2257651695 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_kat.2190259413 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 3543151840 ps |
| CPU time | 618.14 seconds |
| Started | Feb 07 04:34:44 PM PST 24 |
| Finished | Feb 07 04:45:03 PM PST 24 |
| Peak memory | 606928 kb |
| Host | smart-26b684cb-5035-4cf5-88c4-feae2ae29286 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190259413 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_edn_kat.2190259413 |
| Directory | /workspace/0.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_sw_mode.1383843539 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 10323566930 ps |
| CPU time | 2141.84 seconds |
| Started | Feb 07 04:34:33 PM PST 24 |
| Finished | Feb 07 05:10:16 PM PST 24 |
| Peak memory | 599496 kb |
| Host | smart-c6b207e2-47af-4519-b58e-b59acc6798bc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383843539 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.1383843539 |
| Directory | /workspace/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1235203558 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 2738972708 ps |
| CPU time | 268.57 seconds |
| Started | Feb 07 04:35:18 PM PST 24 |
| Finished | Feb 07 04:39:51 PM PST 24 |
| Peak memory | 600388 kb |
| Host | smart-bbe8e24c-80c1-40be-8bcd-f30c63dafe27 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12 35203558 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.1235203558 |
| Directory | /workspace/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_csrng.4217065923 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 6656278316 ps |
| CPU time | 1390.4 seconds |
| Started | Feb 07 04:33:52 PM PST 24 |
| Finished | Feb 07 04:57:03 PM PST 24 |
| Peak memory | 601120 kb |
| Host | smart-13450c55-a615-4527-94fb-54e5b4d01644 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4217065923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.4217065923 |
| Directory | /workspace/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.1674895207 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 2804365400 ps |
| CPU time | 202.59 seconds |
| Started | Feb 07 04:33:30 PM PST 24 |
| Finished | Feb 07 04:36:56 PM PST 24 |
| Peak memory | 599064 kb |
| Host | smart-21317064-f44f-4839-aa72-85c6465a45c7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674895207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.1674895207 |
| Directory | /workspace/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.4280682978 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 3523268528 ps |
| CPU time | 406.13 seconds |
| Started | Feb 07 04:39:10 PM PST 24 |
| Finished | Feb 07 04:45:57 PM PST 24 |
| Peak memory | 599140 kb |
| Host | smart-bcdbf0e1-d49d-4cfe-ba9a-3791b3623efd |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4280682978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.4280682978 |
| Directory | /workspace/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_concurrency.2890107178 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 2030150356 ps |
| CPU time | 190.19 seconds |
| Started | Feb 07 04:32:59 PM PST 24 |
| Finished | Feb 07 04:36:10 PM PST 24 |
| Peak memory | 599036 kb |
| Host | smart-8a11b12e-cb76-41ef-8e15-f3a5c74fad46 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890107178 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_example_concurrency.2890107178 |
| Directory | /workspace/0.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_flash.974262319 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 2585280964 ps |
| CPU time | 244.2 seconds |
| Started | Feb 07 04:33:02 PM PST 24 |
| Finished | Feb 07 04:37:07 PM PST 24 |
| Peak memory | 599020 kb |
| Host | smart-ba906add-0ff7-4514-8cda-2dcddaea03e5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974262319 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.974262319 |
| Directory | /workspace/0.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_manufacturer.812766784 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 2556194168 ps |
| CPU time | 162.38 seconds |
| Started | Feb 07 04:31:55 PM PST 24 |
| Finished | Feb 07 04:34:42 PM PST 24 |
| Peak memory | 600476 kb |
| Host | smart-f01d93fc-d1fb-4b67-8a54-57cf25ea67ea |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812766784 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.chip_sw_example_manufacturer.812766784 |
| Directory | /workspace/0.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_rom.3953472916 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 2275477564 ps |
| CPU time | 107.28 seconds |
| Started | Feb 07 04:31:22 PM PST 24 |
| Finished | Feb 07 04:33:10 PM PST 24 |
| Peak memory | 598480 kb |
| Host | smart-7ce8d34d-94c4-4609-9375-a3c2ab37f134 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953472916 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_rom.3953472916 |
| Directory | /workspace/0.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.761432766 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 57963911380 ps |
| CPU time | 12448.2 seconds |
| Started | Feb 07 04:32:43 PM PST 24 |
| Finished | Feb 07 08:00:13 PM PST 24 |
| Peak memory | 615052 kb |
| Host | smart-cc8d1a2a-3ea2-4d8f-af6c-56b642b59ecf |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=761432766 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.761432766 |
| Directory | /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_crash_alert.184283733 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 5704694530 ps |
| CPU time | 855.67 seconds |
| Started | Feb 07 04:36:24 PM PST 24 |
| Finished | Feb 07 04:50:40 PM PST 24 |
| Peak memory | 600760 kb |
| Host | smart-6eb7aeea-2bc1-402b-ab0c-a050088fafc2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=184283733 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.184283733 |
| Directory | /workspace/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access.2741564329 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 6005469116 ps |
| CPU time | 1265.81 seconds |
| Started | Feb 07 04:33:11 PM PST 24 |
| Finished | Feb 07 04:54:17 PM PST 24 |
| Peak memory | 599500 kb |
| Host | smart-ca8cbe2d-f7ec-42f6-81a4-2caba8ea924f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741564329 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_flash_ctrl_access.2741564329 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3479261169 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 6331595347 ps |
| CPU time | 1053.54 seconds |
| Started | Feb 07 04:32:52 PM PST 24 |
| Finished | Feb 07 04:50:27 PM PST 24 |
| Peak memory | 600832 kb |
| Host | smart-6ac0e73a-1c17-4d57-843c-72752cc15340 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479261169 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.3479261169 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1384774755 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 6810170200 ps |
| CPU time | 1170.04 seconds |
| Started | Feb 07 04:35:54 PM PST 24 |
| Finished | Feb 07 04:55:25 PM PST 24 |
| Peak memory | 600868 kb |
| Host | smart-522d43a9-8f7b-4261-8c77-0419706a9f44 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384774755 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1384774755 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2761542358 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 5937283684 ps |
| CPU time | 1050.38 seconds |
| Started | Feb 07 04:32:09 PM PST 24 |
| Finished | Feb 07 04:49:40 PM PST 24 |
| Peak memory | 599400 kb |
| Host | smart-a5a51a9d-2f5b-445b-bf76-8dd62c4996c1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761542358 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.2761542358 |
| Directory | /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2629985018 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 2918758968 ps |
| CPU time | 386.86 seconds |
| Started | Feb 07 04:33:44 PM PST 24 |
| Finished | Feb 07 04:40:11 PM PST 24 |
| Peak memory | 599284 kb |
| Host | smart-e8f9d198-236d-4b81-aa87-457426748e15 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629985018 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.2629985018 |
| Directory | /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.114575586 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 5730042340 ps |
| CPU time | 1292.79 seconds |
| Started | Feb 07 04:37:55 PM PST 24 |
| Finished | Feb 07 04:59:28 PM PST 24 |
| Peak memory | 600828 kb |
| Host | smart-1d43fe8a-29a0-42e4-98e0-d0a483f37353 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114575586 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.114575586 |
| Directory | /workspace/0.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.1071722445 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 4743556186 ps |
| CPU time | 970.2 seconds |
| Started | Feb 07 04:34:12 PM PST 24 |
| Finished | Feb 07 04:50:23 PM PST 24 |
| Peak memory | 599588 kb |
| Host | smart-462e0deb-36fe-42b4-87c4-618705f03601 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071722445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.1071722445 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2223065990 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 4825476382 ps |
| CPU time | 895.68 seconds |
| Started | Feb 07 04:35:05 PM PST 24 |
| Finished | Feb 07 04:50:01 PM PST 24 |
| Peak memory | 600964 kb |
| Host | smart-0865b1c4-27e9-470c-88bd-aac826a5c529 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2223065990 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.2223065990 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1401555003 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 22378579970 ps |
| CPU time | 2301.34 seconds |
| Started | Feb 07 04:33:15 PM PST 24 |
| Finished | Feb 07 05:11:38 PM PST 24 |
| Peak memory | 602616 kb |
| Host | smart-4958ec16-4e27-41e0-8a43-598187742a72 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1401555003 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.1401555003 |
| Directory | /workspace/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.116487499 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 2218472056 ps |
| CPU time | 195.56 seconds |
| Started | Feb 07 04:40:12 PM PST 24 |
| Finished | Feb 07 04:43:29 PM PST 24 |
| Peak memory | 599496 kb |
| Host | smart-a067a0cc-8518-4682-9b18-d3ede0c00122 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=116487499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.116487499 |
| Directory | /workspace/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio_smoketest.1929993730 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 2752669860 ps |
| CPU time | 197.13 seconds |
| Started | Feb 07 04:37:40 PM PST 24 |
| Finished | Feb 07 04:40:58 PM PST 24 |
| Peak memory | 600840 kb |
| Host | smart-9a60c22e-febc-4095-adbe-dbb62fd0269f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929993730 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_gpio_smoketest.1929993730 |
| Directory | /workspace/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc.3196552423 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 3347272594 ps |
| CPU time | 409.45 seconds |
| Started | Feb 07 04:35:39 PM PST 24 |
| Finished | Feb 07 04:42:29 PM PST 24 |
| Peak memory | 600648 kb |
| Host | smart-866e175c-d5d3-428c-a0e8-c96a8bdf3ccc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196552423 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.3196552423 |
| Directory | /workspace/0.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_idle.54139464 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 2757778182 ps |
| CPU time | 239.94 seconds |
| Started | Feb 07 04:33:32 PM PST 24 |
| Finished | Feb 07 04:37:33 PM PST 24 |
| Peak memory | 600588 kb |
| Host | smart-4cff9428-2efe-4828-b6b2-b3826336b4c4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54139464 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_hmac_enc_idle.54139464 |
| Directory | /workspace/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.4080171729 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 2752117400 ps |
| CPU time | 273.2 seconds |
| Started | Feb 07 04:36:14 PM PST 24 |
| Finished | Feb 07 04:40:48 PM PST 24 |
| Peak memory | 600564 kb |
| Host | smart-468ca7c5-80e9-48c4-a5dd-ee5b355cde0c |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080171729 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.4080171729 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1072981553 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 2981157905 ps |
| CPU time | 355.78 seconds |
| Started | Feb 07 04:35:29 PM PST 24 |
| Finished | Feb 07 04:41:26 PM PST 24 |
| Peak memory | 599236 kb |
| Host | smart-c9dc48ec-9369-4e86-9211-ff6cbd221201 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072981553 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.1072981553 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_smoketest.479648165 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 3045981200 ps |
| CPU time | 378.51 seconds |
| Started | Feb 07 04:36:05 PM PST 24 |
| Finished | Feb 07 04:42:24 PM PST 24 |
| Peak memory | 600512 kb |
| Host | smart-5f7837e5-5b2c-4efb-b604-dc2f477038e0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479648165 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_smoketest.479648165 |
| Directory | /workspace/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2168074074 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 3617780622 ps |
| CPU time | 610.43 seconds |
| Started | Feb 07 04:32:16 PM PST 24 |
| Finished | Feb 07 04:42:27 PM PST 24 |
| Peak memory | 600300 kb |
| Host | smart-bd3dee6c-2ce1-42c1-845f-7f0b3b7ef753 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168074074 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.2168074074 |
| Directory | /workspace/0.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3546170423 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 5442500348 ps |
| CPU time | 1048.05 seconds |
| Started | Feb 07 04:32:08 PM PST 24 |
| Finished | Feb 07 04:49:37 PM PST 24 |
| Peak memory | 601032 kb |
| Host | smart-2adbe042-96e6-4415-b3d5-bebf5bea641d |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546170423 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.3546170423 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.4093524106 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 5012158076 ps |
| CPU time | 992.19 seconds |
| Started | Feb 07 04:33:01 PM PST 24 |
| Finished | Feb 07 04:49:34 PM PST 24 |
| Peak memory | 600988 kb |
| Host | smart-f4d9110f-dae2-45d2-9bd1-9a1f5908f39f |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093524106 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.4093524106 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_inject_scramble_seed.2796191670 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 64741757504 ps |
| CPU time | 12750.6 seconds |
| Started | Feb 07 04:33:00 PM PST 24 |
| Finished | Feb 07 08:05:33 PM PST 24 |
| Peak memory | 616920 kb |
| Host | smart-14e5604d-89d1-4f46-9668-04a575b52ae0 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2796191670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.2796191670 |
| Directory | /workspace/0.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.289441409 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 4697019178 ps |
| CPU time | 454.76 seconds |
| Started | Feb 07 04:33:30 PM PST 24 |
| Finished | Feb 07 04:41:08 PM PST 24 |
| Peak memory | 608396 kb |
| Host | smart-d3211746-7d50-440d-bcaa-ab85b36f7853 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894 41409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.289441409 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3715805450 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 4294802025 ps |
| CPU time | 511.57 seconds |
| Started | Feb 07 04:34:44 PM PST 24 |
| Finished | Feb 07 04:43:17 PM PST 24 |
| Peak memory | 607436 kb |
| Host | smart-c351b4aa-32bf-4b92-b675-55f18954b0ad |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3715805450 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.3715805450 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2235051985 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 3881429289 ps |
| CPU time | 400.99 seconds |
| Started | Feb 07 04:36:14 PM PST 24 |
| Finished | Feb 07 04:42:56 PM PST 24 |
| Peak memory | 608448 kb |
| Host | smart-533f6bea-f4df-4fa0-824a-1ad87c4c15e5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2235051985 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.2235051985 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.924251829 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 5243324552 ps |
| CPU time | 454.09 seconds |
| Started | Feb 07 04:34:07 PM PST 24 |
| Finished | Feb 07 04:41:42 PM PST 24 |
| Peak memory | 608436 kb |
| Host | smart-2e5c7f95-48a8-4ba2-a018-ecaad148bb03 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=924251829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.924251829 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1266825516 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 4147580440 ps |
| CPU time | 676.05 seconds |
| Started | Feb 07 04:33:24 PM PST 24 |
| Finished | Feb 07 04:44:41 PM PST 24 |
| Peak memory | 601928 kb |
| Host | smart-da951e86-ddd9-4390-8fac-730031bff282 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126682 5516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.1266825516 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1160332916 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 3627456120 ps |
| CPU time | 446.31 seconds |
| Started | Feb 07 04:34:52 PM PST 24 |
| Finished | Feb 07 04:42:19 PM PST 24 |
| Peak memory | 601960 kb |
| Host | smart-1ced865d-f25f-40f0-bd4d-71afd67b03e0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11603 32916 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.1160332916 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_app_rom.3010257860 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 2186269880 ps |
| CPU time | 197.79 seconds |
| Started | Feb 07 04:35:25 PM PST 24 |
| Finished | Feb 07 04:38:44 PM PST 24 |
| Peak memory | 600520 kb |
| Host | smart-071f7a31-8863-4805-b605-01403d67c0e4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010257860 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_app_rom.3010257860 |
| Directory | /workspace/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_idle.2012137444 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 2572717308 ps |
| CPU time | 229.86 seconds |
| Started | Feb 07 04:35:14 PM PST 24 |
| Finished | Feb 07 04:39:06 PM PST 24 |
| Peak memory | 600488 kb |
| Host | smart-28a17682-d55c-4e71-b761-ac31abf9920f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012137444 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_idle.2012137444 |
| Directory | /workspace/0.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.555498154 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 2926348100 ps |
| CPU time | 355.28 seconds |
| Started | Feb 07 04:34:53 PM PST 24 |
| Finished | Feb 07 04:40:52 PM PST 24 |
| Peak memory | 600564 kb |
| Host | smart-464a9c4c-9ec2-408a-ae1f-ddba542cdf33 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555498154 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_kmac_mode_cshake.555498154 |
| Directory | /workspace/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.3243390157 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 2914925180 ps |
| CPU time | 413.25 seconds |
| Started | Feb 07 04:35:31 PM PST 24 |
| Finished | Feb 07 04:42:25 PM PST 24 |
| Peak memory | 600600 kb |
| Host | smart-a95398d6-1926-4be5-843d-b9db8cfc27f6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243390157 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_kmac_mode_kmac.3243390157 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3448425618 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 3348096601 ps |
| CPU time | 304.66 seconds |
| Started | Feb 07 04:33:50 PM PST 24 |
| Finished | Feb 07 04:38:55 PM PST 24 |
| Peak memory | 599184 kb |
| Host | smart-8e2e828e-c8b2-4a66-bcd1-f499fa83e6a3 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448425618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.3448425618 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.271864672 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 3300753503 ps |
| CPU time | 306.7 seconds |
| Started | Feb 07 04:37:23 PM PST 24 |
| Finished | Feb 07 04:42:31 PM PST 24 |
| Peak memory | 599204 kb |
| Host | smart-cf18f40d-9e48-415a-84c8-cf0fe1282fef |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27186467 2 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.271864672 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_smoketest.4023558415 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 2779771460 ps |
| CPU time | 355.47 seconds |
| Started | Feb 07 04:37:55 PM PST 24 |
| Finished | Feb 07 04:43:51 PM PST 24 |
| Peak memory | 600520 kb |
| Host | smart-e7821d91-6b3c-4367-9c03-602c6b58e17e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023558415 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_smoketest.4023558415 |
| Directory | /workspace/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.1203591943 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 3264570760 ps |
| CPU time | 298.69 seconds |
| Started | Feb 07 04:33:50 PM PST 24 |
| Finished | Feb 07 04:38:50 PM PST 24 |
| Peak memory | 599032 kb |
| Host | smart-d328a330-3c3c-4ef2-93c5-795547891dd7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203591943 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.1203591943 |
| Directory | /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3111003645 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 3762128539 ps |
| CPU time | 148.78 seconds |
| Started | Feb 07 04:38:37 PM PST 24 |
| Finished | Feb 07 04:41:07 PM PST 24 |
| Peak memory | 603524 kb |
| Host | smart-687e4efb-956e-4d01-978b-f6bd26af47a3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31110036 45 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.3111003645 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.414892162 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 3406079334 ps |
| CPU time | 165.23 seconds |
| Started | Feb 07 04:32:36 PM PST 24 |
| Finished | Feb 07 04:35:22 PM PST 24 |
| Peak memory | 602820 kb |
| Host | smart-c184f314-1120-4dec-885b-208bc8e870c7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414892162 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.414892162 |
| Directory | /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1774075837 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 2357850977 ps |
| CPU time | 135.27 seconds |
| Started | Feb 07 04:33:08 PM PST 24 |
| Finished | Feb 07 04:35:24 PM PST 24 |
| Peak memory | 603036 kb |
| Host | smart-8d15c574-85e2-4905-a6bc-3ef5b1a5cad3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774075837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.1774075837 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.4122997915 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 9047747721 ps |
| CPU time | 1085.33 seconds |
| Started | Feb 07 04:37:23 PM PST 24 |
| Finished | Feb 07 04:55:29 PM PST 24 |
| Peak memory | 603984 kb |
| Host | smart-0b7b13c9-9ef2-4731-8e72-d9fc70658c6e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122997915 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.4122997915 |
| Directory | /workspace/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2840559886 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 5095038212 ps |
| CPU time | 322.82 seconds |
| Started | Feb 07 04:36:56 PM PST 24 |
| Finished | Feb 07 04:42:21 PM PST 24 |
| Peak memory | 606264 kb |
| Host | smart-459d4e22-ee51-4fb3-8f09-717d79096ec3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=lc_ctrl_volat ile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840559886 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_ unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_vol atile_raw_unlock_ext_clk_48mhz.2840559886 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.4267137513 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 10759626360 ps |
| CPU time | 1020.15 seconds |
| Started | Feb 07 04:34:57 PM PST 24 |
| Finished | Feb 07 04:51:58 PM PST 24 |
| Peak memory | 607916 kb |
| Host | smart-69c59793-1ad1-4a34-90da-1487e7d9fe0d |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267137513 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.4267137513 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1935968114 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 37062507095 ps |
| CPU time | 2340.86 seconds |
| Started | Feb 07 04:33:06 PM PST 24 |
| Finished | Feb 07 05:12:08 PM PST 24 |
| Peak memory | 607100 kb |
| Host | smart-254d221e-d301-4977-a319-0ce947f7b2f3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1935968114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testun locks.1935968114 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.4114600963 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 16747584564 ps |
| CPU time | 3766.37 seconds |
| Started | Feb 07 04:34:19 PM PST 24 |
| Finished | Feb 07 05:37:06 PM PST 24 |
| Peak memory | 601096 kb |
| Host | smart-365c26e3-a002-429b-a085-9067f96b5660 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=4114600963 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.4114600963 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3618024753 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 19034827995 ps |
| CPU time | 3610.53 seconds |
| Started | Feb 07 04:34:04 PM PST 24 |
| Finished | Feb 07 05:34:15 PM PST 24 |
| Peak memory | 600888 kb |
| Host | smart-4296c4d2-f515-43b1-afd6-c82a8a5dbfe0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3618024753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3618024753 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2501011998 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 24086398513 ps |
| CPU time | 4282.03 seconds |
| Started | Feb 07 04:37:35 PM PST 24 |
| Finished | Feb 07 05:48:58 PM PST 24 |
| Peak memory | 599648 kb |
| Host | smart-e49f9481-2d12-4c0f-b82e-b82f4ce2af19 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501011998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.2501011998 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.193153263 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 3386831832 ps |
| CPU time | 553.85 seconds |
| Started | Feb 07 04:34:18 PM PST 24 |
| Finished | Feb 07 04:43:32 PM PST 24 |
| Peak memory | 600668 kb |
| Host | smart-206a6630-07e1-4944-9ae5-e022ddef5ff2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193153263 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.193153263 |
| Directory | /workspace/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_randomness.3833558716 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 6074774174 ps |
| CPU time | 1185.64 seconds |
| Started | Feb 07 04:34:06 PM PST 24 |
| Finished | Feb 07 04:53:52 PM PST 24 |
| Peak memory | 599748 kb |
| Host | smart-9894f95c-5e29-4643-9f16-d137f02d4d37 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3833558716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.3833558716 |
| Directory | /workspace/0.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_smoketest.152075156 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 9598783098 ps |
| CPU time | 1887.97 seconds |
| Started | Feb 07 04:36:50 PM PST 24 |
| Finished | Feb 07 05:08:19 PM PST 24 |
| Peak memory | 601092 kb |
| Host | smart-fb1b21f5-39dc-4587-86e7-a4ff84763b27 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152075156 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_smoketest.152075156 |
| Directory | /workspace/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3387883482 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 8757015200 ps |
| CPU time | 1283.28 seconds |
| Started | Feb 07 04:32:40 PM PST 24 |
| Finished | Feb 07 04:54:04 PM PST 24 |
| Peak memory | 601556 kb |
| Host | smart-416145b2-3b59-4b32-84eb-375763696b76 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3387883482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.3387883482 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.3871380771 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 7731953590 ps |
| CPU time | 908.15 seconds |
| Started | Feb 07 04:32:37 PM PST 24 |
| Finished | Feb 07 04:47:46 PM PST 24 |
| Peak memory | 601516 kb |
| Host | smart-989721f6-b52a-4639-ba58-b26f7a2336cd |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3871380771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.3871380771 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.4265722416 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 7541482300 ps |
| CPU time | 1390 seconds |
| Started | Feb 07 04:34:18 PM PST 24 |
| Finished | Feb 07 04:57:29 PM PST 24 |
| Peak memory | 601532 kb |
| Host | smart-a7016082-6d93-41d8-a8dd-48fd25f61155 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=4265722416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.4265722416 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3738854984 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 8458321646 ps |
| CPU time | 800.25 seconds |
| Started | Feb 07 04:32:48 PM PST 24 |
| Finished | Feb 07 04:46:09 PM PST 24 |
| Peak memory | 599500 kb |
| Host | smart-2cb66778-1296-4171-b21a-078a8fbf6c65 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3738854984 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3738854984 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.625655855 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 3141051176 ps |
| CPU time | 253.41 seconds |
| Started | Feb 07 04:38:07 PM PST 24 |
| Finished | Feb 07 04:42:20 PM PST 24 |
| Peak memory | 600560 kb |
| Host | smart-aa238d87-d2a5-437a-bd18-cda48e8ed57e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625655855 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_otp_ctrl_smoketest.625655855 |
| Directory | /workspace/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pattgen_ios.1889057389 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 2861858500 ps |
| CPU time | 231.4 seconds |
| Started | Feb 07 04:33:20 PM PST 24 |
| Finished | Feb 07 04:37:13 PM PST 24 |
| Peak memory | 595584 kb |
| Host | smart-5366a51b-fb2c-4fcd-a619-9cd4f00a418f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889057389 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.1889057389 |
| Directory | /workspace/0.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_sleep_load.3869360746 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 10375596096 ps |
| CPU time | 553.75 seconds |
| Started | Feb 07 04:34:24 PM PST 24 |
| Finished | Feb 07 04:43:38 PM PST 24 |
| Peak memory | 601868 kb |
| Host | smart-82c67588-430b-448e-acc7-cd6fb3d5ec2d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869360746 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.3869360746 |
| Directory | /workspace/0.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.216115057 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 13053933496 ps |
| CPU time | 1961.45 seconds |
| Started | Feb 07 04:35:00 PM PST 24 |
| Finished | Feb 07 05:07:42 PM PST 24 |
| Peak memory | 602368 kb |
| Host | smart-73943f2a-dd6d-43fc-b605-3ba0971555b9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161 15057 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.216115057 |
| Directory | /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2384674615 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 22251674464 ps |
| CPU time | 2840.71 seconds |
| Started | Feb 07 04:33:35 PM PST 24 |
| Finished | Feb 07 05:21:01 PM PST 24 |
| Peak memory | 601640 kb |
| Host | smart-17d15a3c-303f-4f74-884c-88789fb3fe55 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238 4674615 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.2384674615 |
| Directory | /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2075023864 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 18750483317 ps |
| CPU time | 1634.24 seconds |
| Started | Feb 07 04:33:41 PM PST 24 |
| Finished | Feb 07 05:00:57 PM PST 24 |
| Peak memory | 602292 kb |
| Host | smart-d5244619-263f-4956-b0b7-387c0d0e3162 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2075023864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2075023864 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.418160267 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 22606284808 ps |
| CPU time | 1417.02 seconds |
| Started | Feb 07 04:35:30 PM PST 24 |
| Finished | Feb 07 04:59:08 PM PST 24 |
| Peak memory | 601724 kb |
| Host | smart-df925bfd-41a7-4157-b8b8-943e1671d1cc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 418160267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.418160267 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2120338580 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 7193874360 ps |
| CPU time | 483.33 seconds |
| Started | Feb 07 04:33:54 PM PST 24 |
| Finished | Feb 07 04:41:58 PM PST 24 |
| Peak memory | 601708 kb |
| Host | smart-de2b1905-41fb-4506-83f2-9c3090f3b27c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120338580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.2120338580 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3629322477 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 6614687032 ps |
| CPU time | 539.62 seconds |
| Started | Feb 07 04:34:49 PM PST 24 |
| Finished | Feb 07 04:43:50 PM PST 24 |
| Peak memory | 606868 kb |
| Host | smart-d995eb1d-bb56-4191-8f89-9cccfc346493 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3629322477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3629322477 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2163823731 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 3154708900 ps |
| CPU time | 391.77 seconds |
| Started | Feb 07 04:32:26 PM PST 24 |
| Finished | Feb 07 04:38:58 PM PST 24 |
| Peak memory | 606480 kb |
| Host | smart-34c9dd86-00c4-468c-ab1d-9b853d80e2f3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2163823731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.2163823731 |
| Directory | /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3701721278 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 11935291980 ps |
| CPU time | 1465.6 seconds |
| Started | Feb 07 04:34:05 PM PST 24 |
| Finished | Feb 07 04:58:31 PM PST 24 |
| Peak memory | 602444 kb |
| Host | smart-63204ed3-b1fb-482f-989f-05af8cd75f5c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701721278 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3701721278 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3880753437 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 7213070328 ps |
| CPU time | 558 seconds |
| Started | Feb 07 04:34:33 PM PST 24 |
| Finished | Feb 07 04:43:51 PM PST 24 |
| Peak memory | 601332 kb |
| Host | smart-bd56df0c-5930-471d-9b07-17d62d39a4ce |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880753437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3880753437 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3797787311 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 19591896788 ps |
| CPU time | 2486.86 seconds |
| Started | Feb 07 04:33:13 PM PST 24 |
| Finished | Feb 07 05:14:41 PM PST 24 |
| Peak memory | 602460 kb |
| Host | smart-1aa36baf-9cac-4377-b030-684cb3921dbf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3797787311 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3797787311 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3810081621 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 19156388888 ps |
| CPU time | 1771.93 seconds |
| Started | Feb 07 04:34:38 PM PST 24 |
| Finished | Feb 07 05:04:10 PM PST 24 |
| Peak memory | 601812 kb |
| Host | smart-f3bb0422-e59d-4f4c-91ac-cef9bf5a171f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3810081621 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3810081621 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.249615571 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 3184026072 ps |
| CPU time | 260.74 seconds |
| Started | Feb 07 04:37:13 PM PST 24 |
| Finished | Feb 07 04:41:34 PM PST 24 |
| Peak memory | 600460 kb |
| Host | smart-3dd865d8-c53a-4696-b702-4668ddded037 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249615571 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.249615571 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3412552985 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 6595525410 ps |
| CPU time | 666.88 seconds |
| Started | Feb 07 04:33:33 PM PST 24 |
| Finished | Feb 07 04:44:45 PM PST 24 |
| Peak memory | 608340 kb |
| Host | smart-e6bf6ada-1e67-4dab-920f-ebf3ffd5378c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3412552985 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.3412552985 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1322283212 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 5779894200 ps |
| CPU time | 495.9 seconds |
| Started | Feb 07 04:36:00 PM PST 24 |
| Finished | Feb 07 04:44:17 PM PST 24 |
| Peak memory | 601492 kb |
| Host | smart-0f36c368-deb2-4642-b26b-3891aef5281b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1322283212 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.1322283212 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3855331987 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 4803554082 ps |
| CPU time | 304.33 seconds |
| Started | Feb 07 04:37:31 PM PST 24 |
| Finished | Feb 07 04:42:35 PM PST 24 |
| Peak memory | 601336 kb |
| Host | smart-825c110d-1057-4147-a741-b0b4d9861b24 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855331987 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.3855331987 |
| Directory | /workspace/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.4025263620 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 7504011823 ps |
| CPU time | 1097.97 seconds |
| Started | Feb 07 04:38:36 PM PST 24 |
| Finished | Feb 07 04:56:55 PM PST 24 |
| Peak memory | 601468 kb |
| Host | smart-52c95c75-0f7d-4536-8369-3d9d936a897d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025263620 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.4025263620 |
| Directory | /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1421685071 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 3904713224 ps |
| CPU time | 579.75 seconds |
| Started | Feb 07 04:37:13 PM PST 24 |
| Finished | Feb 07 04:46:54 PM PST 24 |
| Peak memory | 599608 kb |
| Host | smart-b21cd1b0-7899-45fe-9fbd-df8ea77d86a2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421685071 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1421685071 |
| Directory | /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.541566434 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 4024463770 ps |
| CPU time | 333.81 seconds |
| Started | Feb 07 04:36:53 PM PST 24 |
| Finished | Feb 07 04:42:29 PM PST 24 |
| Peak memory | 601000 kb |
| Host | smart-ad9c3a29-eb9e-405f-a999-e988c336bffc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541566434 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.541566434 |
| Directory | /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1950884640 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 5421302232 ps |
| CPU time | 354.23 seconds |
| Started | Feb 07 04:34:17 PM PST 24 |
| Finished | Feb 07 04:40:11 PM PST 24 |
| Peak memory | 600844 kb |
| Host | smart-d4517b51-7c3a-41da-a7c2-32fce6bcb0f2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195 0884640 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.1950884640 |
| Directory | /workspace/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.2773581785 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 9681818016 ps |
| CPU time | 778.24 seconds |
| Started | Feb 07 04:34:37 PM PST 24 |
| Finished | Feb 07 04:47:36 PM PST 24 |
| Peak memory | 603840 kb |
| Host | smart-7e683ef7-934a-4108-92f5-3c2e38055578 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773581785 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.2773581785 |
| Directory | /workspace/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2749680723 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 7252418698 ps |
| CPU time | 649.87 seconds |
| Started | Feb 07 04:34:53 PM PST 24 |
| Finished | Feb 07 04:45:43 PM PST 24 |
| Peak memory | 601364 kb |
| Host | smart-1f59f3ec-6435-423d-b79d-65ac0633a624 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749680723 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.2749680723 |
| Directory | /workspace/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3169446892 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 4513281704 ps |
| CPU time | 660.39 seconds |
| Started | Feb 07 04:32:42 PM PST 24 |
| Finished | Feb 07 04:43:43 PM PST 24 |
| Peak memory | 631064 kb |
| Host | smart-f5c2cd94-902c-47f5-86fb-4f52cec583ac |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3169446892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.3169446892 |
| Directory | /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.337517821 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 3099143332 ps |
| CPU time | 326.85 seconds |
| Started | Feb 07 04:38:01 PM PST 24 |
| Finished | Feb 07 04:43:29 PM PST 24 |
| Peak memory | 600516 kb |
| Host | smart-30e4683e-b8e4-43d2-80a4-be495feb2503 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337517821 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_rstmgr_smoketest.337517821 |
| Directory | /workspace/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.3872046238 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 3790212312 ps |
| CPU time | 548.93 seconds |
| Started | Feb 07 04:33:48 PM PST 24 |
| Finished | Feb 07 04:42:58 PM PST 24 |
| Peak memory | 600772 kb |
| Host | smart-e5f5d244-6cbd-4291-8961-f8e50a809fff |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872046238 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rstmgr_sw_req.3872046238 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1384805897 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 2439904600 ps |
| CPU time | 294.27 seconds |
| Started | Feb 07 04:37:12 PM PST 24 |
| Finished | Feb 07 04:42:07 PM PST 24 |
| Peak memory | 600504 kb |
| Host | smart-ef8ca811-a205-45cd-8be5-f51fe4137286 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384805897 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.1384805897 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.590704810 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 2535405102 ps |
| CPU time | 309.3 seconds |
| Started | Feb 07 04:36:29 PM PST 24 |
| Finished | Feb 07 04:41:39 PM PST 24 |
| Peak memory | 599144 kb |
| Host | smart-198b2a1c-62c0-465c-a409-014b3378af6b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590704810 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.590704810 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2313510751 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 2828638900 ps |
| CPU time | 141.97 seconds |
| Started | Feb 07 04:36:12 PM PST 24 |
| Finished | Feb 07 04:38:35 PM PST 24 |
| Peak memory | 598388 kb |
| Host | smart-2168580c-09a3-4330-a3cd-7d5f889c3a37 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313510751 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_lockstep_glitch.2313510751 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3451054713 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 5825229600 ps |
| CPU time | 1164.86 seconds |
| Started | Feb 07 04:33:43 PM PST 24 |
| Finished | Feb 07 04:53:09 PM PST 24 |
| Peak memory | 600776 kb |
| Host | smart-9c6779a2-f8aa-4a6b-9693-03f786c36d40 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3451054713 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.3451054713 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.602383414 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 5512279224 ps |
| CPU time | 534.12 seconds |
| Started | Feb 07 04:36:30 PM PST 24 |
| Finished | Feb 07 04:45:25 PM PST 24 |
| Peak memory | 616320 kb |
| Host | smart-00c9afee-2390-4aee-b9fe-29306771c905 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup:1:new_rules,test_rom:0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602383414 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.602383414 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.457579032 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 2822239210 ps |
| CPU time | 220.53 seconds |
| Started | Feb 07 04:37:28 PM PST 24 |
| Finished | Feb 07 04:41:10 PM PST 24 |
| Peak memory | 599064 kb |
| Host | smart-5b22ac75-aa78-4ede-95cf-7a85b3bb12d6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457579032 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rv_plic_smoketest.457579032 |
| Directory | /workspace/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_irq.1465122696 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 2260597500 ps |
| CPU time | 218.65 seconds |
| Started | Feb 07 04:32:12 PM PST 24 |
| Finished | Feb 07 04:35:51 PM PST 24 |
| Peak memory | 599124 kb |
| Host | smart-a2f13343-db26-4fb3-a989-cc82f8e8ce0b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465122696 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_irq.1465122696 |
| Directory | /workspace/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1308058135 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 2497320568 ps |
| CPU time | 205.62 seconds |
| Started | Feb 07 04:38:19 PM PST 24 |
| Finished | Feb 07 04:41:48 PM PST 24 |
| Peak memory | 599076 kb |
| Host | smart-ce5e57e3-3f9a-45ac-977c-6a06d3375a3a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308058135 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_smoketest.1308058135 |
| Directory | /workspace/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.800784283 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 3458881607 ps |
| CPU time | 337.34 seconds |
| Started | Feb 07 04:36:23 PM PST 24 |
| Finished | Feb 07 04:42:01 PM PST 24 |
| Peak memory | 601336 kb |
| Host | smart-a9147f70-f9a5-4ec2-bf2a-2ac7b52b9830 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8007842 83 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.800784283 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3015010229 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 9103857556 ps |
| CPU time | 1884.9 seconds |
| Started | Feb 07 04:33:35 PM PST 24 |
| Finished | Feb 07 05:05:05 PM PST 24 |
| Peak memory | 600636 kb |
| Host | smart-19e169f5-9f23-424d-8043-32079f404e92 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015010229 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.3015010229 |
| Directory | /workspace/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.4148521191 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 6570650268 ps |
| CPU time | 664.23 seconds |
| Started | Feb 07 04:34:04 PM PST 24 |
| Finished | Feb 07 04:45:08 PM PST 24 |
| Peak memory | 599988 kb |
| Host | smart-daeca633-074f-451a-8449-4e17346b22a7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148521191 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl eep_sram_ret_contents_no_scramble.4148521191 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2645543268 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 6108317284 ps |
| CPU time | 737.48 seconds |
| Started | Feb 07 04:34:26 PM PST 24 |
| Finished | Feb 07 04:46:44 PM PST 24 |
| Peak memory | 601452 kb |
| Host | smart-e5af9500-5e00-474d-9a1e-91df60d4ff8f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645543268 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep _sram_ret_contents_scramble.2645543268 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.570566533 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 4492698790 ps |
| CPU time | 485.7 seconds |
| Started | Feb 07 04:32:26 PM PST 24 |
| Finished | Feb 07 04:40:32 PM PST 24 |
| Peak memory | 618292 kb |
| Host | smart-00605385-c124-44de-8e25-3eb4a0eb5837 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570566533 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.570566533 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_tpm.669929859 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 3245918784 ps |
| CPU time | 395.64 seconds |
| Started | Feb 07 04:32:19 PM PST 24 |
| Finished | Feb 07 04:38:55 PM PST 24 |
| Peak memory | 615192 kb |
| Host | smart-4aee59cf-bc89-4e5b-9cce-b39b5d90e3a8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669929859 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.669929859 |
| Directory | /workspace/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1180364257 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 7723501076 ps |
| CPU time | 992.15 seconds |
| Started | Feb 07 04:34:21 PM PST 24 |
| Finished | Feb 07 04:50:53 PM PST 24 |
| Peak memory | 601624 kb |
| Host | smart-8c004bea-c1f0-48f6-b763-46c1e49184b1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180364257 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.1180364257 |
| Directory | /workspace/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2422081564 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 4756207786 ps |
| CPU time | 579.2 seconds |
| Started | Feb 07 04:34:56 PM PST 24 |
| Finished | Feb 07 04:44:36 PM PST 24 |
| Peak memory | 600904 kb |
| Host | smart-682d187a-25f7-48ee-964b-c234a4338a19 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422081564 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _sram_ctrl_scrambled_access.2422081564 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.422963520 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 4339435057 ps |
| CPU time | 681.74 seconds |
| Started | Feb 07 04:38:47 PM PST 24 |
| Finished | Feb 07 04:50:10 PM PST 24 |
| Peak memory | 601088 kb |
| Host | smart-c8339b3e-5af2-447c-8576-a183570d1b87 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422963520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.422963520 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.920925179 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 5147668397 ps |
| CPU time | 654.4 seconds |
| Started | Feb 07 04:36:32 PM PST 24 |
| Finished | Feb 07 04:47:28 PM PST 24 |
| Peak memory | 601068 kb |
| Host | smart-35d9612a-2471-4f58-a81b-0eb68e3e0bf0 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920925179 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.920925179 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.1025126285 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 2580553188 ps |
| CPU time | 273.44 seconds |
| Started | Feb 07 04:37:10 PM PST 24 |
| Finished | Feb 07 04:41:44 PM PST 24 |
| Peak memory | 600524 kb |
| Host | smart-7a7f3596-aa56-422d-bfff-34b7c1c08604 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025126285 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_sram_ctrl_smoketest.1025126285 |
| Directory | /workspace/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.3422406920 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 4498924192 ps |
| CPU time | 608.23 seconds |
| Started | Feb 07 04:37:10 PM PST 24 |
| Finished | Feb 07 04:47:20 PM PST 24 |
| Peak memory | 601388 kb |
| Host | smart-e716f6a3-0ea2-42c3-b9dc-d33bcf8efc17 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422406920 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.3422406920 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2557298338 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 3716973059 ps |
| CPU time | 333.21 seconds |
| Started | Feb 07 04:32:53 PM PST 24 |
| Finished | Feb 07 04:38:28 PM PST 24 |
| Peak memory | 601036 kb |
| Host | smart-b5f478e3-59a7-453c-817b-da87c7348071 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557298338 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.2557298338 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.703658972 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 23048387954 ps |
| CPU time | 1290.35 seconds |
| Started | Feb 07 04:34:23 PM PST 24 |
| Finished | Feb 07 04:55:55 PM PST 24 |
| Peak memory | 601392 kb |
| Host | smart-5e86805b-d65e-481d-a1a4-622a84c30a3b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70365897 2 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.703658972 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1434094088 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 5133067210 ps |
| CPU time | 349.51 seconds |
| Started | Feb 07 04:34:12 PM PST 24 |
| Finished | Feb 07 04:40:02 PM PST 24 |
| Peak memory | 600532 kb |
| Host | smart-ecb42024-a773-46c0-94dc-b35432f5f404 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434094088 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1434094088 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1605599140 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 13505995490 ps |
| CPU time | 3010.16 seconds |
| Started | Feb 07 04:33:01 PM PST 24 |
| Finished | Feb 07 05:23:13 PM PST 24 |
| Peak memory | 613792 kb |
| Host | smart-f1c6e1f1-3893-4c03-85d2-0598ca138904 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1605599140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.1605599140 |
| Directory | /workspace/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_smoketest.1738778170 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 2405159122 ps |
| CPU time | 268.06 seconds |
| Started | Feb 07 04:38:35 PM PST 24 |
| Finished | Feb 07 04:43:05 PM PST 24 |
| Peak memory | 595660 kb |
| Host | smart-6505db62-65cd-4a8c-88b2-fc9f830b338a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738778170 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_uart_smoketest.1738778170 |
| Directory | /workspace/0.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_smoketest_signed.3710129294 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 8906557570 ps |
| CPU time | 2199.82 seconds |
| Started | Feb 07 04:40:02 PM PST 24 |
| Finished | Feb 07 05:16:44 PM PST 24 |
| Peak memory | 595824 kb |
| Host | smart-274cf4c3-22ac-40c5-af9a-2b6a49bfb92b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=uart_smoketest_signed:1:signed:fake_rsa_test_key_0,rom_with_fa ke_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3710129294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_smoketest_signed.3710129294 |
| Directory | /workspace/0.chip_sw_uart_smoketest_signed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx.1953664478 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 6150486548 ps |
| CPU time | 1040.04 seconds |
| Started | Feb 07 04:32:24 PM PST 24 |
| Finished | Feb 07 04:49:45 PM PST 24 |
| Peak memory | 603096 kb |
| Host | smart-00f76057-165b-47a3-8b96-e8f54fa9fe40 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953664478 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.1953664478 |
| Directory | /workspace/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2117073503 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 12673244585 ps |
| CPU time | 2794.23 seconds |
| Started | Feb 07 04:33:04 PM PST 24 |
| Finished | Feb 07 05:19:40 PM PST 24 |
| Peak memory | 613700 kb |
| Host | smart-b4aa4d0f-24f2-47e9-a92e-f7bd39976c27 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117073503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq.2117073503 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2337171753 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 4912868022 ps |
| CPU time | 994.24 seconds |
| Started | Feb 07 04:32:27 PM PST 24 |
| Finished | Feb 07 04:49:02 PM PST 24 |
| Peak memory | 602844 kb |
| Host | smart-1d2aa6a0-b13c-4259-b380-b282ca96badb |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337171753 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.2337171753 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1857499737 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 5840443652 ps |
| CPU time | 956.71 seconds |
| Started | Feb 07 04:32:45 PM PST 24 |
| Finished | Feb 07 04:48:42 PM PST 24 |
| Peak memory | 602812 kb |
| Host | smart-586b56d9-68bc-40c9-9abb-c26f043928fc |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857499737 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.1857499737 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.2634749944 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 3035238498 ps |
| CPU time | 351.47 seconds |
| Started | Feb 07 04:37:24 PM PST 24 |
| Finished | Feb 07 04:43:16 PM PST 24 |
| Peak memory | 599740 kb |
| Host | smart-a8eab0b0-6569-4d05-8477-69454b1befb2 |
| User | root |
| Command | /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634749944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.2634749944 |
| Directory | /workspace/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_dpi.503014640 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 12380191112 ps |
| CPU time | 2728.56 seconds |
| Started | Feb 07 04:31:59 PM PST 24 |
| Finished | Feb 07 05:17:31 PM PST 24 |
| Peak memory | 599372 kb |
| Host | smart-7ef350dd-f23a-42c0-aa64-a5b5c45b67c9 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=503014640 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.503014640 |
| Directory | /workspace/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pullup.3127129249 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3380258114 ps |
| CPU time | 204.99 seconds |
| Started | Feb 07 04:31:37 PM PST 24 |
| Finished | Feb 07 04:35:05 PM PST 24 |
| Peak memory | 600420 kb |
| Host | smart-dc35ded2-0008-48bc-a6c0-ee5c080c89d2 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127129249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.3127129249 |
| Directory | /workspace/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_setuprx.311657643 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 4479689092 ps |
| CPU time | 526.48 seconds |
| Started | Feb 07 04:32:07 PM PST 24 |
| Finished | Feb 07 04:40:54 PM PST 24 |
| Peak memory | 599428 kb |
| Host | smart-2a9ffdec-6194-4252-9513-33023d5bca21 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311657643 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.311657643 |
| Directory | /workspace/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_stream.1834275170 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 18463776376 ps |
| CPU time | 4415.52 seconds |
| Started | Feb 07 04:32:41 PM PST 24 |
| Finished | Feb 07 05:46:18 PM PST 24 |
| Peak memory | 599344 kb |
| Host | smart-478ee0d8-630a-4b32-81b7-ce2764bd99d6 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=1834275170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.1834275170 |
| Directory | /workspace/0.chip_sw_usbdev_stream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_vbus.3181818978 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 2939730040 ps |
| CPU time | 276.89 seconds |
| Started | Feb 07 04:33:14 PM PST 24 |
| Finished | Feb 07 04:37:51 PM PST 24 |
| Peak memory | 600328 kb |
| Host | smart-7bcc5a77-cdf2-4c3c-8678-dd708db83d31 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181818978 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.3181818978 |
| Directory | /workspace/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_dev.1183910210 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 2980684858 ps |
| CPU time | 147.49 seconds |
| Started | Feb 07 04:35:46 PM PST 24 |
| Finished | Feb 07 04:38:14 PM PST 24 |
| Peak memory | 600864 kb |
| Host | smart-9b0fef67-5dad-4a00-a355-3e990ab70493 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1183910210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.1183910210 |
| Directory | /workspace/0.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_prod.3768037986 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 7042602601 ps |
| CPU time | 826.66 seconds |
| Started | Feb 07 04:36:01 PM PST 24 |
| Finished | Feb 07 04:49:49 PM PST 24 |
| Peak memory | 601748 kb |
| Host | smart-9565ca91-ce75-49e4-89be-b5283f77496f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768037986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.3768037986 |
| Directory | /workspace/0.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_rma.3055633483 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 3859984152 ps |
| CPU time | 272.53 seconds |
| Started | Feb 07 04:32:57 PM PST 24 |
| Finished | Feb 07 04:37:30 PM PST 24 |
| Peak memory | 602068 kb |
| Host | smart-23840e63-4ba7-40ea-ad57-316fece5eef7 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055633483 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.3055633483 |
| Directory | /workspace/0.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_testunlock0.2530812410 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 2860795720 ps |
| CPU time | 204.38 seconds |
| Started | Feb 07 04:35:47 PM PST 24 |
| Finished | Feb 07 04:39:13 PM PST 24 |
| Peak memory | 601524 kb |
| Host | smart-deda302d-ca9d-4df2-a7f1-819f1084b176 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2530812410 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.2530812410 |
| Directory | /workspace/0.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_dev.1719287040 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 9297030567 ps |
| CPU time | 2029.64 seconds |
| Started | Feb 07 04:41:13 PM PST 24 |
| Finished | Feb 07 05:15:04 PM PST 24 |
| Peak memory | 601104 kb |
| Host | smart-8a7d5500-3ee1-4275-809b-af5650ee1a4c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_dev:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719287040 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.rom_e2e_asm_init_dev.1719287040 |
| Directory | /workspace/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod.1575663320 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 8476368828 ps |
| CPU time | 2356.34 seconds |
| Started | Feb 07 04:42:00 PM PST 24 |
| Finished | Feb 07 05:21:19 PM PST 24 |
| Peak memory | 601396 kb |
| Host | smart-63870227-3941-4f3b-8468-c28624bdb8a4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_prod:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575663320 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.rom_e2e_asm_init_prod.1575663320 |
| Directory | /workspace/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.1261494893 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 8064661144 ps |
| CPU time | 2266.85 seconds |
| Started | Feb 07 04:39:11 PM PST 24 |
| Finished | Feb 07 05:16:59 PM PST 24 |
| Peak memory | 601384 kb |
| Host | smart-b42955f2-97e7-40d0-becb-8e36ab034163 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_prod_end:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261494893 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod_end.1261494893 |
| Directory | /workspace/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_rma.327553251 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 8541368625 ps |
| CPU time | 2065.94 seconds |
| Started | Feb 07 04:39:34 PM PST 24 |
| Finished | Feb 07 05:14:01 PM PST 24 |
| Peak memory | 601400 kb |
| Host | smart-56649608-e04d-426d-a6c1-7986708389e4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_rma:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327553251 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.rom_e2e_asm_init_rma.327553251 |
| Directory | /workspace/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.334006333 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 6749691744 ps |
| CPU time | 1523.97 seconds |
| Started | Feb 07 04:41:12 PM PST 24 |
| Finished | Feb 07 05:06:37 PM PST 24 |
| Peak memory | 600020 kb |
| Host | smart-81e83e8b-1d1f-4d95-8b45-de242901d67d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_ flash_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334006333 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_test_unlocked0.334006333 |
| Directory | /workspace/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.412992829 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 12218440056 ps |
| CPU time | 2917.31 seconds |
| Started | Feb 07 04:41:57 PM PST 24 |
| Finished | Feb 07 05:30:35 PM PST 24 |
| Peak memory | 599584 kb |
| Host | smart-6f1b3fcf-16f9-49c1-ad91-da2077b3b9e0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o t_flash_binary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_prod:4,rom_with _fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=412992829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.412992829 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1882657112 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 11772467030 ps |
| CPU time | 2793.15 seconds |
| Started | Feb 07 04:40:29 PM PST 24 |
| Finished | Feb 07 05:27:04 PM PST 24 |
| Peak memory | 602964 kb |
| Host | smart-2f1f563c-f73c-4435-8f9a-e88cbe83c71c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o t_flash_binary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,rom_ with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1882657112 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1882657112 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2211248691 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 12405797752 ps |
| CPU time | 2979.06 seconds |
| Started | Feb 07 04:42:01 PM PST 24 |
| Finished | Feb 07 05:31:42 PM PST 24 |
| Peak memory | 599592 kb |
| Host | smart-aa859af4-75ba-4047-a8ca-43f66d5f99d6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o t_flash_binary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_rma:4,rom_with_ fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211248691 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2211248691 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.981341947 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 10597629906 ps |
| CPU time | 2523.48 seconds |
| Started | Feb 07 04:42:47 PM PST 24 |
| Finished | Feb 07 05:24:51 PM PST 24 |
| Peak memory | 602804 kb |
| Host | smart-4eb59116-9375-440c-a248-4e225babd138 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0 :4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=981341947 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.981341947 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.4147921126 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 8879440200 ps |
| CPU time | 1965.67 seconds |
| Started | Feb 07 04:41:27 PM PST 24 |
| Finished | Feb 07 05:14:14 PM PST 24 |
| Peak memory | 602920 kb |
| Host | smart-deb03bd0-eefa-45e4-ad8f-d52f8e0de759 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bi nary:signed:fake_rsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_dev:4,rom_with_ fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147921126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.4147921126 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1806990965 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 8844389880 ps |
| CPU time | 2108.22 seconds |
| Started | Feb 07 04:42:03 PM PST 24 |
| Finished | Feb 07 05:17:13 PM PST 24 |
| Peak memory | 602924 kb |
| Host | smart-c7f4c36e-2bed-4b5c-af17-193dc33e3363 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bi nary:signed:fake_rsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_prod:4,rom_with _fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1806990965 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1806990965 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1470251692 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 8347644428 ps |
| CPU time | 2145.9 seconds |
| Started | Feb 07 04:41:45 PM PST 24 |
| Finished | Feb 07 05:17:32 PM PST 24 |
| Peak memory | 602976 kb |
| Host | smart-6b3c2784-4a9f-4765-9d0d-d438d5b21162 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bi nary:signed:fake_rsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,rom_ with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1470251692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1470251692 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2975631658 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 8438433086 ps |
| CPU time | 2008.5 seconds |
| Started | Feb 07 04:42:53 PM PST 24 |
| Finished | Feb 07 05:16:22 PM PST 24 |
| Peak memory | 599600 kb |
| Host | smart-1d488f9b-4f1a-427f-87a1-e5a6a4d71d7a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bi nary:signed:fake_rsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_rma:4,rom_with_ fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975631658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2975631658 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2827211311 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 6402350630 ps |
| CPU time | 1719.25 seconds |
| Started | Feb 07 04:41:58 PM PST 24 |
| Finished | Feb 07 05:10:41 PM PST 24 |
| Peak memory | 602808 kb |
| Host | smart-f0f19346-8e1c-43e9-ba0b-e7ebf16ef930 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_b inary:signed:fake_rsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0 :4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2827211311 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2827211311 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.821774865 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 9152383448 ps |
| CPU time | 2106.46 seconds |
| Started | Feb 07 04:40:33 PM PST 24 |
| Finished | Feb 07 05:15:41 PM PST 24 |
| Peak memory | 599676 kb |
| Host | smart-22d88325-dc09-4f74-b4b4-e56f153bfa35 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bi nary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_dev:4,rom_with_fake_keys: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=821774865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.821774865 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3416862256 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 8881595080 ps |
| CPU time | 2047.06 seconds |
| Started | Feb 07 04:40:43 PM PST 24 |
| Finished | Feb 07 05:14:51 PM PST 24 |
| Peak memory | 603052 kb |
| Host | smart-4a16c78a-45c9-4b0f-bb9d-a893eb1774b4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bi nary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_prod:4,rom_with_fake_keys :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3416862256 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3416862256 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2310809660 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 8641808282 ps |
| CPU time | 2125.03 seconds |
| Started | Feb 07 04:40:52 PM PST 24 |
| Finished | Feb 07 05:16:17 PM PST 24 |
| Peak memory | 603040 kb |
| Host | smart-670f6845-2894-4975-a009-e6d518625f12 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bi nary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,rom_with_fake_ keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2310809660 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2310809660 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.300092438 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 8803704492 ps |
| CPU time | 1969.75 seconds |
| Started | Feb 07 04:42:50 PM PST 24 |
| Finished | Feb 07 05:15:40 PM PST 24 |
| Peak memory | 603104 kb |
| Host | smart-628f59ee-3afb-4254-b681-acf453752c64 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bi nary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_rma:4,rom_with_fake_keys: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=300092438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.300092438 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1881831634 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 7160527848 ps |
| CPU time | 1834.85 seconds |
| Started | Feb 07 04:42:41 PM PST 24 |
| Finished | Feb 07 05:13:17 PM PST 24 |
| Peak memory | 599672 kb |
| Host | smart-601374fa-d3de-4426-a998-2e0ed6c7a59f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_b inary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4,rom_wit h_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1881831634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1881831634 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.2655265455 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 8670077108 ps |
| CPU time | 2184.19 seconds |
| Started | Feb 07 04:41:24 PM PST 24 |
| Finished | Feb 07 05:17:49 PM PST 24 |
| Peak memory | 599720 kb |
| Host | smart-a17c09c9-6243-44af-8859-45f4b5b85255 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:signed:fake_rsa_test_key_0,rom_ with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2655265455 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_exception_c_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_exception_c.2655265455 |
| Directory | /workspace/0.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_output.2095457117 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 24923954136 ps |
| CPU time | 3240.56 seconds |
| Started | Feb 07 04:40:42 PM PST 24 |
| Finished | Feb 07 05:34:43 PM PST 24 |
| Peak memory | 602616 kb |
| Host | smart-cdcc5e62-b5b8-4c2d-a5d2-19d11d312b52 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bina ry,otp_img_shutdown_output_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095457117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.rom_e2e_shutdown_output.2095457117 |
| Directory | /workspace/0.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1028227044 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 12069799316 ps |
| CPU time | 3037.19 seconds |
| Started | Feb 07 04:40:52 PM PST 24 |
| Finished | Feb 07 05:31:30 PM PST 24 |
| Peak memory | 600904 kb |
| Host | smart-5e9e29a4-88ce-4346-9a88-75660192ed8e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o t_flash_binary:signed:fake_rsa_dev_key_0:new_rules,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_dev_key_0:new_rules,otp_img_sigve rify_always_dev:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028227044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_al ways_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_s igverify_always_a_bad_b_bad_dev.1028227044 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.2377743325 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 11873661393 ps |
| CPU time | 2804.06 seconds |
| Started | Feb 07 04:42:08 PM PST 24 |
| Finished | Feb 07 05:28:55 PM PST 24 |
| Peak memory | 600708 kb |
| Host | smart-b114e515-efcb-402a-b59f-4fca340f47b6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o t_flash_binary:signed:fake_rsa_prod_key_0:new_rules,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0:new_rules,otp_img_sig verify_always_prod:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377743325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify _always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2 e_sigverify_always_a_bad_b_bad_prod.2377743325 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.496902779 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 11427458560 ps |
| CPU time | 3216.23 seconds |
| Started | Feb 07 04:42:27 PM PST 24 |
| Finished | Feb 07 05:36:04 PM PST 24 |
| Peak memory | 602364 kb |
| Host | smart-4deabd78-b289-4ff8-a112-16033bc952d9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o t_flash_binary:signed:fake_rsa_prod_key_0:new_rules,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0:new_rules,otp_img_sig verify_always_prod_end:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496902779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigver ify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom _e2e_sigverify_always_a_bad_b_bad_prod_end.496902779 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3087552065 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 12040592682 ps |
| CPU time | 3385.62 seconds |
| Started | Feb 07 04:40:06 PM PST 24 |
| Finished | Feb 07 05:36:33 PM PST 24 |
| Peak memory | 600888 kb |
| Host | smart-48ba17ab-1748-4c78-91fb-4f0a124392a7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o t_flash_binary:signed:fake_rsa_prod_key_0:new_rules,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0:new_rules,otp_img_sig verify_always_rma:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087552065 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_ always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e _sigverify_always_a_bad_b_bad_rma.3087552065 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1255611229 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 10185963513 ps |
| CPU time | 2729.77 seconds |
| Started | Feb 07 04:43:05 PM PST 24 |
| Finished | Feb 07 05:28:36 PM PST 24 |
| Peak memory | 602280 kb |
| Host | smart-4c9992b9-7b79-4d19-9d52-e2ce7cfd7434 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_rsa_test_key_0:new_rules,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_test_key_0:new_rules,otp_img_si gverify_always_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255611229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2 e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1255611229 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2151938222 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 9002980684 ps |
| CPU time | 2298.11 seconds |
| Started | Feb 07 04:42:26 PM PST 24 |
| Finished | Feb 07 05:20:44 PM PST 24 |
| Peak memory | 602036 kb |
| Host | smart-a0903040-9c97-4e26-b480-9e1663bf304e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o t_flash_binary:signed:fake_rsa_dev_key_0:new_rules,otp_img_sigverify_always_dev:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151938222 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2151938222 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2918686833 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 8679611891 ps |
| CPU time | 1910.78 seconds |
| Started | Feb 07 04:40:27 PM PST 24 |
| Finished | Feb 07 05:12:21 PM PST 24 |
| Peak memory | 601956 kb |
| Host | smart-7e581c6f-4e47-455c-9ed5-e19a54ba2453 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o t_flash_binary:signed:fake_rsa_prod_key_0:new_rules,otp_img_sigverify_always_prod:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918686833 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2918686833 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1088947905 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 9036683552 ps |
| CPU time | 2390.33 seconds |
| Started | Feb 07 04:41:59 PM PST 24 |
| Finished | Feb 07 05:21:53 PM PST 24 |
| Peak memory | 601836 kb |
| Host | smart-226f0f8f-7c2e-4a5f-88de-cb1a9fb8b9a2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o t_flash_binary:signed:fake_rsa_prod_key_0:new_rules,otp_img_sigverify_always_prod_end:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088947905 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1088947905 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.189882900 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 8537705559 ps |
| CPU time | 1978.23 seconds |
| Started | Feb 07 04:40:25 PM PST 24 |
| Finished | Feb 07 05:13:26 PM PST 24 |
| Peak memory | 602020 kb |
| Host | smart-faa27406-09b4-4a9f-bb8a-5c7089d6e292 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o t_flash_binary:signed:fake_rsa_prod_key_0:new_rules,otp_img_sigverify_always_rma:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189882900 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.189882900 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.221974546 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 7146591075 ps |
| CPU time | 1531.03 seconds |
| Started | Feb 07 04:38:55 PM PST 24 |
| Finished | Feb 07 05:04:27 PM PST 24 |
| Peak memory | 602496 kb |
| Host | smart-ca33cc87-8eb5-4007-9d91-d6c40b8e94d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_rsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221974546 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.221974546 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1051373890 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 8536083009 ps |
| CPU time | 2324.34 seconds |
| Started | Feb 07 04:41:51 PM PST 24 |
| Finished | Feb 07 05:20:38 PM PST 24 |
| Peak memory | 599656 kb |
| Host | smart-402dd46b-0cb8-474e-b093-8965f036d63c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:o t_flash_binary:signed:fake_rsa_dev_key_0:new_rules,otp_img_sigverify_always_dev:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051373890 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1051373890 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3465877385 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 9126736520 ps |
| CPU time | 1892.08 seconds |
| Started | Feb 07 04:40:38 PM PST 24 |
| Finished | Feb 07 05:12:11 PM PST 24 |
| Peak memory | 602272 kb |
| Host | smart-5b742cb4-975d-4624-9cac-fbd1867862aa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:o t_flash_binary:signed:fake_rsa_prod_key_0:new_rules,otp_img_sigverify_always_prod:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465877385 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3465877385 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.172115164 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 9066794423 ps |
| CPU time | 2044.14 seconds |
| Started | Feb 07 04:41:02 PM PST 24 |
| Finished | Feb 07 05:15:07 PM PST 24 |
| Peak memory | 602260 kb |
| Host | smart-fa8b0f6e-8ef4-461e-ba56-74879c95275b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:o t_flash_binary:signed:fake_rsa_prod_key_0:new_rules,otp_img_sigverify_always_prod_end:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172115164 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.172115164 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1119251082 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 8307464892 ps |
| CPU time | 2189.13 seconds |
| Started | Feb 07 04:40:28 PM PST 24 |
| Finished | Feb 07 05:17:00 PM PST 24 |
| Peak memory | 600112 kb |
| Host | smart-c1705344-d3af-4193-9468-46e1c6679ceb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:o t_flash_binary:signed:fake_rsa_prod_key_0:new_rules,otp_img_sigverify_always_rma:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119251082 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1119251082 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2943320769 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 6933920111 ps |
| CPU time | 1621.26 seconds |
| Started | Feb 07 04:41:40 PM PST 24 |
| Finished | Feb 07 05:08:42 PM PST 24 |
| Peak memory | 602372 kb |
| Host | smart-e439c2dc-a5a2-4daa-8d52-76c0d714dc20 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_rsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943320769 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2943320769 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_smoke.1507088189 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 8885539008 ps |
| CPU time | 2435.35 seconds |
| Started | Feb 07 04:36:07 PM PST 24 |
| Finished | Feb 07 05:16:44 PM PST 24 |
| Peak memory | 599636 kb |
| Host | smart-c7f909c4-ef50-4a5f-b49b-6c8664959e96 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_binary:signed:fake_rsa_test_key_0 ,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1507088189 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.1507088189 |
| Directory | /workspace/0.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_static_critical.1171470826 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 10789619370 ps |
| CPU time | 2453.49 seconds |
| Started | Feb 07 04:41:12 PM PST 24 |
| Finished | Feb 07 05:22:06 PM PST 24 |
| Peak memory | 599632 kb |
| Host | smart-c165295a-59f7-4c71-a048-f7aca6042555 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:signed:fake_rsa_test_key_0,rom_with_ fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171470826 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.1171470826 |
| Directory | /workspace/0.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/0.rom_keymgr_functest.3993964524 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 4703004440 ps |
| CPU time | 501.45 seconds |
| Started | Feb 07 04:36:19 PM PST 24 |
| Finished | Feb 07 04:44:40 PM PST 24 |
| Peak memory | 600176 kb |
| Host | smart-0951d57b-da32-48c6-8625-9782292b0831 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993964524 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.3993964524 |
| Directory | /workspace/0.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/0.rom_volatile_raw_unlock.429691541 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 12856576600 ps |
| CPU time | 2087.78 seconds |
| Started | Feb 07 04:37:08 PM PST 24 |
| Finished | Feb 07 05:11:57 PM PST 24 |
| Peak memory | 607068 kb |
| Host | smart-1916841b-4a6d-45fb-bcae-26aa84b273fb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:fake_rsa_test_key_0:ot_flash_binary,rom_with_fake_keys:0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429691541 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.429691541 |
| Directory | /workspace/0.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_mem_access.3899304612 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 13784820770 ps |
| CPU time | 1532.58 seconds |
| Started | Feb 07 04:36:55 PM PST 24 |
| Finished | Feb 07 05:02:29 PM PST 24 |
| Peak memory | 593148 kb |
| Host | smart-487ec2f7-fc23-480f-9d25-89046ccdf2a0 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899304612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.3 899304612 |
| Directory | /workspace/1.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2675597273 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5227472446 ps |
| CPU time | 486.24 seconds |
| Started | Feb 07 04:45:12 PM PST 24 |
| Finished | Feb 07 04:53:20 PM PST 24 |
| Peak memory | 616836 kb |
| Host | smart-f1b09f25-3209-491c-9c07-13fb1c513524 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2 675597273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.2675597273 |
| Directory | /workspace/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sival_flash_info_access.1260249548 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 4202285419 ps |
| CPU time | 518.82 seconds |
| Started | Feb 07 04:37:38 PM PST 24 |
| Finished | Feb 07 04:46:17 PM PST 24 |
| Peak memory | 600656 kb |
| Host | smart-406dba2c-6ca0-4b4e-9020-a88c2c829063 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1260249548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.1260249548 |
| Directory | /workspace/1.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3807882198 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 18878285064 ps |
| CPU time | 559.74 seconds |
| Started | Feb 07 04:42:27 PM PST 24 |
| Finished | Feb 07 04:51:47 PM PST 24 |
| Peak memory | 606044 kb |
| Host | smart-c47ceb64-ba72-403b-82a4-e0a555b60cd3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3807882198 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3807882198 |
| Directory | /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc.2370366159 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 2401800520 ps |
| CPU time | 196.38 seconds |
| Started | Feb 07 04:39:50 PM PST 24 |
| Finished | Feb 07 04:43:06 PM PST 24 |
| Peak memory | 600508 kb |
| Host | smart-6fb0efe5-5d4a-474e-9c72-7e2e4a9bea82 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370366159 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.2370366159 |
| Directory | /workspace/1.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.4106017836 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 2583409387 ps |
| CPU time | 195.13 seconds |
| Started | Feb 07 04:40:27 PM PST 24 |
| Finished | Feb 07 04:43:45 PM PST 24 |
| Peak memory | 599160 kb |
| Host | smart-23ce7bb5-79e2-4620-9ca9-177916436448 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106 017836 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.4106017836 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2251173716 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 2541572136 ps |
| CPU time | 264.05 seconds |
| Started | Feb 07 04:46:11 PM PST 24 |
| Finished | Feb 07 04:50:36 PM PST 24 |
| Peak memory | 600456 kb |
| Host | smart-d1e9061a-2c65-4257-9ffc-440c12abfd18 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251173716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.2251173716 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_entropy.1546393220 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 2456796728 ps |
| CPU time | 272.93 seconds |
| Started | Feb 07 04:40:24 PM PST 24 |
| Finished | Feb 07 04:44:59 PM PST 24 |
| Peak memory | 600436 kb |
| Host | smart-1cf35173-0207-437b-a949-b6548ed170bb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546393220 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.1546393220 |
| Directory | /workspace/1.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_idle.3828242535 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 2745269728 ps |
| CPU time | 186.11 seconds |
| Started | Feb 07 04:41:57 PM PST 24 |
| Finished | Feb 07 04:45:04 PM PST 24 |
| Peak memory | 600460 kb |
| Host | smart-c798681b-690c-44bf-85a5-ffdabbcd7b43 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828242535 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.3828242535 |
| Directory | /workspace/1.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_masking_off.2242145225 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 2921363839 ps |
| CPU time | 374.55 seconds |
| Started | Feb 07 04:42:02 PM PST 24 |
| Finished | Feb 07 04:48:17 PM PST 24 |
| Peak memory | 601060 kb |
| Host | smart-ec49add8-269f-4402-b40f-d84a5d81e573 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242145225 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.2242145225 |
| Directory | /workspace/1.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_smoketest.2062258208 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 2748089160 ps |
| CPU time | 289.91 seconds |
| Started | Feb 07 04:47:22 PM PST 24 |
| Finished | Feb 07 04:52:12 PM PST 24 |
| Peak memory | 599120 kb |
| Host | smart-fd0d3593-d18d-4712-96af-59976b06b56d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062258208 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.2062258208 |
| Directory | /workspace/1.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_entropy.102204652 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 2787331831 ps |
| CPU time | 268.31 seconds |
| Started | Feb 07 04:40:02 PM PST 24 |
| Finished | Feb 07 04:44:32 PM PST 24 |
| Peak memory | 598928 kb |
| Host | smart-434f60c5-7294-4b9d-be41-644d53cd05c4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=102204652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.102204652 |
| Directory | /workspace/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_escalation.1972593058 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 4665780564 ps |
| CPU time | 708.71 seconds |
| Started | Feb 07 04:41:15 PM PST 24 |
| Finished | Feb 07 04:53:05 PM PST 24 |
| Peak memory | 607972 kb |
| Host | smart-6dd8ac82-9775-4921-a9ca-ed748688ece7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1972593058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.1972593058 |
| Directory | /workspace/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.879012427 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 6552989994 ps |
| CPU time | 1613.2 seconds |
| Started | Feb 07 04:41:30 PM PST 24 |
| Finished | Feb 07 05:08:24 PM PST 24 |
| Peak memory | 601916 kb |
| Host | smart-7cf9776a-efb8-48ad-b6fd-118f9f0bc454 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=879012427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.879012427 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3076252615 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 6959190624 ps |
| CPU time | 1520.74 seconds |
| Started | Feb 07 04:41:57 PM PST 24 |
| Finished | Feb 07 05:07:19 PM PST 24 |
| Peak memory | 601864 kb |
| Host | smart-017b1299-a1cf-400b-bd50-0760d6af207a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076252615 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_togg le.3076252615 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.3988983347 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 3506824420 ps |
| CPU time | 401.4 seconds |
| Started | Feb 07 04:41:20 PM PST 24 |
| Finished | Feb 07 04:48:02 PM PST 24 |
| Peak memory | 599140 kb |
| Host | smart-0ea645d3-b7cf-494c-b278-fc001593ef71 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3988983347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.3988983347 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.471328120 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 255792636064 ps |
| CPU time | 11447.9 seconds |
| Started | Feb 07 04:41:14 PM PST 24 |
| Finished | Feb 07 07:52:04 PM PST 24 |
| Peak memory | 602568 kb |
| Host | smart-56eb468a-b0bf-4c44-9695-683b5ff8ef34 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=471328120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.471328120 |
| Directory | /workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_test.2118933278 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3220427836 ps |
| CPU time | 334.69 seconds |
| Started | Feb 07 04:41:07 PM PST 24 |
| Finished | Feb 07 04:46:42 PM PST 24 |
| Peak memory | 600788 kb |
| Host | smart-4be208f6-fc55-4c8d-9011-bcadaaa381aa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118933278 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_alert_test.2118933278 |
| Directory | /workspace/1.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_irq.3048837087 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 3615903496 ps |
| CPU time | 422.18 seconds |
| Started | Feb 07 04:40:06 PM PST 24 |
| Finished | Feb 07 04:47:10 PM PST 24 |
| Peak memory | 599200 kb |
| Host | smart-afc0a3c2-9043-4025-9515-6149575e9dab |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048837087 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.3048837087 |
| Directory | /workspace/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3333550094 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 6588712400 ps |
| CPU time | 528.48 seconds |
| Started | Feb 07 04:40:30 PM PST 24 |
| Finished | Feb 07 04:49:20 PM PST 24 |
| Peak memory | 601328 kb |
| Host | smart-6ec5defe-eb90-4229-8e2b-b902904b4275 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3333550094 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3333550094 |
| Directory | /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.967040385 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 3577929980 ps |
| CPU time | 359.77 seconds |
| Started | Feb 07 04:46:29 PM PST 24 |
| Finished | Feb 07 04:52:30 PM PST 24 |
| Peak memory | 600560 kb |
| Host | smart-75a734bc-bc24-46f9-9e38-5e9baee9aa9c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967040385 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_aon_timer_smoketest.967040385 |
| Directory | /workspace/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.843562726 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 7384481828 ps |
| CPU time | 1021.2 seconds |
| Started | Feb 07 04:41:59 PM PST 24 |
| Finished | Feb 07 04:59:04 PM PST 24 |
| Peak memory | 601380 kb |
| Host | smart-59472bfd-4fa1-405a-8f74-35db0d5b2a04 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 843562726 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.843562726 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2164681955 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 5008050128 ps |
| CPU time | 783.98 seconds |
| Started | Feb 07 04:40:45 PM PST 24 |
| Finished | Feb 07 04:53:50 PM PST 24 |
| Peak memory | 601456 kb |
| Host | smart-ab62c009-0d0a-4fe3-979c-5613963ba805 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2164681955 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.2164681955 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_outputs.3518274817 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 7982777948 ps |
| CPU time | 1095.65 seconds |
| Started | Feb 07 04:43:49 PM PST 24 |
| Finished | Feb 07 05:02:07 PM PST 24 |
| Peak memory | 607880 kb |
| Host | smart-25455f75-fba3-43da-b3c0-3678ca8cf32a |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518274817 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.3518274817 |
| Directory | /workspace/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2350563702 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 4451102824 ps |
| CPU time | 638.46 seconds |
| Started | Feb 07 04:43:50 PM PST 24 |
| Finished | Feb 07 04:54:30 PM PST 24 |
| Peak memory | 594760 kb |
| Host | smart-ac27ce51-2b92-465e-86ba-20ecc9d8c32b |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350563702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.2350563702 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.4010814592 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 4022210872 ps |
| CPU time | 792.99 seconds |
| Started | Feb 07 04:43:32 PM PST 24 |
| Finished | Feb 07 04:56:46 PM PST 24 |
| Peak memory | 594584 kb |
| Host | smart-1831ab28-58a5-4133-92fa-7172c7da4049 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010814592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.4010814592 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4218400131 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 3706175442 ps |
| CPU time | 650.1 seconds |
| Started | Feb 07 04:44:09 PM PST 24 |
| Finished | Feb 07 04:55:00 PM PST 24 |
| Peak memory | 594832 kb |
| Host | smart-b049bf3a-9dfb-4d2d-a35f-3959a094d7f2 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218400131 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4218400131 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3366456005 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 4318835888 ps |
| CPU time | 585.66 seconds |
| Started | Feb 07 04:44:14 PM PST 24 |
| Finished | Feb 07 04:54:00 PM PST 24 |
| Peak memory | 594744 kb |
| Host | smart-cd346a37-1bcd-4204-ab1e-3acbdfe94720 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366456005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.3366456005 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1375801040 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 4692996304 ps |
| CPU time | 801.07 seconds |
| Started | Feb 07 04:43:10 PM PST 24 |
| Finished | Feb 07 04:56:31 PM PST 24 |
| Peak memory | 594812 kb |
| Host | smart-ea237c15-e8a7-47b4-afe1-c68387bc7ef3 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375801040 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.1375801040 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.867919772 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 4993621068 ps |
| CPU time | 850.93 seconds |
| Started | Feb 07 04:43:53 PM PST 24 |
| Finished | Feb 07 04:58:06 PM PST 24 |
| Peak memory | 594568 kb |
| Host | smart-e3dd2d2b-90ea-48ce-aaa5-ab3b0b0d9d93 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867919772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.867919772 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter.4086903304 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 2141379073 ps |
| CPU time | 204.05 seconds |
| Started | Feb 07 04:45:28 PM PST 24 |
| Finished | Feb 07 04:48:56 PM PST 24 |
| Peak memory | 600468 kb |
| Host | smart-791eada2-3de1-4b88-93ce-961f03fb28b3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086903304 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_clkmgr_jitter.4086903304 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1446568244 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 2747202040 ps |
| CPU time | 472.61 seconds |
| Started | Feb 07 04:43:15 PM PST 24 |
| Finished | Feb 07 04:51:08 PM PST 24 |
| Peak memory | 600560 kb |
| Host | smart-7a0eda68-923c-49b5-9c8d-1dfee65d6ce0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446568244 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.1446568244 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1709882829 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 3349104373 ps |
| CPU time | 253.78 seconds |
| Started | Feb 07 04:45:08 PM PST 24 |
| Finished | Feb 07 04:49:23 PM PST 24 |
| Peak memory | 599132 kb |
| Host | smart-db58cf76-a60c-42a6-9818-32af207104e5 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709882829 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.1709882829 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3904302574 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 5146144620 ps |
| CPU time | 421.14 seconds |
| Started | Feb 07 04:44:21 PM PST 24 |
| Finished | Feb 07 04:51:22 PM PST 24 |
| Peak memory | 601256 kb |
| Host | smart-f6748118-e208-4da6-bbaf-6791c55ce515 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904302574 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.3904302574 |
| Directory | /workspace/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3662891741 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 4494019718 ps |
| CPU time | 559.1 seconds |
| Started | Feb 07 04:44:52 PM PST 24 |
| Finished | Feb 07 04:54:11 PM PST 24 |
| Peak memory | 601280 kb |
| Host | smart-25ef4850-5343-4259-b983-c954bcf43ec7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662891741 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.3662891741 |
| Directory | /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2411277007 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 4312974400 ps |
| CPU time | 421.71 seconds |
| Started | Feb 07 04:44:10 PM PST 24 |
| Finished | Feb 07 04:51:12 PM PST 24 |
| Peak memory | 601264 kb |
| Host | smart-935ba868-e32b-48c7-9fd7-d2b5ee21d0d4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411277007 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.2411277007 |
| Directory | /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2066424645 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 4341973770 ps |
| CPU time | 662.45 seconds |
| Started | Feb 07 04:43:22 PM PST 24 |
| Finished | Feb 07 04:54:25 PM PST 24 |
| Peak memory | 601288 kb |
| Host | smart-af41bdfa-a826-435c-9e0a-c42228262bf4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066424645 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.2066424645 |
| Directory | /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.1621584615 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 10974906680 ps |
| CPU time | 1275.4 seconds |
| Started | Feb 07 04:43:47 PM PST 24 |
| Finished | Feb 07 05:05:07 PM PST 24 |
| Peak memory | 601384 kb |
| Host | smart-a46c6626-70d7-4fc9-a2f9-3f52e046ce79 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621584615 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.1621584615 |
| Directory | /workspace/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1723802421 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 3144467124 ps |
| CPU time | 416.76 seconds |
| Started | Feb 07 04:44:19 PM PST 24 |
| Finished | Feb 07 04:51:17 PM PST 24 |
| Peak memory | 600480 kb |
| Host | smart-1159354e-d3b2-49bc-a890-d9b6f7ac1705 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723802421 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.1723802421 |
| Directory | /workspace/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3191546643 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 5107246710 ps |
| CPU time | 663.44 seconds |
| Started | Feb 07 04:43:10 PM PST 24 |
| Finished | Feb 07 04:54:14 PM PST 24 |
| Peak memory | 601004 kb |
| Host | smart-496a3906-19b2-4012-868c-4d9223daa4d5 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191546643 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.3191546643 |
| Directory | /workspace/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.4107966763 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 2677981500 ps |
| CPU time | 318.66 seconds |
| Started | Feb 07 04:47:10 PM PST 24 |
| Finished | Feb 07 04:52:31 PM PST 24 |
| Peak memory | 600544 kb |
| Host | smart-d9fba916-ffbd-4e54-b371-30a6e19e3846 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107966763 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_clkmgr_smoketest.4107966763 |
| Directory | /workspace/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.363912768 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 15995780720 ps |
| CPU time | 4120.89 seconds |
| Started | Feb 07 04:41:17 PM PST 24 |
| Finished | Feb 07 05:49:59 PM PST 24 |
| Peak memory | 601108 kb |
| Host | smart-956d7c13-116c-4eb1-b295-b576fa6d764e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363912768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.363912768 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3383535710 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 10769670113 ps |
| CPU time | 1794.84 seconds |
| Started | Feb 07 04:45:56 PM PST 24 |
| Finished | Feb 07 05:15:52 PM PST 24 |
| Peak memory | 601088 kb |
| Host | smart-632a6831-4a83-4583-b3de-fbe305303ef6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=180_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383535710 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _csrng_edn_concurrency_reduced_freq.3383535710 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.3514878867 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 5582151064 ps |
| CPU time | 530.03 seconds |
| Started | Feb 07 04:41:02 PM PST 24 |
| Finished | Feb 07 04:49:52 PM PST 24 |
| Peak memory | 601640 kb |
| Host | smart-71504e19-6e4d-41ce-b034-76745fad7063 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35148 78867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.3514878867 |
| Directory | /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_kat_test.2588243525 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 3156555808 ps |
| CPU time | 374.08 seconds |
| Started | Feb 07 04:42:11 PM PST 24 |
| Finished | Feb 07 04:48:27 PM PST 24 |
| Peak memory | 599192 kb |
| Host | smart-850527d6-6b34-43d4-842e-6f79833702b2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588243525 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.2588243525 |
| Directory | /workspace/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.959106378 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 11643556269 ps |
| CPU time | 869.35 seconds |
| Started | Feb 07 04:41:16 PM PST 24 |
| Finished | Feb 07 04:55:46 PM PST 24 |
| Peak memory | 602160 kb |
| Host | smart-c08e7789-c97c-4bba-9e92-648d0a915a91 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959106378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_l c_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrn g_lc_hw_debug_en_test.959106378 |
| Directory | /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_smoketest.3254880774 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 2950778700 ps |
| CPU time | 296.32 seconds |
| Started | Feb 07 04:46:35 PM PST 24 |
| Finished | Feb 07 04:51:32 PM PST 24 |
| Peak memory | 599100 kb |
| Host | smart-70ee81df-642f-4000-8deb-0e1436f59719 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254880774 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_csrng_smoketest.3254880774 |
| Directory | /workspace/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_auto_mode.1014329044 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 5383914642 ps |
| CPU time | 1212.23 seconds |
| Started | Feb 07 04:41:25 PM PST 24 |
| Finished | Feb 07 05:01:38 PM PST 24 |
| Peak memory | 601000 kb |
| Host | smart-d3685a9a-79c8-4362-8fcb-f0ca7831adde |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014329044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ auto_mode.1014329044 |
| Directory | /workspace/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_boot_mode.733385840 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 2520733282 ps |
| CPU time | 546.76 seconds |
| Started | Feb 07 04:40:30 PM PST 24 |
| Finished | Feb 07 04:49:38 PM PST 24 |
| Peak memory | 600688 kb |
| Host | smart-6abe9064-2892-4f3d-be68-9470ecec75fb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733385840 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_b oot_mode.733385840 |
| Directory | /workspace/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.232144878 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 5762048290 ps |
| CPU time | 1350.4 seconds |
| Started | Feb 07 04:42:09 PM PST 24 |
| Finished | Feb 07 05:04:41 PM PST 24 |
| Peak memory | 601216 kb |
| Host | smart-955271e9-cac1-47a3-a8dd-aea6d4c4a2d6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=232144878 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.232144878 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1669338632 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 5766563244 ps |
| CPU time | 1084.42 seconds |
| Started | Feb 07 04:40:57 PM PST 24 |
| Finished | Feb 07 04:59:02 PM PST 24 |
| Peak memory | 601164 kb |
| Host | smart-e7790c9a-5c1c-4782-929f-4648d6e7512c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669338632 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.1669338632 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_kat.1821212426 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 3628960260 ps |
| CPU time | 688.52 seconds |
| Started | Feb 07 04:41:51 PM PST 24 |
| Finished | Feb 07 04:53:20 PM PST 24 |
| Peak memory | 605640 kb |
| Host | smart-1ad3564e-d691-4022-8ef9-810fb6058e3d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821212426 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_edn_kat.1821212426 |
| Directory | /workspace/1.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_sw_mode.4151711463 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 6780963998 ps |
| CPU time | 1313.2 seconds |
| Started | Feb 07 04:40:59 PM PST 24 |
| Finished | Feb 07 05:02:52 PM PST 24 |
| Peak memory | 600844 kb |
| Host | smart-780083c3-0030-4754-b201-ad365a5a65e8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151711463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.4151711463 |
| Directory | /workspace/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3184346441 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 2438308736 ps |
| CPU time | 289.75 seconds |
| Started | Feb 07 04:42:08 PM PST 24 |
| Finished | Feb 07 04:47:00 PM PST 24 |
| Peak memory | 599080 kb |
| Host | smart-6c7b600f-d1fd-4ac3-b5c9-e0e5dfe0fd19 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31 84346441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.3184346441 |
| Directory | /workspace/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2334437388 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 3026412104 ps |
| CPU time | 162 seconds |
| Started | Feb 07 04:41:59 PM PST 24 |
| Finished | Feb 07 04:44:44 PM PST 24 |
| Peak memory | 600488 kb |
| Host | smart-2c0f161d-8602-4a6c-a6c5-948a91155696 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334437388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.2334437388 |
| Directory | /workspace/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.461168257 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 3993494096 ps |
| CPU time | 689.53 seconds |
| Started | Feb 07 04:46:40 PM PST 24 |
| Finished | Feb 07 04:58:10 PM PST 24 |
| Peak memory | 599152 kb |
| Host | smart-8d58d439-89bc-430d-919d-4dafb099955f |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=461168257 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.461168257 |
| Directory | /workspace/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_concurrency.755496388 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 3014376594 ps |
| CPU time | 235.21 seconds |
| Started | Feb 07 04:37:08 PM PST 24 |
| Finished | Feb 07 04:41:04 PM PST 24 |
| Peak memory | 599096 kb |
| Host | smart-4ec67c21-cb1e-41bf-a4d0-ab3e8616ee89 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755496388 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_concurrency.755496388 |
| Directory | /workspace/1.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_flash.2898331148 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 2795636564 ps |
| CPU time | 305.26 seconds |
| Started | Feb 07 04:40:11 PM PST 24 |
| Finished | Feb 07 04:45:17 PM PST 24 |
| Peak memory | 600512 kb |
| Host | smart-cc992075-1b69-41ed-8412-52caaf6817c6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898331148 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.2898331148 |
| Directory | /workspace/1.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_manufacturer.545962943 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 3031357670 ps |
| CPU time | 260.79 seconds |
| Started | Feb 07 04:39:38 PM PST 24 |
| Finished | Feb 07 04:43:59 PM PST 24 |
| Peak memory | 600436 kb |
| Host | smart-667a6310-76a8-4504-80cc-36b801a755db |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545962943 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.chip_sw_example_manufacturer.545962943 |
| Directory | /workspace/1.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_rom.3568570531 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 1910590924 ps |
| CPU time | 128.65 seconds |
| Started | Feb 07 04:36:39 PM PST 24 |
| Finished | Feb 07 04:38:49 PM PST 24 |
| Peak memory | 598984 kb |
| Host | smart-ebedac1b-f1f8-4d64-a12a-202517cb3942 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568570531 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_rom.3568570531 |
| Directory | /workspace/1.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_crash_alert.2251405591 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 5195877954 ps |
| CPU time | 732.85 seconds |
| Started | Feb 07 04:45:01 PM PST 24 |
| Finished | Feb 07 04:57:14 PM PST 24 |
| Peak memory | 600988 kb |
| Host | smart-6473b4fe-a57f-4a3e-a1ef-b28192f519b6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=2251405591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.2251405591 |
| Directory | /workspace/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access.1195381910 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 5450400484 ps |
| CPU time | 994.5 seconds |
| Started | Feb 07 04:38:52 PM PST 24 |
| Finished | Feb 07 04:55:27 PM PST 24 |
| Peak memory | 599480 kb |
| Host | smart-e11dfd85-18bb-43bd-8207-e0b93daf8398 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195381910 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_flash_ctrl_access.1195381910 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.3170926296 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 5695206242 ps |
| CPU time | 774.11 seconds |
| Started | Feb 07 04:38:38 PM PST 24 |
| Finished | Feb 07 04:51:34 PM PST 24 |
| Peak memory | 600844 kb |
| Host | smart-83d8dd4f-6e05-47e3-8a5e-503abfbfcba4 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170926296 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.3170926296 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3570482305 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 7486931420 ps |
| CPU time | 1192.11 seconds |
| Started | Feb 07 04:46:23 PM PST 24 |
| Finished | Feb 07 05:06:16 PM PST 24 |
| Peak memory | 600876 kb |
| Host | smart-884e25cd-40cf-451f-89ae-b40c2e1b2a84 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570482305 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3570482305 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.1513128175 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 5661293511 ps |
| CPU time | 1235.35 seconds |
| Started | Feb 07 04:38:24 PM PST 24 |
| Finished | Feb 07 04:59:02 PM PST 24 |
| Peak memory | 599472 kb |
| Host | smart-7b4e0334-1ad0-4151-9791-11a738e38779 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513128175 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.1513128175 |
| Directory | /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.4148239797 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 3677708540 ps |
| CPU time | 412.17 seconds |
| Started | Feb 07 04:38:06 PM PST 24 |
| Finished | Feb 07 04:44:59 PM PST 24 |
| Peak memory | 600616 kb |
| Host | smart-f52a11eb-2c15-4e6b-923b-d8b0cad38598 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148239797 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.4148239797 |
| Directory | /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2469404371 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 5504903008 ps |
| CPU time | 1131.25 seconds |
| Started | Feb 07 04:45:39 PM PST 24 |
| Finished | Feb 07 05:04:31 PM PST 24 |
| Peak memory | 599468 kb |
| Host | smart-624d824b-9191-4073-adb6-fe0c39ba9358 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469404371 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.2469404371 |
| Directory | /workspace/1.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2935322345 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 4399060040 ps |
| CPU time | 1165.57 seconds |
| Started | Feb 07 04:38:53 PM PST 24 |
| Finished | Feb 07 04:58:20 PM PST 24 |
| Peak memory | 599580 kb |
| Host | smart-0aebcfaf-d39f-433f-bb23-ef771b515cae |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935322345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.2935322345 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.426208458 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 5031401427 ps |
| CPU time | 828.14 seconds |
| Started | Feb 07 04:38:42 PM PST 24 |
| Finished | Feb 07 04:52:31 PM PST 24 |
| Peak memory | 599584 kb |
| Host | smart-742009a0-409d-4865-9a93-20879b192573 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=426208458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.426208458 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3201278691 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 5206235634 ps |
| CPU time | 1039.29 seconds |
| Started | Feb 07 04:46:18 PM PST 24 |
| Finished | Feb 07 05:03:38 PM PST 24 |
| Peak memory | 600936 kb |
| Host | smart-d2b3241f-53ed-4daa-b30b-0fcf660108f6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3201278691 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3201278691 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.4236909071 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 3208285300 ps |
| CPU time | 304.78 seconds |
| Started | Feb 07 04:49:58 PM PST 24 |
| Finished | Feb 07 04:55:03 PM PST 24 |
| Peak memory | 599508 kb |
| Host | smart-13304570-391d-4564-bf53-debf82db156c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4236909071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.4236909071 |
| Directory | /workspace/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio.3153708747 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 3743974056 ps |
| CPU time | 433.8 seconds |
| Started | Feb 07 04:38:46 PM PST 24 |
| Finished | Feb 07 04:46:01 PM PST 24 |
| Peak memory | 600852 kb |
| Host | smart-875029bd-3215-4efb-8d6b-997fc2b03e71 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153708747 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_gpio.3153708747 |
| Directory | /workspace/1.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio_smoketest.258582281 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 2902461583 ps |
| CPU time | 244.06 seconds |
| Started | Feb 07 04:48:52 PM PST 24 |
| Finished | Feb 07 04:52:58 PM PST 24 |
| Peak memory | 600512 kb |
| Host | smart-53437399-5e20-4c17-b2d9-3314521af514 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258582281 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_gpio_smoketest.258582281 |
| Directory | /workspace/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc.4229679930 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 2448228276 ps |
| CPU time | 305.52 seconds |
| Started | Feb 07 04:42:03 PM PST 24 |
| Finished | Feb 07 04:47:10 PM PST 24 |
| Peak memory | 599220 kb |
| Host | smart-354212fd-cdac-48e2-88d0-2a6a06c43d63 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229679930 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.4229679930 |
| Directory | /workspace/1.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_idle.99772401 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 3441150496 ps |
| CPU time | 356.18 seconds |
| Started | Feb 07 04:41:43 PM PST 24 |
| Finished | Feb 07 04:47:40 PM PST 24 |
| Peak memory | 600604 kb |
| Host | smart-9c9c6e54-b2ca-4d99-aac8-c6d229a8c595 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99772401 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_hmac_enc_idle.99772401 |
| Directory | /workspace/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.3253662382 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 2753680322 ps |
| CPU time | 227.54 seconds |
| Started | Feb 07 04:41:54 PM PST 24 |
| Finished | Feb 07 04:45:42 PM PST 24 |
| Peak memory | 599212 kb |
| Host | smart-4c75cc01-560e-4264-ab94-4caf3a760e28 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253662382 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.3253662382 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.586858943 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 2756154706 ps |
| CPU time | 274.73 seconds |
| Started | Feb 07 04:46:17 PM PST 24 |
| Finished | Feb 07 04:50:52 PM PST 24 |
| Peak memory | 600580 kb |
| Host | smart-af0c40e7-72d9-4b48-8a02-aad6d057a109 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586858943 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.586858943 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_smoketest.2158896585 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 3402112280 ps |
| CPU time | 392.18 seconds |
| Started | Feb 07 04:47:17 PM PST 24 |
| Finished | Feb 07 04:53:50 PM PST 24 |
| Peak memory | 599120 kb |
| Host | smart-ff23dbbe-5a28-4450-9d0b-fc5a8096666d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158896585 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_hmac_smoketest.2158896585 |
| Directory | /workspace/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.1897681459 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 5587541600 ps |
| CPU time | 1213.35 seconds |
| Started | Feb 07 04:37:37 PM PST 24 |
| Finished | Feb 07 04:57:52 PM PST 24 |
| Peak memory | 601044 kb |
| Host | smart-e40a09a8-797c-47f4-8795-a7873ac9a339 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897681459 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.1897681459 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3041840003 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 5913430152 ps |
| CPU time | 992.93 seconds |
| Started | Feb 07 04:38:46 PM PST 24 |
| Finished | Feb 07 04:55:20 PM PST 24 |
| Peak memory | 600984 kb |
| Host | smart-85d8f81b-ae34-488f-9e42-e86534a2f800 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041840003 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.3041840003 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1383985580 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 4517040860 ps |
| CPU time | 867.88 seconds |
| Started | Feb 07 04:39:02 PM PST 24 |
| Finished | Feb 07 04:53:31 PM PST 24 |
| Peak memory | 601032 kb |
| Host | smart-5f3bd506-7718-43ec-8012-d2989c7c308b |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383985580 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.1383985580 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_inject_scramble_seed.2114813935 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 65568012380 ps |
| CPU time | 11034.1 seconds |
| Started | Feb 07 04:40:52 PM PST 24 |
| Finished | Feb 07 07:44:48 PM PST 24 |
| Peak memory | 616920 kb |
| Host | smart-8186c079-bf58-4666-9926-f883abe1b54b |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2114813935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.2114813935 |
| Directory | /workspace/1.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3265529525 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 4863726430 ps |
| CPU time | 411.19 seconds |
| Started | Feb 07 04:42:17 PM PST 24 |
| Finished | Feb 07 04:49:08 PM PST 24 |
| Peak memory | 607120 kb |
| Host | smart-7df1dcaf-ee5f-4cef-ac7c-ec10f9704631 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265 529525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.3265529525 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.1820398958 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 5508822081 ps |
| CPU time | 679.54 seconds |
| Started | Feb 07 04:43:31 PM PST 24 |
| Finished | Feb 07 04:54:52 PM PST 24 |
| Peak memory | 608312 kb |
| Host | smart-955f5353-b319-4a2f-bc20-b29d85dc2c7c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1820398958 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.1820398958 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1621903326 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 4233866934 ps |
| CPU time | 380.52 seconds |
| Started | Feb 07 04:46:42 PM PST 24 |
| Finished | Feb 07 04:53:03 PM PST 24 |
| Peak memory | 608248 kb |
| Host | smart-eb1d2a2d-d60c-4821-a3fe-78188bcbca0b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1621903326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.1621903326 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.914436598 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 4093392416 ps |
| CPU time | 529.94 seconds |
| Started | Feb 07 04:43:26 PM PST 24 |
| Finished | Feb 07 04:52:17 PM PST 24 |
| Peak memory | 607108 kb |
| Host | smart-3d01c5a7-8c41-44ba-a2c5-ad2b68a35ee3 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=914436598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.914436598 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1706561692 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 3789641792 ps |
| CPU time | 607.32 seconds |
| Started | Feb 07 04:41:18 PM PST 24 |
| Finished | Feb 07 04:51:26 PM PST 24 |
| Peak memory | 601896 kb |
| Host | smart-95036341-c811-420e-b3cb-eae9caf2bcbb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17065 61692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.1706561692 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.536109198 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 17904721916 ps |
| CPU time | 4837.03 seconds |
| Started | Feb 07 04:41:56 PM PST 24 |
| Finished | Feb 07 06:02:34 PM PST 24 |
| Peak memory | 600296 kb |
| Host | smart-eccf1767-a257-4206-9b4a-fbc29809e887 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53610 9198 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.536109198 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_app_rom.3182561851 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 2541834920 ps |
| CPU time | 325.15 seconds |
| Started | Feb 07 04:42:54 PM PST 24 |
| Finished | Feb 07 04:48:21 PM PST 24 |
| Peak memory | 600472 kb |
| Host | smart-ba959df8-4243-4c2e-ab12-5a35a0d78ad3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182561851 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_app_rom.3182561851 |
| Directory | /workspace/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_entropy.991352762 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 2959078028 ps |
| CPU time | 275.23 seconds |
| Started | Feb 07 04:39:37 PM PST 24 |
| Finished | Feb 07 04:44:13 PM PST 24 |
| Peak memory | 600544 kb |
| Host | smart-ac609c09-5cc1-476b-a467-7bb7c228f70f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991352762 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_kmac_entropy.991352762 |
| Directory | /workspace/1.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_idle.2031731420 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 2765669000 ps |
| CPU time | 210.39 seconds |
| Started | Feb 07 04:41:56 PM PST 24 |
| Finished | Feb 07 04:45:28 PM PST 24 |
| Peak memory | 600560 kb |
| Host | smart-65398f85-8f45-4dbd-9d7f-e96466047d5f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031731420 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_idle.2031731420 |
| Directory | /workspace/1.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3096212012 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 2494190356 ps |
| CPU time | 181.67 seconds |
| Started | Feb 07 04:42:12 PM PST 24 |
| Finished | Feb 07 04:45:16 PM PST 24 |
| Peak memory | 600480 kb |
| Host | smart-c163e2ab-addc-46d0-9345-33258c6f0e87 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096212012 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_kmac_mode_cshake.3096212012 |
| Directory | /workspace/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1307023692 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 3651673786 ps |
| CPU time | 299.87 seconds |
| Started | Feb 07 04:42:22 PM PST 24 |
| Finished | Feb 07 04:47:23 PM PST 24 |
| Peak memory | 599120 kb |
| Host | smart-59360182-55e8-46fd-99c2-aacefb41aa15 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307023692 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_kmac_mode_kmac.1307023692 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.4216471928 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 3033780351 ps |
| CPU time | 293.72 seconds |
| Started | Feb 07 04:42:09 PM PST 24 |
| Finished | Feb 07 04:47:04 PM PST 24 |
| Peak memory | 600468 kb |
| Host | smart-db48a8a0-3bd7-4691-a70f-d230bb837a44 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216471928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.4216471928 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2260321560 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 3269494293 ps |
| CPU time | 332.02 seconds |
| Started | Feb 07 04:46:52 PM PST 24 |
| Finished | Feb 07 04:52:26 PM PST 24 |
| Peak memory | 600540 kb |
| Host | smart-33b9e7db-570b-456e-9e84-99738989541f |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22603215 60 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2260321560 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_smoketest.1734564654 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 2606861464 ps |
| CPU time | 261.63 seconds |
| Started | Feb 07 04:48:44 PM PST 24 |
| Finished | Feb 07 04:53:06 PM PST 24 |
| Peak memory | 600564 kb |
| Host | smart-f59383de-777b-4b07-ba04-4c09af75108b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734564654 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_smoketest.1734564654 |
| Directory | /workspace/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3934534253 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 3086759728 ps |
| CPU time | 252.58 seconds |
| Started | Feb 07 04:40:02 PM PST 24 |
| Finished | Feb 07 04:44:16 PM PST 24 |
| Peak memory | 599076 kb |
| Host | smart-6961e4d3-96ce-4571-beed-a624fc3f7595 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934534253 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.3934534253 |
| Directory | /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.1051758898 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 3299714002 ps |
| CPU time | 432.75 seconds |
| Started | Feb 07 04:44:15 PM PST 24 |
| Finished | Feb 07 04:51:29 PM PST 24 |
| Peak memory | 616076 kb |
| Host | smart-3d8c5e9d-ffd8-435a-81fa-f1fd8990a61f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1051758898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.1051758898 |
| Directory | /workspace/1.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2898222114 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 3298436021 ps |
| CPU time | 236.25 seconds |
| Started | Feb 07 04:38:01 PM PST 24 |
| Finished | Feb 07 04:41:58 PM PST 24 |
| Peak memory | 603440 kb |
| Host | smart-a3ee995e-0a46-493c-bf12-24a5683cd0d2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28982221 14 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.2898222114 |
| Directory | /workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.652654231 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 10389269132 ps |
| CPU time | 1250.26 seconds |
| Started | Feb 07 04:39:50 PM PST 24 |
| Finished | Feb 07 05:00:41 PM PST 24 |
| Peak memory | 603988 kb |
| Host | smart-c1cea562-db52-45d5-80e2-0e78c8c0585c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652654231 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.652654231 |
| Directory | /workspace/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3782109121 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 5536008056 ps |
| CPU time | 242.66 seconds |
| Started | Feb 07 04:38:58 PM PST 24 |
| Finished | Feb 07 04:43:01 PM PST 24 |
| Peak memory | 605588 kb |
| Host | smart-141f70a2-bdf9-478d-8ac8-4a28ad9420cc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3782109121 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.3782109121 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2856630275 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 4533590129 ps |
| CPU time | 330.25 seconds |
| Started | Feb 07 04:39:00 PM PST 24 |
| Finished | Feb 07 04:44:31 PM PST 24 |
| Peak memory | 606440 kb |
| Host | smart-a8806223-e4dc-405a-9fb9-e7ac0f20aae3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=lc_ctrl_volat ile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856630275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_ unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_vol atile_raw_unlock_ext_clk_48mhz.2856630275 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1636534499 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 15250045255 ps |
| CPU time | 1192.15 seconds |
| Started | Feb 07 04:41:08 PM PST 24 |
| Finished | Feb 07 05:01:01 PM PST 24 |
| Peak memory | 606912 kb |
| Host | smart-cf455c1f-6cf5-4ad0-a20e-5ab639534939 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636534499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.1636534499 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.3587832591 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 16936319278 ps |
| CPU time | 3586.9 seconds |
| Started | Feb 07 04:41:49 PM PST 24 |
| Finished | Feb 07 05:41:37 PM PST 24 |
| Peak memory | 601108 kb |
| Host | smart-f34dddc7-cb5d-466b-be38-803c00b57bc0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3587832591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.3587832591 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3447239628 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 19025610242 ps |
| CPU time | 3728.76 seconds |
| Started | Feb 07 04:40:12 PM PST 24 |
| Finished | Feb 07 05:42:22 PM PST 24 |
| Peak memory | 601120 kb |
| Host | smart-695e0bff-8dd6-4caa-a189-7b303f91c891 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3447239628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3447239628 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.94461046 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 3088682030 ps |
| CPU time | 442.52 seconds |
| Started | Feb 07 04:41:59 PM PST 24 |
| Finished | Feb 07 04:49:25 PM PST 24 |
| Peak memory | 600496 kb |
| Host | smart-819e6595-7751-4d2e-9e06-559fab56c4d3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94461046 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.94461046 |
| Directory | /workspace/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_randomness.774502600 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 5655401960 ps |
| CPU time | 1101.14 seconds |
| Started | Feb 07 04:40:25 PM PST 24 |
| Finished | Feb 07 04:58:47 PM PST 24 |
| Peak memory | 601064 kb |
| Host | smart-0c9ad93f-bb57-444e-b742-9b8a0db653f4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=774502600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.774502600 |
| Directory | /workspace/1.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_smoketest.167343515 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 10979674936 ps |
| CPU time | 1926.25 seconds |
| Started | Feb 07 04:47:19 PM PST 24 |
| Finished | Feb 07 05:19:26 PM PST 24 |
| Peak memory | 601032 kb |
| Host | smart-bba7873a-93b0-42ae-99a0-69a6cd8ff9fa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167343515 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_smoketest.167343515 |
| Directory | /workspace/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.258095567 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 9319523804 ps |
| CPU time | 1158.44 seconds |
| Started | Feb 07 04:38:54 PM PST 24 |
| Finished | Feb 07 04:58:13 PM PST 24 |
| Peak memory | 600164 kb |
| Host | smart-6ed4a66a-2736-44c8-bd5c-2742862bfde0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=258095567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.258095567 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.326418282 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 7847881860 ps |
| CPU time | 1394.63 seconds |
| Started | Feb 07 04:40:08 PM PST 24 |
| Finished | Feb 07 05:03:23 PM PST 24 |
| Peak memory | 601508 kb |
| Host | smart-08162988-e759-469f-a1c0-09fd591130ca |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=326418282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.326418282 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3530100041 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 7957179976 ps |
| CPU time | 1080.22 seconds |
| Started | Feb 07 04:37:22 PM PST 24 |
| Finished | Feb 07 04:55:23 PM PST 24 |
| Peak memory | 601536 kb |
| Host | smart-19bf5e37-cb22-4c34-8031-1ff111151c11 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3530100041 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.3530100041 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3117749996 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 9977698545 ps |
| CPU time | 934.34 seconds |
| Started | Feb 07 04:39:40 PM PST 24 |
| Finished | Feb 07 04:55:16 PM PST 24 |
| Peak memory | 600912 kb |
| Host | smart-25faf0ad-255e-44c6-96c5-b1c469d466d8 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3117749996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3117749996 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3982725118 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 3174059432 ps |
| CPU time | 282.89 seconds |
| Started | Feb 07 04:48:56 PM PST 24 |
| Finished | Feb 07 04:53:40 PM PST 24 |
| Peak memory | 600512 kb |
| Host | smart-abc4eb27-59f9-4327-bfd9-ef466e9bdf01 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982725118 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_otp_ctrl_smoketest.3982725118 |
| Directory | /workspace/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_plic_sw_irq.4242960332 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 2849112616 ps |
| CPU time | 254.05 seconds |
| Started | Feb 07 04:43:30 PM PST 24 |
| Finished | Feb 07 04:47:47 PM PST 24 |
| Peak memory | 599096 kb |
| Host | smart-e21154db-b858-4988-879a-742f0ff0ec61 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242960332 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_plic_sw_irq.4242960332 |
| Directory | /workspace/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_idle_load.868451360 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 3538386550 ps |
| CPU time | 691.44 seconds |
| Started | Feb 07 04:45:37 PM PST 24 |
| Finished | Feb 07 04:57:09 PM PST 24 |
| Peak memory | 599548 kb |
| Host | smart-8143f534-6835-40da-a56c-ebc04c1c2c9d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868451360 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.868451360 |
| Directory | /workspace/1.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_sleep_load.449828404 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 10509244200 ps |
| CPU time | 511.96 seconds |
| Started | Feb 07 04:45:34 PM PST 24 |
| Finished | Feb 07 04:54:08 PM PST 24 |
| Peak memory | 601848 kb |
| Host | smart-f58254ad-eec4-4285-a2c7-ac397d66c6a4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449828404 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.449828404 |
| Directory | /workspace/1.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3038367105 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 10087220547 ps |
| CPU time | 1318.69 seconds |
| Started | Feb 07 04:39:06 PM PST 24 |
| Finished | Feb 07 05:01:05 PM PST 24 |
| Peak memory | 600964 kb |
| Host | smart-18ec7ba5-2b6a-4389-b76f-0382d7a2bbec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038 367105 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.3038367105 |
| Directory | /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.2793410991 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 24322314450 ps |
| CPU time | 2194.23 seconds |
| Started | Feb 07 04:42:22 PM PST 24 |
| Finished | Feb 07 05:18:57 PM PST 24 |
| Peak memory | 601684 kb |
| Host | smart-b4943588-af93-492d-9ccf-3c066ffadbf4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279 3410991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.2793410991 |
| Directory | /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.79641835 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 12236125310 ps |
| CPU time | 1080.76 seconds |
| Started | Feb 07 04:39:14 PM PST 24 |
| Finished | Feb 07 04:57:15 PM PST 24 |
| Peak memory | 602376 kb |
| Host | smart-99e0316d-f92e-47c0-9f49-908549646b0a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=79641835 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.79641835 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.966323722 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 5837772664 ps |
| CPU time | 459.79 seconds |
| Started | Feb 07 04:38:48 PM PST 24 |
| Finished | Feb 07 04:46:30 PM PST 24 |
| Peak memory | 606564 kb |
| Host | smart-8c0f710d-7a0b-445e-a122-551d35fae409 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=966323722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.966323722 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1296795114 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 8864485630 ps |
| CPU time | 436.73 seconds |
| Started | Feb 07 04:38:04 PM PST 24 |
| Finished | Feb 07 04:45:21 PM PST 24 |
| Peak memory | 600164 kb |
| Host | smart-3c4fa6b9-3ebb-482b-8b2b-f810df9710cf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296795114 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.1296795114 |
| Directory | /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3072331846 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 3388321723 ps |
| CPU time | 384.34 seconds |
| Started | Feb 07 04:39:46 PM PST 24 |
| Finished | Feb 07 04:46:11 PM PST 24 |
| Peak memory | 607848 kb |
| Host | smart-5cca6dc4-b41d-4239-a799-0c6665efada1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3072331846 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.3072331846 |
| Directory | /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1348445759 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 12961814184 ps |
| CPU time | 1246.69 seconds |
| Started | Feb 07 04:39:26 PM PST 24 |
| Finished | Feb 07 05:00:13 PM PST 24 |
| Peak memory | 601060 kb |
| Host | smart-3c7607f5-c625-488c-b6a3-78211a9e2676 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348445759 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1348445759 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.766774631 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 7478624904 ps |
| CPU time | 501.3 seconds |
| Started | Feb 07 04:44:13 PM PST 24 |
| Finished | Feb 07 04:52:35 PM PST 24 |
| Peak memory | 601244 kb |
| Host | smart-8a14525c-a3b2-4bfb-b1e9-ab775b978cbf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766774631 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.766774631 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2133134814 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 5121564577 ps |
| CPU time | 444.69 seconds |
| Started | Feb 07 04:39:58 PM PST 24 |
| Finished | Feb 07 04:47:23 PM PST 24 |
| Peak memory | 600344 kb |
| Host | smart-51ee9fba-e791-4e8e-9d84-1f6bbb48d555 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133134814 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.2133134814 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1587327975 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 23289198247 ps |
| CPU time | 2841.81 seconds |
| Started | Feb 07 04:38:22 PM PST 24 |
| Finished | Feb 07 05:25:45 PM PST 24 |
| Peak memory | 601084 kb |
| Host | smart-b5829c38-6090-4d98-a861-897e1c4edebd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1587327975 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1587327975 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.697825557 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 21225297380 ps |
| CPU time | 2032.38 seconds |
| Started | Feb 07 04:44:53 PM PST 24 |
| Finished | Feb 07 05:18:46 PM PST 24 |
| Peak memory | 600492 kb |
| Host | smart-ce877d6f-d9a0-424f-8c0b-964a69e265dd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=697825557 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.697825557 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4212627735 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 32509915930 ps |
| CPU time | 3266.26 seconds |
| Started | Feb 07 04:39:07 PM PST 24 |
| Finished | Feb 07 05:33:34 PM PST 24 |
| Peak memory | 600676 kb |
| Host | smart-5a45c63e-61e5-468d-adc4-1cad4701bbe6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212627735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_s leep_power_glitch_reset.4212627735 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.933590960 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 5056978920 ps |
| CPU time | 544.11 seconds |
| Started | Feb 07 04:45:28 PM PST 24 |
| Finished | Feb 07 04:54:36 PM PST 24 |
| Peak memory | 600700 kb |
| Host | smart-913f0d46-d0b9-42b8-b514-85fa7265f845 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=933590960 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_sl eep_wake_up.933590960 |
| Directory | /workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.663237445 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 3468457976 ps |
| CPU time | 392.83 seconds |
| Started | Feb 07 04:40:01 PM PST 24 |
| Finished | Feb 07 04:46:38 PM PST 24 |
| Peak memory | 599112 kb |
| Host | smart-9f632036-6555-49b8-b1a0-87ad8f39012f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663237445 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.663237445 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.3441556443 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 3959428536 ps |
| CPU time | 370.03 seconds |
| Started | Feb 07 04:38:47 PM PST 24 |
| Finished | Feb 07 04:44:59 PM PST 24 |
| Peak memory | 608076 kb |
| Host | smart-f1e4ad12-395d-42cf-b510-232606c4f89a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3441556443 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.3441556443 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1135780191 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 5406191240 ps |
| CPU time | 428.22 seconds |
| Started | Feb 07 04:44:19 PM PST 24 |
| Finished | Feb 07 04:51:28 PM PST 24 |
| Peak memory | 600628 kb |
| Host | smart-4dd1dc68-1982-4ff6-b854-d0997d44b2bb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11357801 91 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1135780191 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2126419580 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 4859198270 ps |
| CPU time | 363.2 seconds |
| Started | Feb 07 04:45:31 PM PST 24 |
| Finished | Feb 07 04:51:35 PM PST 24 |
| Peak memory | 601428 kb |
| Host | smart-6be7f462-c1da-4b06-9007-c74164a9c6de |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2126419580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.2126419580 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2379284414 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 4067148406 ps |
| CPU time | 452.84 seconds |
| Started | Feb 07 04:48:32 PM PST 24 |
| Finished | Feb 07 04:56:07 PM PST 24 |
| Peak memory | 600968 kb |
| Host | smart-58cba8fe-a6ee-4423-9e94-696645145baa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379284414 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.2379284414 |
| Directory | /workspace/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.525044401 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 8193487236 ps |
| CPU time | 954.28 seconds |
| Started | Feb 07 04:39:47 PM PST 24 |
| Finished | Feb 07 04:55:42 PM PST 24 |
| Peak memory | 600220 kb |
| Host | smart-98d5e687-c028-4513-84a2-d7f993527b00 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525044401 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.525044401 |
| Directory | /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1908576252 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 4721838316 ps |
| CPU time | 562.28 seconds |
| Started | Feb 07 04:41:41 PM PST 24 |
| Finished | Feb 07 04:51:04 PM PST 24 |
| Peak memory | 601292 kb |
| Host | smart-ff6b1f50-ff7f-404e-baaa-eb76d8d5e581 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908576252 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1908576252 |
| Directory | /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3425327218 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 4195569640 ps |
| CPU time | 289 seconds |
| Started | Feb 07 04:48:53 PM PST 24 |
| Finished | Feb 07 04:53:42 PM PST 24 |
| Peak memory | 600996 kb |
| Host | smart-9ddb651e-a31e-447c-8ebf-f0e77a0497cf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425327218 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.3425327218 |
| Directory | /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.915734167 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 5694958534 ps |
| CPU time | 544.47 seconds |
| Started | Feb 07 04:42:04 PM PST 24 |
| Finished | Feb 07 04:51:10 PM PST 24 |
| Peak memory | 601220 kb |
| Host | smart-a4cd4d6d-a20a-4b25-ad8f-6e9b19fd6980 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915 734167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.915734167 |
| Directory | /workspace/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1003321043 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 9779852976 ps |
| CPU time | 556.78 seconds |
| Started | Feb 07 04:42:20 PM PST 24 |
| Finished | Feb 07 04:51:37 PM PST 24 |
| Peak memory | 605416 kb |
| Host | smart-5a058427-b5b3-4303-a35e-58b6ed250691 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003321043 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.1003321043 |
| Directory | /workspace/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1783129664 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 13903054042 ps |
| CPU time | 1974.74 seconds |
| Started | Feb 07 04:40:44 PM PST 24 |
| Finished | Feb 07 05:13:39 PM PST 24 |
| Peak memory | 601800 kb |
| Host | smart-061c58a6-689b-4afd-857a-983505730a6d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1783129664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.1783129664 |
| Directory | /workspace/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1178134250 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 7764835986 ps |
| CPU time | 911.14 seconds |
| Started | Feb 07 04:41:30 PM PST 24 |
| Finished | Feb 07 04:56:42 PM PST 24 |
| Peak memory | 601352 kb |
| Host | smart-d3d832a2-1199-42f4-9711-4185a0f7ba36 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178134250 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_rstmgr_cpu_info.1178134250 |
| Directory | /workspace/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2267036981 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 5601658250 ps |
| CPU time | 756.12 seconds |
| Started | Feb 07 04:37:32 PM PST 24 |
| Finished | Feb 07 04:50:09 PM PST 24 |
| Peak memory | 631348 kb |
| Host | smart-0ad50191-69ce-459a-b52d-80c367e7d590 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2267036981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.2267036981 |
| Directory | /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.1206292112 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 3117236448 ps |
| CPU time | 318.17 seconds |
| Started | Feb 07 04:47:47 PM PST 24 |
| Finished | Feb 07 04:53:06 PM PST 24 |
| Peak memory | 599088 kb |
| Host | smart-05f038ac-86ac-4535-91f7-5861f2e5061a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206292112 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rstmgr_smoketest.1206292112 |
| Directory | /workspace/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.621526664 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 4545122424 ps |
| CPU time | 360.1 seconds |
| Started | Feb 07 04:38:54 PM PST 24 |
| Finished | Feb 07 04:44:55 PM PST 24 |
| Peak memory | 599884 kb |
| Host | smart-f4a7d00e-fd74-4b58-ac80-45952c4dbde8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621526664 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rstmgr_sw_req.621526664 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.555135109 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 2297771048 ps |
| CPU time | 226.22 seconds |
| Started | Feb 07 04:39:34 PM PST 24 |
| Finished | Feb 07 04:43:21 PM PST 24 |
| Peak memory | 599100 kb |
| Host | smart-20e8c1a0-ab81-43fd-bdab-21389edbfda3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555135109 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.555135109 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3364029092 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 2638040816 ps |
| CPU time | 245.15 seconds |
| Started | Feb 07 04:44:52 PM PST 24 |
| Finished | Feb 07 04:48:59 PM PST 24 |
| Peak memory | 600484 kb |
| Host | smart-445ac7cb-6220-4e37-bb5f-8f05934ab466 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3364029092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.3364029092 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.233295050 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 2689623394 ps |
| CPU time | 232.13 seconds |
| Started | Feb 07 04:45:07 PM PST 24 |
| Finished | Feb 07 04:49:00 PM PST 24 |
| Peak memory | 600508 kb |
| Host | smart-857dcdb8-97a8-49c4-a7c4-4f7e9d8a3ef9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233295050 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.233295050 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1859346888 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 2275106432 ps |
| CPU time | 329.36 seconds |
| Started | Feb 07 04:45:07 PM PST 24 |
| Finished | Feb 07 04:50:37 PM PST 24 |
| Peak memory | 635868 kb |
| Host | smart-e5966366-c446-467c-b25c-ab3a23b05076 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859346888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_lockstep_glitch.1859346888 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1534712606 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 4880334508 ps |
| CPU time | 951.19 seconds |
| Started | Feb 07 04:40:55 PM PST 24 |
| Finished | Feb 07 04:56:48 PM PST 24 |
| Peak memory | 599424 kb |
| Host | smart-e06965b8-9369-4b0b-be08-78121e19408d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15347 12606 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.1534712606 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.385362464 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 5507825100 ps |
| CPU time | 1090.41 seconds |
| Started | Feb 07 04:39:55 PM PST 24 |
| Finished | Feb 07 04:58:06 PM PST 24 |
| Peak memory | 600720 kb |
| Host | smart-95b52e6f-1e95-42c2-ba08-ed8da9aa2a7d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=385362464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.385362464 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3053715954 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 5512272943 ps |
| CPU time | 643.44 seconds |
| Started | Feb 07 04:45:03 PM PST 24 |
| Finished | Feb 07 04:55:47 PM PST 24 |
| Peak memory | 617640 kb |
| Host | smart-dc9dbc64-3c1b-4e16-95cb-dba685a1677f |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053715954 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.3053715954 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.3129972473 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 5156080496 ps |
| CPU time | 354.3 seconds |
| Started | Feb 07 04:44:18 PM PST 24 |
| Finished | Feb 07 04:50:13 PM PST 24 |
| Peak memory | 616648 kb |
| Host | smart-1167adf9-ffe0-4b67-acc9-021944d547f2 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup:1:new_rules,test_rom:0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129972473 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.3129972473 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.499097253 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 5053613072 ps |
| CPU time | 542.58 seconds |
| Started | Feb 07 04:44:45 PM PST 24 |
| Finished | Feb 07 04:53:48 PM PST 24 |
| Peak memory | 617736 kb |
| Host | smart-82b93d39-2b9f-49f7-9476-cf6f0a48a557 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499097253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.499097253 |
| Directory | /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.3657951306 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 2737854800 ps |
| CPU time | 247.74 seconds |
| Started | Feb 07 04:46:46 PM PST 24 |
| Finished | Feb 07 04:50:54 PM PST 24 |
| Peak memory | 600552 kb |
| Host | smart-5ce0f384-37c0-403c-9030-865b9c6f4eb7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657951306 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_plic_smoketest.3657951306 |
| Directory | /workspace/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_irq.2457334406 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 2177007800 ps |
| CPU time | 208.93 seconds |
| Started | Feb 07 04:40:33 PM PST 24 |
| Finished | Feb 07 04:44:03 PM PST 24 |
| Peak memory | 599012 kb |
| Host | smart-75ca9a14-08f6-412c-832f-758e9960a6c6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457334406 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_irq.2457334406 |
| Directory | /workspace/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2220128562 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 2538678030 ps |
| CPU time | 185.83 seconds |
| Started | Feb 07 04:48:31 PM PST 24 |
| Finished | Feb 07 04:51:38 PM PST 24 |
| Peak memory | 600480 kb |
| Host | smart-ea1c1123-0719-4e74-805a-f8cdaf9e83a5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220128562 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_smoketest.2220128562 |
| Directory | /workspace/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.641098464 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 2352321839 ps |
| CPU time | 240.8 seconds |
| Started | Feb 07 04:43:55 PM PST 24 |
| Finished | Feb 07 04:47:56 PM PST 24 |
| Peak memory | 600844 kb |
| Host | smart-de49aed4-b9f8-4d32-beca-5059c1b20731 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6410984 64 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.641098464 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_retention.905315024 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3539568248 ps |
| CPU time | 238.39 seconds |
| Started | Feb 07 04:38:49 PM PST 24 |
| Finished | Feb 07 04:42:49 PM PST 24 |
| Peak memory | 601912 kb |
| Host | smart-16d9ef82-cd7f-480a-9915-6075853f7848 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905315024 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.905315024 |
| Directory | /workspace/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1001173994 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 7766785000 ps |
| CPU time | 1540.5 seconds |
| Started | Feb 07 04:38:52 PM PST 24 |
| Finished | Feb 07 05:04:33 PM PST 24 |
| Peak memory | 600572 kb |
| Host | smart-0cfa8915-c1c4-4692-a58b-ca044cf05e53 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001173994 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.1001173994 |
| Directory | /workspace/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3643222177 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 6588295356 ps |
| CPU time | 686.53 seconds |
| Started | Feb 07 04:43:09 PM PST 24 |
| Finished | Feb 07 04:54:36 PM PST 24 |
| Peak memory | 601356 kb |
| Host | smart-4cc71aff-36b1-46c8-86a7-2ec61d56db22 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643222177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sl eep_sram_ret_contents_no_scramble.3643222177 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3427325119 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 9036155490 ps |
| CPU time | 910.33 seconds |
| Started | Feb 07 04:44:32 PM PST 24 |
| Finished | Feb 07 04:59:43 PM PST 24 |
| Peak memory | 601424 kb |
| Host | smart-7916157c-8a1a-425b-9435-c38426d18a07 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427325119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep _sram_ret_contents_scramble.3427325119 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through.3872974984 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 5723073457 ps |
| CPU time | 717.23 seconds |
| Started | Feb 07 04:38:49 PM PST 24 |
| Finished | Feb 07 04:50:48 PM PST 24 |
| Peak memory | 618252 kb |
| Host | smart-f0741e28-a060-4151-95c5-1bff51c52848 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872974984 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.3872974984 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2885754385 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 4358047256 ps |
| CPU time | 521.14 seconds |
| Started | Feb 07 04:39:12 PM PST 24 |
| Finished | Feb 07 04:47:54 PM PST 24 |
| Peak memory | 618336 kb |
| Host | smart-6de1623e-c26d-46da-9858-4e6d1d094ed8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885754385 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.2885754385 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_tpm.3657876254 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 2782367237 ps |
| CPU time | 283.5 seconds |
| Started | Feb 07 04:37:54 PM PST 24 |
| Finished | Feb 07 04:42:38 PM PST 24 |
| Peak memory | 606988 kb |
| Host | smart-88de6733-3dbb-4c91-8a01-90c918fd1417 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657876254 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.3657876254 |
| Directory | /workspace/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2097272906 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 3020239930 ps |
| CPU time | 384.51 seconds |
| Started | Feb 07 04:39:35 PM PST 24 |
| Finished | Feb 07 04:46:00 PM PST 24 |
| Peak memory | 601972 kb |
| Host | smart-3e60e2c8-125a-4bde-9de5-e4ce93d6727c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097272906 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.2097272906 |
| Directory | /workspace/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2895756710 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 8590796153 ps |
| CPU time | 573.26 seconds |
| Started | Feb 07 04:44:06 PM PST 24 |
| Finished | Feb 07 04:53:40 PM PST 24 |
| Peak memory | 600212 kb |
| Host | smart-63393c3a-da3c-476f-8639-346617cb8299 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895756710 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.2895756710 |
| Directory | /workspace/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2155550154 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 4066425912 ps |
| CPU time | 630.91 seconds |
| Started | Feb 07 04:42:27 PM PST 24 |
| Finished | Feb 07 04:52:59 PM PST 24 |
| Peak memory | 600868 kb |
| Host | smart-41ef0399-1bbc-4a65-b0d3-497c833fc968 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155550154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _sram_ctrl_scrambled_access.2155550154 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3179374770 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 4452466503 ps |
| CPU time | 765.88 seconds |
| Started | Feb 07 04:43:52 PM PST 24 |
| Finished | Feb 07 04:56:40 PM PST 24 |
| Peak memory | 601092 kb |
| Host | smart-a61cbdc3-d109-4c81-a2db-593db2537845 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179374770 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3179374770 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1022252013 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 1871192916 ps |
| CPU time | 216.98 seconds |
| Started | Feb 07 04:51:58 PM PST 24 |
| Finished | Feb 07 04:55:38 PM PST 24 |
| Peak memory | 599008 kb |
| Host | smart-98c5ce85-8f16-47ad-8df6-a6c975ffc0b2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022252013 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_sram_ctrl_smoketest.1022252013 |
| Directory | /workspace/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.768024319 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 20262660830 ps |
| CPU time | 3333.72 seconds |
| Started | Feb 07 04:41:15 PM PST 24 |
| Finished | Feb 07 05:36:49 PM PST 24 |
| Peak memory | 601412 kb |
| Host | smart-8e92f351-966b-4ee2-a40e-62694a326ef2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768024319 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.768024319 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2406167305 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 5069348198 ps |
| CPU time | 673.13 seconds |
| Started | Feb 07 04:41:36 PM PST 24 |
| Finished | Feb 07 04:52:50 PM PST 24 |
| Peak memory | 601420 kb |
| Host | smart-ac438af9-712a-452c-b7ce-db1f8f8aa070 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406167305 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.2406167305 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2739318400 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 2956589063 ps |
| CPU time | 216.27 seconds |
| Started | Feb 07 04:39:56 PM PST 24 |
| Finished | Feb 07 04:43:33 PM PST 24 |
| Peak memory | 601076 kb |
| Host | smart-085c5d57-68ec-411d-bff5-dfdb9edc05fd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739318400 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.2739318400 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.3236574589 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 24980225436 ps |
| CPU time | 2220.52 seconds |
| Started | Feb 07 04:40:49 PM PST 24 |
| Finished | Feb 07 05:17:50 PM PST 24 |
| Peak memory | 601876 kb |
| Host | smart-fa22037a-5338-4395-bf4a-16fec3057742 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32365745 89 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.3236574589 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2376300263 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 3796425732 ps |
| CPU time | 377.8 seconds |
| Started | Feb 07 04:41:47 PM PST 24 |
| Finished | Feb 07 04:48:08 PM PST 24 |
| Peak memory | 600416 kb |
| Host | smart-bbe0d2be-a040-4af5-8cd1-11f95b55bc70 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376300263 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2376300263 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.4230277387 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 12721625726 ps |
| CPU time | 2649.84 seconds |
| Started | Feb 07 04:38:33 PM PST 24 |
| Finished | Feb 07 05:22:44 PM PST 24 |
| Peak memory | 601780 kb |
| Host | smart-80db00e3-71d8-4f99-9ed9-8cc2dfe104aa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4230277387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.4230277387 |
| Directory | /workspace/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_smoketest.1451914025 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 2926690172 ps |
| CPU time | 274.62 seconds |
| Started | Feb 07 04:46:45 PM PST 24 |
| Finished | Feb 07 04:51:20 PM PST 24 |
| Peak memory | 595640 kb |
| Host | smart-be0478fa-b977-43e5-a5f6-aeef813d4f22 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451914025 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_uart_smoketest.1451914025 |
| Directory | /workspace/1.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_smoketest_signed.1790233104 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 9060666188 ps |
| CPU time | 2238.56 seconds |
| Started | Feb 07 04:50:27 PM PST 24 |
| Finished | Feb 07 05:27:47 PM PST 24 |
| Peak memory | 595912 kb |
| Host | smart-e70cabf7-a4e6-4eaa-b3c3-f1c5a9e548fc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=uart_smoketest_signed:1:signed:fake_rsa_test_key_0,rom_with_fa ke_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1790233104 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_smoketest_signed.1790233104 |
| Directory | /workspace/1.chip_sw_uart_smoketest_signed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx.1003273722 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 5983943596 ps |
| CPU time | 1017.29 seconds |
| Started | Feb 07 04:38:45 PM PST 24 |
| Finished | Feb 07 04:55:44 PM PST 24 |
| Peak memory | 603136 kb |
| Host | smart-020b89a1-abb0-4ddc-93dd-f0a4a992e2ec |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003273722 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.1003273722 |
| Directory | /workspace/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1929249642 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 5147696052 ps |
| CPU time | 1142.96 seconds |
| Started | Feb 07 04:38:45 PM PST 24 |
| Finished | Feb 07 04:57:50 PM PST 24 |
| Peak memory | 603864 kb |
| Host | smart-8094db07-9d8d-45cc-915f-7ad21f4bfae6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929249642 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq.1929249642 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1659348587 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 12882926485 ps |
| CPU time | 1916.19 seconds |
| Started | Feb 07 04:37:24 PM PST 24 |
| Finished | Feb 07 05:09:21 PM PST 24 |
| Peak memory | 613740 kb |
| Host | smart-ad0e1292-d795-4f7a-a820-23f2ae761638 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659348587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1659348587 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.252925803 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 77640237814 ps |
| CPU time | 13125.3 seconds |
| Started | Feb 07 04:39:28 PM PST 24 |
| Finished | Feb 07 08:18:16 PM PST 24 |
| Peak memory | 611504 kb |
| Host | smart-02c384c8-14d1-4983-a653-df9480309445 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=252925803 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.252925803 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3507608336 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 5594666144 ps |
| CPU time | 946.04 seconds |
| Started | Feb 07 04:37:50 PM PST 24 |
| Finished | Feb 07 04:53:37 PM PST 24 |
| Peak memory | 602804 kb |
| Host | smart-0eaee630-f628-441e-9f2f-2295227c4313 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507608336 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.3507608336 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1129335417 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 5619939564 ps |
| CPU time | 908.11 seconds |
| Started | Feb 07 04:38:52 PM PST 24 |
| Finished | Feb 07 04:54:01 PM PST 24 |
| Peak memory | 602760 kb |
| Host | smart-008260cd-af5c-4bac-a291-e4a490602821 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129335417 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.1129335417 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.3761876567 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 5129399200 ps |
| CPU time | 996.23 seconds |
| Started | Feb 07 04:38:24 PM PST 24 |
| Finished | Feb 07 04:55:01 PM PST 24 |
| Peak memory | 602728 kb |
| Host | smart-81a726f8-401c-4065-950d-9caaab28a803 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761876567 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.3761876567 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_dev.4030043959 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 3080509933 ps |
| CPU time | 223.53 seconds |
| Started | Feb 07 04:45:00 PM PST 24 |
| Finished | Feb 07 04:48:44 PM PST 24 |
| Peak memory | 601660 kb |
| Host | smart-6d288601-1376-469e-84fb-bd1a27c93e5d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4030043959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.4030043959 |
| Directory | /workspace/1.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_prod.4272701217 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 10124797515 ps |
| CPU time | 1029.02 seconds |
| Started | Feb 07 04:44:06 PM PST 24 |
| Finished | Feb 07 05:01:16 PM PST 24 |
| Peak memory | 601996 kb |
| Host | smart-8d6d8c60-fcb4-44f2-a63b-ceb2ada682c4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272701217 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.4272701217 |
| Directory | /workspace/1.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_rma.2591973296 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 3569078041 ps |
| CPU time | 265.09 seconds |
| Started | Feb 07 04:44:04 PM PST 24 |
| Finished | Feb 07 04:48:30 PM PST 24 |
| Peak memory | 602160 kb |
| Host | smart-201b8e3f-be8c-47ec-9499-ab4e89f8f602 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591973296 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.2591973296 |
| Directory | /workspace/1.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_testunlock0.2389929595 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 7321066329 ps |
| CPU time | 551.89 seconds |
| Started | Feb 07 04:44:33 PM PST 24 |
| Finished | Feb 07 04:53:45 PM PST 24 |
| Peak memory | 602076 kb |
| Host | smart-264fed69-2d6e-4625-aed8-9bb5d8ca2fc6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2389929595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.2389929595 |
| Directory | /workspace/1.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_dev.1638263342 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 9674208124 ps |
| CPU time | 2208.42 seconds |
| Started | Feb 07 04:50:18 PM PST 24 |
| Finished | Feb 07 05:27:09 PM PST 24 |
| Peak memory | 601120 kb |
| Host | smart-bed8a9b9-6dcc-46e3-b82d-847147414509 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_dev:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638263342 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.rom_e2e_asm_init_dev.1638263342 |
| Directory | /workspace/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod.1089440014 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 9002202962 ps |
| CPU time | 2084.67 seconds |
| Started | Feb 07 04:50:34 PM PST 24 |
| Finished | Feb 07 05:25:19 PM PST 24 |
| Peak memory | 601108 kb |
| Host | smart-fb9f14e7-93d9-412d-9ccd-4c21d8e35814 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_prod:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089440014 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.rom_e2e_asm_init_prod.1089440014 |
| Directory | /workspace/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3480326649 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 8699426076 ps |
| CPU time | 2044.11 seconds |
| Started | Feb 07 04:50:08 PM PST 24 |
| Finished | Feb 07 05:24:13 PM PST 24 |
| Peak memory | 599644 kb |
| Host | smart-d8d77d91-2821-4d2c-acd5-0e98ea7b3d93 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_prod_end:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480326649 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod_end.3480326649 |
| Directory | /workspace/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_rma.3918740660 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 8942546386 ps |
| CPU time | 2009.64 seconds |
| Started | Feb 07 04:50:16 PM PST 24 |
| Finished | Feb 07 05:23:50 PM PST 24 |
| Peak memory | 601072 kb |
| Host | smart-d000c5a5-b316-4f66-8da0-c7ee59402263 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_rma:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918740660 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.rom_e2e_asm_init_rma.3918740660 |
| Directory | /workspace/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.59370285 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 7163728135 ps |
| CPU time | 1567.24 seconds |
| Started | Feb 07 04:50:14 PM PST 24 |
| Finished | Feb 07 05:16:22 PM PST 24 |
| Peak memory | 601408 kb |
| Host | smart-97461180-0cbd-421c-9865-3c425c1158fe |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_ flash_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59370285 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_test_unlocked0.59370285 |
| Directory | /workspace/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.106313091 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 8546152800 ps |
| CPU time | 2015.88 seconds |
| Started | Feb 07 04:49:56 PM PST 24 |
| Finished | Feb 07 05:23:32 PM PST 24 |
| Peak memory | 601508 kb |
| Host | smart-521baa44-c3a1-4811-aae6-f9065dee08f4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:signed:fake_rsa_test_key_0,rom_ with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=106313091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_exception_c.106313091 |
| Directory | /workspace/1.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_output.482064633 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 26122959832 ps |
| CPU time | 2977.86 seconds |
| Started | Feb 07 04:50:58 PM PST 24 |
| Finished | Feb 07 05:40:36 PM PST 24 |
| Peak memory | 602596 kb |
| Host | smart-91f1b084-bfea-4363-8eef-2102cd9807e3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bina ry,otp_img_shutdown_output_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482064633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.482064633 |
| Directory | /workspace/1.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_smoke.760175987 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 8495274496 ps |
| CPU time | 2222.37 seconds |
| Started | Feb 07 04:45:56 PM PST 24 |
| Finished | Feb 07 05:22:59 PM PST 24 |
| Peak memory | 600984 kb |
| Host | smart-4b4be69c-b8fa-43a9-b9aa-7bd8facb12bf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_binary:signed:fake_rsa_test_key_0 ,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=760175987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.760175987 |
| Directory | /workspace/1.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_static_critical.2896609191 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 11292247496 ps |
| CPU time | 2017.92 seconds |
| Started | Feb 07 04:51:11 PM PST 24 |
| Finished | Feb 07 05:24:49 PM PST 24 |
| Peak memory | 601020 kb |
| Host | smart-b240de73-032b-4e7d-a1b0-48a10f21b909 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:signed:fake_rsa_test_key_0,rom_with_ fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896609191 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.2896609191 |
| Directory | /workspace/1.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/1.rom_keymgr_functest.2295649087 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 4221844150 ps |
| CPU time | 682.43 seconds |
| Started | Feb 07 04:46:33 PM PST 24 |
| Finished | Feb 07 04:57:56 PM PST 24 |
| Peak memory | 599780 kb |
| Host | smart-f964933d-634b-4e93-8599-64654cf9a92c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295649087 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.2295649087 |
| Directory | /workspace/1.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/1.rom_raw_unlock.2165063015 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 14719355375 ps |
| CPU time | 2364.22 seconds |
| Started | Feb 07 04:49:27 PM PST 24 |
| Finished | Feb 07 05:28:53 PM PST 24 |
| Peak memory | 606496 kb |
| Host | smart-db5f03e3-a853-4cab-877c-d41df3529ade |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:fake_rsa_test_key_0:ot_flash_binary,rom_with_fake_keys:0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165063015 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.2165063015 |
| Directory | /workspace/1.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.rom_volatile_raw_unlock.3580999741 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 12610851222 ps |
| CPU time | 2170.79 seconds |
| Started | Feb 07 04:49:22 PM PST 24 |
| Finished | Feb 07 05:25:33 PM PST 24 |
| Peak memory | 607040 kb |
| Host | smart-48d5795b-42c4-44b6-85b2-4f19cdc9da4b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:fake_rsa_test_key_0:ot_flash_binary,rom_with_fake_keys:0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580999741 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.3580999741 |
| Directory | /workspace/1.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2534095272 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 3579513240 ps |
| CPU time | 527.81 seconds |
| Started | Feb 07 04:57:49 PM PST 24 |
| Finished | Feb 07 05:06:37 PM PST 24 |
| Peak memory | 633912 kb |
| Host | smart-fccbb482-4dee-4e37-9796-7f5af3dd545d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534095272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2534095272 |
| Directory | /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.1325029206 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 6106115165 ps |
| CPU time | 392.6 seconds |
| Started | Feb 07 05:01:59 PM PST 24 |
| Finished | Feb 07 05:08:33 PM PST 24 |
| Peak memory | 604012 kb |
| Host | smart-b9c6fdb2-272f-4b30-8936-e4dc9c8d6628 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325029206 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.1325029206 |
| Directory | /workspace/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1268959994 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 5817111604 ps |
| CPU time | 931.34 seconds |
| Started | Feb 07 05:00:47 PM PST 24 |
| Finished | Feb 07 05:16:20 PM PST 24 |
| Peak memory | 601824 kb |
| Host | smart-377899bc-563a-4927-b05a-1481df38d650 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1268959994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.1268959994 |
| Directory | /workspace/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2089013634 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 4797610462 ps |
| CPU time | 464.75 seconds |
| Started | Feb 07 04:57:53 PM PST 24 |
| Finished | Feb 07 05:05:38 PM PST 24 |
| Peak memory | 603712 kb |
| Host | smart-7c50cd2c-d838-4e2e-aaca-a4669ba28250 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089013634 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.2089013634 |
| Directory | /workspace/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1196800983 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 6084122592 ps |
| CPU time | 936.01 seconds |
| Started | Feb 07 04:58:03 PM PST 24 |
| Finished | Feb 07 05:13:40 PM PST 24 |
| Peak memory | 601784 kb |
| Host | smart-2490e4cd-54d0-40c4-a50b-4162eb14ad33 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1196800983 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.1196800983 |
| Directory | /workspace/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/12.chip_sw_all_escalation_resets.3665213507 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 5668557660 ps |
| CPU time | 762.99 seconds |
| Started | Feb 07 04:58:16 PM PST 24 |
| Finished | Feb 07 05:11:00 PM PST 24 |
| Peak memory | 633704 kb |
| Host | smart-02d3d811-28c3-4a42-8363-ec378d228486 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3665213507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.3665213507 |
| Directory | /workspace/12.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.719042868 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 9511855250 ps |
| CPU time | 786.51 seconds |
| Started | Feb 07 05:02:56 PM PST 24 |
| Finished | Feb 07 05:16:05 PM PST 24 |
| Peak memory | 603916 kb |
| Host | smart-b4550b3f-f63b-45b1-9ca7-65f7658a5ab5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719042868 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.719042868 |
| Directory | /workspace/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.1527242232 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 5233508664 ps |
| CPU time | 901.39 seconds |
| Started | Feb 07 04:58:36 PM PST 24 |
| Finished | Feb 07 05:13:38 PM PST 24 |
| Peak memory | 601828 kb |
| Host | smart-726113a0-fe8e-4d56-8ee9-dff80b65b964 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1527242232 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.1527242232 |
| Directory | /workspace/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2138412096 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 6827763377 ps |
| CPU time | 401.51 seconds |
| Started | Feb 07 05:03:04 PM PST 24 |
| Finished | Feb 07 05:09:47 PM PST 24 |
| Peak memory | 604012 kb |
| Host | smart-c3dcb2e3-3e6c-45f2-8e80-62f1b0c31475 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138412096 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.2138412096 |
| Directory | /workspace/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1491064804 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 5765974492 ps |
| CPU time | 1056.25 seconds |
| Started | Feb 07 05:00:28 PM PST 24 |
| Finished | Feb 07 05:18:05 PM PST 24 |
| Peak memory | 601776 kb |
| Host | smart-615b120d-d960-4ef3-929e-5b18d6d6df60 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1491064804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.1491064804 |
| Directory | /workspace/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1117416272 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 11546593713 ps |
| CPU time | 750.26 seconds |
| Started | Feb 07 04:58:21 PM PST 24 |
| Finished | Feb 07 05:10:52 PM PST 24 |
| Peak memory | 603820 kb |
| Host | smart-941b70ed-88c2-474c-bff9-dad92ce69508 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117416272 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.1117416272 |
| Directory | /workspace/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1327984031 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 12853084896 ps |
| CPU time | 2230.91 seconds |
| Started | Feb 07 04:58:15 PM PST 24 |
| Finished | Feb 07 05:35:26 PM PST 24 |
| Peak memory | 613840 kb |
| Host | smart-1ce3c39c-d5ba-42bb-a06d-50d1f8fad4eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1327984031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.1327984031 |
| Directory | /workspace/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.339921625 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 13199187356 ps |
| CPU time | 2049.37 seconds |
| Started | Feb 07 04:58:37 PM PST 24 |
| Finished | Feb 07 05:32:48 PM PST 24 |
| Peak memory | 613800 kb |
| Host | smart-89d9f25b-b0d7-4c9b-a135-ab5304b5124b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=339921625 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.339921625 |
| Directory | /workspace/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.4249665252 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 14342036840 ps |
| CPU time | 2632.36 seconds |
| Started | Feb 07 04:59:12 PM PST 24 |
| Finished | Feb 07 05:43:08 PM PST 24 |
| Peak memory | 601784 kb |
| Host | smart-f5efb2d6-84c5-4ab9-ae01-42d2764b789f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4249665252 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.4249665252 |
| Directory | /workspace/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/17.chip_sw_all_escalation_resets.1030910944 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 4364892376 ps |
| CPU time | 571.87 seconds |
| Started | Feb 07 04:58:48 PM PST 24 |
| Finished | Feb 07 05:08:20 PM PST 24 |
| Peak memory | 635136 kb |
| Host | smart-686e291d-4285-4235-9e68-9df095d4cadf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1030910944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.1030910944 |
| Directory | /workspace/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1104910183 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 12830129824 ps |
| CPU time | 2305.39 seconds |
| Started | Feb 07 04:59:21 PM PST 24 |
| Finished | Feb 07 05:37:48 PM PST 24 |
| Peak memory | 601772 kb |
| Host | smart-45e99963-8212-48d1-a0b4-4f0e2e837c62 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1104910183 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.1104910183 |
| Directory | /workspace/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.2404556321 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 5171051008 ps |
| CPU time | 906.67 seconds |
| Started | Feb 07 04:59:05 PM PST 24 |
| Finished | Feb 07 05:14:12 PM PST 24 |
| Peak memory | 601824 kb |
| Host | smart-aacbd368-45b1-4c3e-a21b-6cbc4370e23d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2404556321 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.2404556321 |
| Directory | /workspace/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/19.chip_sw_all_escalation_resets.766517777 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 5611648846 ps |
| CPU time | 882.49 seconds |
| Started | Feb 07 04:59:36 PM PST 24 |
| Finished | Feb 07 05:14:19 PM PST 24 |
| Peak memory | 633864 kb |
| Host | smart-5287fd04-951f-4a48-b326-58f53f060dbc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 766517777 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.766517777 |
| Directory | /workspace/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.821579379 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 14287853180 ps |
| CPU time | 2176.58 seconds |
| Started | Feb 07 04:59:52 PM PST 24 |
| Finished | Feb 07 05:36:09 PM PST 24 |
| Peak memory | 613720 kb |
| Host | smart-76d7c366-4c52-426e-bd2e-4b49e14bf1e9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=821579379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.821579379 |
| Directory | /workspace/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_csr_rw.962095107 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 10111709312 ps |
| CPU time | 1409.46 seconds |
| Started | Feb 07 04:45:33 PM PST 24 |
| Finished | Feb 07 05:09:03 PM PST 24 |
| Peak memory | 585728 kb |
| Host | smart-317e7f1d-cde8-45bc-aa7d-fde206bfe0e2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962095107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.ch ip_jtag_csr_rw.962095107 |
| Directory | /workspace/2.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_mem_access.3700350157 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 13828503186 ps |
| CPU time | 1641.18 seconds |
| Started | Feb 07 04:46:17 PM PST 24 |
| Finished | Feb 07 05:13:39 PM PST 24 |
| Peak memory | 592944 kb |
| Host | smart-80a04118-7dfa-4255-bb7e-d1de92b49700 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700350157 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.3 700350157 |
| Directory | /workspace/2.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.2470987354 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 4152169392 ps |
| CPU time | 455.54 seconds |
| Started | Feb 07 04:53:21 PM PST 24 |
| Finished | Feb 07 05:00:57 PM PST 24 |
| Peak memory | 617444 kb |
| Host | smart-3e8f1fc2-4db9-4e4d-90fb-4d8b1ebb3bb2 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2 470987354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.2470987354 |
| Directory | /workspace/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sival_flash_info_access.1684075950 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 4095568300 ps |
| CPU time | 600.64 seconds |
| Started | Feb 07 04:48:21 PM PST 24 |
| Finished | Feb 07 04:58:22 PM PST 24 |
| Peak memory | 599040 kb |
| Host | smart-a2ae5445-d7e5-40b3-a36e-f5b5b6186aa8 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1684075950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.1684075950 |
| Directory | /workspace/2.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1141551017 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 19100657676 ps |
| CPU time | 738.28 seconds |
| Started | Feb 07 04:50:28 PM PST 24 |
| Finished | Feb 07 05:02:49 PM PST 24 |
| Peak memory | 615680 kb |
| Host | smart-c3dd8e26-cf79-4add-a6ff-de2fd42d6f05 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1141551017 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1141551017 |
| Directory | /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc.1091581832 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 2924125696 ps |
| CPU time | 360.85 seconds |
| Started | Feb 07 04:50:54 PM PST 24 |
| Finished | Feb 07 04:56:55 PM PST 24 |
| Peak memory | 600416 kb |
| Host | smart-0d18cc7c-81a6-4c46-9a09-f11c170d5d4f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091581832 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.1091581832 |
| Directory | /workspace/2.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.815314095 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 2698933374 ps |
| CPU time | 314.17 seconds |
| Started | Feb 07 04:49:38 PM PST 24 |
| Finished | Feb 07 04:54:53 PM PST 24 |
| Peak memory | 600480 kb |
| Host | smart-4e370439-c209-4249-aeb6-58f769d45790 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8153 14095 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.815314095 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2442783655 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 2970026941 ps |
| CPU time | 297.45 seconds |
| Started | Feb 07 04:53:46 PM PST 24 |
| Finished | Feb 07 04:58:44 PM PST 24 |
| Peak memory | 600460 kb |
| Host | smart-a2b48599-d8c1-44b8-be65-ea0f3bacf1eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442783655 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.2442783655 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_entropy.3311586352 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 2593704950 ps |
| CPU time | 273.88 seconds |
| Started | Feb 07 04:51:24 PM PST 24 |
| Finished | Feb 07 04:55:59 PM PST 24 |
| Peak memory | 600496 kb |
| Host | smart-d5620930-94e2-4b07-808c-0da2390819df |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311586352 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.3311586352 |
| Directory | /workspace/2.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_idle.1104282169 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 2388225100 ps |
| CPU time | 249.66 seconds |
| Started | Feb 07 04:50:00 PM PST 24 |
| Finished | Feb 07 04:54:10 PM PST 24 |
| Peak memory | 600428 kb |
| Host | smart-479a65ae-8e04-4e8f-a212-5e13a8bc1be9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104282169 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.1104282169 |
| Directory | /workspace/2.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_masking_off.2989608902 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 3027509623 ps |
| CPU time | 362.29 seconds |
| Started | Feb 07 04:51:04 PM PST 24 |
| Finished | Feb 07 04:57:07 PM PST 24 |
| Peak memory | 601032 kb |
| Host | smart-1f9e96d0-9fcd-4bae-9a38-4c7af12b6fa8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989608902 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.2989608902 |
| Directory | /workspace/2.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_smoketest.2279472957 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 2952648280 ps |
| CPU time | 333.62 seconds |
| Started | Feb 07 04:54:40 PM PST 24 |
| Finished | Feb 07 05:00:14 PM PST 24 |
| Peak memory | 600512 kb |
| Host | smart-46ed8bca-5e27-40e6-9b1e-e87a21693259 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279472957 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.2279472957 |
| Directory | /workspace/2.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_entropy.2307860643 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 3010236984 ps |
| CPU time | 335.05 seconds |
| Started | Feb 07 04:50:26 PM PST 24 |
| Finished | Feb 07 04:56:03 PM PST 24 |
| Peak memory | 598980 kb |
| Host | smart-d74100f2-8ef0-4363-8345-a7dfed99c420 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2307860643 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.2307860643 |
| Directory | /workspace/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_escalation.1487795493 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 4574304588 ps |
| CPU time | 609.09 seconds |
| Started | Feb 07 04:50:52 PM PST 24 |
| Finished | Feb 07 05:01:02 PM PST 24 |
| Peak memory | 605604 kb |
| Host | smart-09989fb4-4350-428e-8032-77bed8930dbf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1487795493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.1487795493 |
| Directory | /workspace/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3451566774 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 8958361942 ps |
| CPU time | 2167.18 seconds |
| Started | Feb 07 04:51:13 PM PST 24 |
| Finished | Feb 07 05:27:21 PM PST 24 |
| Peak memory | 601944 kb |
| Host | smart-7b805bba-bbd1-450f-ad08-6df804906f66 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3451566774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.3451566774 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3762950608 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 10765964994 ps |
| CPU time | 1128.9 seconds |
| Started | Feb 07 04:52:12 PM PST 24 |
| Finished | Feb 07 05:11:01 PM PST 24 |
| Peak memory | 602704 kb |
| Host | smart-f76a8b6c-98dc-4a76-967a-69f385c50c14 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762950608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.3762950608 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1617502616 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 4472154620 ps |
| CPU time | 442.21 seconds |
| Started | Feb 07 04:52:06 PM PST 24 |
| Finished | Feb 07 04:59:30 PM PST 24 |
| Peak memory | 601884 kb |
| Host | smart-651532ee-b9b5-498e-88c5-40894ef5b800 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1617502616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.1617502616 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.939056568 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 255404202568 ps |
| CPU time | 13095 seconds |
| Started | Feb 07 04:51:04 PM PST 24 |
| Finished | Feb 07 08:29:21 PM PST 24 |
| Peak memory | 602548 kb |
| Host | smart-f8db4f89-e2fb-4614-9949-a4a3a5ed67e1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=939056568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.939056568 |
| Directory | /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_test.1821445474 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 2227665466 ps |
| CPU time | 317.69 seconds |
| Started | Feb 07 04:51:59 PM PST 24 |
| Finished | Feb 07 04:57:18 PM PST 24 |
| Peak memory | 599388 kb |
| Host | smart-52b26039-e2cf-4c55-9143-848b6ca95122 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821445474 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_alert_test.1821445474 |
| Directory | /workspace/2.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_irq.4064844211 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 3828393496 ps |
| CPU time | 297.59 seconds |
| Started | Feb 07 04:49:46 PM PST 24 |
| Finished | Feb 07 04:54:44 PM PST 24 |
| Peak memory | 600460 kb |
| Host | smart-e6beac7c-e222-45c1-ab0c-4ace8294beee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064844211 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.4064844211 |
| Directory | /workspace/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3487101811 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 6530019652 ps |
| CPU time | 555.24 seconds |
| Started | Feb 07 04:50:39 PM PST 24 |
| Finished | Feb 07 04:59:57 PM PST 24 |
| Peak memory | 599932 kb |
| Host | smart-e6041591-1530-42cd-bd42-cc775793f36c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3487101811 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3487101811 |
| Directory | /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1734651892 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 3059245460 ps |
| CPU time | 276.84 seconds |
| Started | Feb 07 04:54:18 PM PST 24 |
| Finished | Feb 07 04:58:56 PM PST 24 |
| Peak memory | 599076 kb |
| Host | smart-cb3e382b-14e7-40b7-92a7-5d28890ee90a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734651892 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_aon_timer_smoketest.1734651892 |
| Directory | /workspace/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.550042451 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 9613890190 ps |
| CPU time | 1090.29 seconds |
| Started | Feb 07 04:49:28 PM PST 24 |
| Finished | Feb 07 05:07:39 PM PST 24 |
| Peak memory | 601360 kb |
| Host | smart-d404f0da-dbda-4d80-a929-29f73d25e3b5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 550042451 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.550042451 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.245918136 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 6175149552 ps |
| CPU time | 895.03 seconds |
| Started | Feb 07 04:50:08 PM PST 24 |
| Finished | Feb 07 05:05:04 PM PST 24 |
| Peak memory | 601384 kb |
| Host | smart-1aa2b6fe-dbc8-44a1-9ac2-0a088c765221 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =245918136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.245918136 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_outputs.109176516 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 7507776100 ps |
| CPU time | 1185.03 seconds |
| Started | Feb 07 04:53:32 PM PST 24 |
| Finished | Feb 07 05:13:21 PM PST 24 |
| Peak memory | 607828 kb |
| Host | smart-5b62454c-f59e-4689-a21b-bf417b95dcb8 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109176516 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.109176516 |
| Directory | /workspace/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.3656339886 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 13979775843 ps |
| CPU time | 938.24 seconds |
| Started | Feb 07 04:52:03 PM PST 24 |
| Finished | Feb 07 05:07:42 PM PST 24 |
| Peak memory | 604020 kb |
| Host | smart-14994e8d-7e16-4909-a9b4-7ec7b61a1b5c |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3656339886 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.3656339886 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.395979731 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 4000343772 ps |
| CPU time | 579.14 seconds |
| Started | Feb 07 04:51:57 PM PST 24 |
| Finished | Feb 07 05:01:39 PM PST 24 |
| Peak memory | 594644 kb |
| Host | smart-c47052d5-6182-4270-8648-1ece645a146b |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395979731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_fast_dev.395979731 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2886607731 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 4237845440 ps |
| CPU time | 634.44 seconds |
| Started | Feb 07 04:52:37 PM PST 24 |
| Finished | Feb 07 05:03:12 PM PST 24 |
| Peak memory | 594712 kb |
| Host | smart-d4389413-e74e-4e35-b4d6-80f1b1aeb4f4 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886607731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.2886607731 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4090062049 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 4050246448 ps |
| CPU time | 718.17 seconds |
| Started | Feb 07 04:52:48 PM PST 24 |
| Finished | Feb 07 05:04:47 PM PST 24 |
| Peak memory | 594604 kb |
| Host | smart-412eaf19-8f51-48e1-919a-54f17b049d6d |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090062049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4090062049 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2682022267 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 5258669400 ps |
| CPU time | 745.89 seconds |
| Started | Feb 07 04:53:07 PM PST 24 |
| Finished | Feb 07 05:05:33 PM PST 24 |
| Peak memory | 594716 kb |
| Host | smart-af000d44-37c8-48c3-81fe-40b28395cfe5 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682022267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.2682022267 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3096415680 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 4580306230 ps |
| CPU time | 586.07 seconds |
| Started | Feb 07 04:52:23 PM PST 24 |
| Finished | Feb 07 05:02:10 PM PST 24 |
| Peak memory | 594872 kb |
| Host | smart-ccab9b88-9b0e-47bb-b8da-fc56d508da3d |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096415680 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.3096415680 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.933754850 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 5332442872 ps |
| CPU time | 654.61 seconds |
| Started | Feb 07 04:52:09 PM PST 24 |
| Finished | Feb 07 05:03:05 PM PST 24 |
| Peak memory | 594880 kb |
| Host | smart-af75a43c-2b49-4fdd-9a5d-f58a1a6523a9 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933754850 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2. chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.933754850 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter.791505042 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 2713253595 ps |
| CPU time | 241.42 seconds |
| Started | Feb 07 04:54:04 PM PST 24 |
| Finished | Feb 07 04:58:07 PM PST 24 |
| Peak memory | 600492 kb |
| Host | smart-95bf8d94-ec79-4f1a-9115-59577be0598a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791505042 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_clkmgr_jitter.791505042 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2052486721 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 3397230936 ps |
| CPU time | 307.92 seconds |
| Started | Feb 07 04:52:55 PM PST 24 |
| Finished | Feb 07 04:58:04 PM PST 24 |
| Peak memory | 599088 kb |
| Host | smart-c63fdb44-863b-4a31-acfa-f84bb7b44ac3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052486721 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.2052486721 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3219477394 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 2518850232 ps |
| CPU time | 191.27 seconds |
| Started | Feb 07 04:52:46 PM PST 24 |
| Finished | Feb 07 04:55:58 PM PST 24 |
| Peak memory | 599148 kb |
| Host | smart-315188f2-aba6-44cc-9f29-759dda67784c |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219477394 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.3219477394 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3545241219 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 5759294708 ps |
| CPU time | 670.79 seconds |
| Started | Feb 07 04:52:11 PM PST 24 |
| Finished | Feb 07 05:03:22 PM PST 24 |
| Peak memory | 599928 kb |
| Host | smart-683636e9-a93f-4216-8460-79121715a5b0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545241219 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.3545241219 |
| Directory | /workspace/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3444679251 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 3933274450 ps |
| CPU time | 620.66 seconds |
| Started | Feb 07 04:52:53 PM PST 24 |
| Finished | Feb 07 05:03:14 PM PST 24 |
| Peak memory | 601004 kb |
| Host | smart-88d6103d-a94b-4c6a-8a5d-ee485a7e44ea |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444679251 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.3444679251 |
| Directory | /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.1989742465 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 3755111052 ps |
| CPU time | 501.76 seconds |
| Started | Feb 07 04:53:08 PM PST 24 |
| Finished | Feb 07 05:01:31 PM PST 24 |
| Peak memory | 601000 kb |
| Host | smart-621f2ea8-5186-4666-bcec-b0dd880bb3d5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989742465 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.1989742465 |
| Directory | /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3898943807 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 4906663368 ps |
| CPU time | 437.79 seconds |
| Started | Feb 07 04:52:00 PM PST 24 |
| Finished | Feb 07 04:59:21 PM PST 24 |
| Peak memory | 601308 kb |
| Host | smart-aecc9c92-7d9f-4cbc-b730-8c2619e1ae1f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898943807 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.3898943807 |
| Directory | /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.8990568 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 8246346152 ps |
| CPU time | 1192.79 seconds |
| Started | Feb 07 04:52:04 PM PST 24 |
| Finished | Feb 07 05:11:58 PM PST 24 |
| Peak memory | 601396 kb |
| Host | smart-00071b0f-7c95-46ae-a3f8-e1d81d510e1d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8990568 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.8990568 |
| Directory | /workspace/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2641015138 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 3704287282 ps |
| CPU time | 511.74 seconds |
| Started | Feb 07 04:53:50 PM PST 24 |
| Finished | Feb 07 05:02:23 PM PST 24 |
| Peak memory | 601048 kb |
| Host | smart-220d6dc4-96ae-4b48-95c3-ec28d38f82a8 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641015138 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.2641015138 |
| Directory | /workspace/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2226149190 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 4643330552 ps |
| CPU time | 740.75 seconds |
| Started | Feb 07 04:52:24 PM PST 24 |
| Finished | Feb 07 05:04:46 PM PST 24 |
| Peak memory | 600976 kb |
| Host | smart-fd0eb407-f028-4975-9366-380023a2ecfd |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226149190 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.2226149190 |
| Directory | /workspace/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.4262020979 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 2461459954 ps |
| CPU time | 203.86 seconds |
| Started | Feb 07 04:58:00 PM PST 24 |
| Finished | Feb 07 05:01:24 PM PST 24 |
| Peak memory | 600532 kb |
| Host | smart-9d37ce85-7e67-4acb-a831-3f1237abe85d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262020979 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_clkmgr_smoketest.4262020979 |
| Directory | /workspace/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1512117989 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 16626611656 ps |
| CPU time | 3822.63 seconds |
| Started | Feb 07 04:50:30 PM PST 24 |
| Finished | Feb 07 05:54:14 PM PST 24 |
| Peak memory | 601144 kb |
| Host | smart-2d4a6a97-e394-403f-855e-ab698cd5c595 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512117989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.1512117989 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.703262266 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 23178799886 ps |
| CPU time | 4025.09 seconds |
| Started | Feb 07 04:53:55 PM PST 24 |
| Finished | Feb 07 06:01:01 PM PST 24 |
| Peak memory | 601080 kb |
| Host | smart-f9f75998-741a-4aae-8e52-abb84ad2419f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=180_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703262266 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ csrng_edn_concurrency_reduced_freq.703262266 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1686973071 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 4787163050 ps |
| CPU time | 569.92 seconds |
| Started | Feb 07 04:52:32 PM PST 24 |
| Finished | Feb 07 05:02:03 PM PST 24 |
| Peak memory | 601628 kb |
| Host | smart-1b0ef2a1-920f-4958-871d-63e6526adb34 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16869 73071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.1686973071 |
| Directory | /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_kat_test.323994101 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 2948774596 ps |
| CPU time | 290.79 seconds |
| Started | Feb 07 04:50:40 PM PST 24 |
| Finished | Feb 07 04:55:33 PM PST 24 |
| Peak memory | 600512 kb |
| Host | smart-54860abb-6788-45ce-b3de-859b0746985f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323994101 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.323994101 |
| Directory | /workspace/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.980156867 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 10867587185 ps |
| CPU time | 937.88 seconds |
| Started | Feb 07 04:50:56 PM PST 24 |
| Finished | Feb 07 05:06:34 PM PST 24 |
| Peak memory | 602152 kb |
| Host | smart-5ba8c3a2-04c7-43d9-ad28-c12780c908df |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980156867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_l c_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrn g_lc_hw_debug_en_test.980156867 |
| Directory | /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_smoketest.869285607 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 2621630664 ps |
| CPU time | 174.44 seconds |
| Started | Feb 07 04:55:20 PM PST 24 |
| Finished | Feb 07 04:58:15 PM PST 24 |
| Peak memory | 600468 kb |
| Host | smart-e55c37e3-09ae-4bf3-ace4-dac61cbf956e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869285607 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_csrng_smoketest.869285607 |
| Directory | /workspace/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_data_integrity_escalation.2330613570 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 5415091784 ps |
| CPU time | 612.43 seconds |
| Started | Feb 07 04:53:05 PM PST 24 |
| Finished | Feb 07 05:03:18 PM PST 24 |
| Peak memory | 601960 kb |
| Host | smart-9d26f108-2be3-49f6-a6d3-2b907842f23b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2330613570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.2330613570 |
| Directory | /workspace/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_auto_mode.2117619806 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 4947036280 ps |
| CPU time | 1122.45 seconds |
| Started | Feb 07 04:52:15 PM PST 24 |
| Finished | Feb 07 05:11:01 PM PST 24 |
| Peak memory | 601088 kb |
| Host | smart-a85a08f1-d955-4d18-85b3-3e13d6a6ecd3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117619806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ auto_mode.2117619806 |
| Directory | /workspace/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_boot_mode.607241453 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 3224439560 ps |
| CPU time | 547.02 seconds |
| Started | Feb 07 04:50:51 PM PST 24 |
| Finished | Feb 07 04:59:59 PM PST 24 |
| Peak memory | 600696 kb |
| Host | smart-a8ee9bde-bef5-4db7-98ba-50c79fb0f5d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607241453 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_b oot_mode.607241453 |
| Directory | /workspace/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1519183943 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 4930734040 ps |
| CPU time | 734.72 seconds |
| Started | Feb 07 04:52:08 PM PST 24 |
| Finished | Feb 07 05:04:24 PM PST 24 |
| Peak memory | 599804 kb |
| Host | smart-7ca784e1-5956-4ce7-8c7d-66990873bce2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1519183943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.1519183943 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.522324412 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 4993691706 ps |
| CPU time | 904.51 seconds |
| Started | Feb 07 04:53:09 PM PST 24 |
| Finished | Feb 07 05:08:15 PM PST 24 |
| Peak memory | 601128 kb |
| Host | smart-4a88cd48-93f3-4b1d-8068-aaf481df7c56 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522324412 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.522324412 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_kat.1645954128 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 3443611368 ps |
| CPU time | 767.4 seconds |
| Started | Feb 07 04:52:33 PM PST 24 |
| Finished | Feb 07 05:05:21 PM PST 24 |
| Peak memory | 606976 kb |
| Host | smart-102cfdd9-476f-4180-a5ed-0e46cbb87214 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645954128 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_edn_kat.1645954128 |
| Directory | /workspace/2.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_sw_mode.4271628202 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 6697924208 ps |
| CPU time | 1313.22 seconds |
| Started | Feb 07 04:52:37 PM PST 24 |
| Finished | Feb 07 05:14:31 PM PST 24 |
| Peak memory | 599496 kb |
| Host | smart-cd27b4e8-14d1-410c-91f5-b6dd8f67197d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271628202 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.4271628202 |
| Directory | /workspace/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2499817418 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 3296020936 ps |
| CPU time | 261.5 seconds |
| Started | Feb 07 04:50:52 PM PST 24 |
| Finished | Feb 07 04:55:14 PM PST 24 |
| Peak memory | 600432 kb |
| Host | smart-5cf16928-74cd-4833-87ef-9c234480c608 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24 99817418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.2499817418 |
| Directory | /workspace/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_csrng.3432530140 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 7204072640 ps |
| CPU time | 1573.87 seconds |
| Started | Feb 07 04:52:16 PM PST 24 |
| Finished | Feb 07 05:18:32 PM PST 24 |
| Peak memory | 599780 kb |
| Host | smart-cc1039ab-b493-4e5c-af7e-b81e495e0491 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3432530140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.3432530140 |
| Directory | /workspace/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.816634734 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 2485444900 ps |
| CPU time | 190.05 seconds |
| Started | Feb 07 04:51:13 PM PST 24 |
| Finished | Feb 07 04:54:23 PM PST 24 |
| Peak memory | 599152 kb |
| Host | smart-494509b6-3e03-4a19-98b3-b08dd20fe534 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816634734 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.816634734 |
| Directory | /workspace/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.2662859722 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 3431913018 ps |
| CPU time | 439.16 seconds |
| Started | Feb 07 04:58:01 PM PST 24 |
| Finished | Feb 07 05:05:20 PM PST 24 |
| Peak memory | 599132 kb |
| Host | smart-2308e178-30b8-4aa7-9b54-37770d61ce42 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2662859722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.2662859722 |
| Directory | /workspace/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_concurrency.2159873376 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 2833853140 ps |
| CPU time | 309.5 seconds |
| Started | Feb 07 04:47:16 PM PST 24 |
| Finished | Feb 07 04:52:26 PM PST 24 |
| Peak memory | 600464 kb |
| Host | smart-309ffadb-102d-419e-9202-050cf80bc3a3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159873376 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_example_concurrency.2159873376 |
| Directory | /workspace/2.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_flash.2356992626 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 2458062240 ps |
| CPU time | 186.76 seconds |
| Started | Feb 07 04:52:35 PM PST 24 |
| Finished | Feb 07 04:55:44 PM PST 24 |
| Peak memory | 600504 kb |
| Host | smart-fca48d95-94f8-4f60-a067-1e543174ba18 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356992626 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.2356992626 |
| Directory | /workspace/2.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_manufacturer.3502475681 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 3267843110 ps |
| CPU time | 172.77 seconds |
| Started | Feb 07 04:48:31 PM PST 24 |
| Finished | Feb 07 04:51:25 PM PST 24 |
| Peak memory | 600496 kb |
| Host | smart-d8d04dd5-cd31-4ef9-932b-2499cbfac423 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502475681 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.3502475681 |
| Directory | /workspace/2.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_rom.1430270878 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 2370187310 ps |
| CPU time | 125.09 seconds |
| Started | Feb 07 04:46:46 PM PST 24 |
| Finished | Feb 07 04:48:52 PM PST 24 |
| Peak memory | 599064 kb |
| Host | smart-8c8a414e-618a-462a-af8e-1d7d03f508f3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430270878 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_rom.1430270878 |
| Directory | /workspace/2.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1183216611 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 59218680679 ps |
| CPU time | 11196.3 seconds |
| Started | Feb 07 04:48:15 PM PST 24 |
| Finished | Feb 07 07:54:53 PM PST 24 |
| Peak memory | 614992 kb |
| Host | smart-45e8b823-a012-44c3-9fb6-56c34fe6c48a |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1183216611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.1183216611 |
| Directory | /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_crash_alert.1764788717 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 4977095912 ps |
| CPU time | 859.57 seconds |
| Started | Feb 07 04:53:20 PM PST 24 |
| Finished | Feb 07 05:07:40 PM PST 24 |
| Peak memory | 600972 kb |
| Host | smart-f6de7a63-ed00-4fb1-ad57-8599701fe384 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=1764788717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.1764788717 |
| Directory | /workspace/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access.3970830373 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 5386740596 ps |
| CPU time | 1020.95 seconds |
| Started | Feb 07 04:48:30 PM PST 24 |
| Finished | Feb 07 05:05:31 PM PST 24 |
| Peak memory | 600860 kb |
| Host | smart-437338bc-8152-4e9f-b9aa-9af6be5f4833 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970830373 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_flash_ctrl_access.3970830373 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3297250581 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 6368084902 ps |
| CPU time | 1318.01 seconds |
| Started | Feb 07 04:47:52 PM PST 24 |
| Finished | Feb 07 05:09:51 PM PST 24 |
| Peak memory | 600836 kb |
| Host | smart-b618e097-c434-4abc-99ea-29465099a299 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297250581 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.3297250581 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.256564983 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 7463974922 ps |
| CPU time | 1048.08 seconds |
| Started | Feb 07 04:53:01 PM PST 24 |
| Finished | Feb 07 05:10:30 PM PST 24 |
| Peak memory | 599492 kb |
| Host | smart-7fc3d77e-7633-497d-8f44-d75d05705bf6 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256564983 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.256564983 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2828744940 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 5701220380 ps |
| CPU time | 1367.32 seconds |
| Started | Feb 07 04:48:41 PM PST 24 |
| Finished | Feb 07 05:11:32 PM PST 24 |
| Peak memory | 599476 kb |
| Host | smart-b63b5693-b9c3-4671-9f4f-b8704ae64b38 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828744940 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.2828744940 |
| Directory | /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2106558939 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 3422806046 ps |
| CPU time | 430.14 seconds |
| Started | Feb 07 04:48:47 PM PST 24 |
| Finished | Feb 07 04:55:58 PM PST 24 |
| Peak memory | 600656 kb |
| Host | smart-3033d303-da75-4751-b29b-81d66706262e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106558939 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.2106558939 |
| Directory | /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.526688690 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 5771306320 ps |
| CPU time | 565.08 seconds |
| Started | Feb 07 04:49:13 PM PST 24 |
| Finished | Feb 07 04:58:39 PM PST 24 |
| Peak memory | 600260 kb |
| Host | smart-fb06ae85-289b-49f5-b24c-28b64ffe37a3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52 6688690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.526688690 |
| Directory | /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.876273923 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 5832260584 ps |
| CPU time | 1212.35 seconds |
| Started | Feb 07 04:55:17 PM PST 24 |
| Finished | Feb 07 05:15:32 PM PST 24 |
| Peak memory | 600820 kb |
| Host | smart-bdb620bd-4975-4d42-88ed-3336e7be77fe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876273923 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.876273923 |
| Directory | /workspace/2.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1450879412 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 5081981994 ps |
| CPU time | 1002.74 seconds |
| Started | Feb 07 04:47:40 PM PST 24 |
| Finished | Feb 07 05:04:24 PM PST 24 |
| Peak memory | 600972 kb |
| Host | smart-fcd26193-b62b-45a5-ac4c-bca7fc0cd0ea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450879412 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.1450879412 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.562743690 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 6674475314 ps |
| CPU time | 693.67 seconds |
| Started | Feb 07 04:53:42 PM PST 24 |
| Finished | Feb 07 05:05:17 PM PST 24 |
| Peak memory | 600936 kb |
| Host | smart-2b8f7704-e460-4375-9115-60d29275cb8e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=562743690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.562743690 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init.279697160 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 20938008550 ps |
| CPU time | 2147.67 seconds |
| Started | Feb 07 04:47:48 PM PST 24 |
| Finished | Feb 07 05:23:37 PM PST 24 |
| Peak memory | 602304 kb |
| Host | smart-366fb795-9704-4b33-a5a5-f0933edf6221 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279697160 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.279697160 |
| Directory | /workspace/2.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.1750930498 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 20365314641 ps |
| CPU time | 1645.25 seconds |
| Started | Feb 07 04:53:29 PM PST 24 |
| Finished | Feb 07 05:20:56 PM PST 24 |
| Peak memory | 602328 kb |
| Host | smart-ad5d7130-9968-4ffd-af1f-18fedd26ab9a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1750930498 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.1750930498 |
| Directory | /workspace/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2150507971 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 2509031100 ps |
| CPU time | 178.83 seconds |
| Started | Feb 07 04:58:52 PM PST 24 |
| Finished | Feb 07 05:01:55 PM PST 24 |
| Peak memory | 599448 kb |
| Host | smart-9e576442-8eac-4d3e-9eff-ee6b5a089e36 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2150507971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.2150507971 |
| Directory | /workspace/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio_smoketest.2715783274 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 3337754914 ps |
| CPU time | 357.39 seconds |
| Started | Feb 07 04:55:33 PM PST 24 |
| Finished | Feb 07 05:01:32 PM PST 24 |
| Peak memory | 600764 kb |
| Host | smart-4919cf61-aae9-4590-a456-2c0d6ec00db2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715783274 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_gpio_smoketest.2715783274 |
| Directory | /workspace/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc.1410007771 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 3071607182 ps |
| CPU time | 289.95 seconds |
| Started | Feb 07 04:51:46 PM PST 24 |
| Finished | Feb 07 04:56:37 PM PST 24 |
| Peak memory | 599112 kb |
| Host | smart-46678d46-0982-4f6d-b450-9ec973b14048 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410007771 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.1410007771 |
| Directory | /workspace/2.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_idle.880511021 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 3027257972 ps |
| CPU time | 297.52 seconds |
| Started | Feb 07 04:51:48 PM PST 24 |
| Finished | Feb 07 04:56:46 PM PST 24 |
| Peak memory | 599108 kb |
| Host | smart-ac1346d7-4d93-4080-a79d-53ebb52b82c8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880511021 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_hmac_enc_idle.880511021 |
| Directory | /workspace/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.267573821 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 3647404153 ps |
| CPU time | 347.9 seconds |
| Started | Feb 07 04:51:20 PM PST 24 |
| Finished | Feb 07 04:57:08 PM PST 24 |
| Peak memory | 600376 kb |
| Host | smart-1b426de8-32a7-4c43-83dd-7b9164b2859b |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267573821 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.267573821 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3596258225 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 2969051351 ps |
| CPU time | 298.03 seconds |
| Started | Feb 07 04:53:45 PM PST 24 |
| Finished | Feb 07 04:58:43 PM PST 24 |
| Peak memory | 600536 kb |
| Host | smart-4fc3cb41-13e3-4603-811c-67b79c6230ca |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596258225 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.3596258225 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_smoketest.1923561428 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 3296978598 ps |
| CPU time | 397.49 seconds |
| Started | Feb 07 04:54:57 PM PST 24 |
| Finished | Feb 07 05:01:35 PM PST 24 |
| Peak memory | 600544 kb |
| Host | smart-5f9056b5-8913-4660-93a5-a6b1dc89265e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923561428 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_hmac_smoketest.1923561428 |
| Directory | /workspace/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1375877099 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 4123077802 ps |
| CPU time | 726.37 seconds |
| Started | Feb 07 04:48:52 PM PST 24 |
| Finished | Feb 07 05:01:00 PM PST 24 |
| Peak memory | 600652 kb |
| Host | smart-0ad1eb45-97b3-4831-b45f-4fc8cf2958da |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375877099 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.1375877099 |
| Directory | /workspace/2.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.30476117 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 5752923092 ps |
| CPU time | 919.8 seconds |
| Started | Feb 07 04:48:33 PM PST 24 |
| Finished | Feb 07 05:03:56 PM PST 24 |
| Peak memory | 601052 kb |
| Host | smart-da3d0341-575f-4015-a3ea-9f7e7e297e4c |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30476117 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.30476117 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3665875335 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 5445479540 ps |
| CPU time | 1101.34 seconds |
| Started | Feb 07 04:48:57 PM PST 24 |
| Finished | Feb 07 05:07:20 PM PST 24 |
| Peak memory | 601072 kb |
| Host | smart-50ba505d-5ffe-4d48-9e1a-65ad4c4dcfb6 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665875335 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.3665875335 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.118376059 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 6150419716 ps |
| CPU time | 952.56 seconds |
| Started | Feb 07 04:48:03 PM PST 24 |
| Finished | Feb 07 05:03:57 PM PST 24 |
| Peak memory | 601072 kb |
| Host | smart-590577f2-a809-4d85-a88d-a750d50d82fc |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118376059 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.118376059 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_inject_scramble_seed.2471856830 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 65356387811 ps |
| CPU time | 11847.9 seconds |
| Started | Feb 07 04:48:58 PM PST 24 |
| Finished | Feb 07 08:06:28 PM PST 24 |
| Peak memory | 616928 kb |
| Host | smart-55e59a5a-3336-4a2d-8a5b-7a2061619de9 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2471856830 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.2471856830 |
| Directory | /workspace/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2311391988 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 5216400144 ps |
| CPU time | 595.58 seconds |
| Started | Feb 07 04:50:57 PM PST 24 |
| Finished | Feb 07 05:00:53 PM PST 24 |
| Peak memory | 608508 kb |
| Host | smart-b3ff5643-7f26-4cf0-ad56-eaf2ad7bba48 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311 391988 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.2311391988 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3316931013 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 4349245928 ps |
| CPU time | 661.58 seconds |
| Started | Feb 07 04:51:07 PM PST 24 |
| Finished | Feb 07 05:02:09 PM PST 24 |
| Peak memory | 608576 kb |
| Host | smart-ac690291-f76b-4be0-9a02-c5b8397d25d4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3316931013 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.3316931013 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1233040713 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 4330214948 ps |
| CPU time | 461.46 seconds |
| Started | Feb 07 04:54:28 PM PST 24 |
| Finished | Feb 07 05:02:10 PM PST 24 |
| Peak memory | 607148 kb |
| Host | smart-390e4ec8-2695-4a18-b78b-49283f7282b6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1233040713 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.1233040713 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.303911042 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 3414918593 ps |
| CPU time | 393.56 seconds |
| Started | Feb 07 04:51:58 PM PST 24 |
| Finished | Feb 07 04:58:34 PM PST 24 |
| Peak memory | 608196 kb |
| Host | smart-1561646d-8bcc-426e-9fc4-d039709a5a29 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=303911042 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.303911042 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.1393535895 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 4980230984 ps |
| CPU time | 528.25 seconds |
| Started | Feb 07 04:51:07 PM PST 24 |
| Finished | Feb 07 04:59:55 PM PST 24 |
| Peak memory | 601988 kb |
| Host | smart-f777e37f-85fa-4a17-8820-73a52c9e7026 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139353 5895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.1393535895 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.247129039 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 3802433828 ps |
| CPU time | 471.44 seconds |
| Started | Feb 07 04:51:54 PM PST 24 |
| Finished | Feb 07 04:59:47 PM PST 24 |
| Peak memory | 600512 kb |
| Host | smart-4e0511db-9846-425c-9097-c33e41687e01 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24712 9039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.247129039 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3597894691 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 18510380904 ps |
| CPU time | 4273.01 seconds |
| Started | Feb 07 04:52:07 PM PST 24 |
| Finished | Feb 07 06:03:21 PM PST 24 |
| Peak memory | 601692 kb |
| Host | smart-415325d8-1c48-4f3c-a279-ec84cc5eed7e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35978 94691 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.3597894691 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_app_rom.3211299416 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 3079809336 ps |
| CPU time | 213.45 seconds |
| Started | Feb 07 04:51:55 PM PST 24 |
| Finished | Feb 07 04:55:29 PM PST 24 |
| Peak memory | 600508 kb |
| Host | smart-0472e83e-bbde-4960-b606-a6ae40452c10 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211299416 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_app_rom.3211299416 |
| Directory | /workspace/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_entropy.619793059 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 2876586328 ps |
| CPU time | 309.76 seconds |
| Started | Feb 07 04:48:53 PM PST 24 |
| Finished | Feb 07 04:54:04 PM PST 24 |
| Peak memory | 600592 kb |
| Host | smart-6ea368ba-7d5c-4150-86c8-2abe50ff8fc9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619793059 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_kmac_entropy.619793059 |
| Directory | /workspace/2.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_idle.1850584496 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 2287663900 ps |
| CPU time | 228.61 seconds |
| Started | Feb 07 04:53:13 PM PST 24 |
| Finished | Feb 07 04:57:02 PM PST 24 |
| Peak memory | 600548 kb |
| Host | smart-638f8da2-34e8-4d3f-8759-a9e9aa394883 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850584496 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_idle.1850584496 |
| Directory | /workspace/2.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.498702078 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 2944741642 ps |
| CPU time | 255.59 seconds |
| Started | Feb 07 04:51:41 PM PST 24 |
| Finished | Feb 07 04:55:58 PM PST 24 |
| Peak memory | 600532 kb |
| Host | smart-5c5efd9f-d1e8-4749-90da-f3bb1f0cf486 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498702078 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_kmac_mode_cshake.498702078 |
| Directory | /workspace/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2539828040 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 3218075640 ps |
| CPU time | 313.52 seconds |
| Started | Feb 07 04:51:30 PM PST 24 |
| Finished | Feb 07 04:56:44 PM PST 24 |
| Peak memory | 600512 kb |
| Host | smart-a239077b-0426-486c-8180-ed5dd56a0b42 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539828040 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_kmac_mode_kmac.2539828040 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1961392135 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 3136397672 ps |
| CPU time | 432.34 seconds |
| Started | Feb 07 04:51:49 PM PST 24 |
| Finished | Feb 07 04:59:02 PM PST 24 |
| Peak memory | 600404 kb |
| Host | smart-c99fbcd2-e5d6-4910-addc-6f864c62244b |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961392135 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.1961392135 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3739433824 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 2564080493 ps |
| CPU time | 253.37 seconds |
| Started | Feb 07 04:53:36 PM PST 24 |
| Finished | Feb 07 04:57:50 PM PST 24 |
| Peak memory | 600584 kb |
| Host | smart-09ae25da-ef92-4c7f-92e1-8d50ee600b26 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37394338 24 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3739433824 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_smoketest.3908916053 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 2451657896 ps |
| CPU time | 290.84 seconds |
| Started | Feb 07 04:56:19 PM PST 24 |
| Finished | Feb 07 05:01:10 PM PST 24 |
| Peak memory | 600564 kb |
| Host | smart-180aa826-162c-4e4b-ac56-bb74606fedd6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908916053 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_smoketest.3908916053 |
| Directory | /workspace/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1331320481 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 2782433860 ps |
| CPU time | 389.04 seconds |
| Started | Feb 07 04:49:09 PM PST 24 |
| Finished | Feb 07 04:55:39 PM PST 24 |
| Peak memory | 599012 kb |
| Host | smart-450e6392-c7a4-4e73-aa5c-11ee94edf1a3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331320481 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.1331320481 |
| Directory | /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.3913662022 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 4425127956 ps |
| CPU time | 409.04 seconds |
| Started | Feb 07 04:55:15 PM PST 24 |
| Finished | Feb 07 05:02:05 PM PST 24 |
| Peak memory | 616092 kb |
| Host | smart-e03a2f56-b595-4c65-b932-cefcd74e9258 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3913662022 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.3913662022 |
| Directory | /workspace/2.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.4237784547 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 3092186765 ps |
| CPU time | 307.2 seconds |
| Started | Feb 07 04:49:32 PM PST 24 |
| Finished | Feb 07 04:54:40 PM PST 24 |
| Peak memory | 604128 kb |
| Host | smart-1e6671bd-8c43-4a17-862f-2fc6784a9077 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42377845 47 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.4237784547 |
| Directory | /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.1935717852 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 5423619917 ps |
| CPU time | 533.06 seconds |
| Started | Feb 07 04:47:43 PM PST 24 |
| Finished | Feb 07 04:56:36 PM PST 24 |
| Peak memory | 603972 kb |
| Host | smart-76677366-542f-41bf-bd7d-4a94048aedf0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935717852 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.1935717852 |
| Directory | /workspace/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1489307750 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 6059580540 ps |
| CPU time | 313.81 seconds |
| Started | Feb 07 04:49:14 PM PST 24 |
| Finished | Feb 07 04:54:28 PM PST 24 |
| Peak memory | 605616 kb |
| Host | smart-1cf52dc3-a682-49b9-a969-74f9745135c0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1489307750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.1489307750 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1800665959 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 4614731702 ps |
| CPU time | 273.71 seconds |
| Started | Feb 07 04:49:22 PM PST 24 |
| Finished | Feb 07 04:53:56 PM PST 24 |
| Peak memory | 606792 kb |
| Host | smart-a63721ba-08ad-46eb-ac55-a2f751b00601 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=lc_ctrl_volat ile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800665959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_ unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_vol atile_raw_unlock_ext_clk_48mhz.1800665959 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1550871159 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 9191603240 ps |
| CPU time | 1170.51 seconds |
| Started | Feb 07 04:49:34 PM PST 24 |
| Finished | Feb 07 05:09:06 PM PST 24 |
| Peak memory | 607120 kb |
| Host | smart-8ad7acec-ade6-40da-837f-db12ff9351c5 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550871159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.1550871159 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.501172086 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 25809871070 ps |
| CPU time | 1832.69 seconds |
| Started | Feb 07 04:48:31 PM PST 24 |
| Finished | Feb 07 05:19:05 PM PST 24 |
| Peak memory | 608160 kb |
| Host | smart-ef6a79d9-ee4d-4337-a24e-3043c1baae17 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=501172086 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testunl ocks.501172086 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3281723411 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 17212139992 ps |
| CPU time | 3475.14 seconds |
| Started | Feb 07 04:50:29 PM PST 24 |
| Finished | Feb 07 05:48:26 PM PST 24 |
| Peak memory | 601104 kb |
| Host | smart-adb8245d-913d-4163-a951-562c2b286b72 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3281723411 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.3281723411 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1177952741 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 18758937111 ps |
| CPU time | 3211.09 seconds |
| Started | Feb 07 04:50:41 PM PST 24 |
| Finished | Feb 07 05:44:13 PM PST 24 |
| Peak memory | 601100 kb |
| Host | smart-fa6b3cca-6608-4b50-96bb-a5788773ee24 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1177952741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1177952741 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3272208613 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 24223916199 ps |
| CPU time | 4216.75 seconds |
| Started | Feb 07 04:53:28 PM PST 24 |
| Finished | Feb 07 06:03:45 PM PST 24 |
| Peak memory | 599736 kb |
| Host | smart-b348188b-35ee-4b39-a5a4-4663518f1de4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272208613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.3272208613 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.4075176199 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 2798417074 ps |
| CPU time | 395.49 seconds |
| Started | Feb 07 04:49:57 PM PST 24 |
| Finished | Feb 07 04:56:33 PM PST 24 |
| Peak memory | 600516 kb |
| Host | smart-675f1380-036b-4b8e-81be-f50d7307a8ee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075176199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.4075176199 |
| Directory | /workspace/2.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_randomness.532893305 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 6048158600 ps |
| CPU time | 1205.55 seconds |
| Started | Feb 07 04:50:35 PM PST 24 |
| Finished | Feb 07 05:10:42 PM PST 24 |
| Peak memory | 601100 kb |
| Host | smart-6c07befd-3861-406c-a539-8384df10dd93 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=532893305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.532893305 |
| Directory | /workspace/2.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_smoketest.2959088420 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 5947891350 ps |
| CPU time | 1050.92 seconds |
| Started | Feb 07 04:57:59 PM PST 24 |
| Finished | Feb 07 05:15:31 PM PST 24 |
| Peak memory | 601108 kb |
| Host | smart-bfd57d3b-55c3-475d-9169-9f59b1fe9f0a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959088420 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_otbn_smoketest.2959088420 |
| Directory | /workspace/2.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3315277414 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 6853022640 ps |
| CPU time | 1217.12 seconds |
| Started | Feb 07 04:49:33 PM PST 24 |
| Finished | Feb 07 05:09:51 PM PST 24 |
| Peak memory | 600116 kb |
| Host | smart-7b52cfb2-ca06-45ac-9cc7-c77da79f7405 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3315277414 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.3315277414 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.880665642 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 8088434824 ps |
| CPU time | 1176.79 seconds |
| Started | Feb 07 04:49:29 PM PST 24 |
| Finished | Feb 07 05:09:07 PM PST 24 |
| Peak memory | 601468 kb |
| Host | smart-7df839b3-02ac-45d8-b41e-675705af1631 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=880665642 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.880665642 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3950853347 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 8723082016 ps |
| CPU time | 1136.73 seconds |
| Started | Feb 07 04:49:22 PM PST 24 |
| Finished | Feb 07 05:08:20 PM PST 24 |
| Peak memory | 601484 kb |
| Host | smart-5d97f4cd-b2f8-4a78-aae8-791fe14645f7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3950853347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.3950853347 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1636510637 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 5777972188 ps |
| CPU time | 800.57 seconds |
| Started | Feb 07 04:48:47 PM PST 24 |
| Finished | Feb 07 05:02:09 PM PST 24 |
| Peak memory | 600888 kb |
| Host | smart-4f90b387-f02a-4991-90ec-08fbf10acf3e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1636510637 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1636510637 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.299534609 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 2925106972 ps |
| CPU time | 320.1 seconds |
| Started | Feb 07 04:56:42 PM PST 24 |
| Finished | Feb 07 05:02:03 PM PST 24 |
| Peak memory | 600468 kb |
| Host | smart-4a951253-9899-47c8-96a9-34dd4c2eb11c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299534609 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_otp_ctrl_smoketest.299534609 |
| Directory | /workspace/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pattgen_ios.3903319789 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 2188936920 ps |
| CPU time | 180.4 seconds |
| Started | Feb 07 04:47:45 PM PST 24 |
| Finished | Feb 07 04:50:46 PM PST 24 |
| Peak memory | 597432 kb |
| Host | smart-2284661d-3267-43c5-a4b8-2fdccb8d4bc8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903319789 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.3903319789 |
| Directory | /workspace/2.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/2.chip_sw_plic_sw_irq.1350013273 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 3222801646 ps |
| CPU time | 200.59 seconds |
| Started | Feb 07 04:51:33 PM PST 24 |
| Finished | Feb 07 04:54:54 PM PST 24 |
| Peak memory | 599112 kb |
| Host | smart-cb54b667-2ddb-4814-b58b-d8ed76868516 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350013273 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_plic_sw_irq.1350013273 |
| Directory | /workspace/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_idle_load.2384276830 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 4305835080 ps |
| CPU time | 608.34 seconds |
| Started | Feb 07 04:53:23 PM PST 24 |
| Finished | Feb 07 05:03:32 PM PST 24 |
| Peak memory | 601208 kb |
| Host | smart-181f2bb2-fb29-4236-99de-51956dc9cd3c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384276830 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.2384276830 |
| Directory | /workspace/2.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_sleep_load.3994670793 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 10575371832 ps |
| CPU time | 688.36 seconds |
| Started | Feb 07 04:53:18 PM PST 24 |
| Finished | Feb 07 05:04:47 PM PST 24 |
| Peak memory | 601848 kb |
| Host | smart-e3e8d6cb-6820-4c3c-b689-48e2ac0696a5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994670793 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.3994670793 |
| Directory | /workspace/2.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1349709777 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 10316654151 ps |
| CPU time | 1522.38 seconds |
| Started | Feb 07 04:48:44 PM PST 24 |
| Finished | Feb 07 05:14:08 PM PST 24 |
| Peak memory | 600964 kb |
| Host | smart-b023b918-dde6-4ef6-8602-df22bd5984be |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349 709777 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.1349709777 |
| Directory | /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.640955342 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 22291556201 ps |
| CPU time | 1618.06 seconds |
| Started | Feb 07 04:51:40 PM PST 24 |
| Finished | Feb 07 05:18:39 PM PST 24 |
| Peak memory | 601732 kb |
| Host | smart-3bb9b1dc-d3fe-403e-9c39-a8d66f4ee8c1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640 955342 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.640955342 |
| Directory | /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2197776790 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 12450995724 ps |
| CPU time | 1407.66 seconds |
| Started | Feb 07 04:49:45 PM PST 24 |
| Finished | Feb 07 05:13:13 PM PST 24 |
| Peak memory | 601056 kb |
| Host | smart-4df732fb-7f7e-4196-8996-be8e9c07455d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2197776790 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2197776790 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4179494629 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 22807008250 ps |
| CPU time | 1778.55 seconds |
| Started | Feb 07 04:53:14 PM PST 24 |
| Finished | Feb 07 05:22:53 PM PST 24 |
| Peak memory | 600488 kb |
| Host | smart-9eab719e-8d26-4a84-92ec-488f524812f7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4179494629 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4179494629 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2018592518 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 5505532108 ps |
| CPU time | 379.33 seconds |
| Started | Feb 07 04:51:03 PM PST 24 |
| Finished | Feb 07 04:57:23 PM PST 24 |
| Peak memory | 606508 kb |
| Host | smart-64a1d3b6-5dff-4eae-a91a-4904c6c93819 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2018592518 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2018592518 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.318234285 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 8153054320 ps |
| CPU time | 596.21 seconds |
| Started | Feb 07 04:49:30 PM PST 24 |
| Finished | Feb 07 04:59:27 PM PST 24 |
| Peak memory | 601560 kb |
| Host | smart-3081fbe3-b3ef-479f-bb17-9c1aff56b6c6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318234285 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.318234285 |
| Directory | /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3664655971 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 4338737900 ps |
| CPU time | 317.47 seconds |
| Started | Feb 07 04:49:23 PM PST 24 |
| Finished | Feb 07 04:54:41 PM PST 24 |
| Peak memory | 606684 kb |
| Host | smart-eff6cc00-6767-4e0f-a8e0-f46ce9369654 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3664655971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.3664655971 |
| Directory | /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1421349201 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 10152971031 ps |
| CPU time | 1449.08 seconds |
| Started | Feb 07 04:49:42 PM PST 24 |
| Finished | Feb 07 05:13:52 PM PST 24 |
| Peak memory | 602448 kb |
| Host | smart-97b74c7a-fbc7-44c7-ae46-5b51ecd82e7f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421349201 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1421349201 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1381270557 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 6673279076 ps |
| CPU time | 376.75 seconds |
| Started | Feb 07 04:53:33 PM PST 24 |
| Finished | Feb 07 04:59:52 PM PST 24 |
| Peak memory | 601328 kb |
| Host | smart-d46c4062-910d-4bef-86a5-e321540ec881 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381270557 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1381270557 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2774495969 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 7033661025 ps |
| CPU time | 462.28 seconds |
| Started | Feb 07 04:50:58 PM PST 24 |
| Finished | Feb 07 04:58:41 PM PST 24 |
| Peak memory | 600356 kb |
| Host | smart-a61a832f-6f0c-45c2-a265-e887084ffdb1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774495969 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.2774495969 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4209005379 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 20022754647 ps |
| CPU time | 2005.42 seconds |
| Started | Feb 07 04:48:32 PM PST 24 |
| Finished | Feb 07 05:21:58 PM PST 24 |
| Peak memory | 601076 kb |
| Host | smart-e65541e6-a8e1-46e5-aafc-149795266942 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4209005379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4209005379 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1972217185 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 21958317656 ps |
| CPU time | 1946.05 seconds |
| Started | Feb 07 04:52:38 PM PST 24 |
| Finished | Feb 07 05:25:05 PM PST 24 |
| Peak memory | 601844 kb |
| Host | smart-cf724179-8146-49cd-a7e0-0cc865703a48 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1972217185 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1972217185 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4093486606 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 33075843190 ps |
| CPU time | 3031.32 seconds |
| Started | Feb 07 04:49:43 PM PST 24 |
| Finished | Feb 07 05:40:15 PM PST 24 |
| Peak memory | 604456 kb |
| Host | smart-5d374e7f-3e41-439c-84af-65cb401f9654 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093486606 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_s leep_power_glitch_reset.4093486606 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2961541770 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 5763230410 ps |
| CPU time | 532.04 seconds |
| Started | Feb 07 04:52:56 PM PST 24 |
| Finished | Feb 07 05:01:49 PM PST 24 |
| Peak memory | 602092 kb |
| Host | smart-5727b724-a328-4de6-b882-7d7073ad1b3e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2961541770 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.2961541770 |
| Directory | /workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1295912099 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 3166929294 ps |
| CPU time | 313.13 seconds |
| Started | Feb 07 04:50:59 PM PST 24 |
| Finished | Feb 07 04:56:13 PM PST 24 |
| Peak memory | 600452 kb |
| Host | smart-6e0cc23b-1b0e-4eae-ad07-5c80593f5b97 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295912099 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.1295912099 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.837033151 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 6168079185 ps |
| CPU time | 404.35 seconds |
| Started | Feb 07 04:49:02 PM PST 24 |
| Finished | Feb 07 04:55:47 PM PST 24 |
| Peak memory | 608344 kb |
| Host | smart-3f5529d2-2774-4c98-945e-b39fa2f1f142 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=837033151 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.837033151 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4112813289 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 5221439152 ps |
| CPU time | 545.21 seconds |
| Started | Feb 07 04:51:56 PM PST 24 |
| Finished | Feb 07 05:01:03 PM PST 24 |
| Peak memory | 599196 kb |
| Host | smart-d91d0f8d-32df-42c0-a4e2-c3f65817de23 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41128132 89 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4112813289 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.100986738 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 5750931616 ps |
| CPU time | 630.5 seconds |
| Started | Feb 07 04:52:43 PM PST 24 |
| Finished | Feb 07 05:03:14 PM PST 24 |
| Peak memory | 601488 kb |
| Host | smart-6f0f0473-2c79-435f-989d-5ade138bf7b1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=100986738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.100986738 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.948638765 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 5125452248 ps |
| CPU time | 475.11 seconds |
| Started | Feb 07 04:57:30 PM PST 24 |
| Finished | Feb 07 05:05:26 PM PST 24 |
| Peak memory | 601304 kb |
| Host | smart-207ec9eb-1ff8-44df-80fd-f4701f275ea5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948638765 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.948638765 |
| Directory | /workspace/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.470006366 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 7510597240 ps |
| CPU time | 1195.91 seconds |
| Started | Feb 07 04:50:00 PM PST 24 |
| Finished | Feb 07 05:09:57 PM PST 24 |
| Peak memory | 600440 kb |
| Host | smart-41ddbe29-c27b-4eb3-a927-bba798472b66 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470006366 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.470006366 |
| Directory | /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2043544584 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 4863126090 ps |
| CPU time | 511.79 seconds |
| Started | Feb 07 04:49:35 PM PST 24 |
| Finished | Feb 07 04:58:08 PM PST 24 |
| Peak memory | 601316 kb |
| Host | smart-ac999760-ca4d-47c6-ac5b-982ed98b4c27 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043544584 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2043544584 |
| Directory | /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1218704026 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 5450056032 ps |
| CPU time | 368.02 seconds |
| Started | Feb 07 04:55:28 PM PST 24 |
| Finished | Feb 07 05:01:38 PM PST 24 |
| Peak memory | 601276 kb |
| Host | smart-1313d6a8-9ad2-4640-b42f-0a340b0a9854 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218704026 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.1218704026 |
| Directory | /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2937196136 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 5750367816 ps |
| CPU time | 672.37 seconds |
| Started | Feb 07 04:50:49 PM PST 24 |
| Finished | Feb 07 05:02:03 PM PST 24 |
| Peak memory | 601284 kb |
| Host | smart-7cd27d33-2a91-4c63-b4d9-5041d7ce59f4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293 7196136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.2937196136 |
| Directory | /workspace/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1925879165 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 9064899911 ps |
| CPU time | 624.67 seconds |
| Started | Feb 07 04:53:18 PM PST 24 |
| Finished | Feb 07 05:03:43 PM PST 24 |
| Peak memory | 605356 kb |
| Host | smart-39be9999-ea67-4da4-a13c-057352f236d1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925879165 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.1925879165 |
| Directory | /workspace/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.298674793 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 13307749060 ps |
| CPU time | 1866.98 seconds |
| Started | Feb 07 04:49:35 PM PST 24 |
| Finished | Feb 07 05:20:43 PM PST 24 |
| Peak memory | 601812 kb |
| Host | smart-5eb4c8da-ee58-4131-bbd0-e7a3e157428c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=298674793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.298674793 |
| Directory | /workspace/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2310542882 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 7598201714 ps |
| CPU time | 882.21 seconds |
| Started | Feb 07 04:50:42 PM PST 24 |
| Finished | Feb 07 05:05:26 PM PST 24 |
| Peak memory | 599892 kb |
| Host | smart-315abe2d-6e1d-45a9-b5c8-046d1f0e6f45 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310542882 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_rstmgr_cpu_info.2310542882 |
| Directory | /workspace/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2045303999 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 5909149160 ps |
| CPU time | 677.24 seconds |
| Started | Feb 07 04:48:44 PM PST 24 |
| Finished | Feb 07 05:00:02 PM PST 24 |
| Peak memory | 631432 kb |
| Host | smart-79e6bdb9-fdb7-4ae0-a1ce-ecaa356dfb09 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2045303999 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.2045303999 |
| Directory | /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2929318340 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 2594945780 ps |
| CPU time | 247.44 seconds |
| Started | Feb 07 04:57:27 PM PST 24 |
| Finished | Feb 07 05:01:38 PM PST 24 |
| Peak memory | 600496 kb |
| Host | smart-d5daa91e-7490-4468-9947-a2d56a1ac778 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929318340 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rstmgr_smoketest.2929318340 |
| Directory | /workspace/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.36209461 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 4121808816 ps |
| CPU time | 376.32 seconds |
| Started | Feb 07 04:48:47 PM PST 24 |
| Finished | Feb 07 04:55:05 PM PST 24 |
| Peak memory | 600988 kb |
| Host | smart-1e3e1e83-135b-45de-a826-1424b8ebf456 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36209461 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rstmgr_sw_req.36209461 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3137700721 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 2257503068 ps |
| CPU time | 170.15 seconds |
| Started | Feb 07 04:50:56 PM PST 24 |
| Finished | Feb 07 04:53:46 PM PST 24 |
| Peak memory | 599160 kb |
| Host | smart-a91aadbf-8660-4b74-9944-f78ff2ac0e3e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137700721 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.3137700721 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2947710000 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 2307608916 ps |
| CPU time | 254.62 seconds |
| Started | Feb 07 04:54:43 PM PST 24 |
| Finished | Feb 07 04:58:58 PM PST 24 |
| Peak memory | 600476 kb |
| Host | smart-96f87708-ce0e-415b-98f5-9270087ba515 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2947710000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.2947710000 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3339415461 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 2431766126 ps |
| CPU time | 246.77 seconds |
| Started | Feb 07 04:53:27 PM PST 24 |
| Finished | Feb 07 04:57:35 PM PST 24 |
| Peak memory | 600452 kb |
| Host | smart-41ea5145-1236-4eeb-ae74-8f52a7556d64 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339415461 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.3339415461 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.323863208 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 4427003664 ps |
| CPU time | 847.85 seconds |
| Started | Feb 07 04:50:42 PM PST 24 |
| Finished | Feb 07 05:04:51 PM PST 24 |
| Peak memory | 599464 kb |
| Host | smart-799f4750-8b8a-4487-9169-2c7b801f462e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32386 3208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.323863208 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3850300242 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 6005591874 ps |
| CPU time | 1332.72 seconds |
| Started | Feb 07 04:49:57 PM PST 24 |
| Finished | Feb 07 05:12:11 PM PST 24 |
| Peak memory | 600672 kb |
| Host | smart-550425ec-3b42-4f46-93f3-09f9875b294f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3850300242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.3850300242 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.301927436 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 4410787831 ps |
| CPU time | 468.87 seconds |
| Started | Feb 07 04:53:59 PM PST 24 |
| Finished | Feb 07 05:01:48 PM PST 24 |
| Peak memory | 617600 kb |
| Host | smart-6643157f-79b5-4820-8e2a-69ecd7fa8b94 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301927436 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.301927436 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.3806026189 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 5218330204 ps |
| CPU time | 538.64 seconds |
| Started | Feb 07 04:51:54 PM PST 24 |
| Finished | Feb 07 05:00:54 PM PST 24 |
| Peak memory | 616944 kb |
| Host | smart-1cc153dd-3b68-4bbc-b5e3-828f5269c700 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup:1:new_rules,test_rom:0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806026189 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.3806026189 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1524206774 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 4509274200 ps |
| CPU time | 562.04 seconds |
| Started | Feb 07 04:52:32 PM PST 24 |
| Finished | Feb 07 05:01:54 PM PST 24 |
| Peak memory | 617760 kb |
| Host | smart-dd7a8dea-7c87-456a-9038-b462b6c17cb6 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524206774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1524206774 |
| Directory | /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1173002853 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 2652093668 ps |
| CPU time | 309.94 seconds |
| Started | Feb 07 04:57:12 PM PST 24 |
| Finished | Feb 07 05:02:26 PM PST 24 |
| Peak memory | 600516 kb |
| Host | smart-20edd5e4-3424-43a5-a9f9-98f47e8cba1d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173002853 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_plic_smoketest.1173002853 |
| Directory | /workspace/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_irq.444891207 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 3524006444 ps |
| CPU time | 269.24 seconds |
| Started | Feb 07 04:50:30 PM PST 24 |
| Finished | Feb 07 04:55:00 PM PST 24 |
| Peak memory | 600548 kb |
| Host | smart-ace12e48-8add-4482-87ad-3d9aace980f4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444891207 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_timer_irq.444891207 |
| Directory | /workspace/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.315143487 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 2805407844 ps |
| CPU time | 218.08 seconds |
| Started | Feb 07 04:56:03 PM PST 24 |
| Finished | Feb 07 04:59:41 PM PST 24 |
| Peak memory | 600540 kb |
| Host | smart-a2072d9e-eceb-4c20-bae7-e886ae990029 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315143487 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_timer_smoketest.315143487 |
| Directory | /workspace/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.1550476805 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 2714210419 ps |
| CPU time | 229.08 seconds |
| Started | Feb 07 04:51:57 PM PST 24 |
| Finished | Feb 07 04:55:49 PM PST 24 |
| Peak memory | 601060 kb |
| Host | smart-cd706038-624f-4a6d-b2c9-4f45b410bcd4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550476 805 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.1550476805 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_retention.1746729584 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3870012588 ps |
| CPU time | 353.4 seconds |
| Started | Feb 07 04:52:57 PM PST 24 |
| Finished | Feb 07 04:58:51 PM PST 24 |
| Peak memory | 601984 kb |
| Host | smart-f9afc6a0-f487-4034-b2a4-7bd7da887e89 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746729584 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.1746729584 |
| Directory | /workspace/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3626359742 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 7259103310 ps |
| CPU time | 1231.45 seconds |
| Started | Feb 07 04:52:44 PM PST 24 |
| Finished | Feb 07 05:13:17 PM PST 24 |
| Peak memory | 600688 kb |
| Host | smart-48853dc1-4491-4ca2-8daa-e5b9383a5c24 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626359742 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.3626359742 |
| Directory | /workspace/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3626859375 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 8081333658 ps |
| CPU time | 631.18 seconds |
| Started | Feb 07 04:51:07 PM PST 24 |
| Finished | Feb 07 05:01:39 PM PST 24 |
| Peak memory | 600004 kb |
| Host | smart-e5289669-2ac3-4bc0-8a96-c48d1b7d9a1c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626859375 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sl eep_sram_ret_contents_no_scramble.3626859375 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3400189296 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 7207107144 ps |
| CPU time | 571.7 seconds |
| Started | Feb 07 04:52:02 PM PST 24 |
| Finished | Feb 07 05:01:36 PM PST 24 |
| Peak memory | 601452 kb |
| Host | smart-cea97281-11ef-44f2-869f-33a1098ddd22 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400189296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep _sram_ret_contents_scramble.3400189296 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through.243116271 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 7535013323 ps |
| CPU time | 861.06 seconds |
| Started | Feb 07 04:48:10 PM PST 24 |
| Finished | Feb 07 05:02:31 PM PST 24 |
| Peak memory | 617304 kb |
| Host | smart-22b878ab-5ca8-448e-b267-314a0714bdba |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243116271 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.243116271 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3067121345 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 4205892458 ps |
| CPU time | 557.17 seconds |
| Started | Feb 07 04:48:43 PM PST 24 |
| Finished | Feb 07 04:58:02 PM PST 24 |
| Peak memory | 618400 kb |
| Host | smart-f1bab6b7-a097-465b-8c92-fefe1905dc7d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067121345 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.3067121345 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_tpm.2148788815 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 2948424287 ps |
| CPU time | 314.15 seconds |
| Started | Feb 07 04:48:17 PM PST 24 |
| Finished | Feb 07 04:53:32 PM PST 24 |
| Peak memory | 606916 kb |
| Host | smart-328c88f4-d02e-4df3-a542-4a0aef3bd099 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148788815 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.2148788815 |
| Directory | /workspace/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.2457120328 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 2460935912 ps |
| CPU time | 436.64 seconds |
| Started | Feb 07 04:48:33 PM PST 24 |
| Finished | Feb 07 04:55:53 PM PST 24 |
| Peak memory | 601984 kb |
| Host | smart-5d077dea-b840-4ecd-ab4d-29dd4574de6d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457120328 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.2457120328 |
| Directory | /workspace/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1793202453 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 4486107484 ps |
| CPU time | 775.79 seconds |
| Started | Feb 07 04:53:34 PM PST 24 |
| Finished | Feb 07 05:06:32 PM PST 24 |
| Peak memory | 601116 kb |
| Host | smart-947afe1e-e6da-40a5-82f0-4d87c71cd74b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793202453 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _sram_ctrl_scrambled_access.1793202453 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2223226494 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 4169420171 ps |
| CPU time | 518.73 seconds |
| Started | Feb 07 04:51:27 PM PST 24 |
| Finished | Feb 07 05:00:06 PM PST 24 |
| Peak memory | 599368 kb |
| Host | smart-5be9316f-d9d3-41b9-ace9-737226d51be2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223226494 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2223226494 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1897672016 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 5706698033 ps |
| CPU time | 668.85 seconds |
| Started | Feb 07 04:53:24 PM PST 24 |
| Finished | Feb 07 05:04:33 PM PST 24 |
| Peak memory | 599656 kb |
| Host | smart-b2f49228-aacc-425d-8984-9aeeef3fc3e2 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897672016 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1897672016 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1541922676 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 3260157824 ps |
| CPU time | 267.25 seconds |
| Started | Feb 07 04:57:39 PM PST 24 |
| Finished | Feb 07 05:02:08 PM PST 24 |
| Peak memory | 599044 kb |
| Host | smart-6901cf6b-6e2a-4615-8038-0e54fd815f02 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541922676 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.1541922676 |
| Directory | /workspace/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3541878123 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 20030055884 ps |
| CPU time | 3158.68 seconds |
| Started | Feb 07 04:50:37 PM PST 24 |
| Finished | Feb 07 05:43:17 PM PST 24 |
| Peak memory | 600032 kb |
| Host | smart-b4e67323-ffa2-4ab2-87ad-b822fb614b35 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541878123 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.3541878123 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2655391314 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 4183541456 ps |
| CPU time | 766.35 seconds |
| Started | Feb 07 04:55:31 PM PST 24 |
| Finished | Feb 07 05:08:19 PM PST 24 |
| Peak memory | 599780 kb |
| Host | smart-1fb13c6c-9951-4cea-ba14-6928ac1f8578 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655391314 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.2655391314 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2674173058 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 2575467097 ps |
| CPU time | 280.29 seconds |
| Started | Feb 07 04:50:19 PM PST 24 |
| Finished | Feb 07 04:55:01 PM PST 24 |
| Peak memory | 600764 kb |
| Host | smart-e857b3f1-2f66-4ff3-836a-b9b2d1df1130 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674173058 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.2674173058 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1335931730 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 22452919730 ps |
| CPU time | 2063.73 seconds |
| Started | Feb 07 04:50:00 PM PST 24 |
| Finished | Feb 07 05:24:25 PM PST 24 |
| Peak memory | 601912 kb |
| Host | smart-dc1359a4-f5d8-4486-ad31-a4d50a44ec80 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13359317 30 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.1335931730 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2332822307 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 5189392874 ps |
| CPU time | 678.94 seconds |
| Started | Feb 07 04:48:48 PM PST 24 |
| Finished | Feb 07 05:00:09 PM PST 24 |
| Peak memory | 600376 kb |
| Host | smart-e31ebe25-fa7f-45cc-83d2-a141b1e349da |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332822307 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2332822307 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1168367881 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 4922203256 ps |
| CPU time | 657.75 seconds |
| Started | Feb 07 04:48:40 PM PST 24 |
| Finished | Feb 07 04:59:42 PM PST 24 |
| Peak memory | 601812 kb |
| Host | smart-5f4920d6-6760-46f6-80a9-be66097e967f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1168367881 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.1168367881 |
| Directory | /workspace/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_smoketest.3647361192 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 2860204728 ps |
| CPU time | 313.66 seconds |
| Started | Feb 07 04:56:20 PM PST 24 |
| Finished | Feb 07 05:01:34 PM PST 24 |
| Peak memory | 595712 kb |
| Host | smart-cdc65038-9441-4b72-a850-ec89ae5582c8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647361192 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_uart_smoketest.3647361192 |
| Directory | /workspace/2.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_smoketest_signed.1616909293 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 8557977084 ps |
| CPU time | 1766.09 seconds |
| Started | Feb 07 05:00:46 PM PST 24 |
| Finished | Feb 07 05:30:13 PM PST 24 |
| Peak memory | 597616 kb |
| Host | smart-13cefabd-d5f0-400d-9b55-c33495570d65 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=uart_smoketest_signed:1:signed:fake_rsa_test_key_0,rom_with_fa ke_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1616909293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_smoketest_signed.1616909293 |
| Directory | /workspace/2.chip_sw_uart_smoketest_signed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2013575632 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 13900579003 ps |
| CPU time | 2621.01 seconds |
| Started | Feb 07 04:48:12 PM PST 24 |
| Finished | Feb 07 05:31:54 PM PST 24 |
| Peak memory | 613744 kb |
| Host | smart-93e5a74c-5d72-4a63-9504-8a5dd18f3169 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013575632 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq.2013575632 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.718075024 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 4408742910 ps |
| CPU time | 540.52 seconds |
| Started | Feb 07 04:48:46 PM PST 24 |
| Finished | Feb 07 04:57:49 PM PST 24 |
| Peak memory | 605528 kb |
| Host | smart-7acfea72-3b82-4550-b93e-eb5e0dc58b69 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718075024 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.718075024 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3938061933 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 78928644544 ps |
| CPU time | 12840 seconds |
| Started | Feb 07 04:48:35 PM PST 24 |
| Finished | Feb 07 08:22:37 PM PST 24 |
| Peak memory | 611764 kb |
| Host | smart-744d594e-50f3-4dbb-9fd3-add87df9ddd9 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3938061933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.3938061933 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.409074702 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 5685571994 ps |
| CPU time | 975.97 seconds |
| Started | Feb 07 04:47:50 PM PST 24 |
| Finished | Feb 07 05:04:07 PM PST 24 |
| Peak memory | 602704 kb |
| Host | smart-b990af7d-10b0-4ed9-8e68-d5e18b1b2f43 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409074702 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.409074702 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.577120583 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 5241051608 ps |
| CPU time | 646.61 seconds |
| Started | Feb 07 04:47:57 PM PST 24 |
| Finished | Feb 07 04:58:44 PM PST 24 |
| Peak memory | 602744 kb |
| Host | smart-957a597b-dcee-4ea8-86af-612a6a4e242d |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577120583 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.577120583 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1267852674 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 6287051064 ps |
| CPU time | 1014.12 seconds |
| Started | Feb 07 04:47:35 PM PST 24 |
| Finished | Feb 07 05:04:30 PM PST 24 |
| Peak memory | 602812 kb |
| Host | smart-67319920-8a21-4a14-a37e-a76efc6d9eeb |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267852674 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.1267852674 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_dev.1973661014 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 14671894148 ps |
| CPU time | 1453.21 seconds |
| Started | Feb 07 04:52:35 PM PST 24 |
| Finished | Feb 07 05:16:49 PM PST 24 |
| Peak memory | 601968 kb |
| Host | smart-c2bbcbb8-edca-4d7f-a475-4a31e14ed1ea |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1973661014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.1973661014 |
| Directory | /workspace/2.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_prod.1361836656 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 2489489588 ps |
| CPU time | 153.55 seconds |
| Started | Feb 07 04:52:50 PM PST 24 |
| Finished | Feb 07 04:55:24 PM PST 24 |
| Peak memory | 601684 kb |
| Host | smart-9b23cd68-d60c-4ae0-a732-a6f9e22f1c88 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361836656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.1361836656 |
| Directory | /workspace/2.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_rma.2136366454 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 4363979363 ps |
| CPU time | 311.41 seconds |
| Started | Feb 07 04:53:37 PM PST 24 |
| Finished | Feb 07 04:58:53 PM PST 24 |
| Peak memory | 602112 kb |
| Host | smart-ede5d9a3-aa50-4a7b-87b0-668ef3938626 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136366454 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_rma.2136366454 |
| Directory | /workspace/2.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_testunlock0.2039622901 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 6973174668 ps |
| CPU time | 330.1 seconds |
| Started | Feb 07 04:52:40 PM PST 24 |
| Finished | Feb 07 04:58:10 PM PST 24 |
| Peak memory | 602164 kb |
| Host | smart-fdc1a8a7-0be9-4715-a655-856308ed3a0d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2039622901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.2039622901 |
| Directory | /workspace/2.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_dev.2477604604 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 7964691476 ps |
| CPU time | 2028.42 seconds |
| Started | Feb 07 04:58:13 PM PST 24 |
| Finished | Feb 07 05:32:02 PM PST 24 |
| Peak memory | 599992 kb |
| Host | smart-a5755d6b-4ee1-4563-8cb8-a41392cc57fc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_dev:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477604604 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.rom_e2e_asm_init_dev.2477604604 |
| Directory | /workspace/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod.1578167583 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 9253357093 ps |
| CPU time | 1692.87 seconds |
| Started | Feb 07 04:59:14 PM PST 24 |
| Finished | Feb 07 05:27:29 PM PST 24 |
| Peak memory | 599676 kb |
| Host | smart-576ba06c-b4f8-4a3d-9e18-02bc774a6836 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_prod:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578167583 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.rom_e2e_asm_init_prod.1578167583 |
| Directory | /workspace/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2810320397 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 8018731460 ps |
| CPU time | 1910.95 seconds |
| Started | Feb 07 04:58:52 PM PST 24 |
| Finished | Feb 07 05:30:47 PM PST 24 |
| Peak memory | 599960 kb |
| Host | smart-4aa65055-35ac-4af6-bcba-56765b117571 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_prod_end:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810320397 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod_end.2810320397 |
| Directory | /workspace/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_rma.4054385823 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 8962620941 ps |
| CPU time | 2036.72 seconds |
| Started | Feb 07 04:58:14 PM PST 24 |
| Finished | Feb 07 05:32:12 PM PST 24 |
| Peak memory | 600892 kb |
| Host | smart-7aa177e0-3125-405d-b123-4840127300a6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_rma:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054385823 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.rom_e2e_asm_init_rma.4054385823 |
| Directory | /workspace/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.406688422 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 7007657940 ps |
| CPU time | 1562.72 seconds |
| Started | Feb 07 04:57:35 PM PST 24 |
| Finished | Feb 07 05:23:38 PM PST 24 |
| Peak memory | 601400 kb |
| Host | smart-1e90c894-9951-4c67-8414-4198ef75533a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_ flash_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406688422 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_test_unlocked0.406688422 |
| Directory | /workspace/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.1602009165 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 8861317872 ps |
| CPU time | 1872.24 seconds |
| Started | Feb 07 04:59:27 PM PST 24 |
| Finished | Feb 07 05:30:40 PM PST 24 |
| Peak memory | 600024 kb |
| Host | smart-32fb70ef-f9c9-4209-b1da-b3dcbb5f81fb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:signed:fake_rsa_test_key_0,rom_ with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1602009165 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_exception_c_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_exception_c.1602009165 |
| Directory | /workspace/2.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_output.2399876215 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 29063947520 ps |
| CPU time | 2952.34 seconds |
| Started | Feb 07 04:58:38 PM PST 24 |
| Finished | Feb 07 05:47:51 PM PST 24 |
| Peak memory | 600980 kb |
| Host | smart-58f54e23-fc36-4251-b821-7c79cb303abc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bina ry,otp_img_shutdown_output_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399876215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.rom_e2e_shutdown_output.2399876215 |
| Directory | /workspace/2.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_smoke.1817553735 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 8844750226 ps |
| CPU time | 1735.32 seconds |
| Started | Feb 07 04:54:36 PM PST 24 |
| Finished | Feb 07 05:23:31 PM PST 24 |
| Peak memory | 601000 kb |
| Host | smart-eebe053e-49af-4773-8ad0-5aa00632ccc4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_binary:signed:fake_rsa_test_key_0 ,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1817553735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.1817553735 |
| Directory | /workspace/2.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_static_critical.2171274550 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 11239263280 ps |
| CPU time | 2428.2 seconds |
| Started | Feb 07 05:01:07 PM PST 24 |
| Finished | Feb 07 05:41:36 PM PST 24 |
| Peak memory | 600972 kb |
| Host | smart-d63de4e7-04bd-4d88-8be1-72c1a3f1eb06 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:signed:fake_rsa_test_key_0,rom_with_ fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171274550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.2171274550 |
| Directory | /workspace/2.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/2.rom_keymgr_functest.475637238 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 5270898076 ps |
| CPU time | 648.13 seconds |
| Started | Feb 07 04:57:27 PM PST 24 |
| Finished | Feb 07 05:08:19 PM PST 24 |
| Peak memory | 601524 kb |
| Host | smart-1d8b3b84-7f98-4694-b4dd-541ab5d5545c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475637238 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.475637238 |
| Directory | /workspace/2.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/2.rom_volatile_raw_unlock.1873219594 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 11531464070 ps |
| CPU time | 1723.04 seconds |
| Started | Feb 07 04:57:11 PM PST 24 |
| Finished | Feb 07 05:25:54 PM PST 24 |
| Peak memory | 607084 kb |
| Host | smart-1c1b694f-c342-4add-938e-229fdad05f9e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:fake_rsa_test_key_0:ot_flash_binary,rom_with_fake_keys:0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873219594 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.1873219594 |
| Directory | /workspace/2.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/21.chip_sw_all_escalation_resets.2981016373 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 5050558708 ps |
| CPU time | 672.52 seconds |
| Started | Feb 07 04:59:20 PM PST 24 |
| Finished | Feb 07 05:10:34 PM PST 24 |
| Peak memory | 633796 kb |
| Host | smart-45ae8d90-c64c-49df-978c-138ca31f4d5f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2981016373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.2981016373 |
| Directory | /workspace/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2568974209 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 4062634248 ps |
| CPU time | 496.34 seconds |
| Started | Feb 07 04:59:39 PM PST 24 |
| Finished | Feb 07 05:07:56 PM PST 24 |
| Peak memory | 632448 kb |
| Host | smart-d4a6c96a-7656-4bf8-a57a-b420eec4a267 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568974209 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2568974209 |
| Directory | /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1338417562 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 3898036940 ps |
| CPU time | 350.45 seconds |
| Started | Feb 07 04:58:54 PM PST 24 |
| Finished | Feb 07 05:04:46 PM PST 24 |
| Peak memory | 633444 kb |
| Host | smart-7cd10d75-2662-4283-9b1a-3922b8730840 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338417562 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1338417562 |
| Directory | /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2329798089 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 3942372300 ps |
| CPU time | 367.44 seconds |
| Started | Feb 07 05:00:26 PM PST 24 |
| Finished | Feb 07 05:06:34 PM PST 24 |
| Peak memory | 607276 kb |
| Host | smart-cc8576c3-e81d-4e47-b5b7-26262616cd91 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329798089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2329798089 |
| Directory | /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/26.chip_sw_all_escalation_resets.2214881172 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 4882694670 ps |
| CPU time | 562.24 seconds |
| Started | Feb 07 05:00:13 PM PST 24 |
| Finished | Feb 07 05:09:36 PM PST 24 |
| Peak memory | 635540 kb |
| Host | smart-53197b30-0361-48a1-a1a6-2000ac7a2131 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2214881172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.2214881172 |
| Directory | /workspace/26.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1760606486 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 2914692520 ps |
| CPU time | 306.19 seconds |
| Started | Feb 07 05:00:35 PM PST 24 |
| Finished | Feb 07 05:05:43 PM PST 24 |
| Peak memory | 632796 kb |
| Host | smart-6521a6cf-d350-4856-9125-7183283dabcc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760606486 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1760606486 |
| Directory | /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.732511357 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 3943082068 ps |
| CPU time | 391.4 seconds |
| Started | Feb 07 04:59:33 PM PST 24 |
| Finished | Feb 07 05:06:05 PM PST 24 |
| Peak memory | 632420 kb |
| Host | smart-dfa7f27f-6b92-4f0f-bc0f-a37fe7be4ad3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732511357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_s w_alert_handler_lpg_sleep_mode_alerts.732511357 |
| Directory | /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/29.chip_sw_all_escalation_resets.132083591 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 5180274086 ps |
| CPU time | 541.11 seconds |
| Started | Feb 07 04:59:44 PM PST 24 |
| Finished | Feb 07 05:08:46 PM PST 24 |
| Peak memory | 633484 kb |
| Host | smart-935647be-094f-41c3-b323-33e80fc6e29c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 132083591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.132083591 |
| Directory | /workspace/29.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2172342004 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 6318013176 ps |
| CPU time | 606.21 seconds |
| Started | Feb 07 04:56:18 PM PST 24 |
| Finished | Feb 07 05:06:25 PM PST 24 |
| Peak memory | 601296 kb |
| Host | smart-7c47ce8c-5d4b-473f-b9ad-689c41995534 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2172342004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2172342004 |
| Directory | /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/3.chip_sw_data_integrity_escalation.1979182095 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 6715409848 ps |
| CPU time | 757.2 seconds |
| Started | Feb 07 04:55:57 PM PST 24 |
| Finished | Feb 07 05:08:35 PM PST 24 |
| Peak memory | 600580 kb |
| Host | smart-1a5690b3-a732-4fd9-8003-12c6ec0dd748 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1979182095 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.1979182095 |
| Directory | /workspace/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.330973905 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 11213628847 ps |
| CPU time | 1076.32 seconds |
| Started | Feb 07 04:56:07 PM PST 24 |
| Finished | Feb 07 05:14:04 PM PST 24 |
| Peak memory | 604020 kb |
| Host | smart-6693fe0f-a5e9-4a08-a22a-8046dffa0d17 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330973905 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.330973905 |
| Directory | /workspace/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3264758063 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 5877090430 ps |
| CPU time | 580.51 seconds |
| Started | Feb 07 04:55:46 PM PST 24 |
| Finished | Feb 07 05:05:27 PM PST 24 |
| Peak memory | 601272 kb |
| Host | smart-ce4ab211-5d74-4f59-bb2c-705f8449ec81 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32647580 63 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.3264758063 |
| Directory | /workspace/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3453524449 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 5456119762 ps |
| CPU time | 870.94 seconds |
| Started | Feb 07 04:55:45 PM PST 24 |
| Finished | Feb 07 05:10:17 PM PST 24 |
| Peak memory | 601820 kb |
| Host | smart-492bec83-f07c-4999-b981-82a9108765ac |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3453524449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.3453524449 |
| Directory | /workspace/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx.115433250 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 5818830912 ps |
| CPU time | 1014.93 seconds |
| Started | Feb 07 04:55:46 PM PST 24 |
| Finished | Feb 07 05:12:42 PM PST 24 |
| Peak memory | 603132 kb |
| Host | smart-eae66f04-9092-481f-9f5b-bd628a453bb2 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115433250 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.115433250 |
| Directory | /workspace/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2712183254 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 4687906466 ps |
| CPU time | 824.85 seconds |
| Started | Feb 07 04:56:13 PM PST 24 |
| Finished | Feb 07 05:09:59 PM PST 24 |
| Peak memory | 605544 kb |
| Host | smart-9ca23725-de5a-4b0e-83e9-8daf73ce1ca9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712183254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq.2712183254 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1305575718 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 13100302453 ps |
| CPU time | 1488.37 seconds |
| Started | Feb 07 04:57:15 PM PST 24 |
| Finished | Feb 07 05:22:05 PM PST 24 |
| Peak memory | 613752 kb |
| Host | smart-4ca24954-bb74-4061-8e98-5c1401166d5f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305575718 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1305575718 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.85041655 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 6153265380 ps |
| CPU time | 843.68 seconds |
| Started | Feb 07 04:56:53 PM PST 24 |
| Finished | Feb 07 05:10:57 PM PST 24 |
| Peak memory | 610932 kb |
| Host | smart-f06e15a7-3cdd-4600-b32f-0d0ebf3d9a43 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85041655 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.85041655 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.3847478353 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 5344940048 ps |
| CPU time | 1140.48 seconds |
| Started | Feb 07 04:55:24 PM PST 24 |
| Finished | Feb 07 05:14:27 PM PST 24 |
| Peak memory | 602836 kb |
| Host | smart-eddbcd3c-35c7-4460-bfdf-a85d662d41d5 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847478353 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.3847478353 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2767463345 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 5645291430 ps |
| CPU time | 1020.04 seconds |
| Started | Feb 07 04:55:34 PM PST 24 |
| Finished | Feb 07 05:12:35 PM PST 24 |
| Peak memory | 602824 kb |
| Host | smart-9fe5ce1d-40bb-4764-ad67-7df23ed22b7b |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767463345 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.2767463345 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_dev.1066930268 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 3709367251 ps |
| CPU time | 264.21 seconds |
| Started | Feb 07 04:55:09 PM PST 24 |
| Finished | Feb 07 04:59:34 PM PST 24 |
| Peak memory | 601672 kb |
| Host | smart-0518ab0f-c3ef-42ba-bf1f-8c20a80e162d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1066930268 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.1066930268 |
| Directory | /workspace/3.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_prod.3904560744 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 2685610704 ps |
| CPU time | 196.6 seconds |
| Started | Feb 07 04:56:44 PM PST 24 |
| Finished | Feb 07 05:00:01 PM PST 24 |
| Peak memory | 600816 kb |
| Host | smart-502f95d8-5aab-41e5-a623-0c8f3cbcd66b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904560744 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.3904560744 |
| Directory | /workspace/3.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_rma.3699525314 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 9351456965 ps |
| CPU time | 1140.12 seconds |
| Started | Feb 07 04:55:44 PM PST 24 |
| Finished | Feb 07 05:14:46 PM PST 24 |
| Peak memory | 602068 kb |
| Host | smart-d1f9063b-ceae-4195-838d-9a379397c4d5 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699525314 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.3699525314 |
| Directory | /workspace/3.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_testunlock0.3413028945 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 4929654487 ps |
| CPU time | 253.44 seconds |
| Started | Feb 07 04:56:34 PM PST 24 |
| Finished | Feb 07 05:00:48 PM PST 24 |
| Peak memory | 610360 kb |
| Host | smart-0c4f5831-6307-41c4-b7d7-94a36decf919 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3413028945 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.3413028945 |
| Directory | /workspace/3.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3778679431 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 3736992308 ps |
| CPU time | 397.14 seconds |
| Started | Feb 07 05:02:02 PM PST 24 |
| Finished | Feb 07 05:08:40 PM PST 24 |
| Peak memory | 634200 kb |
| Host | smart-3a789837-d4a4-479c-9ecd-7c97d020c55c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778679431 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3778679431 |
| Directory | /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/31.chip_sw_all_escalation_resets.4237049087 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 5973243512 ps |
| CPU time | 710.12 seconds |
| Started | Feb 07 04:59:53 PM PST 24 |
| Finished | Feb 07 05:11:44 PM PST 24 |
| Peak memory | 607320 kb |
| Host | smart-ab0dc8f6-47a1-4e53-a023-73876238255a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4237049087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.4237049087 |
| Directory | /workspace/31.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.731773634 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 3877285888 ps |
| CPU time | 377.46 seconds |
| Started | Feb 07 05:00:18 PM PST 24 |
| Finished | Feb 07 05:06:36 PM PST 24 |
| Peak memory | 632804 kb |
| Host | smart-d49ce402-5ac2-4b56-bfdc-26a30be572ef |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731773634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_s w_alert_handler_lpg_sleep_mode_alerts.731773634 |
| Directory | /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/33.chip_sw_all_escalation_resets.928209991 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 5108323740 ps |
| CPU time | 597.79 seconds |
| Started | Feb 07 05:01:06 PM PST 24 |
| Finished | Feb 07 05:11:05 PM PST 24 |
| Peak memory | 635288 kb |
| Host | smart-6ffaa689-8b59-4b97-9792-5a4e39b035ad |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 928209991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.928209991 |
| Directory | /workspace/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3131496590 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 3961514338 ps |
| CPU time | 394.03 seconds |
| Started | Feb 07 05:00:24 PM PST 24 |
| Finished | Feb 07 05:06:59 PM PST 24 |
| Peak memory | 633656 kb |
| Host | smart-8bf58915-364d-48d3-adc8-f1f493e2132c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131496590 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3131496590 |
| Directory | /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/34.chip_sw_all_escalation_resets.3586529071 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 5820616904 ps |
| CPU time | 706.33 seconds |
| Started | Feb 07 05:00:20 PM PST 24 |
| Finished | Feb 07 05:12:07 PM PST 24 |
| Peak memory | 607372 kb |
| Host | smart-9d58ad55-9409-46bc-b673-49e89a7a3e07 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3586529071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.3586529071 |
| Directory | /workspace/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1103010398 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 4407335136 ps |
| CPU time | 490.32 seconds |
| Started | Feb 07 05:00:57 PM PST 24 |
| Finished | Feb 07 05:09:08 PM PST 24 |
| Peak memory | 634456 kb |
| Host | smart-855ed6fe-7605-4f1c-b14f-bdd86d19a7a4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103010398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1103010398 |
| Directory | /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/35.chip_sw_all_escalation_resets.2793336692 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 4282369616 ps |
| CPU time | 646.34 seconds |
| Started | Feb 07 04:59:56 PM PST 24 |
| Finished | Feb 07 05:10:43 PM PST 24 |
| Peak memory | 634784 kb |
| Host | smart-f0723b8c-36f5-4bab-a70c-a495bf9ecc60 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2793336692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.2793336692 |
| Directory | /workspace/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/36.chip_sw_all_escalation_resets.3894694264 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 5262220930 ps |
| CPU time | 677.5 seconds |
| Started | Feb 07 05:01:22 PM PST 24 |
| Finished | Feb 07 05:12:40 PM PST 24 |
| Peak memory | 635260 kb |
| Host | smart-8907e479-b04e-4147-9e0c-fbcf91f7ba8f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3894694264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.3894694264 |
| Directory | /workspace/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1736362622 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 3915191886 ps |
| CPU time | 369.26 seconds |
| Started | Feb 07 05:02:22 PM PST 24 |
| Finished | Feb 07 05:08:41 PM PST 24 |
| Peak memory | 633724 kb |
| Host | smart-cf601990-2d3e-4961-93c3-67dbbc6ca848 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736362622 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1736362622 |
| Directory | /workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2100288418 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 4148019568 ps |
| CPU time | 583.35 seconds |
| Started | Feb 07 05:01:22 PM PST 24 |
| Finished | Feb 07 05:11:07 PM PST 24 |
| Peak memory | 632560 kb |
| Host | smart-d14a8551-05fa-41be-a853-9bc635fe29fa |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100288418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2100288418 |
| Directory | /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/39.chip_sw_all_escalation_resets.728887497 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 4899805336 ps |
| CPU time | 706.56 seconds |
| Started | Feb 07 05:01:40 PM PST 24 |
| Finished | Feb 07 05:13:27 PM PST 24 |
| Peak memory | 635156 kb |
| Host | smart-5ad760c0-38e1-4892-9c0b-3b14cbbea26d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 728887497 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.728887497 |
| Directory | /workspace/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3684715176 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 4094757330 ps |
| CPU time | 490.65 seconds |
| Started | Feb 07 04:58:53 PM PST 24 |
| Finished | Feb 07 05:07:07 PM PST 24 |
| Peak memory | 633956 kb |
| Host | smart-d52de5de-121c-47b1-87d7-6f5a2afc786c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684715176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_s w_alert_handler_lpg_sleep_mode_alerts.3684715176 |
| Directory | /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1377647700 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 6785755662 ps |
| CPU time | 520.17 seconds |
| Started | Feb 07 04:57:04 PM PST 24 |
| Finished | Feb 07 05:05:46 PM PST 24 |
| Peak memory | 601304 kb |
| Host | smart-7a000f73-afb1-4d9e-8665-a52b7926c60b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1377647700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1377647700 |
| Directory | /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/4.chip_sw_data_integrity_escalation.2215289940 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 5128936280 ps |
| CPU time | 699.04 seconds |
| Started | Feb 07 04:57:26 PM PST 24 |
| Finished | Feb 07 05:09:09 PM PST 24 |
| Peak memory | 601956 kb |
| Host | smart-553b7bc1-1e36-4a3b-afca-57525be92632 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2215289940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.2215289940 |
| Directory | /workspace/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3819698573 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 6449989314 ps |
| CPU time | 504.02 seconds |
| Started | Feb 07 04:57:32 PM PST 24 |
| Finished | Feb 07 05:05:58 PM PST 24 |
| Peak memory | 603436 kb |
| Host | smart-4b03910b-6466-4bfb-aa27-cda901190c58 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819698573 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.3819698573 |
| Directory | /workspace/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2799915773 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 4260987632 ps |
| CPU time | 972.98 seconds |
| Started | Feb 07 04:58:27 PM PST 24 |
| Finished | Feb 07 05:14:40 PM PST 24 |
| Peak memory | 605576 kb |
| Host | smart-96eb85b4-23e2-4ce9-b59f-4be81762a27f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2799915773 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.2799915773 |
| Directory | /workspace/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx.4197019677 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 5474718856 ps |
| CPU time | 1028.6 seconds |
| Started | Feb 07 04:55:59 PM PST 24 |
| Finished | Feb 07 05:13:09 PM PST 24 |
| Peak memory | 602556 kb |
| Host | smart-6eea1e9b-9571-4d6a-8ffc-5bd03bcbdaef |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197019677 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.4197019677 |
| Directory | /workspace/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3746591001 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 13717211041 ps |
| CPU time | 3011.14 seconds |
| Started | Feb 07 04:56:11 PM PST 24 |
| Finished | Feb 07 05:46:23 PM PST 24 |
| Peak memory | 612084 kb |
| Host | smart-d01d0e0c-7dfd-44d5-9436-ea93ba496b03 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746591001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq.3746591001 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3537954762 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 5330203471 ps |
| CPU time | 718.66 seconds |
| Started | Feb 07 04:56:44 PM PST 24 |
| Finished | Feb 07 05:08:43 PM PST 24 |
| Peak memory | 604156 kb |
| Host | smart-a30082f5-3cf8-4c02-a2b9-20c12b6950d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537954762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3537954762 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.428566783 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 6182858972 ps |
| CPU time | 1079.87 seconds |
| Started | Feb 07 04:57:45 PM PST 24 |
| Finished | Feb 07 05:15:45 PM PST 24 |
| Peak memory | 603116 kb |
| Host | smart-166dd630-d7e6-4338-bbfd-2243e75ec951 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428566783 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.428566783 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3809270958 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 5238590968 ps |
| CPU time | 875.76 seconds |
| Started | Feb 07 04:56:21 PM PST 24 |
| Finished | Feb 07 05:10:57 PM PST 24 |
| Peak memory | 602852 kb |
| Host | smart-0479962c-f752-47e4-843c-1dbbd64a1313 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809270958 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.3809270958 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_prod.3171752066 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 2896587363 ps |
| CPU time | 138.61 seconds |
| Started | Feb 07 04:56:40 PM PST 24 |
| Finished | Feb 07 04:58:59 PM PST 24 |
| Peak memory | 601644 kb |
| Host | smart-fc62ac87-9141-4144-a301-e481bbe62bfc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171752066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.3171752066 |
| Directory | /workspace/4.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_rma.3091373134 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 12626553580 ps |
| CPU time | 1375.05 seconds |
| Started | Feb 07 04:58:07 PM PST 24 |
| Finished | Feb 07 05:21:03 PM PST 24 |
| Peak memory | 602168 kb |
| Host | smart-762815a4-4cfe-49e5-8dc1-9bd42e8d8127 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091373134 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.3091373134 |
| Directory | /workspace/4.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1717030396 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 4362184770 ps |
| CPU time | 432.76 seconds |
| Started | Feb 07 05:01:52 PM PST 24 |
| Finished | Feb 07 05:09:05 PM PST 24 |
| Peak memory | 634184 kb |
| Host | smart-1b2fdd3d-282f-4461-b6e9-191065c8c224 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717030396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1717030396 |
| Directory | /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2441596051 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 4052431704 ps |
| CPU time | 444.7 seconds |
| Started | Feb 07 05:01:55 PM PST 24 |
| Finished | Feb 07 05:09:20 PM PST 24 |
| Peak memory | 633756 kb |
| Host | smart-bbc98b42-a3dc-4970-a8c3-5a290b574a1f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441596051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2441596051 |
| Directory | /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/41.chip_sw_all_escalation_resets.2541060214 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 4630616408 ps |
| CPU time | 672.95 seconds |
| Started | Feb 07 05:02:00 PM PST 24 |
| Finished | Feb 07 05:13:14 PM PST 24 |
| Peak memory | 633896 kb |
| Host | smart-4bc2734e-fc44-4c51-beaa-8dc21ba136fd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2541060214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.2541060214 |
| Directory | /workspace/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1475066981 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 4263261460 ps |
| CPU time | 383.85 seconds |
| Started | Feb 07 05:01:07 PM PST 24 |
| Finished | Feb 07 05:07:31 PM PST 24 |
| Peak memory | 632524 kb |
| Host | smart-5499a736-9db9-4fa1-864b-5f77725f0b67 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475066981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1475066981 |
| Directory | /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/42.chip_sw_all_escalation_resets.1576566800 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 4394865336 ps |
| CPU time | 700.8 seconds |
| Started | Feb 07 05:01:25 PM PST 24 |
| Finished | Feb 07 05:13:07 PM PST 24 |
| Peak memory | 635388 kb |
| Host | smart-f8bcf3c3-2032-4fb4-875d-d532dabb70e5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1576566800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.1576566800 |
| Directory | /workspace/42.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2762721249 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 3700542704 ps |
| CPU time | 382.67 seconds |
| Started | Feb 07 05:02:08 PM PST 24 |
| Finished | Feb 07 05:08:31 PM PST 24 |
| Peak memory | 632636 kb |
| Host | smart-d1f5a918-247c-4ac7-9a49-5f273d1f25dc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762721249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2762721249 |
| Directory | /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.727450738 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 3602463944 ps |
| CPU time | 401.27 seconds |
| Started | Feb 07 05:01:19 PM PST 24 |
| Finished | Feb 07 05:08:01 PM PST 24 |
| Peak memory | 632224 kb |
| Host | smart-0ed7739d-75d5-4a94-aa8b-b0f4498f5fe8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727450738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_s w_alert_handler_lpg_sleep_mode_alerts.727450738 |
| Directory | /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/44.chip_sw_all_escalation_resets.988071335 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 5070022266 ps |
| CPU time | 652.77 seconds |
| Started | Feb 07 05:02:11 PM PST 24 |
| Finished | Feb 07 05:13:25 PM PST 24 |
| Peak memory | 633856 kb |
| Host | smart-06e2fc62-4d80-482c-b0c9-14c5f44bbe70 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 988071335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.988071335 |
| Directory | /workspace/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2383884428 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 3757905172 ps |
| CPU time | 373.45 seconds |
| Started | Feb 07 05:02:00 PM PST 24 |
| Finished | Feb 07 05:08:15 PM PST 24 |
| Peak memory | 633472 kb |
| Host | smart-5f6c753d-7cf7-4332-950e-fd6113454b25 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383884428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2383884428 |
| Directory | /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/45.chip_sw_all_escalation_resets.2703914838 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 4707817664 ps |
| CPU time | 571.4 seconds |
| Started | Feb 07 05:02:34 PM PST 24 |
| Finished | Feb 07 05:12:06 PM PST 24 |
| Peak memory | 634112 kb |
| Host | smart-0dcd13c4-d322-4993-a03a-68044001b615 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2703914838 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.2703914838 |
| Directory | /workspace/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2271280187 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 2941301496 ps |
| CPU time | 267.91 seconds |
| Started | Feb 07 05:01:04 PM PST 24 |
| Finished | Feb 07 05:05:32 PM PST 24 |
| Peak memory | 632416 kb |
| Host | smart-65767e57-0972-4b6c-849e-cbfee7cda75c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271280187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2271280187 |
| Directory | /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/47.chip_sw_all_escalation_resets.425860604 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 4150178620 ps |
| CPU time | 570.91 seconds |
| Started | Feb 07 05:03:16 PM PST 24 |
| Finished | Feb 07 05:12:47 PM PST 24 |
| Peak memory | 634904 kb |
| Host | smart-0b015159-0f73-4f66-86b0-8017538ceb9b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 425860604 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.425860604 |
| Directory | /workspace/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1090808356 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 3635063644 ps |
| CPU time | 385.87 seconds |
| Started | Feb 07 05:03:15 PM PST 24 |
| Finished | Feb 07 05:09:42 PM PST 24 |
| Peak memory | 632468 kb |
| Host | smart-f43cceb6-3970-4af3-a736-d2ab2e3fc4dd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090808356 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1090808356 |
| Directory | /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/48.chip_sw_all_escalation_resets.279903149 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 5134801248 ps |
| CPU time | 509.67 seconds |
| Started | Feb 07 05:00:56 PM PST 24 |
| Finished | Feb 07 05:09:27 PM PST 24 |
| Peak memory | 633740 kb |
| Host | smart-7e148125-263d-4f83-b30e-2c63aad184fb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 279903149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.279903149 |
| Directory | /workspace/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1142976852 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 3773970652 ps |
| CPU time | 455.95 seconds |
| Started | Feb 07 05:02:52 PM PST 24 |
| Finished | Feb 07 05:10:34 PM PST 24 |
| Peak memory | 633832 kb |
| Host | smart-3d7e2922-04c4-43f7-9f03-73d65903de8a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142976852 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1142976852 |
| Directory | /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/49.chip_sw_all_escalation_resets.1260008006 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 4552056236 ps |
| CPU time | 528.55 seconds |
| Started | Feb 07 05:02:54 PM PST 24 |
| Finished | Feb 07 05:11:47 PM PST 24 |
| Peak memory | 636580 kb |
| Host | smart-e84bbaf8-8217-4da8-8b5f-c61cc01ae293 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1260008006 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.1260008006 |
| Directory | /workspace/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1686025757 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 3640965888 ps |
| CPU time | 450.62 seconds |
| Started | Feb 07 04:58:00 PM PST 24 |
| Finished | Feb 07 05:05:31 PM PST 24 |
| Peak memory | 632588 kb |
| Host | smart-72d5fcd1-ae20-4759-baa9-44b50138c248 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686025757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_s w_alert_handler_lpg_sleep_mode_alerts.1686025757 |
| Directory | /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_all_escalation_resets.3672612524 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 4895644260 ps |
| CPU time | 709.6 seconds |
| Started | Feb 07 04:56:32 PM PST 24 |
| Finished | Feb 07 05:08:22 PM PST 24 |
| Peak memory | 633852 kb |
| Host | smart-3c14a0ac-a151-4e85-8f3a-db5f7ae64808 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3672612524 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.3672612524 |
| Directory | /workspace/5.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_data_integrity_escalation.3265523587 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 6052777630 ps |
| CPU time | 834.2 seconds |
| Started | Feb 07 04:57:46 PM PST 24 |
| Finished | Feb 07 05:11:41 PM PST 24 |
| Peak memory | 601992 kb |
| Host | smart-fb2e4efd-0977-47c0-bc80-bb51a2688491 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3265523587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.3265523587 |
| Directory | /workspace/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3656344376 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 12922273564 ps |
| CPU time | 818.58 seconds |
| Started | Feb 07 04:59:54 PM PST 24 |
| Finished | Feb 07 05:13:34 PM PST 24 |
| Peak memory | 603976 kb |
| Host | smart-43b08934-f19f-4660-9654-ce586f313489 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656344376 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.3656344376 |
| Directory | /workspace/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2378256975 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 13911308048 ps |
| CPU time | 2016.33 seconds |
| Started | Feb 07 04:57:39 PM PST 24 |
| Finished | Feb 07 05:31:16 PM PST 24 |
| Peak memory | 601836 kb |
| Host | smart-cd60eedf-a9e4-4218-83dd-fb97832d022a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2378256975 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.2378256975 |
| Directory | /workspace/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1780306387 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 4176545960 ps |
| CPU time | 443.9 seconds |
| Started | Feb 07 05:01:53 PM PST 24 |
| Finished | Feb 07 05:09:17 PM PST 24 |
| Peak memory | 634064 kb |
| Host | smart-08619d39-149a-45b7-85a4-ddc6b7736d60 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780306387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1780306387 |
| Directory | /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/50.chip_sw_all_escalation_resets.2546077736 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 5278074592 ps |
| CPU time | 552.03 seconds |
| Started | Feb 07 05:02:22 PM PST 24 |
| Finished | Feb 07 05:11:44 PM PST 24 |
| Peak memory | 635144 kb |
| Host | smart-88edb57c-5124-4d57-a8cf-f986a3604e43 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2546077736 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.2546077736 |
| Directory | /workspace/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2033479093 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 3314374544 ps |
| CPU time | 331.58 seconds |
| Started | Feb 07 05:01:23 PM PST 24 |
| Finished | Feb 07 05:06:55 PM PST 24 |
| Peak memory | 634144 kb |
| Host | smart-7357b430-6079-406f-ad6f-fef14809bb68 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033479093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2033479093 |
| Directory | /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/51.chip_sw_all_escalation_resets.2927609170 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 5353418424 ps |
| CPU time | 908.11 seconds |
| Started | Feb 07 05:01:46 PM PST 24 |
| Finished | Feb 07 05:16:55 PM PST 24 |
| Peak memory | 635152 kb |
| Host | smart-c57fb2a5-2a60-4d1c-b809-27e323f927d9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2927609170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.2927609170 |
| Directory | /workspace/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/52.chip_sw_all_escalation_resets.1119314749 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 4057556724 ps |
| CPU time | 525.74 seconds |
| Started | Feb 07 05:01:56 PM PST 24 |
| Finished | Feb 07 05:10:42 PM PST 24 |
| Peak memory | 634888 kb |
| Host | smart-8be91dba-d63d-44ff-8e93-c6c23b768f2e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1119314749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.1119314749 |
| Directory | /workspace/52.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.847452163 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 3603572904 ps |
| CPU time | 415.18 seconds |
| Started | Feb 07 05:05:06 PM PST 24 |
| Finished | Feb 07 05:12:03 PM PST 24 |
| Peak memory | 633868 kb |
| Host | smart-b443de7d-6811-4630-b8ae-8c6bf50e1a9e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847452163 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_s w_alert_handler_lpg_sleep_mode_alerts.847452163 |
| Directory | /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/54.chip_sw_all_escalation_resets.3711889361 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 4929802826 ps |
| CPU time | 575.3 seconds |
| Started | Feb 07 05:04:51 PM PST 24 |
| Finished | Feb 07 05:14:27 PM PST 24 |
| Peak memory | 600396 kb |
| Host | smart-2774b2db-b7b3-4ef2-a43e-18a11156fe0a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3711889361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.3711889361 |
| Directory | /workspace/54.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3491954617 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 3356466630 ps |
| CPU time | 437.53 seconds |
| Started | Feb 07 05:02:40 PM PST 24 |
| Finished | Feb 07 05:10:04 PM PST 24 |
| Peak memory | 632492 kb |
| Host | smart-c2a23e6d-391f-4edf-9339-2f5ff37bcadc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491954617 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3491954617 |
| Directory | /workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/55.chip_sw_all_escalation_resets.279820876 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 4264875300 ps |
| CPU time | 684.51 seconds |
| Started | Feb 07 05:02:27 PM PST 24 |
| Finished | Feb 07 05:13:57 PM PST 24 |
| Peak memory | 634980 kb |
| Host | smart-82c8e5ba-f494-406b-8624-f1cecbbea6c4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 279820876 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.279820876 |
| Directory | /workspace/55.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/57.chip_sw_all_escalation_resets.829668066 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 5795662360 ps |
| CPU time | 645.75 seconds |
| Started | Feb 07 05:03:11 PM PST 24 |
| Finished | Feb 07 05:13:57 PM PST 24 |
| Peak memory | 635228 kb |
| Host | smart-b94f83fb-e2a5-497d-85a3-48b2ebdc54f1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 829668066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.829668066 |
| Directory | /workspace/57.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3765433307 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 4402232332 ps |
| CPU time | 413.64 seconds |
| Started | Feb 07 05:05:09 PM PST 24 |
| Finished | Feb 07 05:12:07 PM PST 24 |
| Peak memory | 634000 kb |
| Host | smart-a6e5cc8e-844a-46be-963e-26526f65fe67 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765433307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3765433307 |
| Directory | /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/58.chip_sw_all_escalation_resets.4177668948 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 5064082080 ps |
| CPU time | 571.53 seconds |
| Started | Feb 07 05:03:19 PM PST 24 |
| Finished | Feb 07 05:12:51 PM PST 24 |
| Peak memory | 633996 kb |
| Host | smart-f156fe3e-582e-46a6-af8a-f18dc6d5152f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4177668948 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.4177668948 |
| Directory | /workspace/58.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3877768515 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 3664988296 ps |
| CPU time | 467.33 seconds |
| Started | Feb 07 05:02:59 PM PST 24 |
| Finished | Feb 07 05:10:47 PM PST 24 |
| Peak memory | 634108 kb |
| Host | smart-04960723-72a6-4984-a2f3-c52d401773bf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877768515 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3877768515 |
| Directory | /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3693066482 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 3282040192 ps |
| CPU time | 307.77 seconds |
| Started | Feb 07 05:00:16 PM PST 24 |
| Finished | Feb 07 05:05:24 PM PST 24 |
| Peak memory | 632464 kb |
| Host | smart-70f814bb-6008-4c85-abfd-990b557906ed |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693066482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_s w_alert_handler_lpg_sleep_mode_alerts.3693066482 |
| Directory | /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_all_escalation_resets.3652952363 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 4020244136 ps |
| CPU time | 560.35 seconds |
| Started | Feb 07 04:58:36 PM PST 24 |
| Finished | Feb 07 05:07:57 PM PST 24 |
| Peak memory | 635092 kb |
| Host | smart-3962d026-3e7a-4849-898a-10d3703504e2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3652952363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.3652952363 |
| Directory | /workspace/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2336295612 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 6070628608 ps |
| CPU time | 631.17 seconds |
| Started | Feb 07 04:57:01 PM PST 24 |
| Finished | Feb 07 05:07:33 PM PST 24 |
| Peak memory | 604012 kb |
| Host | smart-df57a984-b558-4ea9-b7f2-a5887b516181 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336295612 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.2336295612 |
| Directory | /workspace/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3463468954 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 12634518866 ps |
| CPU time | 1979.15 seconds |
| Started | Feb 07 04:56:41 PM PST 24 |
| Finished | Feb 07 05:29:40 PM PST 24 |
| Peak memory | 613800 kb |
| Host | smart-935a63ad-173b-4aed-bf3c-1508b8cd7168 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3463468954 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.3463468954 |
| Directory | /workspace/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/60.chip_sw_all_escalation_resets.454668378 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 4740290128 ps |
| CPU time | 530.65 seconds |
| Started | Feb 07 05:03:42 PM PST 24 |
| Finished | Feb 07 05:12:33 PM PST 24 |
| Peak memory | 635608 kb |
| Host | smart-02917ce3-2eae-4145-82c9-aba66e7e58dd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 454668378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.454668378 |
| Directory | /workspace/60.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.1595659855 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 4091323472 ps |
| CPU time | 443.78 seconds |
| Started | Feb 07 05:03:55 PM PST 24 |
| Finished | Feb 07 05:11:20 PM PST 24 |
| Peak memory | 633868 kb |
| Host | smart-687ea3f6-e812-4204-b5be-88045798d4ce |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595659855 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1595659855 |
| Directory | /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/61.chip_sw_all_escalation_resets.936064744 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 5837822734 ps |
| CPU time | 529.54 seconds |
| Started | Feb 07 05:04:04 PM PST 24 |
| Finished | Feb 07 05:12:54 PM PST 24 |
| Peak memory | 633876 kb |
| Host | smart-484f01bc-c426-4624-b679-efac25697000 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 936064744 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.936064744 |
| Directory | /workspace/61.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.4126926736 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 3290528776 ps |
| CPU time | 473.55 seconds |
| Started | Feb 07 05:03:11 PM PST 24 |
| Finished | Feb 07 05:11:06 PM PST 24 |
| Peak memory | 633568 kb |
| Host | smart-1b0da14a-83c1-492f-bd3f-c1231595e015 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126926736 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4126926736 |
| Directory | /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/62.chip_sw_all_escalation_resets.1191563600 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 4226062580 ps |
| CPU time | 533.5 seconds |
| Started | Feb 07 05:04:11 PM PST 24 |
| Finished | Feb 07 05:13:05 PM PST 24 |
| Peak memory | 635204 kb |
| Host | smart-ad46121f-8f71-40f0-9f7e-397992e142d3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1191563600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.1191563600 |
| Directory | /workspace/62.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3637751116 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 3543370618 ps |
| CPU time | 358.32 seconds |
| Started | Feb 07 05:02:58 PM PST 24 |
| Finished | Feb 07 05:08:58 PM PST 24 |
| Peak memory | 632500 kb |
| Host | smart-75564472-35a2-4bb1-843b-6c2e9a63811e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637751116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3637751116 |
| Directory | /workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/63.chip_sw_all_escalation_resets.3711372920 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 4882303900 ps |
| CPU time | 571.46 seconds |
| Started | Feb 07 05:02:27 PM PST 24 |
| Finished | Feb 07 05:12:04 PM PST 24 |
| Peak memory | 636320 kb |
| Host | smart-43af5bb5-9939-4d3f-bc34-e47280a05ec4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3711372920 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.3711372920 |
| Directory | /workspace/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/64.chip_sw_all_escalation_resets.4289277848 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 5080660112 ps |
| CPU time | 461.18 seconds |
| Started | Feb 07 05:04:28 PM PST 24 |
| Finished | Feb 07 05:12:10 PM PST 24 |
| Peak memory | 633876 kb |
| Host | smart-7027c4d5-2edb-4b1f-808b-6c61d9d84276 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4289277848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.4289277848 |
| Directory | /workspace/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1318408479 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 3752862868 ps |
| CPU time | 348.82 seconds |
| Started | Feb 07 05:02:36 PM PST 24 |
| Finished | Feb 07 05:08:25 PM PST 24 |
| Peak memory | 633832 kb |
| Host | smart-7270696a-9966-4f00-9efe-54b4418586e5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318408479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1318408479 |
| Directory | /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/66.chip_sw_all_escalation_resets.4075033843 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 5900813672 ps |
| CPU time | 653.04 seconds |
| Started | Feb 07 05:02:54 PM PST 24 |
| Finished | Feb 07 05:13:51 PM PST 24 |
| Peak memory | 635404 kb |
| Host | smart-cf5edb3c-7021-46d1-9455-55805a5a9482 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4075033843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.4075033843 |
| Directory | /workspace/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.616371486 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 3696119792 ps |
| CPU time | 535.92 seconds |
| Started | Feb 07 05:05:36 PM PST 24 |
| Finished | Feb 07 05:14:33 PM PST 24 |
| Peak memory | 633816 kb |
| Host | smart-43059c5c-d0d5-46de-8e18-f6484e7baebd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616371486 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_s w_alert_handler_lpg_sleep_mode_alerts.616371486 |
| Directory | /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/67.chip_sw_all_escalation_resets.1394036093 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 4073412140 ps |
| CPU time | 543.65 seconds |
| Started | Feb 07 05:05:30 PM PST 24 |
| Finished | Feb 07 05:14:35 PM PST 24 |
| Peak memory | 634996 kb |
| Host | smart-8fd67ab3-3288-4fc4-8f4b-601698c43ab1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1394036093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.1394036093 |
| Directory | /workspace/67.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.4099316004 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 3661424856 ps |
| CPU time | 318.57 seconds |
| Started | Feb 07 05:04:00 PM PST 24 |
| Finished | Feb 07 05:09:20 PM PST 24 |
| Peak memory | 634108 kb |
| Host | smart-a5cccca8-7e3d-47c5-962f-c6925b6b34fd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099316004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4099316004 |
| Directory | /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2839282573 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 3754909422 ps |
| CPU time | 412.25 seconds |
| Started | Feb 07 05:05:28 PM PST 24 |
| Finished | Feb 07 05:12:23 PM PST 24 |
| Peak memory | 633708 kb |
| Host | smart-9a2e41fb-d9de-455a-b1d5-e2bc8b120ccb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839282573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2839282573 |
| Directory | /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/69.chip_sw_all_escalation_resets.3618376207 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 6246818708 ps |
| CPU time | 636.83 seconds |
| Started | Feb 07 05:04:27 PM PST 24 |
| Finished | Feb 07 05:15:05 PM PST 24 |
| Peak memory | 634116 kb |
| Host | smart-43a2e51e-bd9b-4ff9-aff3-3c5017c59fb0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3618376207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.3618376207 |
| Directory | /workspace/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2512335937 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 3745844848 ps |
| CPU time | 410.57 seconds |
| Started | Feb 07 05:00:08 PM PST 24 |
| Finished | Feb 07 05:06:59 PM PST 24 |
| Peak memory | 632432 kb |
| Host | smart-732e5b60-6b32-46ae-a9ce-b497534bb387 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512335937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_s w_alert_handler_lpg_sleep_mode_alerts.2512335937 |
| Directory | /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_all_escalation_resets.956704929 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 4543785010 ps |
| CPU time | 545.28 seconds |
| Started | Feb 07 04:57:03 PM PST 24 |
| Finished | Feb 07 05:06:11 PM PST 24 |
| Peak memory | 633948 kb |
| Host | smart-07bb2086-c39e-4f69-8046-bcfeaacfb8f0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 956704929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.956704929 |
| Directory | /workspace/7.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3728543918 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 11226143729 ps |
| CPU time | 838.16 seconds |
| Started | Feb 07 04:57:20 PM PST 24 |
| Finished | Feb 07 05:11:20 PM PST 24 |
| Peak memory | 603924 kb |
| Host | smart-da42e3da-1104-466e-8cab-92b9685d18a5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728543918 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.3728543918 |
| Directory | /workspace/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3171958486 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 4506210224 ps |
| CPU time | 723.41 seconds |
| Started | Feb 07 04:58:03 PM PST 24 |
| Finished | Feb 07 05:10:07 PM PST 24 |
| Peak memory | 601784 kb |
| Host | smart-316af9e2-6fad-4cf1-857b-454b284e76ff |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3171958486 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.3171958486 |
| Directory | /workspace/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1381823580 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 3503716370 ps |
| CPU time | 404.04 seconds |
| Started | Feb 07 05:03:59 PM PST 24 |
| Finished | Feb 07 05:10:44 PM PST 24 |
| Peak memory | 634092 kb |
| Host | smart-0e63da27-c0f9-432f-aeeb-ee56983efecf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381823580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1381823580 |
| Directory | /workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/70.chip_sw_all_escalation_resets.1379455401 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 4756335742 ps |
| CPU time | 551.54 seconds |
| Started | Feb 07 05:04:28 PM PST 24 |
| Finished | Feb 07 05:13:40 PM PST 24 |
| Peak memory | 635284 kb |
| Host | smart-34e0be4a-1418-4f1c-8663-3d813a24cceb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1379455401 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.1379455401 |
| Directory | /workspace/70.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3388555489 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 3274250430 ps |
| CPU time | 462.47 seconds |
| Started | Feb 07 05:04:15 PM PST 24 |
| Finished | Feb 07 05:11:58 PM PST 24 |
| Peak memory | 632764 kb |
| Host | smart-b08d7769-57b8-4af4-bdc6-ed36b75ca002 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388555489 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3388555489 |
| Directory | /workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2410134717 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 3917547470 ps |
| CPU time | 378.66 seconds |
| Started | Feb 07 05:03:31 PM PST 24 |
| Finished | Feb 07 05:09:51 PM PST 24 |
| Peak memory | 633808 kb |
| Host | smart-668f6d1b-b6b5-4469-b0bd-95e1eabd14e1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410134717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2410134717 |
| Directory | /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/72.chip_sw_all_escalation_resets.2558065777 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 5440965936 ps |
| CPU time | 649.26 seconds |
| Started | Feb 07 05:04:15 PM PST 24 |
| Finished | Feb 07 05:15:05 PM PST 24 |
| Peak memory | 635232 kb |
| Host | smart-8bae791a-a133-44de-a0b7-73cedbcd11c5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2558065777 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.2558065777 |
| Directory | /workspace/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.808112719 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 3381889434 ps |
| CPU time | 324.31 seconds |
| Started | Feb 07 05:04:00 PM PST 24 |
| Finished | Feb 07 05:09:25 PM PST 24 |
| Peak memory | 633916 kb |
| Host | smart-651af796-2e49-4bae-af76-266ed13d1968 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808112719 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_s w_alert_handler_lpg_sleep_mode_alerts.808112719 |
| Directory | /workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/74.chip_sw_all_escalation_resets.1374284166 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 5007557460 ps |
| CPU time | 687.33 seconds |
| Started | Feb 07 05:03:59 PM PST 24 |
| Finished | Feb 07 05:15:27 PM PST 24 |
| Peak memory | 633452 kb |
| Host | smart-352fe5de-b60f-4628-a0a4-d0de12b993c0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1374284166 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.1374284166 |
| Directory | /workspace/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.4186737350 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 3397199000 ps |
| CPU time | 488.5 seconds |
| Started | Feb 07 05:04:41 PM PST 24 |
| Finished | Feb 07 05:12:50 PM PST 24 |
| Peak memory | 632472 kb |
| Host | smart-5e0dba27-c44b-4e04-9d77-62a9763e2e19 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186737350 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4186737350 |
| Directory | /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/75.chip_sw_all_escalation_resets.2840460229 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 5940535000 ps |
| CPU time | 689.04 seconds |
| Started | Feb 07 05:05:22 PM PST 24 |
| Finished | Feb 07 05:16:56 PM PST 24 |
| Peak memory | 634888 kb |
| Host | smart-fcbe61b4-a5be-4a4e-bd4d-82ad10db6e9c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2840460229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.2840460229 |
| Directory | /workspace/75.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3040011744 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 3943808436 ps |
| CPU time | 440.61 seconds |
| Started | Feb 07 05:04:08 PM PST 24 |
| Finished | Feb 07 05:11:29 PM PST 24 |
| Peak memory | 634068 kb |
| Host | smart-7d9f1b0f-09ed-46fb-a316-d1130a47d878 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040011744 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3040011744 |
| Directory | /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/76.chip_sw_all_escalation_resets.4251935586 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 4649152066 ps |
| CPU time | 603.53 seconds |
| Started | Feb 07 05:03:22 PM PST 24 |
| Finished | Feb 07 05:13:28 PM PST 24 |
| Peak memory | 635208 kb |
| Host | smart-99653469-e5c0-4984-ad87-155ed6d80cde |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4251935586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.4251935586 |
| Directory | /workspace/76.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1019182060 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 4332757236 ps |
| CPU time | 389.42 seconds |
| Started | Feb 07 05:05:13 PM PST 24 |
| Finished | Feb 07 05:11:44 PM PST 24 |
| Peak memory | 634196 kb |
| Host | smart-85a816fb-ab82-423f-9998-00764f5bd074 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019182060 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1019182060 |
| Directory | /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/77.chip_sw_all_escalation_resets.1537423283 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 5993159368 ps |
| CPU time | 671.04 seconds |
| Started | Feb 07 05:03:05 PM PST 24 |
| Finished | Feb 07 05:14:17 PM PST 24 |
| Peak memory | 634960 kb |
| Host | smart-46669a29-4cc3-4f76-85b4-0069e39cc044 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1537423283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.1537423283 |
| Directory | /workspace/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3654053025 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 3998052606 ps |
| CPU time | 419.98 seconds |
| Started | Feb 07 05:05:11 PM PST 24 |
| Finished | Feb 07 05:12:13 PM PST 24 |
| Peak memory | 634888 kb |
| Host | smart-11352f71-3d9c-463c-ba59-0d9bd9c4b6d0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654053025 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3654053025 |
| Directory | /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2252337618 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 3611942696 ps |
| CPU time | 440.37 seconds |
| Started | Feb 07 05:04:16 PM PST 24 |
| Finished | Feb 07 05:11:37 PM PST 24 |
| Peak memory | 633908 kb |
| Host | smart-5681d932-1f38-4ed1-b50d-bed24cb632dc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252337618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2252337618 |
| Directory | /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/79.chip_sw_all_escalation_resets.3695500297 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 4472602960 ps |
| CPU time | 647.97 seconds |
| Started | Feb 07 05:03:46 PM PST 24 |
| Finished | Feb 07 05:14:35 PM PST 24 |
| Peak memory | 635252 kb |
| Host | smart-babb1870-3e90-41db-b6d6-6e1adec1a44a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3695500297 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.3695500297 |
| Directory | /workspace/79.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_all_escalation_resets.3758866729 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 5572345332 ps |
| CPU time | 877.62 seconds |
| Started | Feb 07 04:59:18 PM PST 24 |
| Finished | Feb 07 05:13:57 PM PST 24 |
| Peak memory | 634924 kb |
| Host | smart-21250b19-dc8b-4ec9-9948-b3a454e50971 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3758866729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.3758866729 |
| Directory | /workspace/8.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.105318658 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 4769540339 ps |
| CPU time | 475.1 seconds |
| Started | Feb 07 04:57:12 PM PST 24 |
| Finished | Feb 07 05:05:10 PM PST 24 |
| Peak memory | 603680 kb |
| Host | smart-07ef6ac4-7fec-4638-82f6-a6b458245080 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105318658 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.105318658 |
| Directory | /workspace/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2074115685 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 12389145118 ps |
| CPU time | 2058.51 seconds |
| Started | Feb 07 05:01:01 PM PST 24 |
| Finished | Feb 07 05:35:21 PM PST 24 |
| Peak memory | 601824 kb |
| Host | smart-61957034-35b2-48ad-9709-14325efb96eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2074115685 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.2074115685 |
| Directory | /workspace/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3576680756 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 3823701266 ps |
| CPU time | 419.91 seconds |
| Started | Feb 07 05:04:20 PM PST 24 |
| Finished | Feb 07 05:11:20 PM PST 24 |
| Peak memory | 632584 kb |
| Host | smart-8a4d8d43-f610-4185-b931-3a0f42ae1002 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576680756 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3576680756 |
| Directory | /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1392038715 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 3670321492 ps |
| CPU time | 380.16 seconds |
| Started | Feb 07 05:07:49 PM PST 24 |
| Finished | Feb 07 05:14:12 PM PST 24 |
| Peak memory | 632404 kb |
| Host | smart-875251db-c7cd-42f3-9043-be17142b6804 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392038715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1392038715 |
| Directory | /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_all_escalation_resets.2896097555 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 5650317000 ps |
| CPU time | 613.91 seconds |
| Started | Feb 07 05:05:39 PM PST 24 |
| Finished | Feb 07 05:15:54 PM PST 24 |
| Peak memory | 605908 kb |
| Host | smart-c0b82de8-ab4b-42db-8158-6e0e442d434a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2896097555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.2896097555 |
| Directory | /workspace/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.276425287 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 3839442046 ps |
| CPU time | 480.25 seconds |
| Started | Feb 07 05:05:37 PM PST 24 |
| Finished | Feb 07 05:13:38 PM PST 24 |
| Peak memory | 632748 kb |
| Host | smart-adc825dc-644a-43b6-b37e-7bc357643487 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276425287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_s w_alert_handler_lpg_sleep_mode_alerts.276425287 |
| Directory | /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/84.chip_sw_all_escalation_resets.2405169407 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 4838276168 ps |
| CPU time | 519.84 seconds |
| Started | Feb 07 05:03:20 PM PST 24 |
| Finished | Feb 07 05:12:04 PM PST 24 |
| Peak memory | 635256 kb |
| Host | smart-aa1b3da2-8c30-46c9-adf5-fdcb72388b3d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2405169407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.2405169407 |
| Directory | /workspace/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2770458869 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 3895815342 ps |
| CPU time | 370.77 seconds |
| Started | Feb 07 05:05:01 PM PST 24 |
| Finished | Feb 07 05:11:12 PM PST 24 |
| Peak memory | 634132 kb |
| Host | smart-8c471ec9-33e6-4482-b363-ed2873f31c23 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770458869 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2770458869 |
| Directory | /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/85.chip_sw_all_escalation_resets.549959668 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 4761870376 ps |
| CPU time | 546.54 seconds |
| Started | Feb 07 05:03:39 PM PST 24 |
| Finished | Feb 07 05:12:46 PM PST 24 |
| Peak memory | 633848 kb |
| Host | smart-aa929193-1055-41eb-b578-ff1206659db0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 549959668 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.549959668 |
| Directory | /workspace/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/86.chip_sw_all_escalation_resets.2571077177 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 6103354052 ps |
| CPU time | 728.34 seconds |
| Started | Feb 07 05:04:18 PM PST 24 |
| Finished | Feb 07 05:16:27 PM PST 24 |
| Peak memory | 634176 kb |
| Host | smart-6472297f-5720-4243-bfbf-1545359fbf6c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2571077177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.2571077177 |
| Directory | /workspace/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1593688425 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 3656071390 ps |
| CPU time | 370.21 seconds |
| Started | Feb 07 05:05:40 PM PST 24 |
| Finished | Feb 07 05:11:51 PM PST 24 |
| Peak memory | 633756 kb |
| Host | smart-0f2c3f46-1749-409f-8bec-ca8051ef8c5e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593688425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1593688425 |
| Directory | /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/87.chip_sw_all_escalation_resets.3065516573 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 4775534916 ps |
| CPU time | 503.44 seconds |
| Started | Feb 07 05:04:16 PM PST 24 |
| Finished | Feb 07 05:12:40 PM PST 24 |
| Peak memory | 601864 kb |
| Host | smart-8dfead6b-3ebf-49a6-9984-39089f24a82b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3065516573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.3065516573 |
| Directory | /workspace/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/88.chip_sw_all_escalation_resets.4011187879 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 4562327112 ps |
| CPU time | 504.63 seconds |
| Started | Feb 07 05:04:25 PM PST 24 |
| Finished | Feb 07 05:12:52 PM PST 24 |
| Peak memory | 635432 kb |
| Host | smart-13563c3e-cc17-4c1e-9fba-6acf09f926d0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4011187879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.4011187879 |
| Directory | /workspace/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.671475112 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 3914425890 ps |
| CPU time | 381.36 seconds |
| Started | Feb 07 05:04:21 PM PST 24 |
| Finished | Feb 07 05:10:46 PM PST 24 |
| Peak memory | 633988 kb |
| Host | smart-a8554d13-4c3d-4cb6-903f-aab58d73cf5f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671475112 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_s w_alert_handler_lpg_sleep_mode_alerts.671475112 |
| Directory | /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/89.chip_sw_all_escalation_resets.2568227654 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 5736297368 ps |
| CPU time | 545.35 seconds |
| Started | Feb 07 05:04:35 PM PST 24 |
| Finished | Feb 07 05:13:41 PM PST 24 |
| Peak memory | 633944 kb |
| Host | smart-ac12a69d-700e-4f4f-8ce7-0e3a72305882 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2568227654 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.2568227654 |
| Directory | /workspace/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2830313921 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 3823736556 ps |
| CPU time | 379.23 seconds |
| Started | Feb 07 05:01:51 PM PST 24 |
| Finished | Feb 07 05:08:11 PM PST 24 |
| Peak memory | 633732 kb |
| Host | smart-7bccd4be-e1f3-4730-ba3d-e6292f4d402a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830313921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s w_alert_handler_lpg_sleep_mode_alerts.2830313921 |
| Directory | /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3350132906 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 12797343904 ps |
| CPU time | 1239.67 seconds |
| Started | Feb 07 04:58:08 PM PST 24 |
| Finished | Feb 07 05:18:48 PM PST 24 |
| Peak memory | 604004 kb |
| Host | smart-ac8b2ef2-0688-47ed-9e97-56e1ed47a083 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350132906 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.3350132906 |
| Directory | /workspace/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3618705780 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 23299530864 ps |
| CPU time | 3904.56 seconds |
| Started | Feb 07 04:58:06 PM PST 24 |
| Finished | Feb 07 06:03:11 PM PST 24 |
| Peak memory | 601768 kb |
| Host | smart-f5a707d2-1159-421d-9acd-82d2acdd116f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3618705780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.3618705780 |
| Directory | /workspace/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/91.chip_sw_all_escalation_resets.1932662484 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 5003412920 ps |
| CPU time | 594.88 seconds |
| Started | Feb 07 05:07:17 PM PST 24 |
| Finished | Feb 07 05:17:14 PM PST 24 |
| Peak memory | 634108 kb |
| Host | smart-3ea0f07c-37ab-4a8d-aed3-0bac92801cf0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1932662484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.1932662484 |
| Directory | /workspace/91.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/93.chip_sw_all_escalation_resets.4275414199 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 4887588088 ps |
| CPU time | 396.96 seconds |
| Started | Feb 07 05:05:28 PM PST 24 |
| Finished | Feb 07 05:12:08 PM PST 24 |
| Peak memory | 635288 kb |
| Host | smart-3b44dbdc-d3a3-43dc-92b5-5a61d08a7d06 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4275414199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.4275414199 |
| Directory | /workspace/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/94.chip_sw_all_escalation_resets.1066749222 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 5033413284 ps |
| CPU time | 414.06 seconds |
| Started | Feb 07 05:04:36 PM PST 24 |
| Finished | Feb 07 05:11:30 PM PST 24 |
| Peak memory | 634148 kb |
| Host | smart-f80c0c38-9816-42f3-9465-c964b1329df8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1066749222 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.1066749222 |
| Directory | /workspace/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/95.chip_sw_all_escalation_resets.1813568317 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 6249083290 ps |
| CPU time | 657.77 seconds |
| Started | Feb 07 05:04:46 PM PST 24 |
| Finished | Feb 07 05:15:45 PM PST 24 |
| Peak memory | 633824 kb |
| Host | smart-3b995bcd-eb12-473a-bbe1-586fc04a38ee |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1813568317 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.1813568317 |
| Directory | /workspace/95.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/96.chip_sw_all_escalation_resets.1791772866 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 4346155434 ps |
| CPU time | 460.42 seconds |
| Started | Feb 07 05:06:58 PM PST 24 |
| Finished | Feb 07 05:14:41 PM PST 24 |
| Peak memory | 633964 kb |
| Host | smart-928c631d-cfb0-4e40-b674-a3745f01c34e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1791772866 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.1791772866 |
| Directory | /workspace/96.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/97.chip_sw_all_escalation_resets.1205232987 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 5238862980 ps |
| CPU time | 630.99 seconds |
| Started | Feb 07 05:04:42 PM PST 24 |
| Finished | Feb 07 05:15:14 PM PST 24 |
| Peak memory | 607380 kb |
| Host | smart-b74522f0-dd2f-4c1f-bdd5-c046a4900870 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1205232987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.1205232987 |
| Directory | /workspace/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/98.chip_sw_all_escalation_resets.2838421806 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 5346333226 ps |
| CPU time | 620.33 seconds |
| Started | Feb 07 05:04:18 PM PST 24 |
| Finished | Feb 07 05:14:40 PM PST 24 |
| Peak memory | 635236 kb |
| Host | smart-e6af1298-e3f3-408f-a9d0-57cf1e26ad9c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2838421806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.2838421806 |
| Directory | /workspace/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/99.chip_sw_all_escalation_resets.2126100285 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 5322333370 ps |
| CPU time | 589.64 seconds |
| Started | Feb 07 05:08:09 PM PST 24 |
| Finished | Feb 07 05:18:03 PM PST 24 |
| Peak memory | 635240 kb |
| Host | smart-a5750d45-e0cc-416f-9c00-cc0518ca8814 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2126100285 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.2126100285 |
| Directory | /workspace/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.4096008706 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 4635417602 ps |
| CPU time | 321.24 seconds |
| Started | Feb 07 04:11:20 PM PST 24 |
| Finished | Feb 07 04:16:41 PM PST 24 |
| Peak memory | 634160 kb |
| Host | smart-61b64d30-0073-408a-9d7d-03f5fc9b7abd |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096008706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 0.chip_padctrl_attributes.4096008706 |
| Directory | /workspace/0.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.959948256 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3991790988 ps |
| CPU time | 245.76 seconds |
| Started | Feb 07 04:11:24 PM PST 24 |
| Finished | Feb 07 04:15:30 PM PST 24 |
| Peak memory | 627628 kb |
| Host | smart-b080303e-3c7d-4519-b5b8-74d3d0f7bbb1 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959948256 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 1.chip_padctrl_attributes.959948256 |
| Directory | /workspace/1.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3418033677 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 4254387536 ps |
| CPU time | 251.44 seconds |
| Started | Feb 07 04:11:21 PM PST 24 |
| Finished | Feb 07 04:15:33 PM PST 24 |
| Peak memory | 625992 kb |
| Host | smart-9a68de24-c606-44b0-ad5f-53ceb87d6b99 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418033677 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 2.chip_padctrl_attributes.3418033677 |
| Directory | /workspace/2.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3808646807 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 4554700853 ps |
| CPU time | 250.54 seconds |
| Started | Feb 07 04:11:23 PM PST 24 |
| Finished | Feb 07 04:15:34 PM PST 24 |
| Peak memory | 626092 kb |
| Host | smart-5c6b3891-74f3-4a88-8a9d-0e05f2ded697 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808646807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 3.chip_padctrl_attributes.3808646807 |
| Directory | /workspace/3.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2899906900 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 4420486298 ps |
| CPU time | 225.56 seconds |
| Started | Feb 07 04:11:25 PM PST 24 |
| Finished | Feb 07 04:15:12 PM PST 24 |
| Peak memory | 633116 kb |
| Host | smart-ae1497b4-bd38-44e2-9756-0f57a7d398d5 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899906900 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 4.chip_padctrl_attributes.2899906900 |
| Directory | /workspace/4.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3603307522 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 4681789562 ps |
| CPU time | 336.37 seconds |
| Started | Feb 07 04:11:22 PM PST 24 |
| Finished | Feb 07 04:16:59 PM PST 24 |
| Peak memory | 634260 kb |
| Host | smart-b73b7296-0460-4ddc-881a-af1a76688733 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603307522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 5.chip_padctrl_attributes.3603307522 |
| Directory | /workspace/5.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.4179104179 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5159852465 ps |
| CPU time | 234.84 seconds |
| Started | Feb 07 04:11:26 PM PST 24 |
| Finished | Feb 07 04:15:21 PM PST 24 |
| Peak memory | 626584 kb |
| Host | smart-f0341c55-3957-4263-890f-28b9d3bc3d7f |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179104179 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 6.chip_padctrl_attributes.4179104179 |
| Directory | /workspace/6.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2876388802 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5416672083 ps |
| CPU time | 236.05 seconds |
| Started | Feb 07 04:11:18 PM PST 24 |
| Finished | Feb 07 04:15:15 PM PST 24 |
| Peak memory | 634212 kb |
| Host | smart-47f8d0e8-45ae-4c74-a53c-fa96979bd44f |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876388802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 7.chip_padctrl_attributes.2876388802 |
| Directory | /workspace/7.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.337816519 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 4171364794 ps |
| CPU time | 232.33 seconds |
| Started | Feb 07 04:11:31 PM PST 24 |
| Finished | Feb 07 04:15:23 PM PST 24 |
| Peak memory | 634252 kb |
| Host | smart-84c92238-8153-4e6c-8df4-7087c60a57ac |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337816519 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 8.chip_padctrl_attributes.337816519 |
| Directory | /workspace/8.chip_padctrl_attributes/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |