Unified Coverage Report :: Module :: sysrst_ctrl

Module : sysrst_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.02	100.00	96.08	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	99.02	100.00	96.08	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.02	100.00	96.08	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.88	99.03	97.85	100.00	92.31	99.26	98.84

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
sysrst_ctrl_csr_assert	100.00						100.00
tlul_assert_device	100.00						100.00
u_prim_flop_2sync_input	100.00	100.00				100.00
u_reg	99.52	99.38	98.40	100.00		99.80	100.00
u_sysrst_ctrl_autoblock	99.46	100.00	97.30		100.00	100.00	100.00
u_sysrst_ctrl_combo	99.79	100.00	98.94		100.00	100.00	100.00
u_sysrst_ctrl_intr	98.61	100.00	94.44			100.00	100.00
u_sysrst_ctrl_keyintr	92.39	95.67	91.56		85.71	94.56	94.47
u_sysrst_ctrl_pin	100.00	100.00	100.00			100.00
u_sysrst_ctrl_ulp	99.03	100.00	95.16		100.00	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sysrst_ctrl

	Line No.	Total	Covered	Percent
TOTAL		17	17	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	310	1	1	100.00
CONT_ASSIGN	311	1	1	100.00

67                        logic [NumAlerts-1:0] alert_test, alerts;
68         1/1            assign alert_test = {reg2hw.alert_test.q & reg2hw.alert_test.qe};
           Tests:       T1 T4 T5 
69                      
70                        for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
71                          prim_alert_sender #(
72                            .AsyncOn(AlertAsyncOn[i]),
73                            .IsFatal(1'b1)
74                          ) u_prim_alert_sender (
75                            .clk_i,
76                            .rst_ni,
77                            .alert_test_i (alert_test[i]),
78                            .alert_req_i  (alerts[0]),
79                            .alert_ack_o  (),
80                            .alert_state_o(),
81                            .alert_rx_i   (alert_rx_i[i]),
82                            .alert_tx_o   (alert_tx_o[i])
83                          );
84                        end
85                      
86                        sysrst_ctrl_reg_top u_reg (
87                          .clk_i,
88                          .rst_ni,
89                          .clk_aon_i,
90                          .rst_aon_ni,
91                          .tl_i,
92                          .tl_o,
93                          .reg2hw,
94                          .hw2reg,
95                          // SEC_CM: BUS.INTEGRITY
96                          .intg_err_o(alerts[0])
97                        );
98                      
99                        ///////////////////////////////////////
100                       // Input inversion and Synchronizers //
101                       ///////////////////////////////////////
102                     
103                       // Optionally invert some of the input signals
104                       logic pwrb_int, key0_int, key1_int, key2_int, ac_present_int, lid_open_int;
105                       logic ec_rst_l_int, flash_wp_l_int;
106        1/1            assign pwrb_int       = reg2hw.key_invert_ctl.pwrb_in.q ^ cio_pwrb_in_i;
           Tests:       T4 T5 T13 
107        1/1            assign key0_int       = reg2hw.key_invert_ctl.key0_in.q ^ cio_key0_in_i;
           Tests:       T1 T4 T5 
108        1/1            assign key1_int       = reg2hw.key_invert_ctl.key1_in.q ^ cio_key1_in_i;
           Tests:       T1 T4 T5 
109        1/1            assign key2_int       = reg2hw.key_invert_ctl.key2_in.q ^ cio_key2_in_i;
           Tests:       T1 T4 T5 
110        1/1            assign ac_present_int = reg2hw.key_invert_ctl.ac_present.q ^ cio_ac_present_i;
           Tests:       T4 T5 T13 
111        1/1            assign lid_open_int   = reg2hw.key_invert_ctl.lid_open.q ^ cio_lid_open_i;
           Tests:       T4 T5 T13 
112                       // Uninverted inputs
113        1/1            assign ec_rst_l_int   = cio_ec_rst_l_i;
           Tests:       T4 T5 T13 
114        1/1            assign flash_wp_l_int = cio_flash_wp_l_i;
           Tests:       T4 T5 T13 
115                     
116                       // Synchronize input signals to AON clock
117                       logic aon_pwrb_int, aon_key0_int, aon_key1_int, aon_key2_int;
118                       logic aon_ac_present_int, aon_lid_open_int, aon_ec_rst_l_int, aon_flash_wp_l_int;
119                       prim_flop_2sync #(
120                         .Width(8)
121                       ) u_prim_flop_2sync_input (
122                         .clk_i(clk_aon_i),
123                         .rst_ni(rst_aon_ni),
124                         .d_i({pwrb_int,
125                               key0_int,
126                               key1_int,
127                               key2_int,
128                               ac_present_int,
129                               lid_open_int,
130                               ec_rst_l_int,
131                               flash_wp_l_int}),
132                         .q_o({
133                           aon_pwrb_int,
134                           aon_key0_int,
135                           aon_key1_int,
136                           aon_key2_int,
137                           aon_ac_present_int,
138                           aon_lid_open_int,
139                           aon_ec_rst_l_int,
140                           aon_flash_wp_l_int
141                         })
142                       );
143                     
144                       ///////////////
145                       // Autoblock //
146                       ///////////////
147                     
148                       // The registers in this module run on the AON clock.
149                       // However, the passthrough signals are NOT synchronous to the AON clock.
150                       logic pwrb_out_hw, key0_out_hw, key1_out_hw, key2_out_hw;
151                       sysrst_ctrl_autoblock u_sysrst_ctrl_autoblock (
152                         .clk_i(clk_aon_i),
153                         .rst_ni(rst_aon_ni),
154                         // (Optionally) inverted input signals on AON clock
155                         .aon_pwrb_int_i(aon_pwrb_int),
156                         // (Optionally) inverted input signals (not synced to AON clock)
157                         .pwrb_int_i(pwrb_int),
158                         .key0_int_i(key0_int),
159                         .key1_int_i(key1_int),
160                         .key2_int_i(key2_int),
161                         // CSRs synced to AON clock
162                         .aon_auto_block_debounce_ctl_i(reg2hw.auto_block_debounce_ctl),
163                         .aon_auto_block_out_ctl_i(reg2hw.auto_block_out_ctl),
164                         // Output signals to pin override logic (not synced to AON clock)
165                         .pwrb_out_hw_o(pwrb_out_hw),
166                         .key0_out_hw_o(key0_out_hw),
167                         .key1_out_hw_o(key1_out_hw),
168                         .key2_out_hw_o(key2_out_hw)
169                       );
170                     
171                       /////////
172                       // ULP //
173                       /////////
174                     
175                       // This module runs on the AON clock entirely.
176                       // Hence, its local signals are not prefixed with aon_*.
177                       logic aon_z3_wakeup_hw;
178                       logic aon_ulp_wakeup_pulse;
179                       sysrst_ctrl_ulp u_sysrst_ctrl_ulp (
180                         .clk_i(clk_aon_i),
181                         .rst_ni(rst_aon_ni),
182                         // (Optionally) inverted input signals on AON clock
183                         .pwrb_int_i(aon_pwrb_int),
184                         .lid_open_int_i(aon_lid_open_int),
185                         .ac_present_int_i(aon_ac_present_int),
186                         // CSRs synced to AON clock
187                         .ulp_ac_debounce_ctl_i(reg2hw.ulp_ac_debounce_ctl),
188                         .ulp_lid_debounce_ctl_i(reg2hw.ulp_lid_debounce_ctl),
189                         .ulp_pwrb_debounce_ctl_i(reg2hw.ulp_pwrb_debounce_ctl),
190                         .ulp_ctl_i(reg2hw.ulp_ctl),
191                         // wakeup pulses on AON clock
192                         .ulp_wakeup_pulse_o(aon_ulp_wakeup_pulse),
193                         .z3_wakeup_hw_o(aon_z3_wakeup_hw)
194                       );
195                     
196                       /////////////////////////////
197                       // Key triggered interrups //
198                       /////////////////////////////
199                     
200                       // This module runs on the AON clock entirely.
201                       // Hence, its local signals are not prefixed with aon_*.
202                       logic [NumKeyIntr-1:0] aon_l2h_key_intr, aon_h2l_key_intr;
203                       sysrst_ctrl_keyintr u_sysrst_ctrl_keyintr (
204                         .clk_i(clk_aon_i),
205                         .rst_ni(rst_aon_ni),
206                         // (Optionally) inverted input signals on AON clock
207                         .pwrb_int_i(aon_pwrb_int),
208                         .key0_int_i(aon_key0_int),
209                         .key1_int_i(aon_key1_int),
210                         .key2_int_i(aon_key2_int),
211                         .ac_present_int_i(aon_ac_present_int),
212                         .ec_rst_l_int_i(aon_ec_rst_l_int),
213                         .flash_wp_l_int_i(aon_flash_wp_l_int),
214                         // CSRs synced to AON clock
215                         .key_intr_ctl_i(reg2hw.key_intr_ctl),
216                         .key_intr_debounce_ctl_i(reg2hw.key_intr_debounce_ctl),
217                         // IRQ running on AON clock
218                         .l2h_key_intr_o(aon_l2h_key_intr),
219                         .h2l_key_intr_o(aon_h2l_key_intr)
220                       );
221                     
222                       /////////////////////
223                       // Combo detection //
224                       /////////////////////
225                     
226                       // This module runs on the AON clock entirely.
227                       // Hence, its local signals are not prefixed with aon_*.
228                       logic [NumCombo-1:0] aon_combo_intr;
229                       logic aon_bat_disable_hw, aon_ec_rst_l_hw;
230                       sysrst_ctrl_combo u_sysrst_ctrl_combo (
231                         .clk_i(clk_aon_i),
232                         .rst_ni(rst_aon_ni),
233                         // (Optionally) inverted input signals on AON clock
234                         .pwrb_int_i(aon_pwrb_int),
235                         .key0_int_i(aon_key0_int),
236                         .key1_int_i(aon_key1_int),
237                         .key2_int_i(aon_key2_int),
238                         .ac_present_int_i(aon_ac_present_int),
239                         .ec_rst_l_int_i(aon_ec_rst_l_int),
240                         // CSRs synced to AON clock
241                         .ec_rst_ctl_i(reg2hw.ec_rst_ctl),
242                         .key_intr_debounce_ctl_i(reg2hw.key_intr_debounce_ctl),
243                         .com_pre_sel_ctl_i(reg2hw.com_pre_sel_ctl),
244                         .com_pre_det_ctl_i(reg2hw.com_pre_det_ctl),
245                         .com_sel_ctl_i(reg2hw.com_sel_ctl),
246                         .com_det_ctl_i(reg2hw.com_det_ctl),
247                         .com_out_ctl_i(reg2hw.com_out_ctl),
248                         // Output signals on AON clock
249                         .combo_intr_o(aon_combo_intr),
250                         .bat_disable_hw_o(aon_bat_disable_hw),
251                         .rst_req_o(rst_req_o),
252                         .ec_rst_l_hw_o(aon_ec_rst_l_hw)
253                       );
254                     
255                       ///////////////////////////////
256                       // Pin visibility / override //
257                       ///////////////////////////////
258                     
259                       // This module operates on both synchronized and unsynchronized signals.
260                       // I.e., the passthrough signals are NOT synchronnous to the AON clock.
261                       logic pwrb_out_int, key0_out_int, key1_out_int, key2_out_int, aon_bat_disable_out_int;
262                       logic aon_z3_wakeup_out_int, aon_ec_rst_out_int_l, aon_flash_wp_out_int_l;
263                       sysrst_ctrl_pin u_sysrst_ctrl_pin (
264                         .clk_i,
265                         .rst_ni,
266                         // Raw input signals (not synced to AON clock)
267                         .cio_pwrb_in_i,
268                         .cio_key0_in_i,
269                         .cio_key1_in_i,
270                         .cio_key2_in_i,
271                         .cio_ac_present_i,
272                         .cio_ec_rst_l_i,
273                         .cio_flash_wp_l_i,
274                         .cio_lid_open_i,
275                         // Signals from autoblock (not synced to AON clock)
276                         .pwrb_out_hw_i(pwrb_out_hw),
277                         .key0_out_hw_i(key0_out_hw),
278                         .key1_out_hw_i(key1_out_hw),
279                         .key2_out_hw_i(key2_out_hw),
280                         // Generated signals, running on AON clock
281                         .aon_bat_disable_hw_i(aon_bat_disable_hw),
282                         .aon_ec_rst_l_hw_i(aon_ec_rst_l_hw),
283                         .aon_z3_wakeup_hw_i(aon_z3_wakeup_hw),
284                         // CSRs synced to AON clock
285                         .aon_pin_allowed_ctl_i(reg2hw.pin_allowed_ctl),
286                         .aon_pin_out_ctl_i(reg2hw.pin_out_ctl),
287                         .aon_pin_out_value_i(reg2hw.pin_out_value),
288                         // CSRs synced to bus clock
289                         .pin_in_value_o(hw2reg.pin_in_value),
290                         // Output signals (not synced to AON clock)
291                         .pwrb_out_int_o(pwrb_out_int),
292                         .key0_out_int_o(key0_out_int),
293                         .key1_out_int_o(key1_out_int),
294                         .key2_out_int_o(key2_out_int),
295                         // Output signals running on AON clock
296                         .aon_bat_disable_out_int_o(aon_bat_disable_out_int),
297                         .aon_z3_wakeup_out_int_o(aon_z3_wakeup_out_int),
298                         .aon_ec_rst_out_int_l_o(aon_ec_rst_out_int_l),
299                         .aon_flash_wp_out_int_l_o(aon_flash_wp_out_int_l)
300                       );
301                     
302                       // Optionally invert some of the output signals
303        1/1            assign cio_pwrb_out_o = reg2hw.key_invert_ctl.pwrb_out.q ^ pwrb_out_int;
           Tests:       T4 T5 T13 
304        1/1            assign cio_key0_out_o = reg2hw.key_invert_ctl.key0_out.q ^ key0_out_int;
           Tests:       T1 T4 T5 
305        1/1            assign cio_key1_out_o = reg2hw.key_invert_ctl.key1_out.q ^ key1_out_int;
           Tests:       T1 T4 T5 
306        1/1            assign cio_key2_out_o = reg2hw.key_invert_ctl.key2_out.q ^ key2_out_int;
           Tests:       T1 T4 T5 
307        1/1            assign cio_bat_disable_o = reg2hw.key_invert_ctl.bat_disable.q ^ aon_bat_disable_out_int;
           Tests:       T5 T14 T17 
308        1/1            assign cio_z3_wakeup_o = reg2hw.key_invert_ctl.z3_wakeup.q ^ aon_z3_wakeup_out_int;
           Tests:       T5 T14 T18 
309                       // uninverted outputs
310        1/1            assign cio_ec_rst_l_o = aon_ec_rst_out_int_l;
           Tests:       T1 T2 T14 
311        1/1            assign cio_flash_wp_l_o = aon_flash_wp_out_int_l;
           Tests:       T14 T17 T26 

---

Cond Coverage for Module : sysrst_ctrl

	Total	Covered	Percent
Conditions	51	49	96.08
Logical	51	49	96.08
Non-Logical	0	0
Event	0	0

 LINE       68
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T64,T77,T67
1	0	Covered	T1,T4,T5
1	1	Covered	T64,T77,T67

 LINE       106
 EXPRESSION (reg2hw.key_invert_ctl.pwrb_in.q ^ cio_pwrb_in_i)
             ---------------1---------------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T4,T5,T13
1	0	Covered	T5,T18,T25
1	1	Covered	T5,T18,T25

 LINE       107
 EXPRESSION (reg2hw.key_invert_ctl.key0_in.q ^ cio_key0_in_i)
             ---------------1---------------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T5,T18,T25
1	1	Covered	T5,T18,T25

 LINE       108
 EXPRESSION (reg2hw.key_invert_ctl.key1_in.q ^ cio_key1_in_i)
             ---------------1---------------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T5,T18,T25
1	1	Covered	T5,T18,T25

 LINE       109
 EXPRESSION (reg2hw.key_invert_ctl.key2_in.q ^ cio_key2_in_i)
             ---------------1---------------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T5,T18,T25
1	1	Covered	T5,T18,T25

 LINE       110
 EXPRESSION (reg2hw.key_invert_ctl.ac_present.q ^ cio_ac_present_i)
             -----------------1----------------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T4,T5,T13
1	0	Covered	T5,T18,T25
1	1	Covered	T5,T18,T25

 LINE       111
 EXPRESSION (reg2hw.key_invert_ctl.lid_open.q ^ cio_lid_open_i)
             ----------------1---------------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T4,T5,T13
1	0	Covered	T5,T18,T25
1	1	Covered	T5,T18,T25

 LINE       303
 EXPRESSION (reg2hw.key_invert_ctl.pwrb_out.q ^ pwrb_out_int)
             ----------------1---------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T4,T5,T13
1	0	Covered	T5,T18,T25
1	1	Covered	T5,T18,T25

 LINE       304
 EXPRESSION (reg2hw.key_invert_ctl.key0_out.q ^ key0_out_int)
             ----------------1---------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T5,T18,T25
1	1	Covered	T5,T18,T25

 LINE       305
 EXPRESSION (reg2hw.key_invert_ctl.key1_out.q ^ key1_out_int)
             ----------------1---------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T5,T18,T25
1	1	Covered	T5,T18,T25

 LINE       306
 EXPRESSION (reg2hw.key_invert_ctl.key2_out.q ^ key2_out_int)
             ----------------1---------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T5,T18,T25
1	1	Covered	T5,T18,T25

 LINE       307
 EXPRESSION (reg2hw.key_invert_ctl.bat_disable.q ^ aon_bat_disable_out_int)
             -----------------1-----------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T14,T17,T26
1	0	Covered	T5,T18,T25
1	1	Not Covered

 LINE       308
 EXPRESSION (reg2hw.key_invert_ctl.z3_wakeup.q ^ aon_z3_wakeup_out_int)
             ----------------1----------------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T14,T26,T6
1	0	Covered	T5,T18,T25
1	1	Not Covered

---

Toggle Coverage for Module : sysrst_ctrl

	Total	Covered	Percent
Totals	47	47	100.00
Total Bits	374	374	100.00
Total Bits 0->1	187	187	100.00
Total Bits 1->0	187	187	100.00

Ports	47	47	100.00
Port Bits	374	374	100.00
Port Bits 0->1	187	187	100.00
Port Bits 1->0	187	187	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
clk_aon_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
rst_ni	Yes	Yes	T17,T87,T103	Yes	T1,T4,T5	INPUT
rst_aon_ni	Yes	Yes	T17,T87,T103	Yes	T1,T4,T5	INPUT
tl_i.d_ready	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T5,T14	Yes	T1,T5,T13	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T5,T13	Yes	T1,T5,T13	INPUT
tl_i.a_valid	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
tl_o.a_ready	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
tl_o.d_error	Yes	Yes	T17,T103,T144	Yes	T17,T103,T144	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T4,T5	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T5,*T2	Yes	T1,T4,T5	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T64,T77,T67	Yes	T64,T77,T67	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T64,T77,T67	Yes	T64,T77,T67	OUTPUT
wkup_req_o	Yes	Yes	T6,T20,T19	Yes	T1,T2,T3	OUTPUT
rst_req_o	Yes	Yes	T20,T32,T42	Yes	T20,T32,T42	OUTPUT
intr_event_detected_o	Yes	Yes	T1,T3,T6	Yes	T1,T3,T6	OUTPUT
cio_ac_present_i	Yes	Yes	T4,T5,T13	Yes	T4,T5,T13	INPUT
cio_ec_rst_l_i	Yes	Yes	T4,T5,T13	Yes	T4,T5,T13	INPUT
cio_key0_in_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
cio_key1_in_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
cio_key2_in_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
cio_pwrb_in_i	Yes	Yes	T4,T5,T13	Yes	T4,T5,T13	INPUT
cio_lid_open_i	Yes	Yes	T4,T5,T13	Yes	T4,T5,T13	INPUT
cio_flash_wp_l_i	Yes	Yes	T4,T5,T13	Yes	T4,T5,T13	INPUT
cio_bat_disable_o	Yes	Yes	T5,T14,T17	Yes	T5,T14,T17	OUTPUT
cio_flash_wp_l_o	Yes	Yes	T14,T17,T26	Yes	T14,T17,T26	OUTPUT
cio_ec_rst_l_o	Yes	Yes	T1,T2,T14	Yes	T1,T2,T14	OUTPUT
cio_key0_out_o	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
cio_key1_out_o	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
cio_key2_out_o	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
cio_pwrb_out_o	Yes	Yes	T4,T5,T13	Yes	T4,T5,T13	OUTPUT
cio_z3_wakeup_o	Yes	Yes	T5,T14,T18	Yes	T5,T14,T18	OUTPUT
cio_bat_disable_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_flash_wp_l_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_ec_rst_l_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_key0_out_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_key1_out_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_key2_out_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_pwrb_out_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_z3_wakeup_en_o	Unreachable	Unreachable		Unreachable		OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : sysrst_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	23	23	100.00	23	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	23	23	100.00	23	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnown_A	1215441677	1215058144	0	0
BatOEnIsOne_A	1215441677	1215058144	0	0
BatOKnown_A	1215441677	1215058144	0	0
ECRSTOEnIsOne_A	1215441677	1215058144	0	0
ECRSTOKnown_A	1215441677	1215058144	0	0
FlashWpOEnIsOne_A	1215441677	1215058144	0	0
FlashWpOKnown_A	1215441677	1215058144	0	0
FpvSecCmRegWeOnehotCheck_A	1215441677	90	0	0
IntrEventOKnown_A	1215441677	1215058144	0	0
Key0OEnIsOne_A	1215441677	1215058144	0	0
Key0OKnown_A	1215441677	1215058144	0	0
Key1OEnIsOne_A	1215441677	1215058144	0	0
Key1OKnown_A	1215441677	1215058144	0	0
Key2OEnIsOne_A	1215441677	1215058144	0	0
Key2OKnown_A	1215441677	1215058144	0	0
OTRstOKnown_A	1215441677	1215058144	0	0
OTWkOKnown_A	1215441677	1215058144	0	0
PwrbOEnIsOne_A	1215441677	1215058144	0	0
PwrbOKnown_A	1215441677	1215058144	0	0
TlOAReadyKnown_A	1215441677	1215058144	0	0
TlODValidKnown_A	1215441677	1215058144	0	0
Z3WakeupOEnIsOne_A	1215441677	1215058144	0	0
Z3WwakupOKnown_A	1215441677	1215058144	0	0

AlertKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1215441677	1215058144	0	0
T1	68287	68227	0	0
T2	215378	215323	0	0
T4	55930	55873	0	0
T5	235905	235818	0	0
T13	202586	202518	0	0
T14	128132	128047	0	0
T15	173596	173500	0	0
T16	337249	337169	0	0
T17	159909	158990	0	0
T18	57201	57150	0	0

BatOEnIsOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1215441677	1215058144	0	0
T1	68287	68227	0	0
T2	215378	215323	0	0
T4	55930	55873	0	0
T5	235905	235818	0	0
T13	202586	202518	0	0
T14	128132	128047	0	0
T15	173596	173500	0	0
T16	337249	337169	0	0
T17	159909	158990	0	0
T18	57201	57150	0	0

BatOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1215441677	1215058144	0	0
T1	68287	68227	0	0
T2	215378	215323	0	0
T4	55930	55873	0	0
T5	235905	235818	0	0
T13	202586	202518	0	0
T14	128132	128047	0	0
T15	173596	173500	0	0
T16	337249	337169	0	0
T17	159909	158990	0	0
T18	57201	57150	0	0

ECRSTOEnIsOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1215441677	1215058144	0	0
T1	68287	68227	0	0
T2	215378	215323	0	0
T4	55930	55873	0	0
T5	235905	235818	0	0
T13	202586	202518	0	0
T14	128132	128047	0	0
T15	173596	173500	0	0
T16	337249	337169	0	0
T17	159909	158990	0	0
T18	57201	57150	0	0

ECRSTOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1215441677	1215058144	0	0
T1	68287	68227	0	0
T2	215378	215323	0	0
T4	55930	55873	0	0
T5	235905	235818	0	0
T13	202586	202518	0	0
T14	128132	128047	0	0
T15	173596	173500	0	0
T16	337249	337169	0	0
T17	159909	158990	0	0
T18	57201	57150	0	0

FlashWpOEnIsOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1215441677	1215058144	0	0
T1	68287	68227	0	0
T2	215378	215323	0	0
T4	55930	55873	0	0
T5	235905	235818	0	0
T13	202586	202518	0	0
T14	128132	128047	0	0
T15	173596	173500	0	0
T16	337249	337169	0	0
T17	159909	158990	0	0
T18	57201	57150	0	0

FlashWpOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1215441677	1215058144	0	0
T1	68287	68227	0	0
T2	215378	215323	0	0
T4	55930	55873	0	0
T5	235905	235818	0	0
T13	202586	202518	0	0
T14	128132	128047	0	0
T15	173596	173500	0	0
T16	337249	337169	0	0
T17	159909	158990	0	0
T18	57201	57150	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1215441677	90	0	0
T31	174951	0	0	0
T125	0	20	0	0
T138	89265	0	0	0
T191	0	10	0	0
T260	0	20	0	0
T265	205895	20	0	0
T266	103245	0	0	0
T282	0	20	0	0
T283	59060	0	0	0
T284	57269	0	0	0
T285	50217	0	0	0
T286	261251	0	0	0
T287	440785	0	0	0
T288	198973	0	0	0

IntrEventOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1215441677	1215058144	0	0
T1	68287	68227	0	0
T2	215378	215323	0	0
T4	55930	55873	0	0
T5	235905	235818	0	0
T13	202586	202518	0	0
T14	128132	128047	0	0
T15	173596	173500	0	0
T16	337249	337169	0	0
T17	159909	158990	0	0
T18	57201	57150	0	0

Key0OEnIsOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1215441677	1215058144	0	0
T1	68287	68227	0	0
T2	215378	215323	0	0
T4	55930	55873	0	0
T5	235905	235818	0	0
T13	202586	202518	0	0
T14	128132	128047	0	0
T15	173596	173500	0	0
T16	337249	337169	0	0
T17	159909	158990	0	0
T18	57201	57150	0	0

Key0OKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1215441677	1215058144	0	0
T1	68287	68227	0	0
T2	215378	215323	0	0
T4	55930	55873	0	0
T5	235905	235818	0	0
T13	202586	202518	0	0
T14	128132	128047	0	0
T15	173596	173500	0	0
T16	337249	337169	0	0
T17	159909	158990	0	0
T18	57201	57150	0	0

Key1OEnIsOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1215441677	1215058144	0	0
T1	68287	68227	0	0
T2	215378	215323	0	0
T4	55930	55873	0	0
T5	235905	235818	0	0
T13	202586	202518	0	0
T14	128132	128047	0	0
T15	173596	173500	0	0
T16	337249	337169	0	0
T17	159909	158990	0	0
T18	57201	57150	0	0

Key1OKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1215441677	1215058144	0	0
T1	68287	68227	0	0
T2	215378	215323	0	0
T4	55930	55873	0	0
T5	235905	235818	0	0
T13	202586	202518	0	0
T14	128132	128047	0	0
T15	173596	173500	0	0
T16	337249	337169	0	0
T17	159909	158990	0	0
T18	57201	57150	0	0

Key2OEnIsOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1215441677	1215058144	0	0
T1	68287	68227	0	0
T2	215378	215323	0	0
T4	55930	55873	0	0
T5	235905	235818	0	0
T13	202586	202518	0	0
T14	128132	128047	0	0
T15	173596	173500	0	0
T16	337249	337169	0	0
T17	159909	158990	0	0
T18	57201	57150	0	0

Key2OKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1215441677	1215058144	0	0
T1	68287	68227	0	0
T2	215378	215323	0	0
T4	55930	55873	0	0
T5	235905	235818	0	0
T13	202586	202518	0	0
T14	128132	128047	0	0
T15	173596	173500	0	0
T16	337249	337169	0	0
T17	159909	158990	0	0
T18	57201	57150	0	0

OTRstOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1215441677	1215058144	0	0
T1	68287	68227	0	0
T2	215378	215323	0	0
T4	55930	55873	0	0
T5	235905	235818	0	0
T13	202586	202518	0	0
T14	128132	128047	0	0
T15	173596	173500	0	0
T16	337249	337169	0	0
T17	159909	158990	0	0
T18	57201	57150	0	0

OTWkOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1215441677	1215058144	0	0
T1	68287	68227	0	0
T2	215378	215323	0	0
T4	55930	55873	0	0
T5	235905	235818	0	0
T13	202586	202518	0	0
T14	128132	128047	0	0
T15	173596	173500	0	0
T16	337249	337169	0	0
T17	159909	158990	0	0
T18	57201	57150	0	0

PwrbOEnIsOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1215441677	1215058144	0	0
T1	68287	68227	0	0
T2	215378	215323	0	0
T4	55930	55873	0	0
T5	235905	235818	0	0
T13	202586	202518	0	0
T14	128132	128047	0	0
T15	173596	173500	0	0
T16	337249	337169	0	0
T17	159909	158990	0	0
T18	57201	57150	0	0

PwrbOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1215441677	1215058144	0	0
T1	68287	68227	0	0
T2	215378	215323	0	0
T4	55930	55873	0	0
T5	235905	235818	0	0
T13	202586	202518	0	0
T14	128132	128047	0	0
T15	173596	173500	0	0
T16	337249	337169	0	0
T17	159909	158990	0	0
T18	57201	57150	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1215441677	1215058144	0	0
T1	68287	68227	0	0
T2	215378	215323	0	0
T4	55930	55873	0	0
T5	235905	235818	0	0
T13	202586	202518	0	0
T14	128132	128047	0	0
T15	173596	173500	0	0
T16	337249	337169	0	0
T17	159909	158990	0	0
T18	57201	57150	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1215441677	1215058144	0	0
T1	68287	68227	0	0
T2	215378	215323	0	0
T4	55930	55873	0	0
T5	235905	235818	0	0
T13	202586	202518	0	0
T14	128132	128047	0	0
T15	173596	173500	0	0
T16	337249	337169	0	0
T17	159909	158990	0	0
T18	57201	57150	0	0

Z3WakeupOEnIsOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1215441677	1215058144	0	0
T1	68287	68227	0	0
T2	215378	215323	0	0
T4	55930	55873	0	0
T5	235905	235818	0	0
T13	202586	202518	0	0
T14	128132	128047	0	0
T15	173596	173500	0	0
T16	337249	337169	0	0
T17	159909	158990	0	0
T18	57201	57150	0	0

Z3WwakupOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1215441677	1215058144	0	0
T1	68287	68227	0	0
T2	215378	215323	0	0
T4	55930	55873	0	0
T5	235905	235818	0	0
T13	202586	202518	0	0
T14	128132	128047	0	0
T15	173596	173500	0	0
T16	337249	337169	0	0
T17	159909	158990	0	0
T18	57201	57150	0	0