| T63 |
/workspace/coverage/default/1.chip_sw_alert_test.1766226241 |
|
|
Mar 05 03:59:48 PM PST 24 |
Mar 05 04:05:25 PM PST 24 |
3300973850 ps |
| T864 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3772448092 |
|
|
Mar 05 03:58:13 PM PST 24 |
Mar 05 04:18:26 PM PST 24 |
6035638776 ps |
| T865 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.4001839745 |
|
|
Mar 05 04:02:22 PM PST 24 |
Mar 05 04:09:00 PM PST 24 |
3055288128 ps |
| T48 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.149906097 |
|
|
Mar 05 04:14:56 PM PST 24 |
Mar 05 04:22:07 PM PST 24 |
4763610416 ps |
| T635 |
/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3785578386 |
|
|
Mar 05 03:50:55 PM PST 24 |
Mar 05 04:04:29 PM PST 24 |
4974790866 ps |
| T636 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.1896981033 |
|
|
Mar 05 04:07:13 PM PST 24 |
Mar 05 04:27:02 PM PST 24 |
5860568021 ps |
| T235 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.1676279330 |
|
|
Mar 05 03:50:19 PM PST 24 |
Mar 05 03:53:27 PM PST 24 |
2467271900 ps |
| T292 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1368625074 |
|
|
Mar 05 03:50:13 PM PST 24 |
Mar 05 04:07:51 PM PST 24 |
6071995150 ps |
| T104 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2752704117 |
|
|
Mar 05 04:02:40 PM PST 24 |
Mar 05 04:09:25 PM PST 24 |
7072281454 ps |
| T637 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.928641281 |
|
|
Mar 05 04:17:49 PM PST 24 |
Mar 05 04:26:41 PM PST 24 |
5325244865 ps |
| T638 |
/workspace/coverage/default/1.rom_keymgr_functest.3089122381 |
|
|
Mar 05 04:05:37 PM PST 24 |
Mar 05 04:14:35 PM PST 24 |
4423666248 ps |
| T245 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.2772443862 |
|
|
Mar 05 04:04:54 PM PST 24 |
Mar 05 04:06:38 PM PST 24 |
2893221247 ps |
| T289 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2089190746 |
|
|
Mar 05 04:13:27 PM PST 24 |
Mar 05 04:25:39 PM PST 24 |
5172544782 ps |
| T866 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.151305860 |
|
|
Mar 05 03:51:40 PM PST 24 |
Mar 05 04:02:43 PM PST 24 |
5246106264 ps |
| T867 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3993003872 |
|
|
Mar 05 04:02:11 PM PST 24 |
Mar 05 04:07:37 PM PST 24 |
3534334344 ps |
| T868 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1142040038 |
|
|
Mar 05 03:55:59 PM PST 24 |
Mar 05 04:05:14 PM PST 24 |
7236098697 ps |
| T311 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1645737017 |
|
|
Mar 05 03:50:28 PM PST 24 |
Mar 05 04:02:04 PM PST 24 |
5230692865 ps |
| T306 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3216677694 |
|
|
Mar 05 04:06:10 PM PST 24 |
Mar 05 04:21:15 PM PST 24 |
5508751526 ps |
| T869 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.1277904444 |
|
|
Mar 05 03:50:21 PM PST 24 |
Mar 05 03:56:28 PM PST 24 |
4662333248 ps |
| T870 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3071774751 |
|
|
Mar 05 04:12:07 PM PST 24 |
Mar 05 04:22:20 PM PST 24 |
3815286000 ps |
| T871 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.3348157426 |
|
|
Mar 05 03:49:52 PM PST 24 |
Mar 05 04:06:26 PM PST 24 |
5397409892 ps |
| T22 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.667678390 |
|
|
Mar 05 04:10:16 PM PST 24 |
Mar 05 04:38:14 PM PST 24 |
23889381012 ps |
| T219 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.499253913 |
|
|
Mar 05 03:51:23 PM PST 24 |
Mar 05 04:12:59 PM PST 24 |
5248254836 ps |
| T419 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2989097249 |
|
|
Mar 05 03:59:19 PM PST 24 |
Mar 05 04:21:54 PM PST 24 |
7129256690 ps |
| T681 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.783037209 |
|
|
Mar 05 04:24:17 PM PST 24 |
Mar 05 04:29:48 PM PST 24 |
3742689738 ps |
| T213 |
/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.2192383939 |
|
|
Mar 05 04:02:37 PM PST 24 |
Mar 05 04:35:20 PM PST 24 |
24520297664 ps |
| T222 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.3320382782 |
|
|
Mar 05 04:08:22 PM PST 24 |
Mar 05 04:17:45 PM PST 24 |
4886443760 ps |
| T10 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.52567454 |
|
|
Mar 05 03:56:12 PM PST 24 |
Mar 05 04:05:25 PM PST 24 |
3733369885 ps |
| T239 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.570615268 |
|
|
Mar 05 04:25:45 PM PST 24 |
Mar 05 04:37:43 PM PST 24 |
5228197000 ps |
| T186 |
/workspace/coverage/default/2.rom_e2e_shutdown_output.3956727523 |
|
|
Mar 05 04:17:59 PM PST 24 |
Mar 05 05:01:32 PM PST 24 |
26048288098 ps |
| T240 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3408565043 |
|
|
Mar 05 03:56:22 PM PST 24 |
Mar 05 04:09:30 PM PST 24 |
8787659234 ps |
| T182 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.2730302057 |
|
|
Mar 05 04:19:53 PM PST 24 |
Mar 05 05:21:10 PM PST 24 |
23496402776 ps |
| T241 |
/workspace/coverage/default/1.chip_tap_straps_prod.2819382364 |
|
|
Mar 05 04:02:31 PM PST 24 |
Mar 05 04:05:25 PM PST 24 |
2546518532 ps |
| T242 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.3535251232 |
|
|
Mar 05 04:05:18 PM PST 24 |
Mar 05 04:38:46 PM PST 24 |
9354674228 ps |
| T197 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3522150645 |
|
|
Mar 05 04:07:52 PM PST 24 |
Mar 05 04:12:23 PM PST 24 |
3378310000 ps |
| T243 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.3384897781 |
|
|
Mar 05 03:50:54 PM PST 24 |
Mar 05 03:54:54 PM PST 24 |
2872132720 ps |
| T196 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.87897442 |
|
|
Mar 05 03:49:47 PM PST 24 |
Mar 05 05:24:49 PM PST 24 |
48026678516 ps |
| T248 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.3803826163 |
|
|
Mar 05 03:49:51 PM PST 24 |
Mar 05 04:03:48 PM PST 24 |
6229426322 ps |
| T216 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3767974676 |
|
|
Mar 05 03:55:49 PM PST 24 |
Mar 05 04:04:58 PM PST 24 |
4686494695 ps |
| T872 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.433478947 |
|
|
Mar 05 03:59:43 PM PST 24 |
Mar 05 04:03:29 PM PST 24 |
2097354222 ps |
| T873 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2569232369 |
|
|
Mar 05 03:50:35 PM PST 24 |
Mar 05 03:59:49 PM PST 24 |
5137546960 ps |
| T874 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.4092448932 |
|
|
Mar 05 04:08:36 PM PST 24 |
Mar 05 04:19:42 PM PST 24 |
4239413065 ps |
| T875 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx.3540132824 |
|
|
Mar 05 03:54:37 PM PST 24 |
Mar 05 04:09:38 PM PST 24 |
5160640584 ps |
| T876 |
/workspace/coverage/default/1.chip_sw_aes_idle.2153799899 |
|
|
Mar 05 03:58:04 PM PST 24 |
Mar 05 04:03:27 PM PST 24 |
3048485002 ps |
| T301 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.3482081950 |
|
|
Mar 05 03:54:44 PM PST 24 |
Mar 05 04:10:25 PM PST 24 |
5857203896 ps |
| T877 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.3870017591 |
|
|
Mar 05 03:58:19 PM PST 24 |
Mar 05 04:05:24 PM PST 24 |
3931863220 ps |
| T8 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3917218780 |
|
|
Mar 05 03:48:38 PM PST 24 |
Mar 05 03:52:50 PM PST 24 |
3302078340 ps |
| T878 |
/workspace/coverage/default/4.chip_tap_straps_rma.3676853501 |
|
|
Mar 05 04:16:28 PM PST 24 |
Mar 05 04:25:38 PM PST 24 |
6427695073 ps |
| T139 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2938415035 |
|
|
Mar 05 03:50:20 PM PST 24 |
Mar 05 03:52:38 PM PST 24 |
2985009699 ps |
| T324 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.1003768931 |
|
|
Mar 05 04:26:29 PM PST 24 |
Mar 05 04:35:30 PM PST 24 |
4533749024 ps |
| T161 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2637761608 |
|
|
Mar 05 04:11:45 PM PST 24 |
Mar 05 04:23:34 PM PST 24 |
7825137380 ps |
| T674 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.1502879594 |
|
|
Mar 05 04:21:25 PM PST 24 |
Mar 05 04:33:26 PM PST 24 |
6411516520 ps |
| T879 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2574152778 |
|
|
Mar 05 03:57:51 PM PST 24 |
Mar 05 04:07:13 PM PST 24 |
7156750820 ps |
| T701 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.1266009272 |
|
|
Mar 05 04:21:28 PM PST 24 |
Mar 05 04:33:33 PM PST 24 |
5281505140 ps |
| T880 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3546019858 |
|
|
Mar 05 04:08:23 PM PST 24 |
Mar 05 04:14:49 PM PST 24 |
2835032136 ps |
| T881 |
/workspace/coverage/default/0.chip_sw_example_concurrency.2755840064 |
|
|
Mar 05 03:49:41 PM PST 24 |
Mar 05 03:53:55 PM PST 24 |
2278176128 ps |
| T882 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1211147182 |
|
|
Mar 05 04:07:36 PM PST 24 |
Mar 05 04:23:37 PM PST 24 |
5649873674 ps |
| T741 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.913962429 |
|
|
Mar 05 04:23:34 PM PST 24 |
Mar 05 04:32:53 PM PST 24 |
4077643700 ps |
| T883 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.2203196266 |
|
|
Mar 05 03:57:39 PM PST 24 |
Mar 05 04:01:36 PM PST 24 |
3004016264 ps |
| T54 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.1893665417 |
|
|
Mar 05 03:56:03 PM PST 24 |
Mar 05 04:01:48 PM PST 24 |
3865817534 ps |
| T376 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4232842487 |
|
|
Mar 05 04:04:05 PM PST 24 |
Mar 05 04:24:29 PM PST 24 |
7271096135 ps |
| T126 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3614802016 |
|
|
Mar 05 03:57:10 PM PST 24 |
Mar 05 03:58:50 PM PST 24 |
1540466303 ps |
| T377 |
/workspace/coverage/default/2.chip_sw_uart_smoketest.2541953653 |
|
|
Mar 05 04:16:02 PM PST 24 |
Mar 05 04:21:25 PM PST 24 |
3552844480 ps |
| T201 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.70176081 |
|
|
Mar 05 04:19:09 PM PST 24 |
Mar 05 04:25:17 PM PST 24 |
2989744022 ps |
| T378 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.1087471471 |
|
|
Mar 05 04:06:52 PM PST 24 |
Mar 05 04:14:26 PM PST 24 |
9186687086 ps |
| T379 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2494702806 |
|
|
Mar 05 04:22:08 PM PST 24 |
Mar 05 04:27:39 PM PST 24 |
3533383400 ps |
| T215 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.3508005914 |
|
|
Mar 05 03:56:42 PM PST 24 |
Mar 05 05:25:30 PM PST 24 |
49617203664 ps |
| T233 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.1099633286 |
|
|
Mar 05 04:02:27 PM PST 24 |
Mar 05 04:06:11 PM PST 24 |
2508474204 ps |
| T380 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1337076917 |
|
|
Mar 05 04:17:17 PM PST 24 |
Mar 05 04:25:34 PM PST 24 |
6430944454 ps |
| T884 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1098216034 |
|
|
Mar 05 03:51:05 PM PST 24 |
Mar 05 03:59:54 PM PST 24 |
6410844950 ps |
| T665 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.2667883072 |
|
|
Mar 05 04:21:24 PM PST 24 |
Mar 05 04:32:33 PM PST 24 |
5167113576 ps |
| T164 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2924030377 |
|
|
Mar 05 03:50:52 PM PST 24 |
Mar 05 04:01:02 PM PST 24 |
6268830022 ps |
| T234 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.55311308 |
|
|
Mar 05 04:16:16 PM PST 24 |
Mar 05 04:22:41 PM PST 24 |
4119510560 ps |
| T691 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.1581371821 |
|
|
Mar 05 04:26:55 PM PST 24 |
Mar 05 04:35:13 PM PST 24 |
4994630918 ps |
| T885 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3098676778 |
|
|
Mar 05 03:51:20 PM PST 24 |
Mar 05 05:04:19 PM PST 24 |
18365768279 ps |
| T705 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.130732909 |
|
|
Mar 05 04:25:39 PM PST 24 |
Mar 05 04:30:08 PM PST 24 |
3489802800 ps |
| T228 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3741974011 |
|
|
Mar 05 04:18:52 PM PST 24 |
Mar 05 04:26:14 PM PST 24 |
3739933354 ps |
| T743 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3675445339 |
|
|
Mar 05 04:23:46 PM PST 24 |
Mar 05 04:29:16 PM PST 24 |
3720953744 ps |
| T145 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.811332386 |
|
|
Mar 05 04:13:18 PM PST 24 |
Mar 05 04:16:56 PM PST 24 |
2308829556 ps |
| T277 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2540730359 |
|
|
Mar 05 04:07:04 PM PST 24 |
Mar 05 04:22:56 PM PST 24 |
5051290501 ps |
| T278 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1233984489 |
|
|
Mar 05 04:10:59 PM PST 24 |
Mar 05 04:24:32 PM PST 24 |
5209167800 ps |
| T279 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2760160038 |
|
|
Mar 05 04:18:33 PM PST 24 |
Mar 05 04:24:43 PM PST 24 |
3941580900 ps |
| T280 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.3207179229 |
|
|
Mar 05 04:06:56 PM PST 24 |
Mar 05 04:26:02 PM PST 24 |
10872769924 ps |
| T85 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2293460324 |
|
|
Mar 05 04:09:22 PM PST 24 |
Mar 05 04:28:36 PM PST 24 |
10215177936 ps |
| T281 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.3408368061 |
|
|
Mar 05 03:51:53 PM PST 24 |
Mar 05 03:55:19 PM PST 24 |
3020395480 ps |
| T282 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1977496908 |
|
|
Mar 05 03:50:26 PM PST 24 |
Mar 05 03:59:07 PM PST 24 |
5950719680 ps |
| T283 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1356138085 |
|
|
Mar 05 03:52:34 PM PST 24 |
Mar 05 03:56:05 PM PST 24 |
3404953192 ps |
| T284 |
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.403930067 |
|
|
Mar 05 04:17:47 PM PST 24 |
Mar 05 04:24:08 PM PST 24 |
3694494490 ps |
| T886 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.401766821 |
|
|
Mar 05 03:56:45 PM PST 24 |
Mar 05 04:15:25 PM PST 24 |
5817746303 ps |
| T679 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.1506306211 |
|
|
Mar 05 04:22:16 PM PST 24 |
Mar 05 04:32:38 PM PST 24 |
6503506406 ps |
| T257 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.378557129 |
|
|
Mar 05 03:50:24 PM PST 24 |
Mar 05 03:59:12 PM PST 24 |
3177911584 ps |
| T356 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3354579607 |
|
|
Mar 05 03:56:39 PM PST 24 |
Mar 05 04:43:51 PM PST 24 |
12314660846 ps |
| T285 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1586256711 |
|
|
Mar 05 03:59:15 PM PST 24 |
Mar 05 04:35:17 PM PST 24 |
15354909482 ps |
| T887 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.1981068536 |
|
|
Mar 05 03:55:15 PM PST 24 |
Mar 05 03:58:29 PM PST 24 |
2723793114 ps |
| T319 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.494164615 |
|
|
Mar 05 03:49:13 PM PST 24 |
Mar 05 04:06:27 PM PST 24 |
5297635248 ps |
| T888 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.76355901 |
|
|
Mar 05 03:58:44 PM PST 24 |
Mar 05 04:08:06 PM PST 24 |
6845221983 ps |
| T680 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.3631802908 |
|
|
Mar 05 04:23:09 PM PST 24 |
Mar 05 04:33:03 PM PST 24 |
6074965706 ps |
| T647 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3773145956 |
|
|
Mar 05 03:57:26 PM PST 24 |
Mar 05 04:54:31 PM PST 24 |
20023390386 ps |
| T600 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1198162062 |
|
|
Mar 05 03:50:42 PM PST 24 |
Mar 05 03:53:25 PM PST 24 |
2610890421 ps |
| T408 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.2375207136 |
|
|
Mar 05 03:51:00 PM PST 24 |
Mar 05 04:00:02 PM PST 24 |
9128338623 ps |
| T58 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1265198700 |
|
|
Mar 05 03:52:05 PM PST 24 |
Mar 05 04:17:37 PM PST 24 |
18841336240 ps |
| T889 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2913030535 |
|
|
Mar 05 03:53:02 PM PST 24 |
Mar 05 04:05:21 PM PST 24 |
5451100163 ps |
| T79 |
/workspace/coverage/default/2.chip_jtag_mem_access.1120410067 |
|
|
Mar 05 04:04:48 PM PST 24 |
Mar 05 04:28:39 PM PST 24 |
13349275050 ps |
| T293 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.1806720657 |
|
|
Mar 05 03:54:51 PM PST 24 |
Mar 05 04:11:30 PM PST 24 |
5603300478 ps |
| T890 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.3292926275 |
|
|
Mar 05 04:22:18 PM PST 24 |
Mar 05 04:31:12 PM PST 24 |
6084967952 ps |
| T891 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.1002371323 |
|
|
Mar 05 03:49:56 PM PST 24 |
Mar 05 04:04:34 PM PST 24 |
10270667488 ps |
| T892 |
/workspace/coverage/default/0.chip_sw_uart_smoketest_signed.1217602154 |
|
|
Mar 05 03:57:58 PM PST 24 |
Mar 05 04:33:59 PM PST 24 |
8658673000 ps |
| T226 |
/workspace/coverage/default/2.chip_sw_alert_test.618239754 |
|
|
Mar 05 04:09:38 PM PST 24 |
Mar 05 04:15:05 PM PST 24 |
3143374274 ps |
| T893 |
/workspace/coverage/default/1.chip_sw_example_flash.3891708263 |
|
|
Mar 05 03:53:38 PM PST 24 |
Mar 05 03:56:42 PM PST 24 |
2630945640 ps |
| T894 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod.3563164174 |
|
|
Mar 05 04:11:33 PM PST 24 |
Mar 05 04:43:12 PM PST 24 |
9440257935 ps |
| T11 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.1615775156 |
|
|
Mar 05 03:57:30 PM PST 24 |
Mar 05 04:07:44 PM PST 24 |
6556860169 ps |
| T895 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1872942111 |
|
|
Mar 05 04:17:09 PM PST 24 |
Mar 05 04:35:02 PM PST 24 |
12713949221 ps |
| T896 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.4141189096 |
|
|
Mar 05 03:58:53 PM PST 24 |
Mar 05 04:02:51 PM PST 24 |
2497104964 ps |
| T623 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.2247848880 |
|
|
Mar 05 04:11:08 PM PST 24 |
Mar 05 04:15:12 PM PST 24 |
3087783952 ps |
| T897 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.3565317711 |
|
|
Mar 05 04:19:26 PM PST 24 |
Mar 05 04:53:10 PM PST 24 |
8180456693 ps |
| T898 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.426820837 |
|
|
Mar 05 03:52:26 PM PST 24 |
Mar 05 04:07:04 PM PST 24 |
7159072280 ps |
| T667 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.519582051 |
|
|
Mar 05 04:26:45 PM PST 24 |
Mar 05 04:36:37 PM PST 24 |
5169159350 ps |
| T899 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.1418460719 |
|
|
Mar 05 04:05:27 PM PST 24 |
Mar 05 04:19:39 PM PST 24 |
5520051072 ps |
| T900 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.922567528 |
|
|
Mar 05 03:49:37 PM PST 24 |
Mar 05 04:10:59 PM PST 24 |
6663526602 ps |
| T146 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.845732601 |
|
|
Mar 05 04:13:15 PM PST 24 |
Mar 05 04:16:57 PM PST 24 |
2736023916 ps |
| T360 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.3453191564 |
|
|
Mar 05 04:25:22 PM PST 24 |
Mar 05 04:36:18 PM PST 24 |
4559250590 ps |
| T361 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2606937331 |
|
|
Mar 05 04:23:24 PM PST 24 |
Mar 05 04:29:42 PM PST 24 |
3264483528 ps |
| T91 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.875871223 |
|
|
Mar 05 04:19:30 PM PST 24 |
Mar 05 04:31:43 PM PST 24 |
5696138800 ps |
| T362 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2453514184 |
|
|
Mar 05 04:07:08 PM PST 24 |
Mar 05 04:15:41 PM PST 24 |
4137110796 ps |
| T363 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3809154764 |
|
|
Mar 05 03:50:44 PM PST 24 |
Mar 05 04:00:51 PM PST 24 |
6714576622 ps |
| T364 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.2346393015 |
|
|
Mar 05 03:58:01 PM PST 24 |
Mar 05 04:29:38 PM PST 24 |
8749520762 ps |
| T365 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.4040830433 |
|
|
Mar 05 03:54:32 PM PST 24 |
Mar 05 04:00:28 PM PST 24 |
3461145180 ps |
| T366 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1857113831 |
|
|
Mar 05 04:02:12 PM PST 24 |
Mar 05 04:09:34 PM PST 24 |
4009524288 ps |
| T367 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3808371609 |
|
|
Mar 05 04:16:46 PM PST 24 |
Mar 05 04:24:47 PM PST 24 |
5970944647 ps |
| T683 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.1134146344 |
|
|
Mar 05 04:22:51 PM PST 24 |
Mar 05 04:32:12 PM PST 24 |
4818647540 ps |
| T735 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2921845498 |
|
|
Mar 05 04:20:14 PM PST 24 |
Mar 05 04:26:28 PM PST 24 |
3246674984 ps |
| T901 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.195091705 |
|
|
Mar 05 04:08:55 PM PST 24 |
Mar 05 04:17:41 PM PST 24 |
5011619492 ps |
| T902 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2182301822 |
|
|
Mar 05 03:49:46 PM PST 24 |
Mar 05 03:54:46 PM PST 24 |
3231080470 ps |
| T75 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.217654721 |
|
|
Mar 05 03:49:44 PM PST 24 |
Mar 05 03:54:00 PM PST 24 |
2856266116 ps |
| T55 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.3221585871 |
|
|
Mar 05 03:50:41 PM PST 24 |
Mar 05 03:56:18 PM PST 24 |
4371470076 ps |
| T148 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3816383564 |
|
|
Mar 05 04:14:26 PM PST 24 |
Mar 05 04:53:51 PM PST 24 |
14744112237 ps |
| T903 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3200695808 |
|
|
Mar 05 04:07:00 PM PST 24 |
Mar 05 04:13:02 PM PST 24 |
3367854072 ps |
| T904 |
/workspace/coverage/default/4.chip_tap_straps_testunlock0.2215838728 |
|
|
Mar 05 04:15:39 PM PST 24 |
Mar 05 04:19:21 PM PST 24 |
2945569041 ps |
| T116 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1755754157 |
|
|
Mar 05 03:48:35 PM PST 24 |
Mar 05 06:43:13 PM PST 24 |
57740907955 ps |
| T905 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2548279911 |
|
|
Mar 05 04:01:35 PM PST 24 |
Mar 05 04:13:08 PM PST 24 |
4360775600 ps |
| T162 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1258740308 |
|
|
Mar 05 04:01:37 PM PST 24 |
Mar 05 04:11:35 PM PST 24 |
3948589660 ps |
| T906 |
/workspace/coverage/default/4.chip_tap_straps_prod.3052896682 |
|
|
Mar 05 04:16:46 PM PST 24 |
Mar 05 04:47:25 PM PST 24 |
18733611503 ps |
| T907 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.334988484 |
|
|
Mar 05 04:06:35 PM PST 24 |
Mar 05 04:20:47 PM PST 24 |
5548157250 ps |
| T702 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3395951216 |
|
|
Mar 05 04:18:44 PM PST 24 |
Mar 05 04:26:20 PM PST 24 |
4051854000 ps |
| T908 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2676001643 |
|
|
Mar 05 04:18:04 PM PST 24 |
Mar 05 04:29:25 PM PST 24 |
13071726111 ps |
| T909 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1347719463 |
|
|
Mar 05 03:57:31 PM PST 24 |
Mar 05 04:33:54 PM PST 24 |
8900926850 ps |
| T695 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3171064082 |
|
|
Mar 05 04:17:27 PM PST 24 |
Mar 05 04:25:26 PM PST 24 |
3910414096 ps |
| T910 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1322842666 |
|
|
Mar 05 04:25:53 PM PST 24 |
Mar 05 04:36:47 PM PST 24 |
5149425204 ps |
| T187 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2367794237 |
|
|
Mar 05 03:55:42 PM PST 24 |
Mar 05 06:49:06 PM PST 24 |
58118285199 ps |
| T911 |
/workspace/coverage/default/2.chip_sw_gpio_smoketest.2124285717 |
|
|
Mar 05 04:14:33 PM PST 24 |
Mar 05 04:19:11 PM PST 24 |
2769387877 ps |
| T912 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3251371582 |
|
|
Mar 05 03:58:27 PM PST 24 |
Mar 05 04:59:14 PM PST 24 |
35153334030 ps |
| T913 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.1553212014 |
|
|
Mar 05 04:02:46 PM PST 24 |
Mar 05 04:09:38 PM PST 24 |
6145377168 ps |
| T914 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.282707969 |
|
|
Mar 05 04:18:50 PM PST 24 |
Mar 05 04:31:43 PM PST 24 |
6016501420 ps |
| T35 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.639150943 |
|
|
Mar 05 03:58:02 PM PST 24 |
Mar 05 04:02:18 PM PST 24 |
3443033886 ps |
| T286 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.1579001238 |
|
|
Mar 05 04:01:10 PM PST 24 |
Mar 05 04:21:30 PM PST 24 |
5878282592 ps |
| T594 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.3301460644 |
|
|
Mar 05 04:11:15 PM PST 24 |
Mar 05 04:26:57 PM PST 24 |
4557704608 ps |
| T165 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1846030362 |
|
|
Mar 05 04:09:10 PM PST 24 |
Mar 05 04:17:18 PM PST 24 |
9169804569 ps |
| T669 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3945384531 |
|
|
Mar 05 04:20:20 PM PST 24 |
Mar 05 04:27:41 PM PST 24 |
3369871158 ps |
| T915 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3715285251 |
|
|
Mar 05 03:59:30 PM PST 24 |
Mar 05 04:34:41 PM PST 24 |
9357632298 ps |
| T916 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1833087116 |
|
|
Mar 05 03:59:42 PM PST 24 |
Mar 05 04:21:01 PM PST 24 |
12746489984 ps |
| T207 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.218275857 |
|
|
Mar 05 04:09:48 PM PST 24 |
Mar 05 04:16:41 PM PST 24 |
4147573796 ps |
| T917 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.816779508 |
|
|
Mar 05 03:54:58 PM PST 24 |
Mar 05 04:19:21 PM PST 24 |
8631298548 ps |
| T918 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2922132535 |
|
|
Mar 05 04:12:52 PM PST 24 |
Mar 05 04:22:47 PM PST 24 |
3435648933 ps |
| T919 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2638518003 |
|
|
Mar 05 04:23:59 PM PST 24 |
Mar 05 04:29:13 PM PST 24 |
2998204684 ps |
| T208 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.695801942 |
|
|
Mar 05 04:12:26 PM PST 24 |
Mar 05 05:14:08 PM PST 24 |
16383259722 ps |
| T721 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3122901142 |
|
|
Mar 05 04:19:44 PM PST 24 |
Mar 05 04:27:18 PM PST 24 |
3170272136 ps |
| T357 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2084130360 |
|
|
Mar 05 03:57:26 PM PST 24 |
Mar 05 04:40:04 PM PST 24 |
9677680120 ps |
| T729 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.718516314 |
|
|
Mar 05 04:22:06 PM PST 24 |
Mar 05 04:34:01 PM PST 24 |
6452799040 ps |
| T158 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4052282867 |
|
|
Mar 05 04:02:46 PM PST 24 |
Mar 05 04:12:38 PM PST 24 |
5740510122 ps |
| T488 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.2276422598 |
|
|
Mar 05 04:07:30 PM PST 24 |
Mar 05 04:30:58 PM PST 24 |
10292038978 ps |
| T420 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.2861549809 |
|
|
Mar 05 03:57:23 PM PST 24 |
Mar 05 04:00:46 PM PST 24 |
2334970712 ps |
| T920 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3356471011 |
|
|
Mar 05 03:56:55 PM PST 24 |
Mar 05 04:31:23 PM PST 24 |
8793119102 ps |
| T921 |
/workspace/coverage/default/1.chip_tap_straps_testunlock0.2716005207 |
|
|
Mar 05 04:02:02 PM PST 24 |
Mar 05 04:09:44 PM PST 24 |
4309728666 ps |
| T238 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3953111081 |
|
|
Mar 05 03:51:06 PM PST 24 |
Mar 05 04:10:50 PM PST 24 |
8708425884 ps |
| T922 |
/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3310835676 |
|
|
Mar 05 04:18:12 PM PST 24 |
Mar 05 04:56:40 PM PST 24 |
14172417700 ps |
| T923 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.4044987114 |
|
|
Mar 05 04:09:37 PM PST 24 |
Mar 05 04:43:25 PM PST 24 |
9615455166 ps |
| T118 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.516083730 |
|
|
Mar 05 04:10:46 PM PST 24 |
Mar 05 04:21:12 PM PST 24 |
3331495100 ps |
| T709 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.3357785147 |
|
|
Mar 05 04:20:38 PM PST 24 |
Mar 05 04:31:05 PM PST 24 |
5596469908 ps |
| T924 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.1729571345 |
|
|
Mar 05 03:48:37 PM PST 24 |
Mar 05 04:04:33 PM PST 24 |
6011657140 ps |
| T925 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3029616288 |
|
|
Mar 05 03:50:04 PM PST 24 |
Mar 05 03:59:47 PM PST 24 |
5082130484 ps |
| T926 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3269630387 |
|
|
Mar 05 04:05:45 PM PST 24 |
Mar 05 04:10:11 PM PST 24 |
3086262314 ps |
| T927 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1950608688 |
|
|
Mar 05 04:07:04 PM PST 24 |
Mar 05 04:11:52 PM PST 24 |
3052928326 ps |
| T928 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1992678627 |
|
|
Mar 05 04:11:48 PM PST 24 |
Mar 05 04:23:40 PM PST 24 |
3844157668 ps |
| T929 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.4134757038 |
|
|
Mar 05 03:52:24 PM PST 24 |
Mar 05 03:58:55 PM PST 24 |
2791294124 ps |
| T930 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1862889618 |
|
|
Mar 05 04:11:20 PM PST 24 |
Mar 05 04:22:33 PM PST 24 |
4682029656 ps |
| T931 |
/workspace/coverage/default/0.chip_sw_otbn_randomness.3615058118 |
|
|
Mar 05 03:51:58 PM PST 24 |
Mar 05 04:07:18 PM PST 24 |
5732880216 ps |
| T932 |
/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.1265258013 |
|
|
Mar 05 03:55:17 PM PST 24 |
Mar 05 04:00:02 PM PST 24 |
2457733336 ps |
| T933 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.481580336 |
|
|
Mar 05 04:15:58 PM PST 24 |
Mar 05 04:19:52 PM PST 24 |
3455017828 ps |
| T934 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3788764619 |
|
|
Mar 05 03:51:45 PM PST 24 |
Mar 05 04:01:08 PM PST 24 |
4052180680 ps |
| T211 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.198564057 |
|
|
Mar 05 03:50:16 PM PST 24 |
Mar 05 04:55:13 PM PST 24 |
15402495210 ps |
| T258 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.1801323307 |
|
|
Mar 05 03:58:23 PM PST 24 |
Mar 05 04:06:00 PM PST 24 |
3308173630 ps |
| T170 |
/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.602156069 |
|
|
Mar 05 03:51:16 PM PST 24 |
Mar 05 03:56:01 PM PST 24 |
2429615384 ps |
| T935 |
/workspace/coverage/default/2.chip_sw_kmac_idle.2026613798 |
|
|
Mar 05 04:10:37 PM PST 24 |
Mar 05 04:14:30 PM PST 24 |
3422299512 ps |
| T936 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.1670198103 |
|
|
Mar 05 03:56:23 PM PST 24 |
Mar 05 04:00:52 PM PST 24 |
2344454376 ps |
| T675 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2072066183 |
|
|
Mar 05 04:22:20 PM PST 24 |
Mar 05 04:28:47 PM PST 24 |
4254006160 ps |
| T937 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1104743331 |
|
|
Mar 05 03:50:50 PM PST 24 |
Mar 05 03:57:19 PM PST 24 |
2896058999 ps |
| T938 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1970879910 |
|
|
Mar 05 03:51:47 PM PST 24 |
Mar 05 03:57:18 PM PST 24 |
3187655080 ps |
| T724 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1811175165 |
|
|
Mar 05 04:21:55 PM PST 24 |
Mar 05 04:28:19 PM PST 24 |
2908588900 ps |
| T939 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.2331005848 |
|
|
Mar 05 04:26:25 PM PST 24 |
Mar 05 04:36:11 PM PST 24 |
5624907232 ps |
| T291 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.415269843 |
|
|
Mar 05 03:52:46 PM PST 24 |
Mar 05 04:07:47 PM PST 24 |
4473913678 ps |
| T700 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3559936560 |
|
|
Mar 05 04:21:21 PM PST 24 |
Mar 05 04:26:44 PM PST 24 |
4250983072 ps |
| T940 |
/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3908850456 |
|
|
Mar 05 03:51:17 PM PST 24 |
Mar 05 03:59:47 PM PST 24 |
4808407700 ps |
| T941 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2174889466 |
|
|
Mar 05 03:59:38 PM PST 24 |
Mar 05 05:07:10 PM PST 24 |
16562696920 ps |
| T723 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.747058807 |
|
|
Mar 05 04:22:54 PM PST 24 |
Mar 05 04:31:10 PM PST 24 |
5309624800 ps |
| T696 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1307877991 |
|
|
Mar 05 04:20:33 PM PST 24 |
Mar 05 04:26:36 PM PST 24 |
3604396300 ps |
| T942 |
/workspace/coverage/default/1.rom_e2e_asm_init_dev.937637192 |
|
|
Mar 05 04:08:50 PM PST 24 |
Mar 05 04:41:20 PM PST 24 |
8594138405 ps |
| T732 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.362522463 |
|
|
Mar 05 04:23:48 PM PST 24 |
Mar 05 04:28:21 PM PST 24 |
3145351160 ps |
| T92 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3572606091 |
|
|
Mar 05 04:23:42 PM PST 24 |
Mar 05 04:28:40 PM PST 24 |
3281844380 ps |
| T652 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.3190680978 |
|
|
Mar 05 04:20:02 PM PST 24 |
Mar 05 04:30:49 PM PST 24 |
5615657878 ps |
| T38 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.493827034 |
|
|
Mar 05 03:50:51 PM PST 24 |
Mar 05 03:57:50 PM PST 24 |
3702545957 ps |
| T943 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3175269606 |
|
|
Mar 05 04:09:04 PM PST 24 |
Mar 05 05:09:52 PM PST 24 |
17014624372 ps |
| T259 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1682089197 |
|
|
Mar 05 04:04:14 PM PST 24 |
Mar 05 04:14:00 PM PST 24 |
4516283147 ps |
| T260 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.4176178707 |
|
|
Mar 05 04:01:13 PM PST 24 |
Mar 05 04:12:05 PM PST 24 |
4584162673 ps |
| T944 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx.1572338245 |
|
|
Mar 05 04:16:19 PM PST 24 |
Mar 05 04:32:18 PM PST 24 |
5163298086 ps |
| T945 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.317457767 |
|
|
Mar 05 04:05:00 PM PST 24 |
Mar 05 04:09:04 PM PST 24 |
2923757630 ps |
| T946 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3607593135 |
|
|
Mar 05 03:58:46 PM PST 24 |
Mar 05 04:31:15 PM PST 24 |
9064415976 ps |
| T486 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3813087851 |
|
|
Mar 05 04:08:26 PM PST 24 |
Mar 05 04:23:53 PM PST 24 |
4720893928 ps |
| T39 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.3114069696 |
|
|
Mar 05 04:11:00 PM PST 24 |
Mar 05 04:17:18 PM PST 24 |
3105810355 ps |
| T947 |
/workspace/coverage/default/1.chip_sw_example_rom.3044634496 |
|
|
Mar 05 03:53:09 PM PST 24 |
Mar 05 03:55:06 PM PST 24 |
2420637586 ps |
| T948 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1658886848 |
|
|
Mar 05 04:15:27 PM PST 24 |
Mar 05 04:19:22 PM PST 24 |
3304685944 ps |
| T949 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2221065975 |
|
|
Mar 05 03:58:57 PM PST 24 |
Mar 05 04:13:50 PM PST 24 |
6729324840 ps |
| T950 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1695842961 |
|
|
Mar 05 03:50:42 PM PST 24 |
Mar 05 03:55:33 PM PST 24 |
2838826027 ps |
| T188 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2705131507 |
|
|
Mar 05 04:09:05 PM PST 24 |
Mar 05 07:34:27 PM PST 24 |
59791666667 ps |
| T129 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2712360768 |
|
|
Mar 05 03:51:00 PM PST 24 |
Mar 05 04:03:19 PM PST 24 |
6069557160 ps |
| T130 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.581465247 |
|
|
Mar 05 04:16:28 PM PST 24 |
Mar 05 04:25:15 PM PST 24 |
4482475544 ps |
| T320 |
/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.321892710 |
|
|
Mar 05 04:18:23 PM PST 24 |
Mar 05 04:29:19 PM PST 24 |
4893127418 ps |
| T951 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.432113345 |
|
|
Mar 05 04:00:31 PM PST 24 |
Mar 05 04:06:31 PM PST 24 |
3549250296 ps |
| T952 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.2217328734 |
|
|
Mar 05 04:04:53 PM PST 24 |
Mar 05 04:08:15 PM PST 24 |
3117484465 ps |
| T953 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.792634378 |
|
|
Mar 05 03:50:04 PM PST 24 |
Mar 05 04:48:37 PM PST 24 |
39790047340 ps |
| T299 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1247586153 |
|
|
Mar 05 03:49:24 PM PST 24 |
Mar 05 04:00:20 PM PST 24 |
4127709312 ps |
| T954 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1503604601 |
|
|
Mar 05 04:16:54 PM PST 24 |
Mar 05 04:32:02 PM PST 24 |
5889014890 ps |
| T955 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2388929204 |
|
|
Mar 05 03:59:06 PM PST 24 |
Mar 05 04:37:09 PM PST 24 |
9199952228 ps |
| T316 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.504932098 |
|
|
Mar 05 03:52:56 PM PST 24 |
Mar 05 03:56:49 PM PST 24 |
2865245308 ps |
| T956 |
/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1612056443 |
|
|
Mar 05 04:11:16 PM PST 24 |
Mar 05 04:20:55 PM PST 24 |
10042619677 ps |
| T708 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.880110500 |
|
|
Mar 05 04:26:11 PM PST 24 |
Mar 05 04:36:09 PM PST 24 |
5011693560 ps |
| T36 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.613214631 |
|
|
Mar 05 04:06:27 PM PST 24 |
Mar 05 04:12:38 PM PST 24 |
3161659032 ps |
| T957 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2276714268 |
|
|
Mar 05 03:52:53 PM PST 24 |
Mar 05 04:06:49 PM PST 24 |
10689854210 ps |
| T958 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.358025054 |
|
|
Mar 05 03:57:20 PM PST 24 |
Mar 05 04:08:30 PM PST 24 |
5449777176 ps |
| T959 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3433793730 |
|
|
Mar 05 03:50:25 PM PST 24 |
Mar 05 04:12:25 PM PST 24 |
7049510100 ps |
| T960 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.1448063552 |
|
|
Mar 05 03:59:02 PM PST 24 |
Mar 05 04:26:51 PM PST 24 |
6057496980 ps |
| T961 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.509165949 |
|
|
Mar 05 03:49:33 PM PST 24 |
Mar 05 03:52:59 PM PST 24 |
2449025040 ps |
| T689 |
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.930689211 |
|
|
Mar 05 04:23:01 PM PST 24 |
Mar 05 04:29:53 PM PST 24 |
3809673496 ps |
| T962 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2889034567 |
|
|
Mar 05 04:16:08 PM PST 24 |
Mar 05 04:32:09 PM PST 24 |
6041788840 ps |
| T718 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3155655205 |
|
|
Mar 05 04:23:50 PM PST 24 |
Mar 05 04:30:54 PM PST 24 |
3968870470 ps |
| T963 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3063678542 |
|
|
Mar 05 03:58:22 PM PST 24 |
Mar 05 04:34:44 PM PST 24 |
8810887008 ps |
| T964 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3345573701 |
|
|
Mar 05 04:00:25 PM PST 24 |
Mar 05 04:36:59 PM PST 24 |
8098770444 ps |
| T726 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3403952249 |
|
|
Mar 05 04:24:49 PM PST 24 |
Mar 05 04:32:16 PM PST 24 |
3664289528 ps |
| T166 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2881580208 |
|
|
Mar 05 03:53:32 PM PST 24 |
Mar 05 03:58:14 PM PST 24 |
2560100852 ps |
| T147 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3085693243 |
|
|
Mar 05 04:04:00 PM PST 24 |
Mar 05 04:09:12 PM PST 24 |
2194407400 ps |
| T965 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.364134470 |
|
|
Mar 05 03:48:59 PM PST 24 |
Mar 05 03:54:29 PM PST 24 |
3894211928 ps |