Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 95.45 94.14 95.17 94.70 97.38 99.55


Total test records in report: 2845
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T571 /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.4271393262 Mar 05 03:31:56 PM PST 24 Mar 05 04:18:11 PM PST 24 148090080328 ps
T1543 /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.3688523451 Mar 05 03:34:39 PM PST 24 Mar 05 03:35:41 PM PST 24 5546246133 ps
T1544 /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.3824386628 Mar 05 03:40:50 PM PST 24 Mar 05 03:41:38 PM PST 24 1073757162 ps
T1545 /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3146297920 Mar 05 03:22:38 PM PST 24 Mar 05 03:55:50 PM PST 24 115226435926 ps
T1546 /workspace/coverage/cover_reg_top/64.xbar_same_source.1595180157 Mar 05 03:35:56 PM PST 24 Mar 05 03:36:51 PM PST 24 1725981739 ps
T1547 /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.3255348002 Mar 05 03:33:35 PM PST 24 Mar 05 03:33:42 PM PST 24 52226899 ps
T1548 /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.1875306147 Mar 05 03:28:13 PM PST 24 Mar 05 03:29:48 PM PST 24 8526850289 ps
T1549 /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.4206182152 Mar 05 03:30:49 PM PST 24 Mar 05 03:52:00 PM PST 24 110411063487 ps
T1550 /workspace/coverage/cover_reg_top/74.xbar_smoke.1263677752 Mar 05 03:37:30 PM PST 24 Mar 05 03:37:38 PM PST 24 185588006 ps
T1551 /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.3893593246 Mar 05 03:17:03 PM PST 24 Mar 05 03:38:24 PM PST 24 12046534728 ps
T1552 /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.929149927 Mar 05 03:22:31 PM PST 24 Mar 05 03:23:07 PM PST 24 2279566444 ps
T1553 /workspace/coverage/cover_reg_top/20.xbar_access_same_device.1622513390 Mar 05 03:25:31 PM PST 24 Mar 05 03:27:40 PM PST 24 2782270965 ps
T807 /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.3212152176 Mar 05 03:32:25 PM PST 24 Mar 05 03:35:28 PM PST 24 1767648889 ps
T1554 /workspace/coverage/cover_reg_top/0.chip_tl_errors.3492092918 Mar 05 03:14:16 PM PST 24 Mar 05 03:15:39 PM PST 24 2001294956 ps
T1555 /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.3156084776 Mar 05 03:38:37 PM PST 24 Mar 05 03:43:16 PM PST 24 750753560 ps
T1556 /workspace/coverage/cover_reg_top/90.xbar_error_random.1178210403 Mar 05 03:40:12 PM PST 24 Mar 05 03:41:00 PM PST 24 570474165 ps
T783 /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.2948231410 Mar 05 03:34:38 PM PST 24 Mar 05 03:52:39 PM PST 24 57335199939 ps
T790 /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.3180100970 Mar 05 03:36:36 PM PST 24 Mar 05 03:39:05 PM PST 24 568591153 ps
T1557 /workspace/coverage/cover_reg_top/12.xbar_random.4284944791 Mar 05 03:22:11 PM PST 24 Mar 05 03:23:30 PM PST 24 2021098349 ps
T1558 /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.1752951004 Mar 05 03:34:00 PM PST 24 Mar 05 03:35:12 PM PST 24 186578709 ps
T1559 /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.3595377835 Mar 05 03:33:50 PM PST 24 Mar 05 03:36:50 PM PST 24 483656903 ps
T1560 /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.2439713045 Mar 05 03:37:07 PM PST 24 Mar 05 03:37:27 PM PST 24 176975394 ps
T1561 /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.1024928643 Mar 05 03:38:15 PM PST 24 Mar 05 03:49:30 PM PST 24 39107148622 ps
T1562 /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.3261241714 Mar 05 03:27:02 PM PST 24 Mar 05 03:33:03 PM PST 24 2649013631 ps
T1563 /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.1914909600 Mar 05 03:27:20 PM PST 24 Mar 05 03:27:32 PM PST 24 102187355 ps
T1564 /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.361821884 Mar 05 03:40:33 PM PST 24 Mar 05 03:42:08 PM PST 24 217904769 ps
T629 /workspace/coverage/cover_reg_top/2.chip_tl_errors.2021458810 Mar 05 03:16:10 PM PST 24 Mar 05 03:18:36 PM PST 24 2876756820 ps
T1565 /workspace/coverage/cover_reg_top/53.xbar_smoke.514617841 Mar 05 03:33:28 PM PST 24 Mar 05 03:33:37 PM PST 24 169138590 ps
T370 /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.2697800425 Mar 05 03:19:25 PM PST 24 Mar 05 03:53:50 PM PST 24 16682548839 ps
T1566 /workspace/coverage/cover_reg_top/79.xbar_same_source.1134200435 Mar 05 03:38:34 PM PST 24 Mar 05 03:38:45 PM PST 24 114341395 ps
T1567 /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.2036331740 Mar 05 03:36:26 PM PST 24 Mar 05 03:37:54 PM PST 24 5053705092 ps
T563 /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.1137473511 Mar 05 03:28:48 PM PST 24 Mar 05 03:40:27 PM PST 24 6130740709 ps
T1568 /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.283055285 Mar 05 03:21:03 PM PST 24 Mar 05 03:21:57 PM PST 24 1293342093 ps
T1569 /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.971503603 Mar 05 03:22:09 PM PST 24 Mar 05 03:27:17 PM PST 24 17596719067 ps
T1570 /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.1606546747 Mar 05 03:33:34 PM PST 24 Mar 05 03:34:10 PM PST 24 738688401 ps
T1571 /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.1713390636 Mar 05 03:37:45 PM PST 24 Mar 05 03:56:33 PM PST 24 91082576912 ps
T1572 /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.1703808580 Mar 05 03:30:56 PM PST 24 Mar 05 03:35:48 PM PST 24 7039598253 ps
T1573 /workspace/coverage/cover_reg_top/47.xbar_error_random.3005026207 Mar 05 03:32:16 PM PST 24 Mar 05 03:32:40 PM PST 24 585743967 ps
T1574 /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.190490319 Mar 05 03:33:25 PM PST 24 Mar 05 03:34:51 PM PST 24 4900059610 ps
T481 /workspace/coverage/cover_reg_top/70.xbar_same_source.1693466937 Mar 05 03:36:49 PM PST 24 Mar 05 03:37:17 PM PST 24 317321396 ps
T1575 /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.4269691207 Mar 05 03:41:03 PM PST 24 Mar 05 03:42:48 PM PST 24 5837220494 ps
T1576 /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.2605624179 Mar 05 03:17:17 PM PST 24 Mar 05 03:17:23 PM PST 24 50678021 ps
T1577 /workspace/coverage/cover_reg_top/72.xbar_access_same_device.2862904831 Mar 05 03:37:16 PM PST 24 Mar 05 03:40:13 PM PST 24 3896077135 ps
T1578 /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.1253517207 Mar 05 03:29:32 PM PST 24 Mar 05 03:30:47 PM PST 24 7156812500 ps
T1579 /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.2885914502 Mar 05 03:35:38 PM PST 24 Mar 05 03:40:23 PM PST 24 8992894542 ps
T624 /workspace/coverage/cover_reg_top/14.chip_tl_errors.3135649588 Mar 05 03:22:58 PM PST 24 Mar 05 03:26:10 PM PST 24 3529995827 ps
T1580 /workspace/coverage/cover_reg_top/64.xbar_stress_all.3896931578 Mar 05 03:35:54 PM PST 24 Mar 05 03:39:35 PM PST 24 2547833029 ps
T1581 /workspace/coverage/cover_reg_top/97.xbar_access_same_device.2179849770 Mar 05 03:41:26 PM PST 24 Mar 05 03:42:47 PM PST 24 1532420135 ps
T1582 /workspace/coverage/cover_reg_top/77.xbar_stress_all.3917052484 Mar 05 03:38:16 PM PST 24 Mar 05 03:45:29 PM PST 24 11227328238 ps
T1583 /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.1583668470 Mar 05 03:38:24 PM PST 24 Mar 05 03:38:33 PM PST 24 39504317 ps
T1584 /workspace/coverage/cover_reg_top/23.xbar_random.287604698 Mar 05 03:26:33 PM PST 24 Mar 05 03:27:00 PM PST 24 307019688 ps
T1585 /workspace/coverage/cover_reg_top/61.xbar_random.1257166461 Mar 05 03:35:10 PM PST 24 Mar 05 03:35:45 PM PST 24 423038370 ps
T1586 /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.2297080233 Mar 05 03:30:39 PM PST 24 Mar 05 03:32:01 PM PST 24 4689485661 ps
T1587 /workspace/coverage/cover_reg_top/53.xbar_error_random.2138441234 Mar 05 03:33:35 PM PST 24 Mar 05 03:35:03 PM PST 24 2633016335 ps
T1588 /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.3158408832 Mar 05 03:33:06 PM PST 24 Mar 05 03:50:27 PM PST 24 52216316038 ps
T1589 /workspace/coverage/cover_reg_top/50.xbar_error_random.2622314961 Mar 05 03:32:56 PM PST 24 Mar 05 03:33:27 PM PST 24 758143262 ps
T1590 /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.3461659903 Mar 05 03:40:31 PM PST 24 Mar 05 03:40:59 PM PST 24 859294213 ps
T1591 /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3135475073 Mar 05 03:14:22 PM PST 24 Mar 05 03:19:54 PM PST 24 9682900157 ps
T1592 /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.774451157 Mar 05 03:29:03 PM PST 24 Mar 05 03:29:30 PM PST 24 123220665 ps
T1593 /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.18512914 Mar 05 03:35:56 PM PST 24 Mar 05 03:36:02 PM PST 24 44802848 ps
T1594 /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.1307611960 Mar 05 03:29:14 PM PST 24 Mar 05 03:29:59 PM PST 24 506212081 ps
T1595 /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.2871608480 Mar 05 03:37:59 PM PST 24 Mar 05 03:39:38 PM PST 24 5565765123 ps
T1596 /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.3711711193 Mar 05 03:35:31 PM PST 24 Mar 05 03:37:57 PM PST 24 3940804555 ps
T1597 /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.1273156397 Mar 05 03:32:49 PM PST 24 Mar 05 03:37:54 PM PST 24 17632845715 ps
T1598 /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.665088425 Mar 05 03:30:49 PM PST 24 Mar 05 03:44:33 PM PST 24 43871673351 ps
T1599 /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.4099150196 Mar 05 03:38:56 PM PST 24 Mar 05 03:39:08 PM PST 24 184621807 ps
T1600 /workspace/coverage/cover_reg_top/92.xbar_stress_all.4033479017 Mar 05 03:40:46 PM PST 24 Mar 05 03:48:59 PM PST 24 11970879881 ps
T1601 /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.982637208 Mar 05 03:26:01 PM PST 24 Mar 05 03:27:34 PM PST 24 8535385101 ps
T1602 /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.1534941973 Mar 05 03:33:19 PM PST 24 Mar 05 03:34:29 PM PST 24 4118841927 ps
T1603 /workspace/coverage/cover_reg_top/31.xbar_same_source.1648482625 Mar 05 03:28:55 PM PST 24 Mar 05 03:30:01 PM PST 24 2226795466 ps
T1604 /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.1320611661 Mar 05 03:39:02 PM PST 24 Mar 05 03:39:09 PM PST 24 51098796 ps
T1605 /workspace/coverage/cover_reg_top/87.xbar_random.3849569874 Mar 05 03:39:52 PM PST 24 Mar 05 03:40:38 PM PST 24 1321175571 ps
T449 /workspace/coverage/cover_reg_top/64.xbar_access_same_device.3419527671 Mar 05 03:35:56 PM PST 24 Mar 05 03:37:24 PM PST 24 1140938087 ps
T1606 /workspace/coverage/cover_reg_top/85.xbar_smoke.2170416056 Mar 05 03:39:22 PM PST 24 Mar 05 03:39:32 PM PST 24 224779623 ps
T1607 /workspace/coverage/cover_reg_top/14.xbar_smoke.4199856095 Mar 05 03:23:01 PM PST 24 Mar 05 03:23:09 PM PST 24 152242625 ps
T1608 /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.3760568196 Mar 05 03:29:56 PM PST 24 Mar 05 03:31:42 PM PST 24 10061081392 ps
T1609 /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.1908704928 Mar 05 03:28:39 PM PST 24 Mar 05 03:28:59 PM PST 24 170194862 ps
T1610 /workspace/coverage/cover_reg_top/95.xbar_same_source.2573095080 Mar 05 03:41:13 PM PST 24 Mar 05 03:41:33 PM PST 24 249309381 ps
T1611 /workspace/coverage/cover_reg_top/18.xbar_random.3659698888 Mar 05 03:24:33 PM PST 24 Mar 05 03:25:43 PM PST 24 1736254689 ps
T1612 /workspace/coverage/cover_reg_top/2.xbar_error_random.134234856 Mar 05 03:16:40 PM PST 24 Mar 05 03:18:17 PM PST 24 2559494817 ps
T1613 /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.2930391569 Mar 05 03:26:00 PM PST 24 Mar 05 03:27:48 PM PST 24 1286707746 ps
T1614 /workspace/coverage/cover_reg_top/24.xbar_smoke.2831352788 Mar 05 03:26:43 PM PST 24 Mar 05 03:26:51 PM PST 24 57521926 ps
T1615 /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.2703773579 Mar 05 03:16:29 PM PST 24 Mar 05 03:18:32 PM PST 24 6925064646 ps
T1616 /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.2123080881 Mar 05 03:38:53 PM PST 24 Mar 05 03:39:16 PM PST 24 233007446 ps
T1617 /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.1143646958 Mar 05 03:41:35 PM PST 24 Mar 05 03:43:06 PM PST 24 8986621509 ps
T1618 /workspace/coverage/cover_reg_top/64.xbar_error_random.974125624 Mar 05 03:35:55 PM PST 24 Mar 05 03:36:48 PM PST 24 1453254578 ps
T1619 /workspace/coverage/cover_reg_top/26.xbar_access_same_device.3744728528 Mar 05 03:27:24 PM PST 24 Mar 05 03:28:45 PM PST 24 1795063930 ps
T450 /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.2777200404 Mar 05 03:27:32 PM PST 24 Mar 05 03:31:54 PM PST 24 933158010 ps
T1620 /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.1211122511 Mar 05 03:18:02 PM PST 24 Mar 05 03:18:21 PM PST 24 174555384 ps
T625 /workspace/coverage/cover_reg_top/29.chip_tl_errors.460338982 Mar 05 03:28:11 PM PST 24 Mar 05 03:34:21 PM PST 24 4008237928 ps
T1621 /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.2091177662 Mar 05 03:18:44 PM PST 24 Mar 05 03:19:17 PM PST 24 683834827 ps
T1622 /workspace/coverage/cover_reg_top/14.xbar_error_random.2536891863 Mar 05 03:23:15 PM PST 24 Mar 05 03:23:52 PM PST 24 436287972 ps
T1623 /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.20631281 Mar 05 03:25:45 PM PST 24 Mar 05 03:32:57 PM PST 24 41109524837 ps
T1624 /workspace/coverage/cover_reg_top/79.xbar_access_same_device.4289512435 Mar 05 03:38:38 PM PST 24 Mar 05 03:40:35 PM PST 24 2575914383 ps
T1625 /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.238334855 Mar 05 03:39:45 PM PST 24 Mar 05 03:41:48 PM PST 24 1165123987 ps
T1626 /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.2785329054 Mar 05 03:24:05 PM PST 24 Mar 05 03:24:47 PM PST 24 1039315588 ps
T1627 /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.2917872420 Mar 05 03:28:09 PM PST 24 Mar 05 03:29:36 PM PST 24 4964337386 ps
T1628 /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1638832293 Mar 05 03:22:32 PM PST 24 Mar 05 03:23:38 PM PST 24 3571094603 ps
T1629 /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.187255557 Mar 05 03:17:35 PM PST 24 Mar 05 03:17:51 PM PST 24 139095411 ps
T1630 /workspace/coverage/cover_reg_top/10.xbar_stress_all.3940747527 Mar 05 03:21:04 PM PST 24 Mar 05 03:21:41 PM PST 24 1017765592 ps
T1631 /workspace/coverage/cover_reg_top/40.xbar_error_random.4030530015 Mar 05 03:30:50 PM PST 24 Mar 05 03:30:58 PM PST 24 69460189 ps
T1632 /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.3245508447 Mar 05 03:33:27 PM PST 24 Mar 05 03:33:33 PM PST 24 51651590 ps
T1633 /workspace/coverage/cover_reg_top/9.xbar_access_same_device.4015312574 Mar 05 03:20:40 PM PST 24 Mar 05 03:22:42 PM PST 24 2500281609 ps
T1634 /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.3223852063 Mar 05 03:25:02 PM PST 24 Mar 05 03:27:06 PM PST 24 7224375263 ps
T1635 /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.333511635 Mar 05 03:34:07 PM PST 24 Mar 05 03:34:13 PM PST 24 41672053 ps
T1636 /workspace/coverage/cover_reg_top/6.xbar_smoke.75707285 Mar 05 03:19:00 PM PST 24 Mar 05 03:19:09 PM PST 24 191119377 ps
T1637 /workspace/coverage/cover_reg_top/26.xbar_smoke.257104037 Mar 05 03:27:19 PM PST 24 Mar 05 03:27:28 PM PST 24 208950667 ps
T1638 /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.361142487 Mar 05 03:19:35 PM PST 24 Mar 05 03:24:16 PM PST 24 15266723806 ps
T1639 /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.1269890164 Mar 05 03:39:21 PM PST 24 Mar 05 03:39:27 PM PST 24 19734800 ps
T1640 /workspace/coverage/cover_reg_top/12.chip_csr_rw.2917505035 Mar 05 03:22:25 PM PST 24 Mar 05 03:27:14 PM PST 24 4241475200 ps
T1641 /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.918561937 Mar 05 03:39:27 PM PST 24 Mar 05 03:39:46 PM PST 24 181175666 ps
T1642 /workspace/coverage/cover_reg_top/45.xbar_random.2912828495 Mar 05 03:31:52 PM PST 24 Mar 05 03:32:34 PM PST 24 416079628 ps
T1643 /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.1891810878 Mar 05 03:38:01 PM PST 24 Mar 05 03:54:48 PM PST 24 81815591570 ps
T1644 /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.1173816767 Mar 05 03:17:51 PM PST 24 Mar 05 05:44:53 PM PST 24 52257592364 ps
T351 /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.3568253388 Mar 05 03:17:41 PM PST 24 Mar 05 03:21:30 PM PST 24 5713278600 ps
T1645 /workspace/coverage/cover_reg_top/41.xbar_smoke.2888950559 Mar 05 03:31:00 PM PST 24 Mar 05 03:31:11 PM PST 24 231237134 ps
T1646 /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.1788320201 Mar 05 03:34:29 PM PST 24 Mar 05 03:36:29 PM PST 24 6396276065 ps
T1647 /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.3267380456 Mar 05 03:30:05 PM PST 24 Mar 05 03:30:46 PM PST 24 988562152 ps
T1648 /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.62804444 Mar 05 03:19:00 PM PST 24 Mar 05 03:19:06 PM PST 24 46246125 ps
T1649 /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.1857142353 Mar 05 03:35:31 PM PST 24 Mar 05 03:41:37 PM PST 24 8128812776 ps
T1650 /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.121924195 Mar 05 03:16:14 PM PST 24 Mar 05 03:22:23 PM PST 24 11213292453 ps
T1651 /workspace/coverage/cover_reg_top/30.xbar_random.3973729617 Mar 05 03:28:30 PM PST 24 Mar 05 03:28:52 PM PST 24 487052571 ps
T1652 /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.900177344 Mar 05 03:31:52 PM PST 24 Mar 05 03:51:48 PM PST 24 59355343085 ps
T1653 /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.1120876461 Mar 05 03:33:59 PM PST 24 Mar 05 03:34:11 PM PST 24 156804693 ps
T1654 /workspace/coverage/cover_reg_top/13.xbar_same_source.3885623138 Mar 05 03:22:38 PM PST 24 Mar 05 03:22:57 PM PST 24 566948325 ps
T1655 /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.1938217163 Mar 05 03:33:50 PM PST 24 Mar 05 03:35:44 PM PST 24 10216315055 ps
T1656 /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.1949698688 Mar 05 03:17:16 PM PST 24 Mar 05 03:48:59 PM PST 24 15498228111 ps
T1657 /workspace/coverage/cover_reg_top/62.xbar_smoke.2668706275 Mar 05 03:35:17 PM PST 24 Mar 05 03:35:29 PM PST 24 267946499 ps
T1658 /workspace/coverage/cover_reg_top/26.xbar_stress_all.608657819 Mar 05 03:27:32 PM PST 24 Mar 05 03:29:15 PM PST 24 2770883033 ps
T1659 /workspace/coverage/cover_reg_top/50.xbar_smoke.2356229521 Mar 05 03:32:49 PM PST 24 Mar 05 03:32:56 PM PST 24 49112404 ps
T1660 /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.137739286 Mar 05 03:17:58 PM PST 24 Mar 05 03:18:05 PM PST 24 41004521 ps
T1661 /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.1023142255 Mar 05 03:33:42 PM PST 24 Mar 05 04:07:03 PM PST 24 123999341259 ps
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T1715 /workspace/coverage/cover_reg_top/28.xbar_error_random.2410676059 Mar 05 03:28:10 PM PST 24 Mar 05 03:28:50 PM PST 24 485797162 ps
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T1719 /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.265987191 Mar 05 03:37:36 PM PST 24 Mar 05 03:42:43 PM PST 24 8888449557 ps
T1720 /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.373868527 Mar 05 03:14:50 PM PST 24 Mar 05 03:15:20 PM PST 24 308276046 ps
T1721 /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.1436998591 Mar 05 03:33:08 PM PST 24 Mar 05 03:36:15 PM PST 24 1638670456 ps
T1722 /workspace/coverage/cover_reg_top/71.xbar_access_same_device.570457528 Mar 05 03:37:04 PM PST 24 Mar 05 03:39:02 PM PST 24 2450378646 ps
T1723 /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.3163356876 Mar 05 03:32:32 PM PST 24 Mar 05 03:32:38 PM PST 24 30345347 ps
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T1725 /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2048808045 Mar 05 03:21:51 PM PST 24 Mar 05 03:22:54 PM PST 24 200505970 ps
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T1727 /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.3820740147 Mar 05 03:29:22 PM PST 24 Mar 05 03:35:54 PM PST 24 2568706218 ps
T1728 /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.669024390 Mar 05 03:37:16 PM PST 24 Mar 05 03:37:37 PM PST 24 168421376 ps
T1729 /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.515041766 Mar 05 03:33:07 PM PST 24 Mar 05 03:36:10 PM PST 24 2700011362 ps
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T1733 /workspace/coverage/cover_reg_top/91.xbar_access_same_device.666229005 Mar 05 03:40:22 PM PST 24 Mar 05 03:41:46 PM PST 24 1562995320 ps
T1734 /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.1404578347 Mar 05 03:25:08 PM PST 24 Mar 05 03:25:41 PM PST 24 739300986 ps
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T1736 /workspace/coverage/cover_reg_top/33.xbar_error_random.3284998436 Mar 05 03:29:22 PM PST 24 Mar 05 03:30:43 PM PST 24 2146341462 ps
T1737 /workspace/coverage/cover_reg_top/51.xbar_error_random.2345424860 Mar 05 03:33:11 PM PST 24 Mar 05 03:33:42 PM PST 24 885377943 ps
T1738 /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.921785744 Mar 05 03:37:16 PM PST 24 Mar 05 03:52:10 PM PST 24 46923240328 ps
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T1740 /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.3253445647 Mar 05 03:34:23 PM PST 24 Mar 05 03:35:38 PM PST 24 2019926597 ps
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T1742 /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.560509338 Mar 05 03:35:50 PM PST 24 Mar 05 03:38:55 PM PST 24 18946107496 ps
T1743 /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.3956886454 Mar 05 03:39:45 PM PST 24 Mar 05 03:40:51 PM PST 24 3841442396 ps
T1744 /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.1969053269 Mar 05 03:41:43 PM PST 24 Mar 05 03:42:37 PM PST 24 642969892 ps
T1745 /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.3275072041 Mar 05 03:29:23 PM PST 24 Mar 05 03:30:16 PM PST 24 1216822960 ps
T1746 /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.3741923400 Mar 05 03:27:18 PM PST 24 Mar 05 03:27:25 PM PST 24 43797990 ps
T1747 /workspace/coverage/cover_reg_top/87.xbar_same_source.3756985547 Mar 05 03:39:42 PM PST 24 Mar 05 03:40:30 PM PST 24 1514111315 ps
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T1749 /workspace/coverage/cover_reg_top/70.xbar_error_random.410317009 Mar 05 03:36:51 PM PST 24 Mar 05 03:37:16 PM PST 24 289769042 ps
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T1754 /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.3100269671 Mar 05 03:41:43 PM PST 24 Mar 05 03:48:52 PM PST 24 12881049176 ps
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T1764 /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.2955018873 Mar 05 03:29:01 PM PST 24 Mar 05 03:30:21 PM PST 24 1018713448 ps
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T1774 /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.773759199 Mar 05 03:18:47 PM PST 24 Mar 05 03:38:17 PM PST 24 65223624743 ps
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