| T966 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.2267789957 |
|
|
Mar 05 04:15:27 PM PST 24 |
Mar 05 04:21:45 PM PST 24 |
5922568450 ps |
| T967 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3378209500 |
|
|
Mar 05 04:09:36 PM PST 24 |
Mar 05 04:19:15 PM PST 24 |
4047397240 ps |
| T717 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.2860653252 |
|
|
Mar 05 04:22:13 PM PST 24 |
Mar 05 04:31:50 PM PST 24 |
4798777594 ps |
| T261 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.3222442133 |
|
|
Mar 05 04:06:12 PM PST 24 |
Mar 05 04:22:10 PM PST 24 |
5544039672 ps |
| T703 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.4094818008 |
|
|
Mar 05 04:21:17 PM PST 24 |
Mar 05 04:33:05 PM PST 24 |
5785855816 ps |
| T658 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.2018437033 |
|
|
Mar 05 04:22:01 PM PST 24 |
Mar 05 04:33:10 PM PST 24 |
5283113120 ps |
| T968 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.4166516170 |
|
|
Mar 05 03:58:32 PM PST 24 |
Mar 05 04:33:37 PM PST 24 |
22061391998 ps |
| T725 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3442871312 |
|
|
Mar 05 04:22:01 PM PST 24 |
Mar 05 04:28:48 PM PST 24 |
3229237248 ps |
| T670 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.668853995 |
|
|
Mar 05 04:18:21 PM PST 24 |
Mar 05 04:30:10 PM PST 24 |
5757910320 ps |
| T229 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.484879192 |
|
|
Mar 05 04:18:45 PM PST 24 |
Mar 05 04:33:31 PM PST 24 |
4785408216 ps |
| T124 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.4275189353 |
|
|
Mar 05 03:49:52 PM PST 24 |
Mar 05 03:53:33 PM PST 24 |
3255257514 ps |
| T969 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.2991644999 |
|
|
Mar 05 04:20:42 PM PST 24 |
Mar 05 04:30:21 PM PST 24 |
4767443214 ps |
| T970 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1070991843 |
|
|
Mar 05 04:03:38 PM PST 24 |
Mar 05 04:11:23 PM PST 24 |
4261000609 ps |
| T971 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.883064972 |
|
|
Mar 05 04:15:45 PM PST 24 |
Mar 05 04:27:22 PM PST 24 |
4850277944 ps |
| T12 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.2457317068 |
|
|
Mar 05 03:48:57 PM PST 24 |
Mar 05 03:58:56 PM PST 24 |
5717988297 ps |
| T330 |
/workspace/coverage/default/0.chip_sw_hmac_enc.1943280458 |
|
|
Mar 05 03:51:11 PM PST 24 |
Mar 05 03:54:54 PM PST 24 |
2708633018 ps |
| T599 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.712751848 |
|
|
Mar 05 04:03:13 PM PST 24 |
Mar 05 04:13:46 PM PST 24 |
5005054552 ps |
| T972 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.439488364 |
|
|
Mar 05 04:09:20 PM PST 24 |
Mar 05 04:20:58 PM PST 24 |
4523491300 ps |
| T300 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1820442499 |
|
|
Mar 05 03:56:07 PM PST 24 |
Mar 05 04:07:41 PM PST 24 |
4605437784 ps |
| T601 |
/workspace/coverage/default/0.rom_volatile_raw_unlock.2544898138 |
|
|
Mar 05 03:54:58 PM PST 24 |
Mar 05 03:56:47 PM PST 24 |
2015994328 ps |
| T973 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.3638292140 |
|
|
Mar 05 04:12:24 PM PST 24 |
Mar 05 04:20:55 PM PST 24 |
6320298672 ps |
| T974 |
/workspace/coverage/default/1.chip_sival_flash_info_access.2510516051 |
|
|
Mar 05 03:54:48 PM PST 24 |
Mar 05 03:59:33 PM PST 24 |
3302564360 ps |
| T975 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3917964819 |
|
|
Mar 05 04:21:02 PM PST 24 |
Mar 05 04:27:11 PM PST 24 |
3935336448 ps |
| T976 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.4135837257 |
|
|
Mar 05 04:11:21 PM PST 24 |
Mar 05 04:20:12 PM PST 24 |
4669263856 ps |
| T70 |
/workspace/coverage/default/3.chip_tap_straps_testunlock0.27751139 |
|
|
Mar 05 04:17:43 PM PST 24 |
Mar 05 04:28:55 PM PST 24 |
7520645979 ps |
| T977 |
/workspace/coverage/default/1.chip_sw_inject_scramble_seed.1802429575 |
|
|
Mar 05 03:57:08 PM PST 24 |
Mar 05 07:00:17 PM PST 24 |
63509328842 ps |
| T307 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.638038310 |
|
|
Mar 05 04:06:00 PM PST 24 |
Mar 05 04:15:15 PM PST 24 |
4728927938 ps |
| T602 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.121388836 |
|
|
Mar 05 03:50:23 PM PST 24 |
Mar 05 03:52:51 PM PST 24 |
3507455285 ps |
| T713 |
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2871445885 |
|
|
Mar 05 04:25:27 PM PST 24 |
Mar 05 04:31:35 PM PST 24 |
3875254050 ps |
| T690 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3243002605 |
|
|
Mar 05 04:22:40 PM PST 24 |
Mar 05 04:29:01 PM PST 24 |
3821162488 ps |
| T105 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2959183904 |
|
|
Mar 05 04:12:44 PM PST 24 |
Mar 05 04:34:58 PM PST 24 |
18650609536 ps |
| T978 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3056068212 |
|
|
Mar 05 04:16:42 PM PST 24 |
Mar 05 04:50:56 PM PST 24 |
12612175850 ps |
| T979 |
/workspace/coverage/default/2.chip_sw_kmac_entropy.3376815913 |
|
|
Mar 05 04:08:03 PM PST 24 |
Mar 05 04:12:40 PM PST 24 |
3436217400 ps |
| T603 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1157255389 |
|
|
Mar 05 03:57:44 PM PST 24 |
Mar 05 03:59:41 PM PST 24 |
1910611091 ps |
| T980 |
/workspace/coverage/default/2.chip_sw_example_concurrency.1217335384 |
|
|
Mar 05 04:04:51 PM PST 24 |
Mar 05 04:09:26 PM PST 24 |
3019299428 ps |
| T421 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.2749583006 |
|
|
Mar 05 04:00:06 PM PST 24 |
Mar 05 04:17:17 PM PST 24 |
5135992512 ps |
| T191 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2429173895 |
|
|
Mar 05 03:52:11 PM PST 24 |
Mar 05 04:01:06 PM PST 24 |
4586101030 ps |
| T981 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1786229811 |
|
|
Mar 05 04:15:33 PM PST 24 |
Mar 05 04:21:06 PM PST 24 |
4042317224 ps |
| T93 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.1410926160 |
|
|
Mar 05 04:17:32 PM PST 24 |
Mar 05 04:26:54 PM PST 24 |
5678046136 ps |
| T982 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1449732235 |
|
|
Mar 05 03:55:20 PM PST 24 |
Mar 05 04:01:50 PM PST 24 |
4603714452 ps |
| T983 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.1212317972 |
|
|
Mar 05 04:00:47 PM PST 24 |
Mar 05 04:21:17 PM PST 24 |
9200228896 ps |
| T984 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.2439143156 |
|
|
Mar 05 04:08:09 PM PST 24 |
Mar 05 04:17:01 PM PST 24 |
6244438232 ps |
| T297 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2147452764 |
|
|
Mar 05 03:50:40 PM PST 24 |
Mar 05 04:18:57 PM PST 24 |
7462882248 ps |
| T985 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2707043497 |
|
|
Mar 05 04:08:08 PM PST 24 |
Mar 05 04:30:25 PM PST 24 |
8127196012 ps |
| T986 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.3645759296 |
|
|
Mar 05 04:08:54 PM PST 24 |
Mar 05 04:26:04 PM PST 24 |
11541415448 ps |
| T71 |
/workspace/coverage/default/3.chip_tap_straps_rma.3219360368 |
|
|
Mar 05 04:16:00 PM PST 24 |
Mar 05 04:23:11 PM PST 24 |
5282615318 ps |
| T214 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.4203997406 |
|
|
Mar 05 03:56:45 PM PST 24 |
Mar 05 05:21:28 PM PST 24 |
47054655746 ps |
| T650 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.125137579 |
|
|
Mar 05 04:19:16 PM PST 24 |
Mar 05 04:31:17 PM PST 24 |
4716568420 ps |
| T987 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.3573721975 |
|
|
Mar 05 04:00:24 PM PST 24 |
Mar 05 04:08:02 PM PST 24 |
3978701484 ps |
| T988 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3211129846 |
|
|
Mar 05 04:13:36 PM PST 24 |
Mar 05 04:22:46 PM PST 24 |
4489300104 ps |
| T989 |
/workspace/coverage/default/0.chip_sw_aes_idle.2469947829 |
|
|
Mar 05 03:50:28 PM PST 24 |
Mar 05 03:54:19 PM PST 24 |
3147522516 ps |
| T990 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.2680426554 |
|
|
Mar 05 04:08:07 PM PST 24 |
Mar 05 04:25:09 PM PST 24 |
5361630488 ps |
| T991 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3120002090 |
|
|
Mar 05 03:50:36 PM PST 24 |
Mar 05 04:02:33 PM PST 24 |
4569987790 ps |
| T218 |
/workspace/coverage/default/0.chip_sw_flash_init.3654485886 |
|
|
Mar 05 03:49:03 PM PST 24 |
Mar 05 04:22:48 PM PST 24 |
17515637260 ps |
| T177 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2419519353 |
|
|
Mar 05 04:06:52 PM PST 24 |
Mar 05 04:13:38 PM PST 24 |
3713963639 ps |
| T149 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1902109763 |
|
|
Mar 05 03:53:12 PM PST 24 |
Mar 05 05:02:58 PM PST 24 |
20811368763 ps |
| T621 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3919121325 |
|
|
Mar 05 03:57:32 PM PST 24 |
Mar 05 04:03:43 PM PST 24 |
3022882840 ps |
| T992 |
/workspace/coverage/default/0.chip_tap_straps_prod.2058620000 |
|
|
Mar 05 03:50:52 PM PST 24 |
Mar 05 04:06:40 PM PST 24 |
8986523272 ps |
| T993 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2349224936 |
|
|
Mar 05 03:52:24 PM PST 24 |
Mar 05 03:54:13 PM PST 24 |
2417703430 ps |
| T994 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3413470015 |
|
|
Mar 05 04:01:28 PM PST 24 |
Mar 05 04:40:07 PM PST 24 |
8955628907 ps |
| T995 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1581319050 |
|
|
Mar 05 03:50:53 PM PST 24 |
Mar 05 04:14:35 PM PST 24 |
6219442760 ps |
| T332 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3934095438 |
|
|
Mar 05 03:53:08 PM PST 24 |
Mar 05 04:00:01 PM PST 24 |
5679975520 ps |
| T217 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1782815919 |
|
|
Mar 05 03:49:46 PM PST 24 |
Mar 05 03:57:52 PM PST 24 |
5153643005 ps |
| T996 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1931405506 |
|
|
Mar 05 04:11:50 PM PST 24 |
Mar 05 04:28:39 PM PST 24 |
10562675650 ps |
| T997 |
/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3377572769 |
|
|
Mar 05 04:16:51 PM PST 24 |
Mar 05 04:27:38 PM PST 24 |
7103430865 ps |
| T998 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1424930891 |
|
|
Mar 05 04:25:53 PM PST 24 |
Mar 05 04:34:17 PM PST 24 |
3942406250 ps |
| T999 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2922109434 |
|
|
Mar 05 03:54:31 PM PST 24 |
Mar 05 04:06:39 PM PST 24 |
5044447320 ps |
| T1000 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.1215157358 |
|
|
Mar 05 04:25:53 PM PST 24 |
Mar 05 04:34:54 PM PST 24 |
4744883032 ps |
| T694 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2162458573 |
|
|
Mar 05 04:25:51 PM PST 24 |
Mar 05 04:33:21 PM PST 24 |
4129013262 ps |
| T28 |
/workspace/coverage/default/2.chip_sw_gpio.482718649 |
|
|
Mar 05 04:05:47 PM PST 24 |
Mar 05 04:13:45 PM PST 24 |
3844648124 ps |
| T1001 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.4149866746 |
|
|
Mar 05 03:49:03 PM PST 24 |
Mar 05 04:35:05 PM PST 24 |
14601476880 ps |
| T183 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3190751667 |
|
|
Mar 05 03:55:47 PM PST 24 |
Mar 05 04:09:38 PM PST 24 |
6030531260 ps |
| T1002 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.2799745759 |
|
|
Mar 05 04:00:43 PM PST 24 |
Mar 05 04:28:27 PM PST 24 |
6697313196 ps |
| T1003 |
/workspace/coverage/default/0.rom_keymgr_functest.745951151 |
|
|
Mar 05 03:53:31 PM PST 24 |
Mar 05 04:00:27 PM PST 24 |
4035472628 ps |
| T1004 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1744482971 |
|
|
Mar 05 04:17:44 PM PST 24 |
Mar 05 04:23:57 PM PST 24 |
3753097176 ps |
| T1005 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3299151624 |
|
|
Mar 05 04:17:39 PM PST 24 |
Mar 05 04:33:24 PM PST 24 |
9149407292 ps |
| T1006 |
/workspace/coverage/default/1.chip_sw_hmac_smoketest.2089500485 |
|
|
Mar 05 04:04:43 PM PST 24 |
Mar 05 04:10:49 PM PST 24 |
2860189678 ps |
| T672 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2332075947 |
|
|
Mar 05 04:22:24 PM PST 24 |
Mar 05 04:28:31 PM PST 24 |
3601664944 ps |
| T1007 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1307732150 |
|
|
Mar 05 04:16:05 PM PST 24 |
Mar 05 04:20:56 PM PST 24 |
3465256783 ps |
| T1008 |
/workspace/coverage/default/2.rom_e2e_asm_init_dev.2958316239 |
|
|
Mar 05 04:18:34 PM PST 24 |
Mar 05 04:49:01 PM PST 24 |
8258840124 ps |
| T698 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1543022069 |
|
|
Mar 05 04:21:12 PM PST 24 |
Mar 05 04:28:26 PM PST 24 |
3459266608 ps |
| T706 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.2740230957 |
|
|
Mar 05 04:22:12 PM PST 24 |
Mar 05 04:33:45 PM PST 24 |
5220525050 ps |
| T24 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.3008500432 |
|
|
Mar 05 03:49:30 PM PST 24 |
Mar 05 04:35:21 PM PST 24 |
11991081560 ps |
| T1009 |
/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1908267905 |
|
|
Mar 05 04:17:58 PM PST 24 |
Mar 05 04:48:46 PM PST 24 |
12802300832 ps |
| T657 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.3053121674 |
|
|
Mar 05 04:18:40 PM PST 24 |
Mar 05 04:29:12 PM PST 24 |
5213816436 ps |
| T677 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.2585829106 |
|
|
Mar 05 04:21:51 PM PST 24 |
Mar 05 04:31:41 PM PST 24 |
4548321856 ps |
| T1010 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.1378131288 |
|
|
Mar 05 04:08:55 PM PST 24 |
Mar 05 04:46:28 PM PST 24 |
9393532033 ps |
| T159 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2731707718 |
|
|
Mar 05 03:54:32 PM PST 24 |
Mar 05 04:01:45 PM PST 24 |
5204341726 ps |
| T1011 |
/workspace/coverage/default/2.rom_e2e_static_critical.2685878924 |
|
|
Mar 05 04:19:44 PM PST 24 |
Mar 05 04:55:03 PM PST 24 |
10941708296 ps |
| T1012 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.3605554773 |
|
|
Mar 05 04:08:07 PM PST 24 |
Mar 05 04:16:28 PM PST 24 |
4631737816 ps |
| T1013 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.482484641 |
|
|
Mar 05 04:07:28 PM PST 24 |
Mar 05 04:09:27 PM PST 24 |
2836416171 ps |
| T1014 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1980058042 |
|
|
Mar 05 04:06:34 PM PST 24 |
Mar 05 04:19:56 PM PST 24 |
6273815983 ps |
| T666 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.1745578043 |
|
|
Mar 05 04:19:20 PM PST 24 |
Mar 05 04:30:02 PM PST 24 |
5780122560 ps |
| T1015 |
/workspace/coverage/default/0.rom_e2e_smoke.1381149861 |
|
|
Mar 05 03:52:20 PM PST 24 |
Mar 05 04:27:58 PM PST 24 |
8963370260 ps |
| T1016 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.886800983 |
|
|
Mar 05 03:50:01 PM PST 24 |
Mar 05 04:07:35 PM PST 24 |
7392906838 ps |
| T422 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1561112347 |
|
|
Mar 05 04:09:29 PM PST 24 |
Mar 05 04:27:04 PM PST 24 |
5753047992 ps |
| T80 |
/workspace/coverage/default/0.chip_jtag_mem_access.536114763 |
|
|
Mar 05 03:43:50 PM PST 24 |
Mar 05 04:04:38 PM PST 24 |
13593087880 ps |
| T1017 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.2611965169 |
|
|
Mar 05 03:50:46 PM PST 24 |
Mar 05 03:58:49 PM PST 24 |
5364546196 ps |
| T1018 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.388078996 |
|
|
Mar 05 03:53:05 PM PST 24 |
Mar 05 04:04:35 PM PST 24 |
6359943274 ps |
| T1019 |
/workspace/coverage/default/0.chip_sw_flash_crash_alert.4014957703 |
|
|
Mar 05 03:51:43 PM PST 24 |
Mar 05 04:02:08 PM PST 24 |
5401824278 ps |
| T1020 |
/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.4093298917 |
|
|
Mar 05 03:54:53 PM PST 24 |
Mar 05 04:01:30 PM PST 24 |
3472874940 ps |
| T1021 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.2870535396 |
|
|
Mar 05 04:09:35 PM PST 24 |
Mar 05 04:36:39 PM PST 24 |
8542953760 ps |
| T487 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2823794436 |
|
|
Mar 05 03:51:08 PM PST 24 |
Mar 05 04:07:02 PM PST 24 |
4827415660 ps |
| T1022 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.183568812 |
|
|
Mar 05 04:12:15 PM PST 24 |
Mar 05 04:28:51 PM PST 24 |
7743299048 ps |
| T714 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3508283330 |
|
|
Mar 05 04:09:48 PM PST 24 |
Mar 05 04:18:36 PM PST 24 |
3112045720 ps |
| T1023 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1586158783 |
|
|
Mar 05 03:48:28 PM PST 24 |
Mar 05 07:33:34 PM PST 24 |
78634389358 ps |
| T1024 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter.1045546858 |
|
|
Mar 05 04:02:11 PM PST 24 |
Mar 05 04:05:36 PM PST 24 |
2430690802 ps |
| T1025 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2722014003 |
|
|
Mar 05 04:03:16 PM PST 24 |
Mar 05 04:12:09 PM PST 24 |
5585021720 ps |
| T678 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.291158488 |
|
|
Mar 05 04:15:26 PM PST 24 |
Mar 05 04:23:01 PM PST 24 |
3712012808 ps |
| T1026 |
/workspace/coverage/default/2.chip_sw_csrng_kat_test.505929115 |
|
|
Mar 05 04:10:55 PM PST 24 |
Mar 05 04:14:06 PM PST 24 |
3071338040 ps |
| T593 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3284145336 |
|
|
Mar 05 04:15:55 PM PST 24 |
Mar 05 05:12:37 PM PST 24 |
24630740856 ps |
| T25 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.4025641046 |
|
|
Mar 05 03:49:04 PM PST 24 |
Mar 05 03:57:34 PM PST 24 |
3556291036 ps |
| T648 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3039706055 |
|
|
Mar 05 03:50:15 PM PST 24 |
Mar 05 04:51:47 PM PST 24 |
20027715082 ps |
| T106 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2479866627 |
|
|
Mar 05 03:52:11 PM PST 24 |
Mar 05 04:00:39 PM PST 24 |
7860710872 ps |
| T1027 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.1288572520 |
|
|
Mar 05 04:08:10 PM PST 24 |
Mar 05 04:22:31 PM PST 24 |
5956608600 ps |
| T1028 |
/workspace/coverage/default/2.chip_tap_straps_rma.3092475075 |
|
|
Mar 05 04:12:17 PM PST 24 |
Mar 05 04:15:55 PM PST 24 |
2883058535 ps |
| T1029 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2480943816 |
|
|
Mar 05 03:54:52 PM PST 24 |
Mar 05 03:58:54 PM PST 24 |
3038223316 ps |
| T1030 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter.2228153499 |
|
|
Mar 05 03:51:21 PM PST 24 |
Mar 05 03:54:26 PM PST 24 |
2680959813 ps |
| T684 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.3848843132 |
|
|
Mar 05 04:21:10 PM PST 24 |
Mar 05 04:30:22 PM PST 24 |
5994995498 ps |
| T1031 |
/workspace/coverage/default/1.chip_sw_aes_entropy.3379686717 |
|
|
Mar 05 03:59:45 PM PST 24 |
Mar 05 04:03:27 PM PST 24 |
2518592050 ps |
| T1032 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.3464831737 |
|
|
Mar 05 04:18:12 PM PST 24 |
Mar 05 04:25:20 PM PST 24 |
6834864843 ps |
| T1033 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2914237896 |
|
|
Mar 05 04:00:50 PM PST 24 |
Mar 05 04:35:23 PM PST 24 |
9350357736 ps |
| T1034 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.2842018926 |
|
|
Mar 05 04:14:48 PM PST 24 |
Mar 05 04:27:54 PM PST 24 |
3649539640 ps |
| T1035 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.1702800646 |
|
|
Mar 05 04:17:37 PM PST 24 |
Mar 05 04:26:58 PM PST 24 |
5321667370 ps |
| T1036 |
/workspace/coverage/default/2.chip_sival_flash_info_access.4147901340 |
|
|
Mar 05 04:07:18 PM PST 24 |
Mar 05 04:13:56 PM PST 24 |
3393778580 ps |
| T686 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.3259487277 |
|
|
Mar 05 04:25:37 PM PST 24 |
Mar 05 04:34:06 PM PST 24 |
4420969402 ps |
| T1037 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2613290320 |
|
|
Mar 05 04:07:59 PM PST 24 |
Mar 05 04:17:05 PM PST 24 |
6643887808 ps |
| T1038 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3116547035 |
|
|
Mar 05 04:16:57 PM PST 24 |
Mar 05 04:42:00 PM PST 24 |
12846880422 ps |
| T1039 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2845127629 |
|
|
Mar 05 03:50:45 PM PST 24 |
Mar 05 03:58:14 PM PST 24 |
3609655092 ps |
| T738 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1626931788 |
|
|
Mar 05 04:25:01 PM PST 24 |
Mar 05 04:31:09 PM PST 24 |
4198797154 ps |
| T1040 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3212800230 |
|
|
Mar 05 03:56:37 PM PST 24 |
Mar 05 04:15:04 PM PST 24 |
6554782616 ps |
| T314 |
/workspace/coverage/default/0.chip_sival_flash_info_access.2180930368 |
|
|
Mar 05 03:50:13 PM PST 24 |
Mar 05 03:55:16 PM PST 24 |
2469104698 ps |
| T1041 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3469666716 |
|
|
Mar 05 04:14:21 PM PST 24 |
Mar 05 04:21:01 PM PST 24 |
5438080040 ps |
| T1042 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.372814045 |
|
|
Mar 05 03:50:39 PM PST 24 |
Mar 05 04:09:59 PM PST 24 |
5928298729 ps |
| T1043 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.3663862085 |
|
|
Mar 05 04:07:38 PM PST 24 |
Mar 05 04:31:04 PM PST 24 |
7915582754 ps |
| T710 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.281150819 |
|
|
Mar 05 04:19:39 PM PST 24 |
Mar 05 04:27:07 PM PST 24 |
3574892886 ps |
| T1044 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.265874088 |
|
|
Mar 05 03:56:47 PM PST 24 |
Mar 05 03:58:36 PM PST 24 |
2429111224 ps |
| T1045 |
/workspace/coverage/default/0.chip_sw_edn_kat.2145889161 |
|
|
Mar 05 03:50:07 PM PST 24 |
Mar 05 03:57:17 PM PST 24 |
3359068584 ps |
| T1046 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.2701863029 |
|
|
Mar 05 04:14:15 PM PST 24 |
Mar 05 04:27:26 PM PST 24 |
5802769608 ps |
| T1047 |
/workspace/coverage/default/2.chip_tap_straps_dev.3015943976 |
|
|
Mar 05 04:12:04 PM PST 24 |
Mar 05 04:29:12 PM PST 24 |
9173189498 ps |
| T94 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2466045608 |
|
|
Mar 05 04:19:02 PM PST 24 |
Mar 05 04:26:19 PM PST 24 |
3326539860 ps |
| T1048 |
/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.479686747 |
|
|
Mar 05 03:56:59 PM PST 24 |
Mar 05 04:00:26 PM PST 24 |
2619216072 ps |
| T1049 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.2218360455 |
|
|
Mar 05 03:55:14 PM PST 24 |
Mar 05 03:59:21 PM PST 24 |
2583909476 ps |
| T736 |
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.450981674 |
|
|
Mar 05 04:22:49 PM PST 24 |
Mar 05 04:30:37 PM PST 24 |
4117492690 ps |
| T212 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2477143556 |
|
|
Mar 05 04:00:32 PM PST 24 |
Mar 05 04:50:01 PM PST 24 |
10849374032 ps |
| T178 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3579377558 |
|
|
Mar 05 03:49:46 PM PST 24 |
Mar 05 03:59:02 PM PST 24 |
4859466612 ps |
| T1050 |
/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3594316817 |
|
|
Mar 05 04:20:43 PM PST 24 |
Mar 05 04:47:31 PM PST 24 |
6944837290 ps |
| T1051 |
/workspace/coverage/default/1.chip_sw_flash_init.1386450675 |
|
|
Mar 05 03:57:09 PM PST 24 |
Mar 05 04:34:27 PM PST 24 |
24864107416 ps |
| T1052 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1280443509 |
|
|
Mar 05 03:50:53 PM PST 24 |
Mar 05 04:04:29 PM PST 24 |
4566489427 ps |
| T325 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.688942955 |
|
|
Mar 05 04:07:47 PM PST 24 |
Mar 05 04:17:54 PM PST 24 |
19735307314 ps |
| T223 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.127803682 |
|
|
Mar 05 03:57:34 PM PST 24 |
Mar 05 04:10:36 PM PST 24 |
7759758286 ps |
| T1053 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.119981633 |
|
|
Mar 05 03:54:51 PM PST 24 |
Mar 05 04:08:00 PM PST 24 |
5749283496 ps |
| T1054 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.436465687 |
|
|
Mar 05 03:52:02 PM PST 24 |
Mar 05 04:03:25 PM PST 24 |
5794015041 ps |
| T676 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3868973111 |
|
|
Mar 05 04:24:40 PM PST 24 |
Mar 05 04:30:46 PM PST 24 |
3648387240 ps |
| T150 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1214547096 |
|
|
Mar 05 04:03:41 PM PST 24 |
Mar 05 05:10:08 PM PST 24 |
23324405491 ps |
| T1055 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1426015894 |
|
|
Mar 05 04:18:30 PM PST 24 |
Mar 05 04:24:17 PM PST 24 |
3966055000 ps |
| T1056 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.848152090 |
|
|
Mar 05 03:51:22 PM PST 24 |
Mar 05 03:58:03 PM PST 24 |
4815013636 ps |
| T1057 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3927244470 |
|
|
Mar 05 03:56:56 PM PST 24 |
Mar 05 04:10:09 PM PST 24 |
4485967502 ps |
| T1058 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3712250697 |
|
|
Mar 05 04:02:27 PM PST 24 |
Mar 05 04:12:33 PM PST 24 |
3858711750 ps |
| T1059 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3742801321 |
|
|
Mar 05 04:11:13 PM PST 24 |
Mar 05 04:37:31 PM PST 24 |
6319544710 ps |
| T1060 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.2200783523 |
|
|
Mar 05 04:07:19 PM PST 24 |
Mar 05 05:40:01 PM PST 24 |
48116314190 ps |
| T1061 |
/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.69581965 |
|
|
Mar 05 04:12:50 PM PST 24 |
Mar 05 04:23:00 PM PST 24 |
4774623828 ps |
| T1062 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.81625726 |
|
|
Mar 05 03:59:14 PM PST 24 |
Mar 05 04:08:25 PM PST 24 |
6363287224 ps |
| T1063 |
/workspace/coverage/default/1.rom_e2e_static_critical.3403552085 |
|
|
Mar 05 04:08:59 PM PST 24 |
Mar 05 04:45:40 PM PST 24 |
10698859894 ps |
| T1064 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2227841678 |
|
|
Mar 05 03:51:50 PM PST 24 |
Mar 05 04:00:09 PM PST 24 |
4493638856 ps |
| T1065 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.1906933957 |
|
|
Mar 05 04:08:14 PM PST 24 |
Mar 05 04:25:26 PM PST 24 |
7608979678 ps |
| T1066 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.92212723 |
|
|
Mar 05 03:56:15 PM PST 24 |
Mar 05 04:10:25 PM PST 24 |
5452406816 ps |
| T1067 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2997361654 |
|
|
Mar 05 04:03:21 PM PST 24 |
Mar 05 04:15:41 PM PST 24 |
4838109240 ps |
| T1068 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.3703646322 |
|
|
Mar 05 04:25:00 PM PST 24 |
Mar 05 04:37:32 PM PST 24 |
5045316800 ps |
| T1069 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.3332299937 |
|
|
Mar 05 03:57:59 PM PST 24 |
Mar 05 04:49:53 PM PST 24 |
11811947000 ps |
| T656 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.2939739483 |
|
|
Mar 05 04:17:59 PM PST 24 |
Mar 05 04:26:51 PM PST 24 |
5752520184 ps |
| T1070 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.4282838024 |
|
|
Mar 05 04:22:39 PM PST 24 |
Mar 05 04:34:41 PM PST 24 |
6164533048 ps |
| T1071 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.677353128 |
|
|
Mar 05 03:51:12 PM PST 24 |
Mar 05 03:58:05 PM PST 24 |
6159388852 ps |
| T335 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.2172256933 |
|
|
Mar 05 04:15:41 PM PST 24 |
Mar 05 04:26:20 PM PST 24 |
5036559416 ps |
| T336 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.389977930 |
|
|
Mar 05 04:25:11 PM PST 24 |
Mar 05 04:32:52 PM PST 24 |
4875989940 ps |
| T337 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2443407501 |
|
|
Mar 05 03:49:54 PM PST 24 |
Mar 05 04:31:19 PM PST 24 |
27522625990 ps |
| T338 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.1984828843 |
|
|
Mar 05 04:03:18 PM PST 24 |
Mar 05 04:07:46 PM PST 24 |
3087917984 ps |
| T339 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1912322196 |
|
|
Mar 05 04:04:38 PM PST 24 |
Mar 05 04:09:41 PM PST 24 |
2443386490 ps |
| T340 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.3282528346 |
|
|
Mar 05 03:48:52 PM PST 24 |
Mar 05 04:59:40 PM PST 24 |
18298372190 ps |
| T341 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3907492458 |
|
|
Mar 05 04:03:08 PM PST 24 |
Mar 05 04:25:42 PM PST 24 |
5219163158 ps |
| T342 |
/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1267334241 |
|
|
Mar 05 04:09:11 PM PST 24 |
Mar 05 07:24:22 PM PST 24 |
254511336788 ps |
| T343 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1478553753 |
|
|
Mar 05 04:12:19 PM PST 24 |
Mar 05 04:31:56 PM PST 24 |
7847499018 ps |
| T344 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3562268705 |
|
|
Mar 05 04:16:10 PM PST 24 |
Mar 05 04:24:53 PM PST 24 |
6610959206 ps |
| T1072 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3334371591 |
|
|
Mar 05 04:25:05 PM PST 24 |
Mar 05 04:31:26 PM PST 24 |
4161693630 ps |
| T1073 |
/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.1991251519 |
|
|
Mar 05 04:15:35 PM PST 24 |
Mar 05 04:19:33 PM PST 24 |
3130050568 ps |
| T1074 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3198949814 |
|
|
Mar 05 04:12:23 PM PST 24 |
Mar 05 04:16:18 PM PST 24 |
3134123455 ps |
| T1075 |
/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3955086300 |
|
|
Mar 05 04:12:42 PM PST 24 |
Mar 05 04:48:21 PM PST 24 |
19272631037 ps |
| T1076 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.2431969320 |
|
|
Mar 05 03:51:32 PM PST 24 |
Mar 05 03:55:20 PM PST 24 |
2391911000 ps |
| T1077 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2835270557 |
|
|
Mar 05 03:54:22 PM PST 24 |
Mar 05 03:57:26 PM PST 24 |
2394632998 ps |
| T326 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.726520391 |
|
|
Mar 05 03:51:43 PM PST 24 |
Mar 05 04:01:00 PM PST 24 |
19157823380 ps |
| T302 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.4013232580 |
|
|
Mar 05 03:50:02 PM PST 24 |
Mar 05 04:04:41 PM PST 24 |
4728649416 ps |
| T1078 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.3105439056 |
|
|
Mar 05 04:24:37 PM PST 24 |
Mar 05 04:33:57 PM PST 24 |
5093173004 ps |
| T1079 |
/workspace/coverage/default/2.chip_sw_aes_entropy.93292111 |
|
|
Mar 05 04:08:30 PM PST 24 |
Mar 05 04:13:12 PM PST 24 |
3109475976 ps |
| T1080 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.752363883 |
|
|
Mar 05 04:09:48 PM PST 24 |
Mar 05 04:25:13 PM PST 24 |
6141604228 ps |
| T1081 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.522235656 |
|
|
Mar 05 04:10:45 PM PST 24 |
Mar 05 04:22:40 PM PST 24 |
7256754829 ps |
| T1082 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1841818747 |
|
|
Mar 05 04:11:56 PM PST 24 |
Mar 05 04:26:24 PM PST 24 |
5131331656 ps |
| T1083 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.443180955 |
|
|
Mar 05 03:59:09 PM PST 24 |
Mar 05 04:08:45 PM PST 24 |
5303206512 ps |
| T1084 |
/workspace/coverage/default/0.rom_e2e_static_critical.2353183375 |
|
|
Mar 05 03:58:01 PM PST 24 |
Mar 05 04:32:17 PM PST 24 |
11162086614 ps |
| T1085 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access.230892581 |
|
|
Mar 05 03:54:54 PM PST 24 |
Mar 05 04:10:58 PM PST 24 |
5550731900 ps |
| T198 |
/workspace/coverage/default/0.chip_jtag_csr_rw.668238180 |
|
|
Mar 05 03:43:37 PM PST 24 |
Mar 05 04:03:39 PM PST 24 |
11921357150 ps |
| T1086 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.3957172585 |
|
|
Mar 05 04:03:29 PM PST 24 |
Mar 05 04:07:24 PM PST 24 |
2267383519 ps |
| T1087 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3425833183 |
|
|
Mar 05 03:56:09 PM PST 24 |
Mar 05 04:00:35 PM PST 24 |
2959295739 ps |
| T1088 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.1795053644 |
|
|
Mar 05 04:00:28 PM PST 24 |
Mar 05 04:46:09 PM PST 24 |
8572302117 ps |
| T192 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.579961165 |
|
|
Mar 05 04:03:09 PM PST 24 |
Mar 05 04:12:01 PM PST 24 |
4494058712 ps |
| T1089 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.386476122 |
|
|
Mar 05 03:51:06 PM PST 24 |
Mar 05 04:14:26 PM PST 24 |
15072533390 ps |
| T1090 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access.2810469201 |
|
|
Mar 05 04:07:25 PM PST 24 |
Mar 05 04:25:26 PM PST 24 |
5934521904 ps |
| T671 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.473853515 |
|
|
Mar 05 04:26:51 PM PST 24 |
Mar 05 04:34:40 PM PST 24 |
4701937004 ps |
| T693 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.1406240637 |
|
|
Mar 05 04:24:43 PM PST 24 |
Mar 05 04:32:42 PM PST 24 |
5441604470 ps |
| T1091 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2387349089 |
|
|
Mar 05 03:49:19 PM PST 24 |
Mar 05 03:54:09 PM PST 24 |
2291162384 ps |
| T1092 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.561898665 |
|
|
Mar 05 04:00:55 PM PST 24 |
Mar 05 04:15:01 PM PST 24 |
8080696859 ps |
| T1093 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2785081365 |
|
|
Mar 05 04:03:44 PM PST 24 |
Mar 05 04:16:50 PM PST 24 |
4430254046 ps |
| T1094 |
/workspace/coverage/default/0.chip_sw_example_flash.1273654408 |
|
|
Mar 05 03:50:48 PM PST 24 |
Mar 05 03:54:56 PM PST 24 |
2506740814 ps |
| T318 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.2999706805 |
|
|
Mar 05 04:19:01 PM PST 24 |
Mar 05 04:30:17 PM PST 24 |
4905271704 ps |
| T1095 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.2292827445 |
|
|
Mar 05 04:07:03 PM PST 24 |
Mar 05 04:13:00 PM PST 24 |
4457293350 ps |
| T1096 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.1736236869 |
|
|
Mar 05 04:22:45 PM PST 24 |
Mar 05 04:32:53 PM PST 24 |
5331236118 ps |
| T1097 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx.710884084 |
|
|
Mar 05 04:15:25 PM PST 24 |
Mar 05 04:33:07 PM PST 24 |
5840461380 ps |
| T722 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.863289221 |
|
|
Mar 05 04:16:41 PM PST 24 |
Mar 05 04:24:20 PM PST 24 |
3994657650 ps |
| T1098 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2733417256 |
|
|
Mar 05 03:57:05 PM PST 24 |
Mar 05 05:22:12 PM PST 24 |
47932054196 ps |
| T1099 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2578083575 |
|
|
Mar 05 04:12:46 PM PST 24 |
Mar 05 04:14:41 PM PST 24 |
2222141946 ps |
| T1100 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.3790630345 |
|
|
Mar 05 04:09:23 PM PST 24 |
Mar 05 04:27:37 PM PST 24 |
5479414416 ps |
| T160 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3116409351 |
|
|
Mar 05 04:11:00 PM PST 24 |
Mar 05 04:17:14 PM PST 24 |
5766000948 ps |
| T1101 |
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.735254230 |
|
|
Mar 05 04:17:01 PM PST 24 |
Mar 05 04:24:53 PM PST 24 |
6479794589 ps |
| T1102 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.127069068 |
|
|
Mar 05 03:57:58 PM PST 24 |
Mar 05 05:02:35 PM PST 24 |
16400125688 ps |
| T640 |
/workspace/coverage/default/2.rom_raw_unlock.2022597573 |
|
|
Mar 05 04:15:08 PM PST 24 |
Mar 05 04:50:52 PM PST 24 |
16542992277 ps |
| T40 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.598723412 |
|
|
Mar 05 03:57:37 PM PST 24 |
Mar 05 04:04:32 PM PST 24 |
2995023808 ps |
| T1103 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.2308963032 |
|
|
Mar 05 04:05:39 PM PST 24 |
Mar 05 04:08:51 PM PST 24 |
2207688024 ps |
| T1104 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2985203165 |
|
|
Mar 05 04:02:19 PM PST 24 |
Mar 05 04:14:34 PM PST 24 |
4451568660 ps |
| T1105 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.179010338 |
|
|
Mar 05 04:01:27 PM PST 24 |
Mar 05 04:29:21 PM PST 24 |
7290818933 ps |
| T742 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.2825699416 |
|
|
Mar 05 04:24:08 PM PST 24 |
Mar 05 04:31:44 PM PST 24 |
4115407100 ps |
| T1106 |
/workspace/coverage/default/1.chip_sw_alert_handler_escalation.1111388646 |
|
|
Mar 05 03:58:56 PM PST 24 |
Mar 05 04:07:09 PM PST 24 |
5578369080 ps |
| T1107 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.3132683596 |
|
|
Mar 05 04:09:38 PM PST 24 |
Mar 05 04:17:03 PM PST 24 |
3869318556 ps |
| T1108 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.4112024528 |
|
|
Mar 05 04:01:45 PM PST 24 |
Mar 05 04:11:29 PM PST 24 |
7059437908 ps |
| T37 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2138157187 |
|
|
Mar 05 03:51:29 PM PST 24 |
Mar 05 03:55:58 PM PST 24 |
2306023604 ps |
| T651 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.1559297617 |
|
|
Mar 05 03:55:59 PM PST 24 |
Mar 05 04:06:27 PM PST 24 |
5723805870 ps |
| T1109 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1357521616 |
|
|
Mar 05 03:54:20 PM PST 24 |
Mar 05 03:58:57 PM PST 24 |
2571028914 ps |
| T1110 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1023313289 |
|
|
Mar 05 04:18:24 PM PST 24 |
Mar 05 04:25:04 PM PST 24 |
4191305150 ps |
| T1111 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.3474211411 |
|
|
Mar 05 03:59:22 PM PST 24 |
Mar 05 04:02:58 PM PST 24 |
2555758400 ps |
| T1112 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.3125106976 |
|
|
Mar 05 03:50:35 PM PST 24 |
Mar 05 03:57:21 PM PST 24 |
2745513096 ps |
| T1113 |
/workspace/coverage/default/2.chip_sw_kmac_smoketest.347936463 |
|
|
Mar 05 04:14:57 PM PST 24 |
Mar 05 04:21:30 PM PST 24 |
2625351680 ps |
| T1114 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2189783551 |
|
|
Mar 05 03:51:30 PM PST 24 |
Mar 05 04:37:24 PM PST 24 |
25084563480 ps |
| T1115 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.1005882522 |
|
|
Mar 05 04:25:15 PM PST 24 |
Mar 05 04:34:21 PM PST 24 |
5036091916 ps |
| T1116 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2077264315 |
|
|
Mar 05 04:16:21 PM PST 24 |
Mar 05 04:30:14 PM PST 24 |
6086913496 ps |
| T1117 |
/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.810761236 |
|
|
Mar 05 04:09:16 PM PST 24 |
Mar 05 04:14:17 PM PST 24 |
2863380984 ps |
| T1118 |
/workspace/coverage/default/0.chip_sw_edn_sw_mode.575557512 |
|
|
Mar 05 03:50:28 PM PST 24 |
Mar 05 04:16:24 PM PST 24 |
6604006250 ps |
| T1119 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.419963207 |
|
|
Mar 05 03:49:26 PM PST 24 |
Mar 05 04:12:11 PM PST 24 |
6916780408 ps |
| T1120 |
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.1993894273 |
|
|
Mar 05 04:15:56 PM PST 24 |
Mar 05 04:58:17 PM PST 24 |
13839583104 ps |
| T119 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.1333742679 |
|
|
Mar 05 04:01:11 PM PST 24 |
Mar 05 04:12:51 PM PST 24 |
4400435272 ps |
| T274 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1720607957 |
|
|
Mar 05 03:51:00 PM PST 24 |
Mar 05 03:55:18 PM PST 24 |
2951785668 ps |
| T209 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1251991541 |
|
|
Mar 05 03:50:05 PM PST 24 |
Mar 05 03:59:18 PM PST 24 |
5851288026 ps |
| T1121 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.2147681940 |
|
|
Mar 05 04:23:29 PM PST 24 |
Mar 05 04:33:01 PM PST 24 |
6237364200 ps |