| T1122 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.51873424 |
|
|
Mar 05 03:51:40 PM PST 24 |
Mar 05 03:57:05 PM PST 24 |
3136024562 ps |
| T622 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.683641164 |
|
|
Mar 05 03:51:15 PM PST 24 |
Mar 05 03:57:10 PM PST 24 |
3621806556 ps |
| T1123 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1494784728 |
|
|
Mar 05 04:16:09 PM PST 24 |
Mar 05 04:24:34 PM PST 24 |
7719887928 ps |
| T1124 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1492644010 |
|
|
Mar 05 04:12:18 PM PST 24 |
Mar 05 04:23:15 PM PST 24 |
3433564752 ps |
| T1125 |
/workspace/coverage/default/0.chip_sw_aes_enc.3739419040 |
|
|
Mar 05 03:51:13 PM PST 24 |
Mar 05 03:54:31 PM PST 24 |
2472415624 ps |
| T1126 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1136399241 |
|
|
Mar 05 04:05:07 PM PST 24 |
Mar 05 04:09:21 PM PST 24 |
2438745400 ps |
| T1127 |
/workspace/coverage/default/2.chip_sw_aes_idle.666986875 |
|
|
Mar 05 04:09:08 PM PST 24 |
Mar 05 04:13:25 PM PST 24 |
3255782012 ps |
| T1128 |
/workspace/coverage/default/1.chip_sw_kmac_idle.62249274 |
|
|
Mar 05 04:00:39 PM PST 24 |
Mar 05 04:05:40 PM PST 24 |
3172784940 ps |
| T1129 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.800784989 |
|
|
Mar 05 04:22:33 PM PST 24 |
Mar 05 04:32:40 PM PST 24 |
6306731632 ps |
| T739 |
/workspace/coverage/default/93.chip_sw_all_escalation_resets.2972209068 |
|
|
Mar 05 04:25:30 PM PST 24 |
Mar 05 04:37:24 PM PST 24 |
5411790572 ps |
| T267 |
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2878909443 |
|
|
Mar 05 04:21:15 PM PST 24 |
Mar 05 04:27:54 PM PST 24 |
3919805540 ps |
| T1130 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3427353103 |
|
|
Mar 05 04:01:00 PM PST 24 |
Mar 05 04:31:08 PM PST 24 |
7232312869 ps |
| T1131 |
/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.4045244656 |
|
|
Mar 05 04:04:14 PM PST 24 |
Mar 05 04:08:25 PM PST 24 |
3082481430 ps |
| T1132 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.4130895754 |
|
|
Mar 05 03:52:43 PM PST 24 |
Mar 05 03:56:26 PM PST 24 |
2064225516 ps |
| T1133 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1362751603 |
|
|
Mar 05 03:51:17 PM PST 24 |
Mar 05 04:08:30 PM PST 24 |
5656851456 ps |
| T1134 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2541816561 |
|
|
Mar 05 03:54:14 PM PST 24 |
Mar 05 05:01:49 PM PST 24 |
22886685760 ps |
| T312 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.510581221 |
|
|
Mar 05 04:10:38 PM PST 24 |
Mar 05 04:16:38 PM PST 24 |
3528024792 ps |
| T727 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.3085818045 |
|
|
Mar 05 04:25:06 PM PST 24 |
Mar 05 04:37:30 PM PST 24 |
4392557940 ps |
| T49 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.3369987794 |
|
|
Mar 05 04:03:23 PM PST 24 |
Mar 05 04:12:08 PM PST 24 |
3657715944 ps |
| T131 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.3357965331 |
|
|
Mar 05 04:20:23 PM PST 24 |
Mar 05 04:30:43 PM PST 24 |
4706047688 ps |
| T1135 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.2149627856 |
|
|
Mar 05 03:58:04 PM PST 24 |
Mar 05 04:48:57 PM PST 24 |
12079500696 ps |
| T1136 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1014300976 |
|
|
Mar 05 04:07:29 PM PST 24 |
Mar 05 04:22:55 PM PST 24 |
6326656343 ps |
| T1137 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1482998729 |
|
|
Mar 05 04:07:40 PM PST 24 |
Mar 05 04:10:52 PM PST 24 |
2422936172 ps |
| T1138 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.3883540516 |
|
|
Mar 05 03:53:01 PM PST 24 |
Mar 05 04:08:11 PM PST 24 |
5214345418 ps |
| T1139 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.105532580 |
|
|
Mar 05 03:56:17 PM PST 24 |
Mar 05 04:20:14 PM PST 24 |
6404798856 ps |
| T1140 |
/workspace/coverage/default/1.chip_sw_flash_crash_alert.3085844932 |
|
|
Mar 05 04:02:52 PM PST 24 |
Mar 05 04:13:39 PM PST 24 |
5721925752 ps |
| T1141 |
/workspace/coverage/default/2.chip_sw_edn_kat.1867647639 |
|
|
Mar 05 04:10:53 PM PST 24 |
Mar 05 04:18:07 PM PST 24 |
3482957840 ps |
| T1142 |
/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.839629318 |
|
|
Mar 05 04:17:50 PM PST 24 |
Mar 05 04:27:16 PM PST 24 |
7576597770 ps |
| T298 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.3997121406 |
|
|
Mar 05 03:59:21 PM PST 24 |
Mar 05 04:20:52 PM PST 24 |
5955755576 ps |
| T1143 |
/workspace/coverage/default/0.chip_sw_hmac_smoketest.4053985597 |
|
|
Mar 05 03:54:39 PM PST 24 |
Mar 05 04:00:52 PM PST 24 |
3298916136 ps |
| T688 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3018435249 |
|
|
Mar 05 04:17:28 PM PST 24 |
Mar 05 04:25:49 PM PST 24 |
3908001300 ps |
| T1144 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2613063033 |
|
|
Mar 05 04:07:45 PM PST 24 |
Mar 05 04:42:43 PM PST 24 |
22164931726 ps |
| T52 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.171000382 |
|
|
Mar 05 03:55:43 PM PST 24 |
Mar 05 04:03:47 PM PST 24 |
5318492030 ps |
| T388 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.3055148291 |
|
|
Mar 05 04:16:54 PM PST 24 |
Mar 05 04:28:29 PM PST 24 |
5559203548 ps |
| T268 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.907173401 |
|
|
Mar 05 03:52:02 PM PST 24 |
Mar 05 03:58:23 PM PST 24 |
3088078600 ps |
| T389 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.770183524 |
|
|
Mar 05 04:14:17 PM PST 24 |
Mar 05 04:26:03 PM PST 24 |
6667701748 ps |
| T390 |
/workspace/coverage/default/1.chip_tap_straps_dev.169416481 |
|
|
Mar 05 04:03:46 PM PST 24 |
Mar 05 04:05:56 PM PST 24 |
2348553080 ps |
| T391 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.2074243332 |
|
|
Mar 05 04:18:38 PM PST 24 |
Mar 05 04:28:23 PM PST 24 |
5141164822 ps |
| T392 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.818529557 |
|
|
Mar 05 04:09:03 PM PST 24 |
Mar 05 04:15:19 PM PST 24 |
3919264196 ps |
| T393 |
/workspace/coverage/default/0.chip_sw_usbdev_config_host.1419609024 |
|
|
Mar 05 03:49:44 PM PST 24 |
Mar 05 04:19:57 PM PST 24 |
8274124092 ps |
| T394 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.3130627238 |
|
|
Mar 05 04:19:17 PM PST 24 |
Mar 05 04:29:26 PM PST 24 |
4507935388 ps |
| T395 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.120462787 |
|
|
Mar 05 03:51:22 PM PST 24 |
Mar 05 03:54:40 PM PST 24 |
2477244842 ps |
| T1145 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2541974030 |
|
|
Mar 05 04:04:00 PM PST 24 |
Mar 05 04:09:03 PM PST 24 |
3411838733 ps |
| T682 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1796862892 |
|
|
Mar 05 04:24:38 PM PST 24 |
Mar 05 04:31:03 PM PST 24 |
3411863848 ps |
| T1146 |
/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.569557183 |
|
|
Mar 05 04:08:17 PM PST 24 |
Mar 05 04:39:54 PM PST 24 |
8902370301 ps |
| T1147 |
/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1492768567 |
|
|
Mar 05 03:59:17 PM PST 24 |
Mar 05 07:28:03 PM PST 24 |
254706472264 ps |
| T1148 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3878504953 |
|
|
Mar 05 03:51:01 PM PST 24 |
Mar 05 04:55:13 PM PST 24 |
15644474616 ps |
| T1149 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.1269158679 |
|
|
Mar 05 04:04:58 PM PST 24 |
Mar 05 04:08:46 PM PST 24 |
2576349878 ps |
| T1150 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.4008572477 |
|
|
Mar 05 03:59:59 PM PST 24 |
Mar 05 04:07:38 PM PST 24 |
4116407582 ps |
| T632 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3359853231 |
|
|
Mar 05 04:06:01 PM PST 24 |
Mar 05 04:22:26 PM PST 24 |
5935707268 ps |
| T1151 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1507485789 |
|
|
Mar 05 04:01:28 PM PST 24 |
Mar 05 04:39:59 PM PST 24 |
8374893136 ps |
| T210 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.403059759 |
|
|
Mar 05 04:00:22 PM PST 24 |
Mar 05 04:09:25 PM PST 24 |
5122177270 ps |
| T1152 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1764649111 |
|
|
Mar 05 03:50:56 PM PST 24 |
Mar 05 04:05:23 PM PST 24 |
8197553344 ps |
| T1153 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.3343096330 |
|
|
Mar 05 03:49:29 PM PST 24 |
Mar 05 03:53:10 PM PST 24 |
2426969488 ps |
| T1154 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3349543530 |
|
|
Mar 05 04:15:30 PM PST 24 |
Mar 05 04:31:47 PM PST 24 |
4997128776 ps |
| T1155 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.163170360 |
|
|
Mar 05 03:49:20 PM PST 24 |
Mar 05 04:29:29 PM PST 24 |
26677010918 ps |
| T398 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1036774062 |
|
|
Mar 05 03:51:38 PM PST 24 |
Mar 05 04:19:38 PM PST 24 |
20434190618 ps |
| T1156 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2268743209 |
|
|
Mar 05 03:56:39 PM PST 24 |
Mar 05 04:34:36 PM PST 24 |
9051059740 ps |
| T1157 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.649078479 |
|
|
Mar 05 03:50:20 PM PST 24 |
Mar 05 04:00:33 PM PST 24 |
5268520136 ps |
| T1158 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2110753128 |
|
|
Mar 05 04:07:40 PM PST 24 |
Mar 05 04:58:33 PM PST 24 |
18879102335 ps |
| T1159 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.2119124822 |
|
|
Mar 05 03:49:27 PM PST 24 |
Mar 05 07:01:00 PM PST 24 |
63378534909 ps |
| T1160 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.247490014 |
|
|
Mar 05 04:00:45 PM PST 24 |
Mar 05 04:08:05 PM PST 24 |
4175857548 ps |
| T275 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.3929071826 |
|
|
Mar 05 04:02:38 PM PST 24 |
Mar 05 04:06:11 PM PST 24 |
2382729045 ps |
| T1161 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.50419055 |
|
|
Mar 05 04:18:29 PM PST 24 |
Mar 05 04:25:15 PM PST 24 |
3599767866 ps |
| T411 |
/workspace/coverage/default/1.chip_jtag_mem_access.3111678840 |
|
|
Mar 05 03:55:07 PM PST 24 |
Mar 05 04:19:37 PM PST 24 |
12860338234 ps |
| T1162 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.506196005 |
|
|
Mar 05 04:10:22 PM PST 24 |
Mar 05 04:34:49 PM PST 24 |
7777179780 ps |
| T685 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.3112623434 |
|
|
Mar 05 04:25:10 PM PST 24 |
Mar 05 04:35:15 PM PST 24 |
5482707448 ps |
| T653 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3287926097 |
|
|
Mar 05 04:20:17 PM PST 24 |
Mar 05 04:27:33 PM PST 24 |
3844370880 ps |
| T1163 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.2856721299 |
|
|
Mar 05 03:54:24 PM PST 24 |
Mar 05 03:58:02 PM PST 24 |
2145925528 ps |
| T697 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.1448073856 |
|
|
Mar 05 04:20:34 PM PST 24 |
Mar 05 04:31:33 PM PST 24 |
4754108040 ps |
| T1164 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4245529853 |
|
|
Mar 05 04:01:33 PM PST 24 |
Mar 05 04:12:53 PM PST 24 |
4029690612 ps |
| T294 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.4239971067 |
|
|
Mar 05 04:11:19 PM PST 24 |
Mar 05 04:31:00 PM PST 24 |
6138810392 ps |
| T305 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1578154518 |
|
|
Mar 05 03:50:02 PM PST 24 |
Mar 05 04:00:32 PM PST 24 |
4573770201 ps |
| T1165 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.1935580173 |
|
|
Mar 05 03:49:08 PM PST 24 |
Mar 05 04:03:14 PM PST 24 |
5344186806 ps |
| T1166 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1766642398 |
|
|
Mar 05 03:57:31 PM PST 24 |
Mar 05 04:35:13 PM PST 24 |
8946974438 ps |
| T329 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3638185254 |
|
|
Mar 05 04:03:51 PM PST 24 |
Mar 05 04:15:32 PM PST 24 |
4788277281 ps |
| T1167 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1403532560 |
|
|
Mar 05 04:06:17 PM PST 24 |
Mar 05 04:22:42 PM PST 24 |
5753907646 ps |
| T1168 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.217797891 |
|
|
Mar 05 03:53:26 PM PST 24 |
Mar 05 04:09:22 PM PST 24 |
6968808629 ps |
| T1169 |
/workspace/coverage/default/1.chip_sw_uart_smoketest_signed.1037533307 |
|
|
Mar 05 04:09:42 PM PST 24 |
Mar 05 04:37:13 PM PST 24 |
8457206280 ps |
| T1170 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2965352430 |
|
|
Mar 05 04:07:27 PM PST 24 |
Mar 05 04:28:35 PM PST 24 |
12501131774 ps |
| T51 |
/workspace/coverage/default/1.chip_jtag_csr_rw.1063378371 |
|
|
Mar 05 03:55:03 PM PST 24 |
Mar 05 04:40:11 PM PST 24 |
19831793650 ps |
| T381 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.3373784079 |
|
|
Mar 05 04:18:24 PM PST 24 |
Mar 05 04:46:48 PM PST 24 |
8758041913 ps |
| T382 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1490002260 |
|
|
Mar 05 04:07:51 PM PST 24 |
Mar 05 04:14:54 PM PST 24 |
6864560432 ps |
| T383 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1845779800 |
|
|
Mar 05 04:23:15 PM PST 24 |
Mar 05 04:29:16 PM PST 24 |
3708058416 ps |
| T303 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.1843145649 |
|
|
Mar 05 04:01:37 PM PST 24 |
Mar 05 04:17:09 PM PST 24 |
4982220520 ps |
| T384 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3903663089 |
|
|
Mar 05 04:10:46 PM PST 24 |
Mar 05 04:26:52 PM PST 24 |
7608242154 ps |
| T385 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1226091176 |
|
|
Mar 05 04:16:56 PM PST 24 |
Mar 05 04:20:36 PM PST 24 |
2390880688 ps |
| T386 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1126546998 |
|
|
Mar 05 03:51:37 PM PST 24 |
Mar 05 04:01:24 PM PST 24 |
4701162736 ps |
| T349 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.2650644342 |
|
|
Mar 05 04:09:56 PM PST 24 |
Mar 05 04:20:54 PM PST 24 |
3101857960 ps |
| T387 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.1477142408 |
|
|
Mar 05 04:04:20 PM PST 24 |
Mar 05 04:09:34 PM PST 24 |
2716868544 ps |
| T1171 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1395158426 |
|
|
Mar 05 03:51:44 PM PST 24 |
Mar 05 04:16:20 PM PST 24 |
7470088008 ps |
| T719 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.914591927 |
|
|
Mar 05 04:24:37 PM PST 24 |
Mar 05 04:30:35 PM PST 24 |
3444756214 ps |
| T1172 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.198751592 |
|
|
Mar 05 04:11:19 PM PST 24 |
Mar 05 04:23:31 PM PST 24 |
5364269752 ps |
| T1173 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod.127023584 |
|
|
Mar 05 03:58:57 PM PST 24 |
Mar 05 04:32:25 PM PST 24 |
9137148932 ps |
| T1174 |
/workspace/coverage/default/0.chip_sw_aes_entropy.1526093942 |
|
|
Mar 05 03:50:25 PM PST 24 |
Mar 05 03:54:24 PM PST 24 |
2913777000 ps |
| T1175 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.1681588212 |
|
|
Mar 05 04:23:43 PM PST 24 |
Mar 05 04:33:28 PM PST 24 |
5145059710 ps |
| T1176 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3590354164 |
|
|
Mar 05 03:58:23 PM PST 24 |
Mar 05 04:32:15 PM PST 24 |
8972769297 ps |
| T1177 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2944136764 |
|
|
Mar 05 04:11:05 PM PST 24 |
Mar 05 04:16:28 PM PST 24 |
3354036312 ps |
| T1178 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.251007590 |
|
|
Mar 05 04:17:22 PM PST 24 |
Mar 05 04:25:54 PM PST 24 |
3717201400 ps |
| T1179 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.1962678209 |
|
|
Mar 05 04:10:21 PM PST 24 |
Mar 05 04:16:46 PM PST 24 |
3926907000 ps |
| T734 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1694774594 |
|
|
Mar 05 04:20:43 PM PST 24 |
Mar 05 04:27:15 PM PST 24 |
3641148460 ps |
| T1180 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3942458541 |
|
|
Mar 05 04:09:08 PM PST 24 |
Mar 05 04:37:24 PM PST 24 |
8158441700 ps |
| T1181 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2283661180 |
|
|
Mar 05 04:08:47 PM PST 24 |
Mar 05 04:15:30 PM PST 24 |
2933710965 ps |
| T1182 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1109757510 |
|
|
Mar 05 03:57:31 PM PST 24 |
Mar 05 04:06:42 PM PST 24 |
8382183730 ps |
| T639 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2234636621 |
|
|
Mar 05 03:58:48 PM PST 24 |
Mar 05 04:08:39 PM PST 24 |
4248671028 ps |
| T595 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.1343024932 |
|
|
Mar 05 03:50:13 PM PST 24 |
Mar 05 04:09:12 PM PST 24 |
4469375726 ps |
| T333 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2103893473 |
|
|
Mar 05 04:16:27 PM PST 24 |
Mar 05 04:28:43 PM PST 24 |
4878576970 ps |
| T359 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1472905896 |
|
|
Mar 05 04:03:09 PM PST 24 |
Mar 05 04:07:50 PM PST 24 |
2607404848 ps |
| T1183 |
/workspace/coverage/default/0.chip_sw_aes_smoketest.3675782486 |
|
|
Mar 05 03:54:46 PM PST 24 |
Mar 05 03:57:55 PM PST 24 |
2448377052 ps |
| T1184 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2186709815 |
|
|
Mar 05 04:02:11 PM PST 24 |
Mar 05 04:10:30 PM PST 24 |
3281450866 ps |
| T1185 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.2063605560 |
|
|
Mar 05 04:10:01 PM PST 24 |
Mar 05 04:13:40 PM PST 24 |
2709296963 ps |
| T327 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2881081101 |
|
|
Mar 05 03:58:46 PM PST 24 |
Mar 05 04:07:21 PM PST 24 |
18897628868 ps |
| T1186 |
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.367986626 |
|
|
Mar 05 04:22:02 PM PST 24 |
Mar 05 04:29:40 PM PST 24 |
4333512320 ps |
| T1187 |
/workspace/coverage/default/2.chip_sw_example_flash.4056913661 |
|
|
Mar 05 04:05:17 PM PST 24 |
Mar 05 04:09:05 PM PST 24 |
2045423838 ps |
| T1188 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3056434526 |
|
|
Mar 05 03:49:53 PM PST 24 |
Mar 05 04:05:05 PM PST 24 |
10611542294 ps |
| T1189 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1104141239 |
|
|
Mar 05 04:02:39 PM PST 24 |
Mar 05 04:06:53 PM PST 24 |
2612436963 ps |
| T737 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1637197133 |
|
|
Mar 05 04:23:44 PM PST 24 |
Mar 05 04:31:43 PM PST 24 |
5292289430 ps |
| T1190 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.3803395396 |
|
|
Mar 05 04:09:22 PM PST 24 |
Mar 05 07:57:17 PM PST 24 |
64864390287 ps |
| T730 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1949467714 |
|
|
Mar 05 04:20:23 PM PST 24 |
Mar 05 04:24:32 PM PST 24 |
3108131000 ps |
| T1191 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.650885243 |
|
|
Mar 05 04:01:31 PM PST 24 |
Mar 05 04:09:02 PM PST 24 |
4508325740 ps |
| T1192 |
/workspace/coverage/default/1.chip_sw_edn_kat.978456310 |
|
|
Mar 05 04:01:52 PM PST 24 |
Mar 05 04:16:26 PM PST 24 |
2982609880 ps |
| T295 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.351616065 |
|
|
Mar 05 03:52:07 PM PST 24 |
Mar 05 04:14:27 PM PST 24 |
6271117448 ps |
| T1193 |
/workspace/coverage/default/2.chip_sw_example_rom.2446342916 |
|
|
Mar 05 04:05:23 PM PST 24 |
Mar 05 04:07:52 PM PST 24 |
2378581756 ps |
| T1194 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.312783167 |
|
|
Mar 05 04:15:34 PM PST 24 |
Mar 05 04:43:39 PM PST 24 |
8244520102 ps |
| T1195 |
/workspace/coverage/default/0.chip_tap_straps_rma.2425837032 |
|
|
Mar 05 03:50:28 PM PST 24 |
Mar 05 03:53:18 PM PST 24 |
2420887205 ps |
| T1196 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1294829011 |
|
|
Mar 05 03:50:28 PM PST 24 |
Mar 05 05:26:03 PM PST 24 |
48382980198 ps |
| T1197 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.3044398229 |
|
|
Mar 05 03:55:12 PM PST 24 |
Mar 05 04:11:20 PM PST 24 |
5216628880 ps |
| T720 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1982076932 |
|
|
Mar 05 04:21:42 PM PST 24 |
Mar 05 04:28:33 PM PST 24 |
3439316904 ps |
| T1198 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.2056460625 |
|
|
Mar 05 03:55:41 PM PST 24 |
Mar 05 04:18:01 PM PST 24 |
7316367660 ps |
| T317 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.607608826 |
|
|
Mar 05 04:18:38 PM PST 24 |
Mar 05 04:32:49 PM PST 24 |
4565028436 ps |
| T1199 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2173657914 |
|
|
Mar 05 04:05:15 PM PST 24 |
Mar 05 04:09:41 PM PST 24 |
2254484410 ps |
| T668 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.3713596665 |
|
|
Mar 05 04:23:52 PM PST 24 |
Mar 05 04:34:28 PM PST 24 |
4894094104 ps |
| T276 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.4165559880 |
|
|
Mar 05 03:53:11 PM PST 24 |
Mar 05 03:58:31 PM PST 24 |
2996955640 ps |
| T1200 |
/workspace/coverage/default/2.chip_sw_alert_handler_escalation.389444385 |
|
|
Mar 05 04:09:41 PM PST 24 |
Mar 05 04:17:44 PM PST 24 |
5288465128 ps |
| T1201 |
/workspace/coverage/default/2.chip_sw_aes_enc.247969534 |
|
|
Mar 05 04:08:46 PM PST 24 |
Mar 05 04:13:26 PM PST 24 |
2108703082 ps |
| T1202 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.145097777 |
|
|
Mar 05 03:48:35 PM PST 24 |
Mar 05 04:00:13 PM PST 24 |
4290116976 ps |
| T57 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.2811036946 |
|
|
Mar 05 03:50:10 PM PST 24 |
Mar 05 03:58:55 PM PST 24 |
5532549992 ps |
| T1203 |
/workspace/coverage/default/0.chip_sw_coremark.2875568709 |
|
|
Mar 05 03:52:04 PM PST 24 |
Mar 05 06:38:30 PM PST 24 |
50321874940 ps |
| T1204 |
/workspace/coverage/default/1.chip_sw_otbn_randomness.1596264639 |
|
|
Mar 05 03:59:13 PM PST 24 |
Mar 05 04:18:00 PM PST 24 |
5635850014 ps |
| T1205 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2122632180 |
|
|
Mar 05 04:01:59 PM PST 24 |
Mar 05 04:08:03 PM PST 24 |
4150511494 ps |
| T733 |
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1631532863 |
|
|
Mar 05 04:21:33 PM PST 24 |
Mar 05 04:28:51 PM PST 24 |
3776983464 ps |
| T1206 |
/workspace/coverage/default/0.chip_sw_aes_masking_off.2083442775 |
|
|
Mar 05 03:51:15 PM PST 24 |
Mar 05 03:57:01 PM PST 24 |
2723314196 ps |
| T1207 |
/workspace/coverage/default/0.chip_sw_uart_smoketest.3134606099 |
|
|
Mar 05 03:54:57 PM PST 24 |
Mar 05 03:59:44 PM PST 24 |
2499875500 ps |
| T313 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2594319976 |
|
|
Mar 05 04:06:32 PM PST 24 |
Mar 05 04:19:17 PM PST 24 |
4579357015 ps |
| T56 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.4282597539 |
|
|
Mar 05 04:09:27 PM PST 24 |
Mar 05 04:14:10 PM PST 24 |
3747120418 ps |
| T1208 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3518304237 |
|
|
Mar 05 03:59:01 PM PST 24 |
Mar 05 04:55:10 PM PST 24 |
11845942150 ps |
| T1209 |
/workspace/coverage/default/2.chip_sw_hmac_enc.1099884835 |
|
|
Mar 05 04:09:27 PM PST 24 |
Mar 05 04:12:46 PM PST 24 |
2118491168 ps |
| T1210 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2879494816 |
|
|
Mar 05 04:13:44 PM PST 24 |
Mar 05 04:33:51 PM PST 24 |
5492369064 ps |
| T236 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1256858312 |
|
|
Mar 05 04:14:47 PM PST 24 |
Mar 05 04:24:15 PM PST 24 |
5138391636 ps |
| T1211 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.3467510594 |
|
|
Mar 05 03:51:10 PM PST 24 |
Mar 05 04:17:17 PM PST 24 |
11248175250 ps |
| T728 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.306319567 |
|
|
Mar 05 04:23:45 PM PST 24 |
Mar 05 04:29:11 PM PST 24 |
3413600436 ps |
| T1212 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3077160885 |
|
|
Mar 05 03:50:02 PM PST 24 |
Mar 05 04:02:19 PM PST 24 |
4600330604 ps |
| T699 |
/workspace/coverage/default/56.chip_sw_all_escalation_resets.1847359152 |
|
|
Mar 05 04:22:32 PM PST 24 |
Mar 05 04:34:07 PM PST 24 |
4786630032 ps |
| T1213 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.1146234137 |
|
|
Mar 05 04:12:27 PM PST 24 |
Mar 05 04:16:13 PM PST 24 |
2019014148 ps |
| T1214 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.355863402 |
|
|
Mar 05 03:57:05 PM PST 24 |
Mar 05 04:20:25 PM PST 24 |
9236695326 ps |
| T1215 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.296302166 |
|
|
Mar 05 04:07:25 PM PST 24 |
Mar 05 05:26:32 PM PST 24 |
48289733922 ps |
| T1216 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.18235955 |
|
|
Mar 05 03:58:45 PM PST 24 |
Mar 05 04:49:10 PM PST 24 |
12382142236 ps |
| T1217 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.1785920527 |
|
|
Mar 05 03:59:15 PM PST 24 |
Mar 05 04:48:42 PM PST 24 |
30153000440 ps |
| T1218 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1394969974 |
|
|
Mar 05 03:49:18 PM PST 24 |
Mar 05 04:57:27 PM PST 24 |
23245158058 ps |
| T687 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.1769426560 |
|
|
Mar 05 04:20:35 PM PST 24 |
Mar 05 04:31:58 PM PST 24 |
5321837400 ps |
| T269 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.492301299 |
|
|
Mar 05 04:20:23 PM PST 24 |
Mar 05 04:26:54 PM PST 24 |
4080599398 ps |
| T1219 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3949727567 |
|
|
Mar 05 04:11:42 PM PST 24 |
Mar 05 04:35:13 PM PST 24 |
9410536118 ps |
| T1220 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.460107224 |
|
|
Mar 05 03:50:30 PM PST 24 |
Mar 05 03:54:16 PM PST 24 |
2773834752 ps |
| T1221 |
/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.28086479 |
|
|
Mar 05 04:17:59 PM PST 24 |
Mar 05 05:02:07 PM PST 24 |
13845376406 ps |
| T1222 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1425372205 |
|
|
Mar 05 03:49:15 PM PST 24 |
Mar 05 04:10:25 PM PST 24 |
6028937367 ps |
| T334 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.656698952 |
|
|
Mar 05 04:17:32 PM PST 24 |
Mar 05 04:34:17 PM PST 24 |
6680175582 ps |
| T1223 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1388087174 |
|
|
Mar 05 04:16:51 PM PST 24 |
Mar 05 04:31:07 PM PST 24 |
5806411062 ps |
| T1224 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2304802879 |
|
|
Mar 05 03:50:58 PM PST 24 |
Mar 05 03:59:25 PM PST 24 |
5231191224 ps |
| T1225 |
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.562671864 |
|
|
Mar 05 04:26:14 PM PST 24 |
Mar 05 04:32:26 PM PST 24 |
3782293804 ps |
| T649 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2548887536 |
|
|
Mar 05 04:09:00 PM PST 24 |
Mar 05 05:15:02 PM PST 24 |
20869649715 ps |
| T1226 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.917924790 |
|
|
Mar 05 03:55:05 PM PST 24 |
Mar 05 04:09:09 PM PST 24 |
5407132520 ps |
| T1227 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.76271580 |
|
|
Mar 05 04:17:44 PM PST 24 |
Mar 05 04:58:07 PM PST 24 |
14573450334 ps |
| T1228 |
/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.260639466 |
|
|
Mar 05 04:07:05 PM PST 24 |
Mar 05 04:18:09 PM PST 24 |
5140165442 ps |
| T1229 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.282324297 |
|
|
Mar 05 03:57:47 PM PST 24 |
Mar 05 04:21:54 PM PST 24 |
7738570059 ps |
| T53 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.2718465522 |
|
|
Mar 05 04:05:31 PM PST 24 |
Mar 05 04:09:10 PM PST 24 |
2808595000 ps |
| T740 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.861321824 |
|
|
Mar 05 04:24:39 PM PST 24 |
Mar 05 04:36:03 PM PST 24 |
4389806380 ps |
| T1230 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2026458403 |
|
|
Mar 05 03:50:55 PM PST 24 |
Mar 05 04:03:17 PM PST 24 |
4783724532 ps |
| T9 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3202509384 |
|
|
Mar 05 03:55:41 PM PST 24 |
Mar 05 04:00:33 PM PST 24 |
2583958928 ps |
| T1231 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2283486530 |
|
|
Mar 05 04:00:29 PM PST 24 |
Mar 05 04:26:10 PM PST 24 |
11060883880 ps |
| T1232 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1742469823 |
|
|
Mar 05 03:55:32 PM PST 24 |
Mar 05 04:12:16 PM PST 24 |
5777572158 ps |
| T1233 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2953335324 |
|
|
Mar 05 03:58:03 PM PST 24 |
Mar 05 04:05:05 PM PST 24 |
3273907780 ps |
| T1234 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.1776121958 |
|
|
Mar 05 04:14:25 PM PST 24 |
Mar 05 04:17:55 PM PST 24 |
2506472648 ps |
| T731 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.688012739 |
|
|
Mar 05 04:22:26 PM PST 24 |
Mar 05 04:31:45 PM PST 24 |
4428997968 ps |
| T1235 |
/workspace/coverage/default/2.chip_sw_flash_init.1052288062 |
|
|
Mar 05 04:06:32 PM PST 24 |
Mar 05 04:34:53 PM PST 24 |
15650948216 ps |
| T224 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2813449134 |
|
|
Mar 05 03:50:12 PM PST 24 |
Mar 05 03:58:52 PM PST 24 |
6567324760 ps |
| T1236 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3010587352 |
|
|
Mar 05 04:12:01 PM PST 24 |
Mar 05 04:22:04 PM PST 24 |
5398870890 ps |
| T716 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1398893103 |
|
|
Mar 05 04:21:26 PM PST 24 |
Mar 05 04:30:21 PM PST 24 |
3763630364 ps |
| T1237 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1111881926 |
|
|
Mar 05 03:52:22 PM PST 24 |
Mar 05 04:08:48 PM PST 24 |
8598686196 ps |
| T1238 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.224323645 |
|
|
Mar 05 03:57:34 PM PST 24 |
Mar 05 04:04:05 PM PST 24 |
4747564224 ps |
| T1239 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1520679318 |
|
|
Mar 05 03:56:05 PM PST 24 |
Mar 05 04:02:40 PM PST 24 |
3681962752 ps |
| T715 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.3322618778 |
|
|
Mar 05 04:18:10 PM PST 24 |
Mar 05 04:29:35 PM PST 24 |
5036049730 ps |
| T1240 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2475852048 |
|
|
Mar 05 03:59:03 PM PST 24 |
Mar 05 04:39:42 PM PST 24 |
21688742854 ps |
| T1241 |
/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.701397589 |
|
|
Mar 05 04:05:30 PM PST 24 |
Mar 05 04:10:51 PM PST 24 |
2797595056 ps |
| T1242 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.830258811 |
|
|
Mar 05 04:15:53 PM PST 24 |
Mar 05 04:30:06 PM PST 24 |
5315541790 ps |
| T76 |
/workspace/coverage/cover_reg_top/9.chip_tl_errors.2148685647 |
|
|
Mar 05 03:20:26 PM PST 24 |
Mar 05 03:24:41 PM PST 24 |
3777402920 ps |
| T77 |
/workspace/coverage/cover_reg_top/51.xbar_stress_all.1562431045 |
|
|
Mar 05 03:33:11 PM PST 24 |
Mar 05 03:36:15 PM PST 24 |
2115351261 ps |
| T78 |
/workspace/coverage/cover_reg_top/7.chip_tl_errors.3922599629 |
|
|
Mar 05 03:19:27 PM PST 24 |
Mar 05 03:26:08 PM PST 24 |
4406112143 ps |
| T81 |
/workspace/coverage/cover_reg_top/66.xbar_random.1126916351 |
|
|
Mar 05 03:36:11 PM PST 24 |
Mar 05 03:36:26 PM PST 24 |
129045566 ps |
| T82 |
/workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.3084764020 |
|
|
Mar 05 03:37:51 PM PST 24 |
Mar 05 03:43:42 PM PST 24 |
6861453909 ps |
| T230 |
/workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.2534391101 |
|
|
Mar 05 03:17:43 PM PST 24 |
Mar 05 03:17:55 PM PST 24 |
197304889 ps |
| T231 |
/workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.1496187886 |
|
|
Mar 05 03:28:24 PM PST 24 |
Mar 05 03:29:55 PM PST 24 |
4992967370 ps |
| T491 |
/workspace/coverage/cover_reg_top/42.xbar_stress_all.3727760742 |
|
|
Mar 05 03:31:18 PM PST 24 |
Mar 05 03:32:46 PM PST 24 |
2131921117 ps |
| T501 |
/workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.1661989626 |
|
|
Mar 05 03:35:22 PM PST 24 |
Mar 05 03:35:36 PM PST 24 |
92674195 ps |
| T820 |
/workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.3183133645 |
|
|
Mar 05 03:33:13 PM PST 24 |
Mar 05 03:33:19 PM PST 24 |
43167885 ps |
| T551 |
/workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.1011960142 |
|
|
Mar 05 03:35:09 PM PST 24 |
Mar 05 03:36:50 PM PST 24 |
5404696085 ps |
| T786 |
/workspace/coverage/cover_reg_top/24.xbar_access_same_device.3326941589 |
|
|
Mar 05 03:26:48 PM PST 24 |
Mar 05 03:26:55 PM PST 24 |
80255318 ps |
| T423 |
/workspace/coverage/cover_reg_top/60.xbar_error_random.2682391096 |
|
|
Mar 05 03:35:00 PM PST 24 |
Mar 05 03:35:15 PM PST 24 |
112123772 ps |
| T404 |
/workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.2144630850 |
|
|
Mar 05 03:29:53 PM PST 24 |
Mar 05 03:30:48 PM PST 24 |
543308956 ps |
| T582 |
/workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.967312219 |
|
|
Mar 05 03:30:56 PM PST 24 |
Mar 05 03:31:03 PM PST 24 |
52923100 ps |
| T662 |
/workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.2522885057 |
|
|
Mar 05 03:37:50 PM PST 24 |
Mar 05 03:39:30 PM PST 24 |
5153778216 ps |
| T492 |
/workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.3501312038 |
|
|
Mar 05 03:25:46 PM PST 24 |
Mar 05 03:25:52 PM PST 24 |
34810997 ps |
| T663 |
/workspace/coverage/cover_reg_top/36.xbar_smoke.3567364459 |
|
|
Mar 05 03:29:55 PM PST 24 |
Mar 05 03:30:01 PM PST 24 |
118927903 ps |
| T512 |
/workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.3716534166 |
|
|
Mar 05 03:34:39 PM PST 24 |
Mar 05 03:39:48 PM PST 24 |
18116286733 ps |
| T566 |
/workspace/coverage/cover_reg_top/60.xbar_random.936045826 |
|
|
Mar 05 03:34:53 PM PST 24 |
Mar 05 03:35:01 PM PST 24 |
114790053 ps |
| T493 |
/workspace/coverage/cover_reg_top/79.xbar_random.838462265 |
|
|
Mar 05 03:38:37 PM PST 24 |
Mar 05 03:39:13 PM PST 24 |
375605439 ps |
| T496 |
/workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.602431440 |
|
|
Mar 05 03:40:00 PM PST 24 |
Mar 05 03:42:02 PM PST 24 |
7112685087 ps |
| T490 |
/workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.933373179 |
|
|
Mar 05 03:29:22 PM PST 24 |
Mar 05 03:34:50 PM PST 24 |
17326187837 ps |
| T424 |
/workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.2912318513 |
|
|
Mar 05 03:32:41 PM PST 24 |
Mar 05 03:35:54 PM PST 24 |
2576510382 ps |
| T494 |
/workspace/coverage/cover_reg_top/4.xbar_random.3529469026 |
|
|
Mar 05 03:18:02 PM PST 24 |
Mar 05 03:18:36 PM PST 24 |
366199903 ps |
| T529 |
/workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.1729802593 |
|
|
Mar 05 03:29:32 PM PST 24 |
Mar 05 03:30:42 PM PST 24 |
4508485041 ps |
| T396 |
/workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.4023839607 |
|
|
Mar 05 03:20:14 PM PST 24 |
Mar 05 03:21:11 PM PST 24 |
1402731480 ps |
| T399 |
/workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.4123687140 |
|
|
Mar 05 03:40:10 PM PST 24 |
Mar 05 03:42:57 PM PST 24 |
2907080818 ps |
| T540 |
/workspace/coverage/cover_reg_top/81.xbar_smoke.597912012 |
|
|
Mar 05 03:38:50 PM PST 24 |
Mar 05 03:38:57 PM PST 24 |
57291482 ps |
| T347 |
/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.125722907 |
|
|
Mar 05 03:14:58 PM PST 24 |
Mar 05 03:18:43 PM PST 24 |
5131671616 ps |
| T765 |
/workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.1748883920 |
|
|
Mar 05 03:40:00 PM PST 24 |
Mar 05 03:41:22 PM PST 24 |
7914536603 ps |
| T514 |
/workspace/coverage/cover_reg_top/97.xbar_smoke.3606450016 |
|
|
Mar 05 03:41:30 PM PST 24 |
Mar 05 03:41:36 PM PST 24 |
51795234 ps |
| T664 |
/workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.1905613179 |
|
|
Mar 05 03:29:24 PM PST 24 |
Mar 05 03:38:19 PM PST 24 |
32752922842 ps |
| T509 |
/workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.3530352517 |
|
|
Mar 05 03:33:48 PM PST 24 |
Mar 05 03:34:16 PM PST 24 |
294605797 ps |
| T519 |
/workspace/coverage/cover_reg_top/2.xbar_smoke.2946764474 |
|
|
Mar 05 03:16:21 PM PST 24 |
Mar 05 03:16:28 PM PST 24 |
43861262 ps |
| T425 |
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.263114743 |
|
|
Mar 05 03:23:22 PM PST 24 |
Mar 05 03:27:50 PM PST 24 |
4525068740 ps |
| T495 |
/workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.3898475501 |
|
|
Mar 05 03:29:39 PM PST 24 |
Mar 05 03:30:21 PM PST 24 |
980453779 ps |
| T1243 |
/workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.303518257 |
|
|
Mar 05 03:41:25 PM PST 24 |
Mar 05 03:41:31 PM PST 24 |
46971728 ps |
| T586 |
/workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.1867248748 |
|
|
Mar 05 03:26:26 PM PST 24 |
Mar 05 03:26:40 PM PST 24 |
115201800 ps |
| T474 |
/workspace/coverage/cover_reg_top/73.xbar_random.1548915857 |
|
|
Mar 05 03:37:21 PM PST 24 |
Mar 05 03:38:03 PM PST 24 |
479879266 ps |
| T525 |
/workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.3869171739 |
|
|
Mar 05 03:26:47 PM PST 24 |
Mar 05 03:26:54 PM PST 24 |
48744278 ps |
| T821 |
/workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.618299137 |
|
|
Mar 05 03:23:24 PM PST 24 |
Mar 05 03:24:33 PM PST 24 |
6937019711 ps |
| T562 |
/workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.4248140648 |
|
|
Mar 05 03:36:11 PM PST 24 |
Mar 05 03:37:29 PM PST 24 |
6886868634 ps |
| T537 |
/workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.3637115088 |
|
|
Mar 05 03:20:34 PM PST 24 |
Mar 05 03:21:58 PM PST 24 |
7888160635 ps |
| T604 |
/workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.4195534621 |
|
|
Mar 05 03:32:57 PM PST 24 |
Mar 05 03:43:25 PM PST 24 |
36779146012 ps |
| T645 |
/workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.1220305008 |
|
|
Mar 05 03:33:42 PM PST 24 |
Mar 05 03:34:29 PM PST 24 |
1205184856 ps |
| T570 |
/workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.2402709697 |
|
|
Mar 05 03:26:25 PM PST 24 |
Mar 05 03:26:31 PM PST 24 |
48867306 ps |
| T745 |
/workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.2382101415 |
|
|
Mar 05 03:33:42 PM PST 24 |
Mar 05 03:35:13 PM PST 24 |
4907641451 ps |
| T565 |
/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.2080753723 |
|
|
Mar 05 03:18:51 PM PST 24 |
Mar 05 03:20:26 PM PST 24 |
205745528 ps |
| T468 |
/workspace/coverage/cover_reg_top/11.xbar_random.1077899849 |
|
|
Mar 05 03:21:29 PM PST 24 |
Mar 05 03:22:51 PM PST 24 |
2089878505 ps |
| T403 |
/workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.460730656 |
|
|
Mar 05 03:38:19 PM PST 24 |
Mar 05 03:44:23 PM PST 24 |
2997265401 ps |
| T1244 |
/workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.736848025 |
|
|
Mar 05 03:32:01 PM PST 24 |
Mar 05 03:32:56 PM PST 24 |
3136255465 ps |
| T497 |
/workspace/coverage/cover_reg_top/15.chip_tl_errors.2435822414 |
|
|
Mar 05 03:23:24 PM PST 24 |
Mar 05 03:27:52 PM PST 24 |
3460174404 ps |
| T482 |
/workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.2798884304 |
|
|
Mar 05 03:27:56 PM PST 24 |
Mar 05 03:29:45 PM PST 24 |
9158010583 ps |
| T471 |
/workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.1863587366 |
|
|
Mar 05 03:33:05 PM PST 24 |
Mar 05 03:33:11 PM PST 24 |
48164599 ps |
| T502 |
/workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.2863259837 |
|
|
Mar 05 03:41:19 PM PST 24 |
Mar 05 03:41:36 PM PST 24 |
153648488 ps |