T1245 |
/workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.1260051853 |
|
|
Mar 05 03:26:48 PM PST 24 |
Mar 05 03:28:02 PM PST 24 |
7048014990 ps |
T539 |
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3505344257 |
|
|
Mar 05 03:22:31 PM PST 24 |
Mar 05 03:23:45 PM PST 24 |
6865706682 ps |
T550 |
/workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.1262473001 |
|
|
Mar 05 03:27:18 PM PST 24 |
Mar 05 03:28:59 PM PST 24 |
6113769769 ps |
T548 |
/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.4104659374 |
|
|
Mar 05 03:27:10 PM PST 24 |
Mar 05 03:33:36 PM PST 24 |
5378020052 ps |
T535 |
/workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.997230228 |
|
|
Mar 05 03:35:22 PM PST 24 |
Mar 05 03:36:56 PM PST 24 |
5586747303 ps |
T401 |
/workspace/coverage/cover_reg_top/67.xbar_stress_all.620120009 |
|
|
Mar 05 03:36:18 PM PST 24 |
Mar 05 03:43:04 PM PST 24 |
11908580952 ps |
T559 |
/workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.170744849 |
|
|
Mar 05 03:28:28 PM PST 24 |
Mar 05 03:29:36 PM PST 24 |
6551155239 ps |
T530 |
/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.788353826 |
|
|
Mar 05 03:31:36 PM PST 24 |
Mar 05 03:41:53 PM PST 24 |
12983797803 ps |
T769 |
/workspace/coverage/cover_reg_top/20.xbar_error_random.4155501110 |
|
|
Mar 05 03:25:31 PM PST 24 |
Mar 05 03:26:44 PM PST 24 |
1837075938 ps |
T451 |
/workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.2019815399 |
|
|
Mar 05 03:30:57 PM PST 24 |
Mar 05 03:31:50 PM PST 24 |
565319260 ps |
T405 |
/workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.120914619 |
|
|
Mar 05 03:36:32 PM PST 24 |
Mar 05 03:58:42 PM PST 24 |
77730039182 ps |
T499 |
/workspace/coverage/cover_reg_top/22.chip_tl_errors.995764103 |
|
|
Mar 05 03:26:01 PM PST 24 |
Mar 05 03:28:44 PM PST 24 |
2978899850 ps |
T556 |
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3059035499 |
|
|
Mar 05 03:15:40 PM PST 24 |
Mar 05 03:16:22 PM PST 24 |
2273865440 ps |
T755 |
/workspace/coverage/cover_reg_top/60.xbar_access_same_device.33532124 |
|
|
Mar 05 03:35:01 PM PST 24 |
Mar 05 03:35:47 PM PST 24 |
930546039 ps |
T534 |
/workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.1791942554 |
|
|
Mar 05 03:39:36 PM PST 24 |
Mar 05 03:49:13 PM PST 24 |
30672516689 ps |
T577 |
/workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.3600442136 |
|
|
Mar 05 03:32:17 PM PST 24 |
Mar 05 03:32:59 PM PST 24 |
1036828223 ps |
T1246 |
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.3351888671 |
|
|
Mar 05 03:14:42 PM PST 24 |
Mar 05 03:14:53 PM PST 24 |
72866179 ps |
T485 |
/workspace/coverage/cover_reg_top/35.xbar_random_large_delays.2267759804 |
|
|
Mar 05 03:29:45 PM PST 24 |
Mar 05 03:44:14 PM PST 24 |
77237416980 ps |
T567 |
/workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.1803963428 |
|
|
Mar 05 03:29:32 PM PST 24 |
Mar 05 03:31:18 PM PST 24 |
6150231847 ps |
T429 |
/workspace/coverage/cover_reg_top/6.xbar_random.3448718258 |
|
|
Mar 05 03:19:07 PM PST 24 |
Mar 05 03:20:12 PM PST 24 |
1722331292 ps |
T466 |
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3243694062 |
|
|
Mar 05 03:21:12 PM PST 24 |
Mar 05 03:27:07 PM PST 24 |
6779987009 ps |
T750 |
/workspace/coverage/cover_reg_top/65.xbar_access_same_device.3954683308 |
|
|
Mar 05 03:36:00 PM PST 24 |
Mar 05 03:37:36 PM PST 24 |
2209146479 ps |
T746 |
/workspace/coverage/cover_reg_top/96.xbar_access_same_device.1083965143 |
|
|
Mar 05 03:41:18 PM PST 24 |
Mar 05 03:42:33 PM PST 24 |
1548308919 ps |
T508 |
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.2308115859 |
|
|
Mar 05 03:22:39 PM PST 24 |
Mar 05 03:23:05 PM PST 24 |
206473689 ps |
T1247 |
/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.3878206144 |
|
|
Mar 05 03:31:20 PM PST 24 |
Mar 05 03:31:38 PM PST 24 |
52477711 ps |
T587 |
/workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.3526572132 |
|
|
Mar 05 03:32:29 PM PST 24 |
Mar 05 03:41:07 PM PST 24 |
4254354964 ps |
T527 |
/workspace/coverage/cover_reg_top/89.xbar_random_large_delays.1842493718 |
|
|
Mar 05 03:40:13 PM PST 24 |
Mar 05 03:43:48 PM PST 24 |
18402095431 ps |
T572 |
/workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.3489213714 |
|
|
Mar 05 03:32:00 PM PST 24 |
Mar 05 03:37:51 PM PST 24 |
21563064434 ps |
T437 |
/workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.3598507834 |
|
|
Mar 05 03:18:11 PM PST 24 |
Mar 05 03:34:33 PM PST 24 |
58269070147 ps |
T520 |
/workspace/coverage/cover_reg_top/30.xbar_smoke.222226693 |
|
|
Mar 05 03:28:24 PM PST 24 |
Mar 05 03:28:30 PM PST 24 |
52469439 ps |
T543 |
/workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.2291513637 |
|
|
Mar 05 03:24:33 PM PST 24 |
Mar 05 03:26:05 PM PST 24 |
8917039271 ps |
T533 |
/workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.3220416031 |
|
|
Mar 05 03:29:41 PM PST 24 |
Mar 05 03:30:13 PM PST 24 |
704084759 ps |
T1248 |
/workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.738486387 |
|
|
Mar 05 03:40:47 PM PST 24 |
Mar 05 03:42:12 PM PST 24 |
7494021285 ps |
T558 |
/workspace/coverage/cover_reg_top/1.xbar_random.726524988 |
|
|
Mar 05 03:15:37 PM PST 24 |
Mar 05 03:16:09 PM PST 24 |
796900660 ps |
T767 |
/workspace/coverage/cover_reg_top/40.xbar_access_same_device.2739086433 |
|
|
Mar 05 03:30:51 PM PST 24 |
Mar 05 03:30:58 PM PST 24 |
73048925 ps |
T513 |
/workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.2430030196 |
|
|
Mar 05 03:39:52 PM PST 24 |
Mar 05 03:43:58 PM PST 24 |
4718080234 ps |
T1249 |
/workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.3549202662 |
|
|
Mar 05 03:30:41 PM PST 24 |
Mar 05 03:30:48 PM PST 24 |
47499429 ps |
T591 |
/workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.1596886031 |
|
|
Mar 05 03:33:26 PM PST 24 |
Mar 05 03:40:25 PM PST 24 |
10572122817 ps |
T1250 |
/workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.2625651713 |
|
|
Mar 05 03:38:24 PM PST 24 |
Mar 05 03:38:32 PM PST 24 |
45538611 ps |
T554 |
/workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.3916616180 |
|
|
Mar 05 03:36:11 PM PST 24 |
Mar 05 03:37:37 PM PST 24 |
5030615456 ps |
T747 |
/workspace/coverage/cover_reg_top/83.xbar_access_same_device.4008796757 |
|
|
Mar 05 03:39:03 PM PST 24 |
Mar 05 03:40:17 PM PST 24 |
1027881612 ps |
T592 |
/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.3255933583 |
|
|
Mar 05 03:29:54 PM PST 24 |
Mar 05 03:31:39 PM PST 24 |
1284560371 ps |
T1251 |
/workspace/coverage/cover_reg_top/38.xbar_smoke.532084995 |
|
|
Mar 05 03:30:15 PM PST 24 |
Mar 05 03:30:25 PM PST 24 |
215990507 ps |
T518 |
/workspace/coverage/cover_reg_top/74.xbar_same_source.737677724 |
|
|
Mar 05 03:37:43 PM PST 24 |
Mar 05 03:37:56 PM PST 24 |
132215607 ps |
T400 |
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2215518687 |
|
|
Mar 05 03:22:11 PM PST 24 |
Mar 05 03:42:23 PM PST 24 |
69951200086 ps |
T524 |
/workspace/coverage/cover_reg_top/86.xbar_same_source.3838070379 |
|
|
Mar 05 03:39:35 PM PST 24 |
Mar 05 03:39:46 PM PST 24 |
87468115 ps |
T1252 |
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.3570110843 |
|
|
Mar 05 03:15:06 PM PST 24 |
Mar 05 03:22:20 PM PST 24 |
5407844486 ps |
T588 |
/workspace/coverage/cover_reg_top/57.xbar_error_random.3172359951 |
|
|
Mar 05 03:34:21 PM PST 24 |
Mar 05 03:35:40 PM PST 24 |
2164681128 ps |
T458 |
/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.2437761315 |
|
|
Mar 05 03:24:55 PM PST 24 |
Mar 05 03:36:48 PM PST 24 |
12578655148 ps |
T553 |
/workspace/coverage/cover_reg_top/58.xbar_same_source.3981855695 |
|
|
Mar 05 03:34:39 PM PST 24 |
Mar 05 03:34:52 PM PST 24 |
328972676 ps |
T430 |
/workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.208978051 |
|
|
Mar 05 03:37:13 PM PST 24 |
Mar 05 03:43:08 PM PST 24 |
6922900514 ps |
T402 |
/workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.437846195 |
|
|
Mar 05 03:41:41 PM PST 24 |
Mar 05 03:56:50 PM PST 24 |
8429495051 ps |
T1253 |
/workspace/coverage/cover_reg_top/23.xbar_error_random.304843327 |
|
|
Mar 05 03:26:38 PM PST 24 |
Mar 05 03:27:46 PM PST 24 |
2065162631 ps |
T167 |
/workspace/coverage/cover_reg_top/15.chip_csr_rw.2386108166 |
|
|
Mar 05 03:23:36 PM PST 24 |
Mar 05 03:36:10 PM PST 24 |
6209565040 ps |
T576 |
/workspace/coverage/cover_reg_top/38.xbar_stress_all.323547961 |
|
|
Mar 05 03:30:24 PM PST 24 |
Mar 05 03:31:05 PM PST 24 |
313785680 ps |
T644 |
/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.2849327415 |
|
|
Mar 05 03:31:20 PM PST 24 |
Mar 05 03:35:08 PM PST 24 |
6994325748 ps |
T1254 |
/workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.2200345965 |
|
|
Mar 05 03:37:04 PM PST 24 |
Mar 05 03:38:42 PM PST 24 |
5444497775 ps |
T1255 |
/workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.1943818856 |
|
|
Mar 05 03:37:04 PM PST 24 |
Mar 05 03:38:41 PM PST 24 |
5461025971 ps |
T528 |
/workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.2622704112 |
|
|
Mar 05 03:41:26 PM PST 24 |
Mar 05 03:42:10 PM PST 24 |
483449417 ps |
T1256 |
/workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.762252492 |
|
|
Mar 05 03:39:10 PM PST 24 |
Mar 05 03:40:16 PM PST 24 |
3997203803 ps |
T440 |
/workspace/coverage/cover_reg_top/62.xbar_same_source.2154522638 |
|
|
Mar 05 03:35:22 PM PST 24 |
Mar 05 03:36:01 PM PST 24 |
503668404 ps |
T538 |
/workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.2740543110 |
|
|
Mar 05 03:38:46 PM PST 24 |
Mar 05 03:40:16 PM PST 24 |
7830838481 ps |
T454 |
/workspace/coverage/cover_reg_top/83.xbar_random_large_delays.1785150236 |
|
|
Mar 05 03:39:03 PM PST 24 |
Mar 05 03:56:10 PM PST 24 |
83830954465 ps |
T569 |
/workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.2270428360 |
|
|
Mar 05 03:29:46 PM PST 24 |
Mar 05 03:45:54 PM PST 24 |
54999102021 ps |
T433 |
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3147379485 |
|
|
Mar 05 03:21:26 PM PST 24 |
Mar 05 03:35:45 PM PST 24 |
79923992927 ps |
T1257 |
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3844398049 |
|
|
Mar 05 03:22:03 PM PST 24 |
Mar 05 03:22:09 PM PST 24 |
39900263 ps |
T753 |
/workspace/coverage/cover_reg_top/52.xbar_access_same_device.2411927029 |
|
|
Mar 05 03:33:20 PM PST 24 |
Mar 05 03:35:04 PM PST 24 |
2241115215 ps |
T431 |
/workspace/coverage/cover_reg_top/19.xbar_random.1359599675 |
|
|
Mar 05 03:25:02 PM PST 24 |
Mar 05 03:25:26 PM PST 24 |
219563308 ps |
T751 |
/workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.132585882 |
|
|
Mar 05 03:41:05 PM PST 24 |
Mar 05 03:50:14 PM PST 24 |
28702941974 ps |
T1258 |
/workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.626289830 |
|
|
Mar 05 03:36:41 PM PST 24 |
Mar 05 03:37:17 PM PST 24 |
788172915 ps |
T541 |
/workspace/coverage/cover_reg_top/56.xbar_random.4161418270 |
|
|
Mar 05 03:34:05 PM PST 24 |
Mar 05 03:34:35 PM PST 24 |
647340724 ps |
T462 |
/workspace/coverage/cover_reg_top/2.xbar_stress_all.1878912930 |
|
|
Mar 05 03:16:50 PM PST 24 |
Mar 05 03:18:23 PM PST 24 |
1100030473 ps |
T1259 |
/workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.1719306417 |
|
|
Mar 05 03:19:58 PM PST 24 |
Mar 05 03:20:05 PM PST 24 |
52680588 ps |
T438 |
/workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.2691081800 |
|
|
Mar 05 03:26:37 PM PST 24 |
Mar 05 03:39:49 PM PST 24 |
44422883594 ps |
T168 |
/workspace/coverage/cover_reg_top/17.chip_csr_rw.3465486815 |
|
|
Mar 05 03:24:25 PM PST 24 |
Mar 05 03:36:04 PM PST 24 |
5392764415 ps |
T748 |
/workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.1665529706 |
|
|
Mar 05 03:32:01 PM PST 24 |
Mar 05 03:59:51 PM PST 24 |
88238178714 ps |
T547 |
/workspace/coverage/cover_reg_top/43.xbar_same_source.4266405111 |
|
|
Mar 05 03:31:46 PM PST 24 |
Mar 05 03:32:13 PM PST 24 |
376784548 ps |
T453 |
/workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.2180588709 |
|
|
Mar 05 03:28:53 PM PST 24 |
Mar 05 03:58:37 PM PST 24 |
97808392886 ps |
T581 |
/workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.441612971 |
|
|
Mar 05 03:40:09 PM PST 24 |
Mar 05 03:40:27 PM PST 24 |
163075244 ps |
T432 |
/workspace/coverage/cover_reg_top/68.xbar_stress_all.2086565051 |
|
|
Mar 05 03:36:36 PM PST 24 |
Mar 05 03:45:58 PM PST 24 |
13533910857 ps |
T515 |
/workspace/coverage/cover_reg_top/93.xbar_random.2192065627 |
|
|
Mar 05 03:40:47 PM PST 24 |
Mar 05 03:42:17 PM PST 24 |
2122209429 ps |
T1260 |
/workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.2344331746 |
|
|
Mar 05 03:33:02 PM PST 24 |
Mar 05 03:34:24 PM PST 24 |
4195331766 ps |
T1261 |
/workspace/coverage/cover_reg_top/8.xbar_smoke.107982542 |
|
|
Mar 05 03:19:50 PM PST 24 |
Mar 05 03:19:57 PM PST 24 |
50606387 ps |
T1262 |
/workspace/coverage/cover_reg_top/35.xbar_error_random.880923502 |
|
|
Mar 05 03:29:45 PM PST 24 |
Mar 05 03:30:11 PM PST 24 |
686518449 ps |
T760 |
/workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.3995657230 |
|
|
Mar 05 03:37:19 PM PST 24 |
Mar 05 03:49:07 PM PST 24 |
39222236093 ps |
T504 |
/workspace/coverage/cover_reg_top/27.chip_tl_errors.1734607320 |
|
|
Mar 05 03:27:39 PM PST 24 |
Mar 05 03:31:29 PM PST 24 |
3786758540 ps |
T757 |
/workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.3634073907 |
|
|
Mar 05 03:30:12 PM PST 24 |
Mar 05 03:50:44 PM PST 24 |
65861534675 ps |
T560 |
/workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.2917789120 |
|
|
Mar 05 03:33:35 PM PST 24 |
Mar 05 03:50:01 PM PST 24 |
54694673455 ps |
T1263 |
/workspace/coverage/cover_reg_top/87.xbar_error_random.3338308866 |
|
|
Mar 05 03:39:41 PM PST 24 |
Mar 05 03:39:59 PM PST 24 |
213155540 ps |
T1264 |
/workspace/coverage/cover_reg_top/98.xbar_error_random.2094109963 |
|
|
Mar 05 03:41:43 PM PST 24 |
Mar 05 03:42:24 PM PST 24 |
1444136242 ps |
T1265 |
/workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.1186467412 |
|
|
Mar 05 03:34:38 PM PST 24 |
Mar 05 03:34:47 PM PST 24 |
55143865 ps |
T798 |
/workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.1451649094 |
|
|
Mar 05 03:20:13 PM PST 24 |
Mar 05 03:22:00 PM PST 24 |
214109134 ps |
T434 |
/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.1411119456 |
|
|
Mar 05 03:40:02 PM PST 24 |
Mar 05 03:57:27 PM PST 24 |
15739380300 ps |
T169 |
/workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.1476992201 |
|
|
Mar 05 03:16:01 PM PST 24 |
Mar 05 04:20:45 PM PST 24 |
28450365136 ps |
T589 |
/workspace/coverage/cover_reg_top/94.xbar_error_random.4275849773 |
|
|
Mar 05 03:41:06 PM PST 24 |
Mar 05 03:41:30 PM PST 24 |
304443216 ps |
T1266 |
/workspace/coverage/cover_reg_top/71.xbar_random.2183628139 |
|
|
Mar 05 03:37:04 PM PST 24 |
Mar 05 03:37:15 PM PST 24 |
170106262 ps |
T1267 |
/workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.3310393592 |
|
|
Mar 05 03:36:00 PM PST 24 |
Mar 05 03:36:23 PM PST 24 |
183788289 ps |
T1268 |
/workspace/coverage/cover_reg_top/5.xbar_random.3509519726 |
|
|
Mar 05 03:18:34 PM PST 24 |
Mar 05 03:18:40 PM PST 24 |
24075420 ps |
T1269 |
/workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.3159367473 |
|
|
Mar 05 03:35:23 PM PST 24 |
Mar 05 03:35:59 PM PST 24 |
869510120 ps |
T442 |
/workspace/coverage/cover_reg_top/73.xbar_stress_all.3544092792 |
|
|
Mar 05 03:37:31 PM PST 24 |
Mar 05 03:41:05 PM PST 24 |
2706031089 ps |
T1270 |
/workspace/coverage/cover_reg_top/84.xbar_random.1209861908 |
|
|
Mar 05 03:39:14 PM PST 24 |
Mar 05 03:39:24 PM PST 24 |
190074399 ps |
T578 |
/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.681854121 |
|
|
Mar 05 03:40:05 PM PST 24 |
Mar 05 03:49:01 PM PST 24 |
6511680839 ps |
T531 |
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.362004309 |
|
|
Mar 05 03:15:21 PM PST 24 |
Mar 05 03:17:10 PM PST 24 |
10133806678 ps |
T1271 |
/workspace/coverage/cover_reg_top/55.xbar_same_source.1201533371 |
|
|
Mar 05 03:33:57 PM PST 24 |
Mar 05 03:34:05 PM PST 24 |
154470219 ps |
T564 |
/workspace/coverage/cover_reg_top/34.xbar_random.1093025156 |
|
|
Mar 05 03:29:31 PM PST 24 |
Mar 05 03:29:53 PM PST 24 |
209326911 ps |
T787 |
/workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.1022903168 |
|
|
Mar 05 03:37:03 PM PST 24 |
Mar 05 03:43:21 PM PST 24 |
3403535364 ps |
T500 |
/workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.79389945 |
|
|
Mar 05 03:17:25 PM PST 24 |
Mar 05 03:28:47 PM PST 24 |
37718413033 ps |
T1272 |
/workspace/coverage/cover_reg_top/68.xbar_smoke.2217792398 |
|
|
Mar 05 03:36:27 PM PST 24 |
Mar 05 03:36:37 PM PST 24 |
233377593 ps |
T561 |
/workspace/coverage/cover_reg_top/85.xbar_same_source.1869887514 |
|
|
Mar 05 03:39:30 PM PST 24 |
Mar 05 03:40:11 PM PST 24 |
531793173 ps |
T1273 |
/workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.2780962206 |
|
|
Mar 05 03:29:06 PM PST 24 |
Mar 05 03:29:13 PM PST 24 |
54283779 ps |
T516 |
/workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.2365898716 |
|
|
Mar 05 03:38:39 PM PST 24 |
Mar 05 03:56:14 PM PST 24 |
56062975245 ps |
T1274 |
/workspace/coverage/cover_reg_top/49.xbar_smoke.1019435117 |
|
|
Mar 05 03:32:48 PM PST 24 |
Mar 05 03:32:57 PM PST 24 |
181122853 ps |
T484 |
/workspace/coverage/cover_reg_top/93.xbar_random_large_delays.3573487282 |
|
|
Mar 05 03:40:47 PM PST 24 |
Mar 05 03:53:11 PM PST 24 |
72786370539 ps |
T1275 |
/workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.4121337120 |
|
|
Mar 05 03:27:10 PM PST 24 |
Mar 05 03:27:21 PM PST 24 |
86665392 ps |
T1276 |
/workspace/coverage/cover_reg_top/44.xbar_random.3303761777 |
|
|
Mar 05 03:31:36 PM PST 24 |
Mar 05 03:31:42 PM PST 24 |
33091378 ps |
T761 |
/workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.1158152302 |
|
|
Mar 05 03:33:43 PM PST 24 |
Mar 05 03:36:46 PM PST 24 |
10777293996 ps |
T1277 |
/workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.2290598778 |
|
|
Mar 05 03:40:55 PM PST 24 |
Mar 05 03:41:52 PM PST 24 |
617769983 ps |
T1278 |
/workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.3819017107 |
|
|
Mar 05 03:40:22 PM PST 24 |
Mar 05 03:40:28 PM PST 24 |
42226138 ps |
T1279 |
/workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.409080500 |
|
|
Mar 05 03:18:45 PM PST 24 |
Mar 05 03:18:52 PM PST 24 |
93818426 ps |
T483 |
/workspace/coverage/cover_reg_top/76.xbar_random.2043059327 |
|
|
Mar 05 03:37:58 PM PST 24 |
Mar 05 03:38:44 PM PST 24 |
1324896383 ps |
T1280 |
/workspace/coverage/cover_reg_top/8.xbar_error_random.3457648478 |
|
|
Mar 05 03:20:05 PM PST 24 |
Mar 05 03:20:31 PM PST 24 |
641567552 ps |
T1281 |
/workspace/coverage/cover_reg_top/34.xbar_smoke.3569982424 |
|
|
Mar 05 03:29:32 PM PST 24 |
Mar 05 03:29:43 PM PST 24 |
227169607 ps |
T768 |
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.4275344834 |
|
|
Mar 05 03:21:05 PM PST 24 |
Mar 05 03:22:06 PM PST 24 |
1530285573 ps |
T1282 |
/workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.3383742150 |
|
|
Mar 05 03:39:03 PM PST 24 |
Mar 05 03:39:31 PM PST 24 |
520740920 ps |
T526 |
/workspace/coverage/cover_reg_top/12.xbar_stress_all.4226734972 |
|
|
Mar 05 03:22:17 PM PST 24 |
Mar 05 03:26:38 PM PST 24 |
7160555644 ps |
T1283 |
/workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.952214941 |
|
|
Mar 05 03:40:56 PM PST 24 |
Mar 05 03:42:01 PM PST 24 |
1411551850 ps |
T1284 |
/workspace/coverage/cover_reg_top/43.xbar_smoke.1175591556 |
|
|
Mar 05 03:31:29 PM PST 24 |
Mar 05 03:31:38 PM PST 24 |
188681840 ps |
T1285 |
/workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.3869395931 |
|
|
Mar 05 03:40:34 PM PST 24 |
Mar 05 03:42:37 PM PST 24 |
6853018365 ps |
T447 |
/workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.2004464061 |
|
|
Mar 05 03:28:20 PM PST 24 |
Mar 05 03:50:42 PM PST 24 |
28317749890 ps |
T1286 |
/workspace/coverage/cover_reg_top/28.xbar_smoke.3172206742 |
|
|
Mar 05 03:27:54 PM PST 24 |
Mar 05 03:28:02 PM PST 24 |
114123539 ps |
T584 |
/workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.4045732942 |
|
|
Mar 05 03:39:37 PM PST 24 |
Mar 05 03:40:18 PM PST 24 |
382766661 ps |
T1287 |
/workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.3774762283 |
|
|
Mar 05 03:23:24 PM PST 24 |
Mar 05 03:23:29 PM PST 24 |
44854936 ps |
T1288 |
/workspace/coverage/cover_reg_top/85.xbar_error_random.2356644427 |
|
|
Mar 05 03:39:27 PM PST 24 |
Mar 05 03:39:47 PM PST 24 |
466429702 ps |
T456 |
/workspace/coverage/cover_reg_top/50.xbar_stress_all.3993172247 |
|
|
Mar 05 03:32:56 PM PST 24 |
Mar 05 03:37:22 PM PST 24 |
6990379198 ps |
T1289 |
/workspace/coverage/cover_reg_top/0.xbar_random.3946248090 |
|
|
Mar 05 03:14:28 PM PST 24 |
Mar 05 03:14:36 PM PST 24 |
56656739 ps |
T756 |
/workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.729770868 |
|
|
Mar 05 03:26:58 PM PST 24 |
Mar 05 03:58:55 PM PST 24 |
106986602499 ps |
T805 |
/workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.120500511 |
|
|
Mar 05 03:36:35 PM PST 24 |
Mar 05 03:36:59 PM PST 24 |
111506251 ps |
T1290 |
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.2491421022 |
|
|
Mar 05 03:21:33 PM PST 24 |
Mar 05 03:22:07 PM PST 24 |
255908316 ps |
T1291 |
/workspace/coverage/cover_reg_top/59.xbar_error_random.2256043739 |
|
|
Mar 05 03:34:44 PM PST 24 |
Mar 05 03:35:21 PM PST 24 |
1046210868 ps |
T1292 |
/workspace/coverage/cover_reg_top/48.xbar_error_random.2502414612 |
|
|
Mar 05 03:32:36 PM PST 24 |
Mar 05 03:33:05 PM PST 24 |
321029956 ps |
T1293 |
/workspace/coverage/cover_reg_top/56.xbar_error_random.1374682674 |
|
|
Mar 05 03:34:11 PM PST 24 |
Mar 05 03:34:51 PM PST 24 |
1036997460 ps |
T793 |
/workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.3234669119 |
|
|
Mar 05 03:35:09 PM PST 24 |
Mar 05 03:38:16 PM PST 24 |
568279415 ps |
T1294 |
/workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.3315005584 |
|
|
Mar 05 03:38:50 PM PST 24 |
Mar 05 03:49:45 PM PST 24 |
36733391393 ps |
T772 |
/workspace/coverage/cover_reg_top/73.xbar_access_same_device.2689597862 |
|
|
Mar 05 03:37:15 PM PST 24 |
Mar 05 03:37:43 PM PST 24 |
641921481 ps |
T749 |
/workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.956290791 |
|
|
Mar 05 03:39:10 PM PST 24 |
Mar 05 03:51:29 PM PST 24 |
41669954925 ps |
T1295 |
/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.1233020027 |
|
|
Mar 05 03:30:25 PM PST 24 |
Mar 05 03:31:10 PM PST 24 |
519203579 ps |
T521 |
/workspace/coverage/cover_reg_top/15.xbar_random_large_delays.3063457657 |
|
|
Mar 05 03:23:31 PM PST 24 |
Mar 05 03:43:44 PM PST 24 |
119410489496 ps |
T1296 |
/workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.3095421285 |
|
|
Mar 05 03:27:09 PM PST 24 |
Mar 05 03:27:53 PM PST 24 |
1101017265 ps |
T532 |
/workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.1422671914 |
|
|
Mar 05 03:23:55 PM PST 24 |
Mar 05 03:28:45 PM PST 24 |
16317650244 ps |
T777 |
/workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.988069284 |
|
|
Mar 05 03:40:49 PM PST 24 |
Mar 05 03:47:54 PM PST 24 |
7814158280 ps |
T350 |
/workspace/coverage/cover_reg_top/7.chip_csr_rw.4227626727 |
|
|
Mar 05 03:19:44 PM PST 24 |
Mar 05 03:26:22 PM PST 24 |
4395992665 ps |
T1297 |
/workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.883696163 |
|
|
Mar 05 03:25:17 PM PST 24 |
Mar 05 03:25:24 PM PST 24 |
60452896 ps |
T460 |
/workspace/coverage/cover_reg_top/39.xbar_random_large_delays.127544685 |
|
|
Mar 05 03:30:34 PM PST 24 |
Mar 05 03:47:50 PM PST 24 |
93349437162 ps |
T779 |
/workspace/coverage/cover_reg_top/89.xbar_access_same_device.3327615892 |
|
|
Mar 05 03:40:06 PM PST 24 |
Mar 05 03:42:05 PM PST 24 |
2917675932 ps |
T1298 |
/workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.974155344 |
|
|
Mar 05 03:36:11 PM PST 24 |
Mar 05 03:36:17 PM PST 24 |
49250031 ps |
T473 |
/workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.1149639862 |
|
|
Mar 05 03:30:44 PM PST 24 |
Mar 05 03:32:47 PM PST 24 |
10655973779 ps |
T1299 |
/workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.2592891552 |
|
|
Mar 05 03:31:45 PM PST 24 |
Mar 05 03:34:43 PM PST 24 |
4896072110 ps |
T773 |
/workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.3719060722 |
|
|
Mar 05 03:38:06 PM PST 24 |
Mar 05 03:50:02 PM PST 24 |
39437025163 ps |
T1300 |
/workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.3017346302 |
|
|
Mar 05 03:35:16 PM PST 24 |
Mar 05 03:35:57 PM PST 24 |
877061652 ps |
T762 |
/workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.582502682 |
|
|
Mar 05 03:38:02 PM PST 24 |
Mar 05 03:40:50 PM PST 24 |
2391312313 ps |
T1301 |
/workspace/coverage/cover_reg_top/75.xbar_smoke.3911574151 |
|
|
Mar 05 03:37:58 PM PST 24 |
Mar 05 03:38:07 PM PST 24 |
208749770 ps |
T763 |
/workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.4227912558 |
|
|
Mar 05 03:32:48 PM PST 24 |
Mar 05 03:40:25 PM PST 24 |
11248768691 ps |
T511 |
/workspace/coverage/cover_reg_top/15.xbar_stress_all.1105234081 |
|
|
Mar 05 03:23:36 PM PST 24 |
Mar 05 03:25:49 PM PST 24 |
1200118690 ps |
T1302 |
/workspace/coverage/cover_reg_top/36.xbar_error_random.1454648783 |
|
|
Mar 05 03:30:07 PM PST 24 |
Mar 05 03:31:04 PM PST 24 |
1418384371 ps |
T441 |
/workspace/coverage/cover_reg_top/95.xbar_stress_all.562784489 |
|
|
Mar 05 03:41:10 PM PST 24 |
Mar 05 03:43:53 PM PST 24 |
1957425849 ps |
T552 |
/workspace/coverage/cover_reg_top/24.xbar_random.463185453 |
|
|
Mar 05 03:26:47 PM PST 24 |
Mar 05 03:27:15 PM PST 24 |
279819023 ps |
T568 |
/workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.3013744687 |
|
|
Mar 05 03:19:08 PM PST 24 |
Mar 05 03:24:32 PM PST 24 |
17445712218 ps |
T1303 |
/workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.2469192178 |
|
|
Mar 05 03:35:33 PM PST 24 |
Mar 05 03:35:48 PM PST 24 |
33563613 ps |
T1304 |
/workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.1562166930 |
|
|
Mar 05 03:36:28 PM PST 24 |
Mar 05 03:36:34 PM PST 24 |
29090064 ps |
T754 |
/workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.2394606597 |
|
|
Mar 05 03:37:50 PM PST 24 |
Mar 05 03:43:51 PM PST 24 |
10183174694 ps |
T435 |
/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.1983160331 |
|
|
Mar 05 03:30:26 PM PST 24 |
Mar 05 03:44:45 PM PST 24 |
16988947956 ps |
T1305 |
/workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.2628291337 |
|
|
Mar 05 03:33:04 PM PST 24 |
Mar 05 03:34:56 PM PST 24 |
9658181688 ps |
T1306 |
/workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.3660429101 |
|
|
Mar 05 03:30:17 PM PST 24 |
Mar 05 03:30:28 PM PST 24 |
191284526 ps |
T1307 |
/workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.2365738319 |
|
|
Mar 05 03:19:58 PM PST 24 |
Mar 05 03:21:33 PM PST 24 |
8700933589 ps |
T542 |
/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.969502097 |
|
|
Mar 05 03:26:25 PM PST 24 |
Mar 05 03:28:12 PM PST 24 |
270300748 ps |
T1308 |
/workspace/coverage/cover_reg_top/38.xbar_random_large_delays.3733751895 |
|
|
Mar 05 03:30:19 PM PST 24 |
Mar 05 03:34:51 PM PST 24 |
23392846520 ps |
T505 |
/workspace/coverage/cover_reg_top/3.chip_tl_errors.2927007397 |
|
|
Mar 05 03:17:10 PM PST 24 |
Mar 05 03:19:13 PM PST 24 |
2499897489 ps |
T507 |
/workspace/coverage/cover_reg_top/28.chip_tl_errors.428315607 |
|
|
Mar 05 03:27:57 PM PST 24 |
Mar 05 03:32:59 PM PST 24 |
4011961005 ps |
T806 |
/workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.189533301 |
|
|
Mar 05 03:41:13 PM PST 24 |
Mar 05 03:43:45 PM PST 24 |
354015217 ps |
T780 |
/workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.3109428707 |
|
|
Mar 05 03:23:55 PM PST 24 |
Mar 05 03:53:13 PM PST 24 |
88510482881 ps |
T774 |
/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.2345376198 |
|
|
Mar 05 03:28:49 PM PST 24 |
Mar 05 03:33:37 PM PST 24 |
3717357492 ps |
T788 |
/workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.3128898608 |
|
|
Mar 05 03:32:07 PM PST 24 |
Mar 05 03:37:35 PM PST 24 |
8894271048 ps |
T1309 |
/workspace/coverage/cover_reg_top/20.xbar_random.3741995190 |
|
|
Mar 05 03:25:25 PM PST 24 |
Mar 05 03:26:01 PM PST 24 |
806841544 ps |
T1310 |
/workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.2447650908 |
|
|
Mar 05 03:37:59 PM PST 24 |
Mar 05 03:38:44 PM PST 24 |
238444864 ps |
T1311 |
/workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.526536062 |
|
|
Mar 05 03:40:30 PM PST 24 |
Mar 05 03:40:36 PM PST 24 |
50997285 ps |
T1312 |
/workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.2774644487 |
|
|
Mar 05 03:38:56 PM PST 24 |
Mar 05 03:40:23 PM PST 24 |
8386810235 ps |
T1313 |
/workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.1310246342 |
|
|
Mar 05 03:39:42 PM PST 24 |
Mar 05 03:40:14 PM PST 24 |
761313593 ps |
T1314 |
/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.2325067084 |
|
|
Mar 05 03:27:31 PM PST 24 |
Mar 05 03:30:02 PM PST 24 |
2004924101 ps |
T1315 |
/workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.3055559765 |
|
|
Mar 05 03:36:27 PM PST 24 |
Mar 05 03:43:32 PM PST 24 |
24492242679 ps |
T1316 |
/workspace/coverage/cover_reg_top/9.xbar_error_random.1716470695 |
|
|
Mar 05 03:20:41 PM PST 24 |
Mar 05 03:21:16 PM PST 24 |
1003472165 ps |
T796 |
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2502569232 |
|
|
Mar 05 03:14:50 PM PST 24 |
Mar 05 03:16:11 PM PST 24 |
197034612 ps |
T1317 |
/workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.352396597 |
|
|
Mar 05 03:32:36 PM PST 24 |
Mar 05 03:34:08 PM PST 24 |
5348799749 ps |
T1318 |
/workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.3760498348 |
|
|
Mar 05 03:31:00 PM PST 24 |
Mar 05 03:31:46 PM PST 24 |
154721406 ps |
T1319 |
/workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.2477274657 |
|
|
Mar 05 03:18:08 PM PST 24 |
Mar 05 03:19:54 PM PST 24 |
5788261248 ps |
T1320 |
/workspace/coverage/cover_reg_top/17.xbar_access_same_device.1969199914 |
|
|
Mar 05 03:24:19 PM PST 24 |
Mar 05 03:24:34 PM PST 24 |
127059137 ps |
T455 |
/workspace/coverage/cover_reg_top/74.xbar_random.1852857371 |
|
|
Mar 05 03:37:36 PM PST 24 |
Mar 05 03:37:49 PM PST 24 |
133126026 ps |
T1321 |
/workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.973319895 |
|
|
Mar 05 03:40:04 PM PST 24 |
Mar 05 03:41:20 PM PST 24 |
7464325367 ps |
T479 |
/workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.2146675485 |
|
|
Mar 05 03:38:01 PM PST 24 |
Mar 05 03:38:50 PM PST 24 |
558363611 ps |
T480 |
/workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.3088123949 |
|
|
Mar 05 03:32:14 PM PST 24 |
Mar 05 03:35:16 PM PST 24 |
11502127637 ps |
T1322 |
/workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.1165608594 |
|
|
Mar 05 03:34:53 PM PST 24 |
Mar 05 03:35:43 PM PST 24 |
4434372214 ps |
T1323 |
/workspace/coverage/cover_reg_top/37.xbar_error_random.2095673915 |
|
|
Mar 05 03:30:18 PM PST 24 |
Mar 05 03:31:31 PM PST 24 |
2342596818 ps |
T775 |
/workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.3459333163 |
|
|
Mar 05 03:29:32 PM PST 24 |
Mar 05 03:47:38 PM PST 24 |
61896723335 ps |
T348 |
/workspace/coverage/cover_reg_top/8.chip_csr_rw.552864211 |
|
|
Mar 05 03:20:20 PM PST 24 |
Mar 05 03:24:47 PM PST 24 |
4093763430 ps |
T1324 |
/workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.3243493202 |
|
|
Mar 05 03:37:52 PM PST 24 |
Mar 05 03:39:36 PM PST 24 |
9644172700 ps |
T475 |
/workspace/coverage/cover_reg_top/54.xbar_stress_all.2744547726 |
|
|
Mar 05 03:33:51 PM PST 24 |
Mar 05 03:38:09 PM PST 24 |
2764332347 ps |
T1325 |
/workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.4125189407 |
|
|
Mar 05 03:36:48 PM PST 24 |
Mar 05 03:38:35 PM PST 24 |
6042584636 ps |
T1326 |
/workspace/coverage/cover_reg_top/64.xbar_random.130362564 |
|
|
Mar 05 03:35:45 PM PST 24 |
Mar 05 03:36:47 PM PST 24 |
1740937841 ps |
T557 |
/workspace/coverage/cover_reg_top/48.xbar_stress_all.2372931575 |
|
|
Mar 05 03:32:39 PM PST 24 |
Mar 05 03:33:06 PM PST 24 |
388479080 ps |
T1327 |
/workspace/coverage/cover_reg_top/8.xbar_same_source.2888329442 |
|
|
Mar 05 03:20:07 PM PST 24 |
Mar 05 03:20:27 PM PST 24 |
214249469 ps |
T1328 |
/workspace/coverage/cover_reg_top/46.xbar_error_random.3852771174 |
|
|
Mar 05 03:32:04 PM PST 24 |
Mar 05 03:32:25 PM PST 24 |
203675192 ps |
T1329 |
/workspace/coverage/cover_reg_top/42.xbar_random.2267394569 |
|
|
Mar 05 03:31:12 PM PST 24 |
Mar 05 03:32:07 PM PST 24 |
1695852433 ps |
T778 |
/workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.3278903954 |
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Mar 05 03:29:45 PM PST 24 |
Mar 05 03:46:55 PM PST 24 |
56690507873 ps |
T1330 |
/workspace/coverage/cover_reg_top/79.xbar_smoke.1481839559 |
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|
Mar 05 03:38:25 PM PST 24 |
Mar 05 03:38:33 PM PST 24 |
48599082 ps |
T503 |
/workspace/coverage/cover_reg_top/25.chip_tl_errors.777483776 |
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Mar 05 03:27:01 PM PST 24 |
Mar 05 03:31:04 PM PST 24 |
3406121033 ps |
T467 |
/workspace/coverage/cover_reg_top/22.xbar_stress_all.576390746 |
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Mar 05 03:26:30 PM PST 24 |
Mar 05 03:32:17 PM PST 24 |
9482742930 ps |
T522 |
/workspace/coverage/cover_reg_top/59.xbar_same_source.1371462743 |
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Mar 05 03:34:46 PM PST 24 |
Mar 05 03:35:58 PM PST 24 |
2343441825 ps |
T1331 |
/workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.1203314595 |
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Mar 05 03:25:56 PM PST 24 |
Mar 05 03:26:08 PM PST 24 |
87148285 ps |
T1332 |
/workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.3747488799 |
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Mar 05 03:32:49 PM PST 24 |
Mar 05 03:33:04 PM PST 24 |
300207440 ps |
T1333 |
/workspace/coverage/cover_reg_top/91.xbar_random_large_delays.758837807 |
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Mar 05 03:40:34 PM PST 24 |
Mar 05 03:48:41 PM PST 24 |
43175132504 ps |
T478 |
/workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.2116257854 |
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Mar 05 03:40:47 PM PST 24 |
Mar 05 03:48:34 PM PST 24 |
3929513977 ps |
T1334 |
/workspace/coverage/cover_reg_top/63.xbar_random_large_delays.2627782609 |
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Mar 05 03:35:38 PM PST 24 |
Mar 05 03:36:54 PM PST 24 |
6982989214 ps |
T1335 |
/workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.2988617610 |
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Mar 05 03:39:23 PM PST 24 |
Mar 05 03:47:30 PM PST 24 |
14220921637 ps |
T436 |
/workspace/coverage/cover_reg_top/33.xbar_stress_all.3517873607 |
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Mar 05 03:29:23 PM PST 24 |
Mar 05 03:41:44 PM PST 24 |
18132066360 ps |
T789 |
/workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.1104161025 |
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Mar 05 03:20:50 PM PST 24 |
Mar 05 03:23:21 PM PST 24 |
3372500832 ps |
T1336 |
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.141250331 |
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Mar 05 03:14:22 PM PST 24 |
Mar 05 03:16:26 PM PST 24 |
4757165940 ps |
T463 |
/workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.3822941065 |
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Mar 05 03:25:31 PM PST 24 |
Mar 05 03:59:59 PM PST 24 |
113732211423 ps |
T1337 |
/workspace/coverage/cover_reg_top/27.xbar_access_same_device.3370143682 |
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Mar 05 03:27:47 PM PST 24 |
Mar 05 03:28:56 PM PST 24 |
900491207 ps |
T374 |
/workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.2163117024 |
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Mar 05 03:17:50 PM PST 24 |
Mar 05 03:50:41 PM PST 24 |
15621595900 ps |
T1338 |
/workspace/coverage/cover_reg_top/70.xbar_smoke.2946775411 |
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Mar 05 03:36:41 PM PST 24 |
Mar 05 03:36:48 PM PST 24 |
45608181 ps |
T1339 |
/workspace/coverage/cover_reg_top/63.xbar_smoke.976538888 |
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Mar 05 03:35:31 PM PST 24 |
Mar 05 03:35:41 PM PST 24 |
217572369 ps |
T1340 |
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3699990162 |
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Mar 05 03:20:58 PM PST 24 |
Mar 05 03:21:05 PM PST 24 |
36559800 ps |
T764 |
/workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.1598594251 |
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Mar 05 03:37:29 PM PST 24 |
Mar 05 03:39:05 PM PST 24 |
988100653 ps |
T574 |
/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.1423274786 |
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Mar 05 03:26:40 PM PST 24 |
Mar 05 03:35:02 PM PST 24 |
6407670871 ps |
T1341 |
/workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.3155296757 |
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Mar 05 03:24:18 PM PST 24 |
Mar 05 03:24:51 PM PST 24 |
734752014 ps |
T1342 |
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.212613554 |
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Mar 05 03:21:01 PM PST 24 |
Mar 05 03:21:15 PM PST 24 |
107739143 ps |
T472 |
/workspace/coverage/cover_reg_top/67.xbar_access_same_device.888122725 |
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Mar 05 03:36:19 PM PST 24 |
Mar 05 03:37:00 PM PST 24 |
1076041777 ps |
T1343 |
/workspace/coverage/cover_reg_top/42.xbar_smoke.2285989007 |
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Mar 05 03:31:13 PM PST 24 |
Mar 05 03:31:24 PM PST 24 |
216106693 ps |
T1344 |
/workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.3078361589 |
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Mar 05 03:39:05 PM PST 24 |
Mar 05 03:41:26 PM PST 24 |
8053066907 ps |
T1345 |
/workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.3422084092 |
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Mar 05 03:33:26 PM PST 24 |
Mar 05 03:35:02 PM PST 24 |
8922878894 ps |
T583 |
/workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.2055252080 |
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Mar 05 03:41:19 PM PST 24 |
Mar 05 03:46:31 PM PST 24 |
16597232348 ps |
T1346 |
/workspace/coverage/cover_reg_top/99.xbar_stress_all.1639751587 |
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Mar 05 03:41:52 PM PST 24 |
Mar 05 03:42:17 PM PST 24 |
802730428 ps |
T469 |
/workspace/coverage/cover_reg_top/19.xbar_stress_all.3080333290 |
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Mar 05 03:25:11 PM PST 24 |
Mar 05 03:34:34 PM PST 24 |
16164570695 ps |
T1347 |
/workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.3171971735 |
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Mar 05 03:35:20 PM PST 24 |
Mar 05 03:35:27 PM PST 24 |
59640850 ps |
T510 |
/workspace/coverage/cover_reg_top/11.chip_tl_errors.2100930132 |
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Mar 05 03:21:18 PM PST 24 |
Mar 05 03:25:40 PM PST 24 |
3922259326 ps |
T1348 |
/workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.2220384497 |
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Mar 05 03:28:33 PM PST 24 |
Mar 05 03:41:47 PM PST 24 |
47957909386 ps |
T1349 |
/workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.3093554585 |
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Mar 05 03:28:32 PM PST 24 |
Mar 05 03:28:50 PM PST 24 |
179009432 ps |
T1350 |
/workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.2704181546 |
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Mar 05 03:40:13 PM PST 24 |
Mar 05 03:41:51 PM PST 24 |
8825804500 ps |
T1351 |
/workspace/coverage/cover_reg_top/33.xbar_random_large_delays.4222925540 |
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Mar 05 03:29:15 PM PST 24 |
Mar 05 03:30:38 PM PST 24 |
7715841284 ps |
T1352 |
/workspace/coverage/cover_reg_top/80.xbar_smoke.4085580128 |
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Mar 05 03:38:32 PM PST 24 |
Mar 05 03:38:42 PM PST 24 |
225619024 ps |
T1353 |
/workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.3651912253 |
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Mar 05 03:27:39 PM PST 24 |
Mar 05 03:27:46 PM PST 24 |
50230453 ps |