| T373 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_boot_mode.515017520 |
|
|
Aug 22 04:39:43 AM UTC 24 |
Aug 22 04:45:53 AM UTC 24 |
2738577080 ps |
| T856 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.481610814 |
|
|
Aug 22 03:56:40 AM UTC 24 |
Aug 22 04:46:05 AM UTC 24 |
15207531334 ps |
| T70 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_test.3095180307 |
|
|
Aug 22 04:43:30 AM UTC 24 |
Aug 22 04:47:22 AM UTC 24 |
3255456024 ps |
| T857 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_auto_mode.618023559 |
|
|
Aug 22 04:32:38 AM UTC 24 |
Aug 22 04:47:57 AM UTC 24 |
6266239872 ps |
| T858 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1106698202 |
|
|
Aug 22 04:18:12 AM UTC 24 |
Aug 22 04:48:17 AM UTC 24 |
20136261554 ps |
| T281 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_mem_scramble.484015957 |
|
|
Aug 22 04:44:22 AM UTC 24 |
Aug 22 04:49:43 AM UTC 24 |
3564237162 ps |
| T859 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_ok.1257735865 |
|
|
Aug 22 04:34:08 AM UTC 24 |
Aug 22 04:50:10 AM UTC 24 |
7910359068 ps |
| T860 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_masking_off.2763917679 |
|
|
Aug 22 04:47:16 AM UTC 24 |
Aug 22 04:50:14 AM UTC 24 |
2551526135 ps |
| T861 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.4133431861 |
|
|
Aug 22 04:49:59 AM UTC 24 |
Aug 22 04:54:00 AM UTC 24 |
2619480632 ps |
| T862 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.364309384 |
|
|
Aug 22 04:37:41 AM UTC 24 |
Aug 22 04:55:03 AM UTC 24 |
6951955648 ps |
| T863 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_sw_mode.3618946992 |
|
|
Aug 22 04:40:30 AM UTC 24 |
Aug 22 04:58:23 AM UTC 24 |
7794512712 ps |
| T864 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_kat.3208482660 |
|
|
Aug 22 04:52:14 AM UTC 24 |
Aug 22 04:59:22 AM UTC 24 |
3495999560 ps |
| T865 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc.856825228 |
|
|
Aug 22 04:58:06 AM UTC 24 |
Aug 22 05:01:47 AM UTC 24 |
2829515762 ps |
| T358 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_self_hash.897684475 |
|
|
Aug 22 03:36:26 AM UTC 24 |
Aug 22 05:02:21 AM UTC 24 |
26117989350 ps |
| T231 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_dev.2111717457 |
|
|
Aug 22 03:55:04 AM UTC 24 |
Aug 22 05:02:39 AM UTC 24 |
51249093456 ps |
| T566 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.666764130 |
|
|
Aug 22 04:58:41 AM UTC 24 |
Aug 22 05:02:44 AM UTC 24 |
3122320136 ps |
| T866 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.2084521555 |
|
|
Aug 22 04:57:35 AM UTC 24 |
Aug 22 05:03:03 AM UTC 24 |
5064860180 ps |
| T315 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc.1789498489 |
|
|
Aug 22 05:01:30 AM UTC 24 |
Aug 22 05:04:45 AM UTC 24 |
3345888304 ps |
| T170 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_entropy.911042237 |
|
|
Aug 22 05:00:49 AM UTC 24 |
Aug 22 05:05:09 AM UTC 24 |
3018854972 ps |
| T867 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.4125224741 |
|
|
Aug 22 04:57:43 AM UTC 24 |
Aug 22 05:05:33 AM UTC 24 |
6863201619 ps |
| T868 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_escalation.1232289058 |
|
|
Aug 22 05:01:57 AM UTC 24 |
Aug 22 05:06:39 AM UTC 24 |
5019268020 ps |
| T869 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_idle.2629044635 |
|
|
Aug 22 05:05:27 AM UTC 24 |
Aug 22 05:08:41 AM UTC 24 |
3240978748 ps |
| T162 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_status.1429486261 |
|
|
Aug 22 05:06:02 AM UTC 24 |
Aug 22 05:09:05 AM UTC 24 |
2652362199 ps |
| T870 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_entropy.3614558342 |
|
|
Aug 22 05:06:50 AM UTC 24 |
Aug 22 05:10:04 AM UTC 24 |
3504827000 ps |
| T871 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3294897185 |
|
|
Aug 22 05:05:18 AM UTC 24 |
Aug 22 05:10:36 AM UTC 24 |
5152618856 ps |
| T282 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.4246848477 |
|
|
Aug 22 05:02:45 AM UTC 24 |
Aug 22 05:10:52 AM UTC 24 |
5024625411 ps |
| T872 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_kat_test.870813521 |
|
|
Aug 22 05:08:30 AM UTC 24 |
Aug 22 05:11:30 AM UTC 24 |
2787961500 ps |
| T283 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2549624245 |
|
|
Aug 22 05:05:11 AM UTC 24 |
Aug 22 05:11:41 AM UTC 24 |
4065412160 ps |
| T150 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4224104936 |
|
|
Aug 22 05:07:43 AM UTC 24 |
Aug 22 05:13:06 AM UTC 24 |
4874821224 ps |
| T873 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_idle.3442977469 |
|
|
Aug 22 05:12:28 AM UTC 24 |
Aug 22 05:16:47 AM UTC 24 |
3006825900 ps |
| T171 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3383203858 |
|
|
Aug 22 04:56:18 AM UTC 24 |
Aug 22 05:13:13 AM UTC 24 |
12438980824 ps |
| T874 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_multistream.2953209104 |
|
|
Aug 22 04:54:00 AM UTC 24 |
Aug 22 05:14:38 AM UTC 24 |
7426623016 ps |
| T875 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1108765138 |
|
|
Aug 22 05:10:54 AM UTC 24 |
Aug 22 05:19:02 AM UTC 24 |
3977130050 ps |
| T876 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation.2766636123 |
|
|
Aug 22 05:05:54 AM UTC 24 |
Aug 22 05:19:33 AM UTC 24 |
6497966088 ps |
| T52 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_csr_rw.1311740875 |
|
|
Aug 22 05:09:20 AM UTC 24 |
Aug 22 05:20:32 AM UTC 24 |
9064861616 ps |
| T877 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2079630782 |
|
|
Aug 22 05:14:01 AM UTC 24 |
Aug 22 05:21:02 AM UTC 24 |
3449586920 ps |
| T878 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.570942406 |
|
|
Aug 22 04:28:46 AM UTC 24 |
Aug 22 05:21:44 AM UTC 24 |
18268455413 ps |
| T596 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3990090039 |
|
|
Aug 22 04:40:54 AM UTC 24 |
Aug 22 05:22:51 AM UTC 24 |
20372259212 ps |
| T879 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_kmac.3976024625 |
|
|
Aug 22 05:08:51 AM UTC 24 |
Aug 22 05:23:09 AM UTC 24 |
6765536856 ps |
| T168 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_10.1376970046 |
|
|
Aug 22 05:16:51 AM UTC 24 |
Aug 22 05:23:27 AM UTC 24 |
3640012116 ps |
| T251 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_plic_sw_irq.1956140922 |
|
|
Aug 22 05:20:13 AM UTC 24 |
Aug 22 05:23:51 AM UTC 24 |
2503448342 ps |
| T222 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_aes.1669618562 |
|
|
Aug 22 05:11:49 AM UTC 24 |
Aug 22 05:25:40 AM UTC 24 |
7055068760 ps |
| T880 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_frequency.270790433 |
|
|
Aug 22 05:21:40 AM UTC 24 |
Aug 22 05:26:17 AM UTC 24 |
3581351848 ps |
| T881 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1641469218 |
|
|
Aug 22 05:20:22 AM UTC 24 |
Aug 22 05:27:37 AM UTC 24 |
5095238576 ps |
| T209 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_mem_access.3677313572 |
|
|
Aug 22 05:10:19 AM UTC 24 |
Aug 22 05:27:43 AM UTC 24 |
13624715268 ps |
| T882 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac.3950366980 |
|
|
Aug 22 05:25:28 AM UTC 24 |
Aug 22 05:28:41 AM UTC 24 |
2877188644 ps |
| T883 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1426102759 |
|
|
Aug 22 05:23:09 AM UTC 24 |
Aug 22 05:29:29 AM UTC 24 |
5366332420 ps |
| T884 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_coremark.4201700178 |
|
|
Aug 22 01:42:56 AM UTC 24 |
Aug 22 05:29:52 AM UTC 24 |
71621920760 ps |
| T303 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_execution_main.721633101 |
|
|
Aug 22 05:25:04 AM UTC 24 |
Aug 22 05:31:52 AM UTC 24 |
6873224122 ps |
| T320 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.302066055 |
|
|
Aug 22 05:18:58 AM UTC 24 |
Aug 22 05:32:01 AM UTC 24 |
6719664840 ps |
| T885 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_cshake.2524969168 |
|
|
Aug 22 05:28:50 AM UTC 24 |
Aug 22 05:32:02 AM UTC 24 |
2961628592 ps |
| T886 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.1031184721 |
|
|
Aug 22 05:14:10 AM UTC 24 |
Aug 22 05:32:20 AM UTC 24 |
7053855584 ps |
| T341 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_csrng.3395781824 |
|
|
Aug 22 05:17:06 AM UTC 24 |
Aug 22 05:32:28 AM UTC 24 |
6894828454 ps |
| T574 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_dev.3823970432 |
|
|
Aug 22 05:22:45 AM UTC 24 |
Aug 22 05:35:18 AM UTC 24 |
10929173215 ps |
| T158 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_alert.1608313878 |
|
|
Aug 22 05:31:30 AM UTC 24 |
Aug 22 05:35:27 AM UTC 24 |
3502463308 ps |
| T887 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.698778653 |
|
|
Aug 22 05:29:40 AM UTC 24 |
Aug 22 05:35:57 AM UTC 24 |
5855570330 ps |
| T888 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_peri.3537559036 |
|
|
Aug 22 05:18:51 AM UTC 24 |
Aug 22 05:36:31 AM UTC 24 |
10584844360 ps |
| T225 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_otbn.4238736807 |
|
|
Aug 22 04:49:45 AM UTC 24 |
Aug 22 05:38:50 AM UTC 24 |
14919597420 ps |
| T889 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_prod.970263754 |
|
|
Aug 22 05:30:38 AM UTC 24 |
Aug 22 05:39:51 AM UTC 24 |
7637918815 ps |
| T269 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rom_ctrl_integrity_check.2289694462 |
|
|
Aug 22 05:34:37 AM UTC 24 |
Aug 22 05:40:18 AM UTC 24 |
9638158015 ps |
| T890 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_outputs.1382972982 |
|
|
Aug 22 05:30:53 AM UTC 24 |
Aug 22 05:40:30 AM UTC 24 |
7926230838 ps |
| T318 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.1850967374 |
|
|
Aug 22 05:35:08 AM UTC 24 |
Aug 22 05:42:38 AM UTC 24 |
4748496200 ps |
| T891 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3529991004 |
|
|
Aug 22 05:08:23 AM UTC 24 |
Aug 22 05:43:44 AM UTC 24 |
26407595505 ps |
| T82 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_testunlock0.755461857 |
|
|
Aug 22 05:39:53 AM UTC 24 |
Aug 22 05:45:56 AM UTC 24 |
6390461005 ps |
| T892 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3882892168 |
|
|
Aug 22 05:25:45 AM UTC 24 |
Aug 22 05:46:13 AM UTC 24 |
10393571098 ps |
| T893 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3950898114 |
|
|
Aug 22 05:41:02 AM UTC 24 |
Aug 22 05:47:41 AM UTC 24 |
4557945866 ps |
| T575 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.507714061 |
|
|
Aug 22 05:42:03 AM UTC 24 |
Aug 22 05:47:52 AM UTC 24 |
4802920080 ps |
| T894 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3372050853 |
|
|
Aug 22 05:41:49 AM UTC 24 |
Aug 22 05:48:58 AM UTC 24 |
7965122131 ps |
| T370 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_rv_dm_ndm_reset_req.2279853646 |
|
|
Aug 22 05:45:08 AM UTC 24 |
Aug 22 05:48:59 AM UTC 24 |
3416260498 ps |
| T895 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.656243942 |
|
|
Aug 22 05:43:13 AM UTC 24 |
Aug 22 05:50:11 AM UTC 24 |
5016497864 ps |
| T310 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2807317600 |
|
|
Aug 22 05:44:29 AM UTC 24 |
Aug 22 05:50:45 AM UTC 24 |
5622896750 ps |
| T352 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_crash_alert.4293660426 |
|
|
Aug 22 05:45:30 AM UTC 24 |
Aug 22 05:51:04 AM UTC 24 |
5348021800 ps |
| T234 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_rma.2272938263 |
|
|
Aug 22 04:38:27 AM UTC 24 |
Aug 22 05:51:35 AM UTC 24 |
45545510047 ps |
| T896 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_write_clear.3502938228 |
|
|
Aug 22 05:50:32 AM UTC 24 |
Aug 22 05:54:03 AM UTC 24 |
3171639240 ps |
| T897 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.427397836 |
|
|
Aug 22 05:47:48 AM UTC 24 |
Aug 22 05:55:17 AM UTC 24 |
5237569702 ps |
| T83 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_rma.3562946310 |
|
|
Aug 22 05:49:11 AM UTC 24 |
Aug 22 05:55:35 AM UTC 24 |
6282177521 ps |
| T252 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_sleep_load.2834407373 |
|
|
Aug 22 05:51:12 AM UTC 24 |
Aug 22 05:55:36 AM UTC 24 |
4316974078 ps |
| T898 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_smoketest.2401338467 |
|
|
Aug 22 05:52:36 AM UTC 24 |
Aug 22 05:56:18 AM UTC 24 |
3282372648 ps |
| T899 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.4000115065 |
|
|
Aug 22 05:53:03 AM UTC 24 |
Aug 22 05:56:21 AM UTC 24 |
3082104647 ps |
| T900 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3790142119 |
|
|
Aug 22 05:51:41 AM UTC 24 |
Aug 22 05:57:14 AM UTC 24 |
5316534848 ps |
| T901 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_smoketest.1314600394 |
|
|
Aug 22 05:55:18 AM UTC 24 |
Aug 22 05:57:52 AM UTC 24 |
2833741140 ps |
| T902 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency.741580402 |
|
|
Aug 22 04:52:01 AM UTC 24 |
Aug 22 05:59:22 AM UTC 24 |
21049188960 ps |
| T903 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2844933393 |
|
|
Aug 22 05:11:18 AM UTC 24 |
Aug 22 05:59:51 AM UTC 24 |
16681220390 ps |
| T904 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2290994661 |
|
|
Aug 22 05:54:08 AM UTC 24 |
Aug 22 06:00:34 AM UTC 24 |
4169002108 ps |
| T232 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prod.4051779782 |
|
|
Aug 22 04:44:37 AM UTC 24 |
Aug 22 06:00:44 AM UTC 24 |
51547394670 ps |
| T905 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_smoketest.2733705230 |
|
|
Aug 22 05:55:47 AM UTC 24 |
Aug 22 06:02:14 AM UTC 24 |
7001227288 ps |
| T345 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4141142183 |
|
|
Aug 22 05:55:39 AM UTC 24 |
Aug 22 06:02:27 AM UTC 24 |
5038263812 ps |
| T906 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter.3682694289 |
|
|
Aug 22 06:03:29 AM UTC 24 |
Aug 22 06:05:59 AM UTC 24 |
3036718489 ps |
| T907 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3595786547 |
|
|
Aug 22 06:06:40 AM UTC 24 |
Aug 22 06:09:42 AM UTC 24 |
3429493220 ps |
| T908 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_keymgr_functest.781724161 |
|
|
Aug 22 06:03:50 AM UTC 24 |
Aug 22 06:10:00 AM UTC 24 |
4723462560 ps |
| T228 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init_reduced_freq.3583710077 |
|
|
Aug 22 05:49:18 AM UTC 24 |
Aug 22 06:12:55 AM UTC 24 |
26534722901 ps |
| T909 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_smoketest.1883980059 |
|
|
Aug 22 06:11:07 AM UTC 24 |
Aug 22 06:14:01 AM UTC 24 |
2867157806 ps |
| T910 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_smoketest.3422784672 |
|
|
Aug 22 06:12:14 AM UTC 24 |
Aug 22 06:14:24 AM UTC 24 |
2389502440 ps |
| T911 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_idle_load.3872322926 |
|
|
Aug 22 06:11:00 AM UTC 24 |
Aug 22 06:16:53 AM UTC 24 |
4807855804 ps |
| T192 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2435875930 |
|
|
Aug 22 06:14:04 AM UTC 24 |
Aug 22 06:17:00 AM UTC 24 |
2944324104 ps |
| T165 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.4234234076 |
|
|
Aug 22 03:39:10 AM UTC 24 |
Aug 22 06:17:11 AM UTC 24 |
60429008488 ps |
| T376 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1527982132 |
|
|
Aug 22 06:15:41 AM UTC 24 |
Aug 22 06:18:22 AM UTC 24 |
3002486180 ps |
| T21 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.136314402 |
|
|
Aug 22 06:14:11 AM UTC 24 |
Aug 22 06:18:35 AM UTC 24 |
5211660152 ps |
| T912 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_scrambling_smoketest.2416716103 |
|
|
Aug 22 06:16:29 AM UTC 24 |
Aug 22 06:18:59 AM UTC 24 |
2882572098 ps |
| T913 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_concurrency.1161658984 |
|
|
Aug 22 06:18:35 AM UTC 24 |
Aug 22 06:22:00 AM UTC 24 |
3566941992 ps |
| T346 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sival_flash_info_access.3309838400 |
|
|
Aug 22 06:19:56 AM UTC 24 |
Aug 22 06:23:26 AM UTC 24 |
3465286216 ps |
| T914 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_smoketest.1235973898 |
|
|
Aug 22 06:21:30 AM UTC 24 |
Aug 22 06:24:33 AM UTC 24 |
3288451862 ps |
| T915 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_smoketest.2767592814 |
|
|
Aug 22 06:25:48 AM UTC 24 |
Aug 22 06:29:38 AM UTC 24 |
3467486880 ps |
| T916 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_smoketest.3726796581 |
|
|
Aug 22 06:27:46 AM UTC 24 |
Aug 22 06:30:28 AM UTC 24 |
2478338792 ps |
| T44 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_virus.893729734 |
|
|
Aug 22 06:17:04 AM UTC 24 |
Aug 22 06:32:44 AM UTC 24 |
5838892104 ps |
| T917 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_smoketest.292604571 |
|
|
Aug 22 06:30:20 AM UTC 24 |
Aug 22 06:34:02 AM UTC 24 |
2815646194 ps |
| T918 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_manufacturer.2021973020 |
|
|
Aug 22 06:32:20 AM UTC 24 |
Aug 22 06:34:45 AM UTC 24 |
2521851576 ps |
| T125 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_rand_baudrate.3977065337 |
|
|
Aug 22 06:19:01 AM UTC 24 |
Aug 22 06:35:14 AM UTC 24 |
7695990220 ps |
| T919 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_inject_scramble_seed.4066138585 |
|
|
Aug 22 03:40:22 AM UTC 24 |
Aug 22 06:35:44 AM UTC 24 |
62918287246 ps |
| T920 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_entropy.1213091988 |
|
|
Aug 22 06:36:51 AM UTC 24 |
Aug 22 06:39:03 AM UTC 24 |
2187625246 ps |
| T921 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_flash.2092099495 |
|
|
Aug 22 06:37:13 AM UTC 24 |
Aug 22 06:39:40 AM UTC 24 |
2805027656 ps |
| T922 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pwm_pulses.1704120540 |
|
|
Aug 22 06:27:39 AM UTC 24 |
Aug 22 06:41:17 AM UTC 24 |
8373520014 ps |
| T51 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio_smoketest.2377946449 |
|
|
Aug 22 06:39:13 AM UTC 24 |
Aug 22 06:42:08 AM UTC 24 |
3004213923 ps |
| T923 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx1.111006576 |
|
|
Aug 22 06:37:19 AM UTC 24 |
Aug 22 06:43:42 AM UTC 24 |
4099895598 ps |
| T924 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_smoketest.2485656500 |
|
|
Aug 22 06:40:31 AM UTC 24 |
Aug 22 06:44:06 AM UTC 24 |
3258337520 ps |
| T925 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_smoketest.1172818642 |
|
|
Aug 22 06:40:59 AM UTC 24 |
Aug 22 06:44:12 AM UTC 24 |
3514351214 ps |
| T43 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_tpm.95973719 |
|
|
Aug 22 06:41:35 AM UTC 24 |
Aug 22 06:45:56 AM UTC 24 |
3994192640 ps |
| T926 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_rom.2757404575 |
|
|
Aug 22 06:44:19 AM UTC 24 |
Aug 22 06:45:58 AM UTC 24 |
1909712244 ps |
| T927 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1593480277 |
|
|
Aug 22 03:24:40 AM UTC 24 |
Aug 22 06:46:42 AM UTC 24 |
77463888387 ps |
| T344 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops.1925645333 |
|
|
Aug 22 06:40:45 AM UTC 24 |
Aug 22 06:48:00 AM UTC 24 |
4181633180 ps |
| T347 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pattgen_ios.1044744976 |
|
|
Aug 22 06:45:49 AM UTC 24 |
Aug 22 06:49:04 AM UTC 24 |
3132000680 ps |
| T38 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio.731454611 |
|
|
Aug 22 06:45:14 AM UTC 24 |
Aug 22 06:50:02 AM UTC 24 |
3709629268 ps |
| T270 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_data_integrity_escalation.1283683758 |
|
|
Aug 22 06:43:39 AM UTC 24 |
Aug 22 06:50:28 AM UTC 24 |
5644896918 ps |
| T272 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1690003834 |
|
|
Aug 22 06:01:25 AM UTC 24 |
Aug 22 06:51:22 AM UTC 24 |
24873310965 ps |
| T273 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx.1094752559 |
|
|
Aug 22 06:46:04 AM UTC 24 |
Aug 22 06:51:41 AM UTC 24 |
4006060388 ps |
| T71 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_retention.1817987206 |
|
|
Aug 22 06:49:51 AM UTC 24 |
Aug 22 06:53:37 AM UTC 24 |
4683431720 ps |
| T274 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_device_tx_rx.98222099 |
|
|
Aug 22 06:49:37 AM UTC 24 |
Aug 22 06:54:49 AM UTC 24 |
4321460992 ps |
| T275 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx.1715770578 |
|
|
Aug 22 06:46:11 AM UTC 24 |
Aug 22 06:57:02 AM UTC 24 |
5514675100 ps |
| T276 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init.1869737769 |
|
|
Aug 22 06:39:07 AM UTC 24 |
Aug 22 06:57:38 AM UTC 24 |
19133226648 ps |
| T277 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2135326791 |
|
|
Aug 22 06:54:47 AM UTC 24 |
Aug 22 06:58:46 AM UTC 24 |
2712354852 ps |
| T278 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2595027725 |
|
|
Aug 22 06:50:26 AM UTC 24 |
Aug 22 06:59:16 AM UTC 24 |
4800880976 ps |
| T279 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1008810319 |
|
|
Aug 22 06:49:30 AM UTC 24 |
Aug 22 07:02:13 AM UTC 24 |
6671663256 ps |
| T174 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.678057067 |
|
|
Aug 22 07:00:56 AM UTC 24 |
Aug 22 07:02:21 AM UTC 24 |
2389967316 ps |
| T928 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3003958787 |
|
|
Aug 22 07:00:13 AM UTC 24 |
Aug 22 07:03:36 AM UTC 24 |
3134140108 ps |
| T40 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_host_tx_rx.2555121252 |
|
|
Aug 22 07:01:39 AM UTC 24 |
Aug 22 07:04:18 AM UTC 24 |
2325777404 ps |
| T929 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx3.1264678083 |
|
|
Aug 22 06:58:14 AM UTC 24 |
Aug 22 07:04:33 AM UTC 24 |
4016965120 ps |
| T930 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.71861956 |
|
|
Aug 22 06:18:01 AM UTC 24 |
Aug 22 07:05:13 AM UTC 24 |
14619564470 ps |
| T73 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.2036402908 |
|
|
Aug 22 07:01:31 AM UTC 24 |
Aug 22 07:05:17 AM UTC 24 |
3335034376 ps |
| T207 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through_collision.823442631 |
|
|
Aug 22 07:03:27 AM UTC 24 |
Aug 22 07:09:20 AM UTC 24 |
4080653276 ps |
| T931 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_rst.267889920 |
|
|
Aug 22 07:06:59 AM UTC 24 |
Aug 22 07:09:26 AM UTC 24 |
2403054752 ps |
| T932 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2545834991 |
|
|
Aug 22 06:51:00 AM UTC 24 |
Aug 22 07:10:11 AM UTC 24 |
8812239710 ps |
| T933 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1182909426 |
|
|
Aug 22 07:06:30 AM UTC 24 |
Aug 22 07:10:14 AM UTC 24 |
4298530928 ps |
| T934 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1051667175 |
|
|
Aug 22 07:00:06 AM UTC 24 |
Aug 22 07:12:23 AM UTC 24 |
5682649219 ps |
| T578 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.3518592902 |
|
|
Aug 22 07:11:18 AM UTC 24 |
Aug 22 07:13:03 AM UTC 24 |
2501371431 ps |
| T935 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access.2889470752 |
|
|
Aug 22 07:04:15 AM UTC 24 |
Aug 22 07:15:26 AM UTC 24 |
5068976200 ps |
| T579 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3641873982 |
|
|
Aug 22 07:14:34 AM UTC 24 |
Aug 22 07:16:07 AM UTC 24 |
2373493173 ps |
| T208 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through.3144882651 |
|
|
Aug 22 07:08:33 AM UTC 24 |
Aug 22 07:16:34 AM UTC 24 |
6512933115 ps |
| T936 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1048268854 |
|
|
Aug 22 06:32:34 AM UTC 24 |
Aug 22 07:19:10 AM UTC 24 |
15478219388 ps |
| T937 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.2500198452 |
|
|
Aug 22 07:22:28 AM UTC 24 |
Aug 22 07:25:54 AM UTC 24 |
2401797541 ps |
| T938 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_smoke.4158326442 |
|
|
Aug 22 06:39:47 AM UTC 24 |
Aug 22 07:26:41 AM UTC 24 |
14646927856 ps |
| T355 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_irq.1483325076 |
|
|
Aug 22 07:22:35 AM UTC 24 |
Aug 22 07:28:12 AM UTC 24 |
3799423408 ps |
| T939 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2044581796 |
|
|
Aug 22 07:16:45 AM UTC 24 |
Aug 22 07:29:09 AM UTC 24 |
8414352644 ps |
| T940 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_irq.2675463637 |
|
|
Aug 22 07:27:39 AM UTC 24 |
Aug 22 07:31:00 AM UTC 24 |
2671027124 ps |
| T941 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prodend.2785628614 |
|
|
Aug 22 07:20:58 AM UTC 24 |
Aug 22 07:31:08 AM UTC 24 |
8713290201 ps |
| T588 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3510847933 |
|
|
Aug 22 07:32:53 AM UTC 24 |
Aug 22 07:36:12 AM UTC 24 |
3191135420 ps |
| T942 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.1645370508 |
|
|
Aug 22 07:29:48 AM UTC 24 |
Aug 22 07:37:04 AM UTC 24 |
5677268589 ps |
| T943 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1401545065 |
|
|
Aug 22 07:12:30 AM UTC 24 |
Aug 22 07:38:41 AM UTC 24 |
20400103810 ps |
| T944 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2951716353 |
|
|
Aug 22 07:34:34 AM UTC 24 |
Aug 22 07:39:37 AM UTC 24 |
7211110352 ps |
| T945 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2476002258 |
|
|
Aug 22 07:32:16 AM UTC 24 |
Aug 22 07:39:54 AM UTC 24 |
8048894375 ps |
| T214 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_outputs.1558900234 |
|
|
Aug 22 07:35:56 AM UTC 24 |
Aug 22 07:40:27 AM UTC 24 |
4376567600 ps |
| T237 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_cpu_info.3526501728 |
|
|
Aug 22 07:32:23 AM UTC 24 |
Aug 22 07:40:43 AM UTC 24 |
7256604632 ps |
| T946 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.789796700 |
|
|
Aug 22 06:53:35 AM UTC 24 |
Aug 22 07:40:59 AM UTC 24 |
14457061164 ps |
| T42 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.587714431 |
|
|
Aug 22 07:36:19 AM UTC 24 |
Aug 22 07:42:58 AM UTC 24 |
5145804792 ps |
| T947 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_masking_off.59453619 |
|
|
Aug 22 07:39:46 AM UTC 24 |
Aug 22 07:43:34 AM UTC 24 |
3200293718 ps |
| T340 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_alert_info.334789387 |
|
|
Aug 22 07:20:22 AM UTC 24 |
Aug 22 07:43:41 AM UTC 24 |
13283163580 ps |
| T948 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_static_critical.726641723 |
|
|
Aug 22 06:48:30 AM UTC 24 |
Aug 22 07:44:31 AM UTC 24 |
16840118700 ps |
| T409 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.438137593 |
|
|
Aug 22 07:36:11 AM UTC 24 |
Aug 22 07:45:41 AM UTC 24 |
4827244806 ps |
| T949 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1529441455 |
|
|
Aug 22 07:29:39 AM UTC 24 |
Aug 22 07:46:41 AM UTC 24 |
9139833384 ps |
| T950 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_req.399579631 |
|
|
Aug 22 07:42:39 AM UTC 24 |
Aug 22 07:47:13 AM UTC 24 |
4222112772 ps |
| T284 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_mem_scramble.1447647648 |
|
|
Aug 22 07:42:00 AM UTC 24 |
Aug 22 07:47:46 AM UTC 24 |
3976284370 ps |
| T951 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3454236233 |
|
|
Aug 22 07:43:18 AM UTC 24 |
Aug 22 07:47:51 AM UTC 24 |
6997163128 ps |
| T952 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2835218692 |
|
|
Aug 22 07:39:54 AM UTC 24 |
Aug 22 07:48:07 AM UTC 24 |
9947510992 ps |
| T953 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2109204297 |
|
|
Aug 22 07:42:16 AM UTC 24 |
Aug 22 07:48:16 AM UTC 24 |
5241449328 ps |
| T954 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2592359646 |
|
|
Aug 22 07:47:11 AM UTC 24 |
Aug 22 07:49:54 AM UTC 24 |
2673793230 ps |
| T955 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3493954503 |
|
|
Aug 22 07:33:47 AM UTC 24 |
Aug 22 07:50:07 AM UTC 24 |
12157768273 ps |
| T956 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_wdog_reset.878576922 |
|
|
Aug 22 07:43:54 AM UTC 24 |
Aug 22 07:50:59 AM UTC 24 |
4311701842 ps |
| T957 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.1497398444 |
|
|
Aug 22 07:47:05 AM UTC 24 |
Aug 22 07:52:33 AM UTC 24 |
8926911140 ps |
| T958 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc.3832516375 |
|
|
Aug 22 07:52:58 AM UTC 24 |
Aug 22 07:55:52 AM UTC 24 |
3072361872 ps |
| T959 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_escalation.578137586 |
|
|
Aug 22 07:53:20 AM UTC 24 |
Aug 22 07:58:00 AM UTC 24 |
5477258824 ps |
| T47 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_output.563023267 |
|
|
Aug 22 07:13:14 AM UTC 24 |
Aug 22 07:58:09 AM UTC 24 |
30988239310 ps |
| T960 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_randomness.3246491386 |
|
|
Aug 22 07:49:29 AM UTC 24 |
Aug 22 07:59:28 AM UTC 24 |
5945322186 ps |
| T961 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prod.465836534 |
|
|
Aug 22 06:54:40 AM UTC 24 |
Aug 22 07:59:36 AM UTC 24 |
47803035232 ps |
| T962 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4132090965 |
|
|
Aug 22 04:44:06 AM UTC 24 |
Aug 22 08:00:48 AM UTC 24 |
255423784450 ps |
| T963 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_exception_c.4161954316 |
|
|
Aug 22 07:18:38 AM UTC 24 |
Aug 22 08:04:41 AM UTC 24 |
15156232259 ps |
| T195 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_rma_unlocked.1233329360 |
|
|
Aug 22 06:59:52 AM UTC 24 |
Aug 22 08:04:48 AM UTC 24 |
43531295001 ps |
| T964 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3657528452 |
|
|
Aug 22 07:49:21 AM UTC 24 |
Aug 22 08:05:20 AM UTC 24 |
13102547978 ps |
| T965 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_timeout.3774579926 |
|
|
Aug 22 08:02:22 AM UTC 24 |
Aug 22 08:07:33 AM UTC 24 |
3801548600 ps |
| T966 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_ok.832367993 |
|
|
Aug 22 07:52:43 AM UTC 24 |
Aug 22 08:07:40 AM UTC 24 |
7748575246 ps |
| T246 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_test.243847523 |
|
|
Aug 22 08:05:29 AM UTC 24 |
Aug 22 08:08:30 AM UTC 24 |
2424179870 ps |
| T967 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_auto_mode.1668476883 |
|
|
Aug 22 07:58:06 AM UTC 24 |
Aug 22 08:09:12 AM UTC 24 |
4664758696 ps |
| T968 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_idle.1402690836 |
|
|
Aug 22 08:08:49 AM UTC 24 |
Aug 22 08:11:00 AM UTC 24 |
2110735988 ps |
| T969 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_kat.3538478006 |
|
|
Aug 22 08:04:17 AM UTC 24 |
Aug 22 08:11:24 AM UTC 24 |
3718205070 ps |
| T970 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.4144921726 |
|
|
Aug 22 08:06:06 AM UTC 24 |
Aug 22 08:12:44 AM UTC 24 |
7488177840 ps |
| T971 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3543962347 |
|
|
Aug 22 08:03:19 AM UTC 24 |
Aug 22 08:13:21 AM UTC 24 |
5250574233 ps |
| T285 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1675317893 |
|
|
Aug 22 08:05:59 AM UTC 24 |
Aug 22 08:13:21 AM UTC 24 |
5095814568 ps |
| T972 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_kat_test.3190961794 |
|
|
Aug 22 08:16:23 AM UTC 24 |
Aug 22 08:18:57 AM UTC 24 |
2182398756 ps |
| T973 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_self_hash.3305823663 |
|
|
Aug 22 06:53:50 AM UTC 24 |
Aug 22 08:19:10 AM UTC 24 |
26698105960 ps |
| T974 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_kat_test.3910925257 |
|
|
Aug 22 08:16:07 AM UTC 24 |
Aug 22 08:19:44 AM UTC 24 |
3225472970 ps |
| T975 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2796908162 |
|
|
Aug 22 07:56:35 AM UTC 24 |
Aug 22 08:20:14 AM UTC 24 |
9285097850 ps |
| T618 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2800905768 |
|
|
Aug 22 08:03:26 AM UTC 24 |
Aug 22 08:20:28 AM UTC 24 |
12712129068 ps |
| T976 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_sw_mode.2888246950 |
|
|
Aug 22 08:01:09 AM UTC 24 |
Aug 22 08:20:57 AM UTC 24 |
8388510000 ps |
| T977 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.2539657604 |
|
|
Aug 22 08:15:59 AM UTC 24 |
Aug 22 08:21:28 AM UTC 24 |
7571208284 ps |
| T978 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_entropy.2607532205 |
|
|
Aug 22 08:18:55 AM UTC 24 |
Aug 22 08:22:18 AM UTC 24 |
2355444384 ps |
| T979 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.2485593366 |
|
|
Aug 22 07:33:25 AM UTC 24 |
Aug 22 08:23:15 AM UTC 24 |
17033817922 ps |
| T389 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3078919189 |
|
|
Aug 22 08:19:37 AM UTC 24 |
Aug 22 08:24:55 AM UTC 24 |
10220368151 ps |
| T980 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1459740026 |
|
|
Aug 22 07:43:47 AM UTC 24 |
Aug 22 08:25:54 AM UTC 24 |
33227525444 ps |
| T981 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_idle.4222024451 |
|
|
Aug 22 08:22:28 AM UTC 24 |
Aug 22 08:26:00 AM UTC 24 |
2859560600 ps |
| T223 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_aes.138579642 |
|
|
Aug 22 07:57:35 AM UTC 24 |
Aug 22 08:26:36 AM UTC 24 |
12973598418 ps |
| T982 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac.1496030348 |
|
|
Aug 22 08:23:25 AM UTC 24 |
Aug 22 08:26:47 AM UTC 24 |
3321939314 ps |
| T983 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_idle.3060274454 |
|
|
Aug 22 08:24:02 AM UTC 24 |
Aug 22 08:27:03 AM UTC 24 |
2995974352 ps |
| T984 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.154444842 |
|
|
Aug 22 08:18:41 AM UTC 24 |
Aug 22 08:27:09 AM UTC 24 |
7604301500 ps |
| T985 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation.2454861179 |
|
|
Aug 22 08:12:25 AM UTC 24 |
Aug 22 08:27:28 AM UTC 24 |
7847645950 ps |
| T986 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.386293716 |
|
|
Aug 22 07:58:14 AM UTC 24 |
Aug 22 08:28:08 AM UTC 24 |
13875064009 ps |
| T987 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_cshake.749128385 |
|
|
Aug 22 08:25:26 AM UTC 24 |
Aug 22 08:28:22 AM UTC 24 |
2841166320 ps |
| T342 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_csrng.3686166750 |
|
|
Aug 22 08:17:50 AM UTC 24 |
Aug 22 08:30:24 AM UTC 24 |
6158450544 ps |
| T988 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_entropy.3995491725 |
|
|
Aug 22 08:28:14 AM UTC 24 |
Aug 22 08:31:22 AM UTC 24 |
3355261156 ps |
| T989 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1388486468 |
|
|
Aug 22 08:15:06 AM UTC 24 |
Aug 22 08:34:11 AM UTC 24 |
7905384144 ps |
| T349 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en.3690703871 |
|
|
Aug 22 08:30:39 AM UTC 24 |
Aug 22 08:34:29 AM UTC 24 |
2781269581 ps |
| T565 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_boot_mode.743696479 |
|
|
Aug 22 08:28:42 AM UTC 24 |
Aug 22 08:34:36 AM UTC 24 |
3031384118 ps |
| T990 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3138267369 |
|
|
Aug 22 08:30:32 AM UTC 24 |
Aug 22 08:36:19 AM UTC 24 |
5207437550 ps |
| T991 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_dev.2707459846 |
|
|
Aug 22 07:19:00 AM UTC 24 |
Aug 22 08:37:01 AM UTC 24 |
47635014856 ps |
| T286 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3875482785 |
|
|
Aug 22 08:31:38 AM UTC 24 |
Aug 22 08:37:14 AM UTC 24 |
4665120555 ps |
| T992 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3569338768 |
|
|
Aug 22 08:30:46 AM UTC 24 |
Aug 22 08:37:37 AM UTC 24 |
4781923118 ps |
| T210 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_mem_access.2959457737 |
|
|
Aug 22 08:23:30 AM UTC 24 |
Aug 22 08:38:51 AM UTC 24 |
14109192475 ps |
| T993 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.134246233 |
|
|
Aug 22 08:33:33 AM UTC 24 |
Aug 22 08:39:32 AM UTC 24 |
4612825000 ps |
| T994 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2056686646 |
|
|
Aug 22 08:34:33 AM UTC 24 |
Aug 22 08:40:29 AM UTC 24 |
4899344940 ps |
| T995 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1109301592 |
|
|
Aug 22 07:52:49 AM UTC 24 |
Aug 22 08:41:44 AM UTC 24 |
18266524331 ps |
| T62 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_csr_rw.1375411622 |
|
|
Aug 22 08:22:33 AM UTC 24 |
Aug 22 08:42:17 AM UTC 24 |
17714984840 ps |
| T996 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_oneshot.1566605209 |
|
|
Aug 22 08:39:49 AM UTC 24 |
Aug 22 08:43:01 AM UTC 24 |
2978594136 ps |
| T319 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_20.82330232 |
|
|
Aug 22 08:36:22 AM UTC 24 |
Aug 22 08:45:06 AM UTC 24 |
4362604222 ps |
| T169 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_10.915884348 |
|
|
Aug 22 08:39:42 AM UTC 24 |
Aug 22 08:45:15 AM UTC 24 |
4055334580 ps |
| T151 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2269665875 |
|
|
Aug 22 08:39:27 AM UTC 24 |
Aug 22 08:46:09 AM UTC 24 |
6043981000 ps |
| T239 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3964261315 |
|
|
Aug 22 08:43:18 AM UTC 24 |
Aug 22 08:46:16 AM UTC 24 |
3210112780 ps |
| T997 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_kmac.4184020690 |
|
|
Aug 22 08:22:50 AM UTC 24 |
Aug 22 08:46:45 AM UTC 24 |
10796332240 ps |
| T152 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.266958464 |
|
|
Aug 22 08:42:28 AM UTC 24 |
Aug 22 08:47:36 AM UTC 24 |
4758938370 ps |
| T998 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1111305408 |
|
|
Aug 22 08:09:25 AM UTC 24 |
Aug 22 08:49:12 AM UTC 24 |
19987601717 ps |
| T999 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter.3501545463 |
|
|
Aug 22 08:46:30 AM UTC 24 |
Aug 22 08:49:34 AM UTC 24 |
2490757979 ps |
| T1000 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3484232656 |
|
|
Aug 22 08:45:21 AM UTC 24 |
Aug 22 08:50:27 AM UTC 24 |
4913671002 ps |
| T321 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.491915805 |
|
|
Aug 22 08:38:52 AM UTC 24 |
Aug 22 08:51:44 AM UTC 24 |
5775902500 ps |
| T1001 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3674181403 |
|
|
Aug 22 08:45:13 AM UTC 24 |
Aug 22 08:51:51 AM UTC 24 |
3910018420 ps |
| T114 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_rv_dm_ndm_reset_req.1824435278 |
|
|
Aug 22 08:47:41 AM UTC 24 |
Aug 22 08:52:35 AM UTC 24 |
5121046612 ps |
| T1002 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.470928690 |
|
|
Aug 22 08:45:06 AM UTC 24 |
Aug 22 08:52:01 AM UTC 24 |
4258840740 ps |
| T304 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_execution_main.3745287727 |
|
|
Aug 22 08:46:00 AM UTC 24 |
Aug 22 08:52:28 AM UTC 24 |
7773882396 ps |
| T78 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_testunlock0.2296874555 |
|
|
Aug 22 08:50:17 AM UTC 24 |
Aug 22 08:53:22 AM UTC 24 |
3358116252 ps |
| T1003 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_reset_frequency.663222173 |
|
|
Aug 22 08:48:31 AM UTC 24 |
Aug 22 08:53:32 AM UTC 24 |
3036414640 ps |
| T1004 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2048814292 |
|
|
Aug 22 08:49:54 AM UTC 24 |
Aug 22 08:53:45 AM UTC 24 |
3118150142 ps |
| T1005 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_peri.207470843 |
|
|
Aug 22 08:40:38 AM UTC 24 |
Aug 22 08:54:35 AM UTC 24 |
10537616312 ps |
| T1006 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_prod.1918650561 |
|
|
Aug 22 08:45:30 AM UTC 24 |
Aug 22 08:55:32 AM UTC 24 |
8908060693 ps |
| T1007 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.3850256909 |
|
|
Aug 22 08:44:21 AM UTC 24 |
Aug 22 08:56:51 AM UTC 24 |
11881651559 ps |
| T1008 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_app_rom.2862525685 |
|
|
Aug 22 08:55:16 AM UTC 24 |
Aug 22 08:57:34 AM UTC 24 |
3198258488 ps |