| T156 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_alert.2640375944 |
|
|
Aug 22 08:47:12 AM UTC 24 |
Aug 22 08:59:23 AM UTC 24 |
6216691228 ps |
| T79 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_rma.4143541211 |
|
|
Aug 22 09:00:10 AM UTC 24 |
Aug 22 09:03:29 AM UTC 24 |
3164128155 ps |
| T1009 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.96372364 |
|
|
Aug 22 08:30:54 AM UTC 24 |
Aug 22 09:04:20 AM UTC 24 |
25586138180 ps |
| T359 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3698185821 |
|
|
Aug 22 09:00:33 AM UTC 24 |
Aug 22 09:05:15 AM UTC 24 |
5348459480 ps |
| T343 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.4189831629 |
|
|
Aug 22 09:01:05 AM UTC 24 |
Aug 22 09:06:18 AM UTC 24 |
3882057048 ps |
| T226 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_otbn.2599027162 |
|
|
Aug 22 08:25:17 AM UTC 24 |
Aug 22 09:06:25 AM UTC 24 |
12488192738 ps |
| T577 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_dev.2207563640 |
|
|
Aug 22 08:48:24 AM UTC 24 |
Aug 22 09:06:31 AM UTC 24 |
15378860464 ps |
| T299 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.4249738174 |
|
|
Aug 22 09:05:02 AM UTC 24 |
Aug 22 09:07:26 AM UTC 24 |
3113066878 ps |
| T1010 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3131652572 |
|
|
Aug 22 09:01:45 AM UTC 24 |
Aug 22 09:08:13 AM UTC 24 |
4269392850 ps |
| T74 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1045051820 |
|
|
Aug 22 08:54:47 AM UTC 24 |
Aug 22 09:08:34 AM UTC 24 |
25265711748 ps |
| T183 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_program_error.581815423 |
|
|
Aug 22 09:01:59 AM UTC 24 |
Aug 22 09:08:47 AM UTC 24 |
4141119000 ps |
| T357 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.422787459 |
|
|
Aug 22 09:07:59 AM UTC 24 |
Aug 22 09:10:30 AM UTC 24 |
2622806588 ps |
| T1011 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_outputs.260775313 |
|
|
Aug 22 09:00:25 AM UTC 24 |
Aug 22 09:11:54 AM UTC 24 |
8025103120 ps |
| T1012 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.3725302324 |
|
|
Aug 22 09:08:31 AM UTC 24 |
Aug 22 09:12:50 AM UTC 24 |
5530749750 ps |
| T1013 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency.107307136 |
|
|
Aug 22 08:25:10 AM UTC 24 |
Aug 22 09:13:08 AM UTC 24 |
16139996918 ps |
| T1014 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_rma.1211726967 |
|
|
Aug 22 08:04:10 AM UTC 24 |
Aug 22 09:15:54 AM UTC 24 |
48703018596 ps |
| T1015 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3271685780 |
|
|
Aug 22 09:15:47 AM UTC 24 |
Aug 22 09:19:05 AM UTC 24 |
2666860110 ps |
| T1016 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_sleep_load.3643902354 |
|
|
Aug 22 09:12:47 AM UTC 24 |
Aug 22 09:19:15 AM UTC 24 |
10645592736 ps |
| T1017 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_write_clear.358797726 |
|
|
Aug 22 09:16:08 AM UTC 24 |
Aug 22 09:19:42 AM UTC 24 |
2323468910 ps |
| T1018 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.109288829 |
|
|
Aug 22 06:43:14 AM UTC 24 |
Aug 22 09:20:15 AM UTC 24 |
59465895011 ps |
| T1019 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3921862418 |
|
|
Aug 22 09:14:38 AM UTC 24 |
Aug 22 09:20:39 AM UTC 24 |
5400267271 ps |
| T1020 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_mem_protection.372005812 |
|
|
Aug 22 09:11:19 AM UTC 24 |
Aug 22 09:22:42 AM UTC 24 |
5196783324 ps |
| T600 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_crash_alert.469537622 |
|
|
Aug 22 09:14:58 AM UTC 24 |
Aug 22 09:23:00 AM UTC 24 |
5707951808 ps |
| T1021 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_smoketest.1196809846 |
|
|
Aug 22 09:25:09 AM UTC 24 |
Aug 22 09:28:39 AM UTC 24 |
2485093178 ps |
| T576 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1937034165 |
|
|
Aug 22 09:22:38 AM UTC 24 |
Aug 22 09:28:43 AM UTC 24 |
5652743591 ps |
| T1022 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_idle_load.621719594 |
|
|
Aug 22 09:22:59 AM UTC 24 |
Aug 22 09:29:18 AM UTC 24 |
4585989336 ps |
| T1023 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_smoketest.2980534076 |
|
|
Aug 22 09:27:36 AM UTC 24 |
Aug 22 09:31:16 AM UTC 24 |
3897214760 ps |
| T1024 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init_reduced_freq.1751827048 |
|
|
Aug 22 09:11:33 AM UTC 24 |
Aug 22 09:32:15 AM UTC 24 |
24604221973 ps |
| T1025 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.556826492 |
|
|
Aug 22 09:14:51 AM UTC 24 |
Aug 22 09:33:46 AM UTC 24 |
11880654637 ps |
| T1026 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx1.1736432086 |
|
|
Aug 22 09:27:29 AM UTC 24 |
Aug 22 09:34:20 AM UTC 24 |
4130596998 ps |
| T1027 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_scrambling_smoketest.1652119293 |
|
|
Aug 22 09:31:02 AM UTC 24 |
Aug 22 09:34:35 AM UTC 24 |
3071806340 ps |
| T124 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx2.2554578715 |
|
|
Aug 22 09:29:45 AM UTC 24 |
Aug 22 09:35:46 AM UTC 24 |
4043208492 ps |
| T1028 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_smoketest.3169167379 |
|
|
Aug 22 09:32:19 AM UTC 24 |
Aug 22 09:36:11 AM UTC 24 |
3271479856 ps |
| T1029 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_smoketest.2800807912 |
|
|
Aug 22 09:35:19 AM UTC 24 |
Aug 22 09:38:17 AM UTC 24 |
3072383524 ps |
| T1030 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_inject_scramble_seed.2773914420 |
|
|
Aug 22 06:40:52 AM UTC 24 |
Aug 22 09:38:45 AM UTC 24 |
64719697578 ps |
| T1031 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_smoketest.1000787484 |
|
|
Aug 22 09:36:15 AM UTC 24 |
Aug 22 09:39:11 AM UTC 24 |
3108199676 ps |
| T356 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2989836193 |
|
|
Aug 22 09:31:58 AM UTC 24 |
Aug 22 09:39:17 AM UTC 24 |
4868755613 ps |
| T1032 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_smoketest.3533439547 |
|
|
Aug 22 09:34:46 AM UTC 24 |
Aug 22 09:39:26 AM UTC 24 |
2946201364 ps |
| T653 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2380820177 |
|
|
Aug 22 09:35:12 AM UTC 24 |
Aug 22 09:39:51 AM UTC 24 |
4386329030 ps |
| T378 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1964120734 |
|
|
Aug 22 09:35:47 AM UTC 24 |
Aug 22 09:40:10 AM UTC 24 |
4831197264 ps |
| T1033 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_dev.921229282 |
|
|
Aug 22 09:28:17 AM UTC 24 |
Aug 22 09:40:22 AM UTC 24 |
10691865481 ps |
| T1034 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1281979768 |
|
|
Aug 22 09:38:06 AM UTC 24 |
Aug 22 09:41:11 AM UTC 24 |
3451980808 ps |
| T568 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.949813822 |
|
|
Aug 22 08:52:52 AM UTC 24 |
Aug 22 09:42:56 AM UTC 24 |
24976344519 ps |
| T1035 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_testunlock0.4214351079 |
|
|
Aug 22 09:42:33 AM UTC 24 |
Aug 22 09:44:55 AM UTC 24 |
2918342085 ps |
| T1036 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_smoketest.4118320557 |
|
|
Aug 22 09:42:26 AM UTC 24 |
Aug 22 09:45:20 AM UTC 24 |
3075956440 ps |
| T1037 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_prod.2975107805 |
|
|
Aug 22 09:43:48 AM UTC 24 |
Aug 22 09:45:51 AM UTC 24 |
3035584045 ps |
| T1038 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_smoketest.948224433 |
|
|
Aug 22 09:42:05 AM UTC 24 |
Aug 22 09:46:56 AM UTC 24 |
5271053760 ps |
| T1039 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_testunlock0.3799218813 |
|
|
Aug 22 09:43:42 AM UTC 24 |
Aug 22 09:48:22 AM UTC 24 |
5044139507 ps |
| T1040 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_rma.979522813 |
|
|
Aug 22 09:45:14 AM UTC 24 |
Aug 22 09:51:05 AM UTC 24 |
6294363960 ps |
| T1041 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_smoketest.2881820199 |
|
|
Aug 22 09:50:36 AM UTC 24 |
Aug 22 09:53:12 AM UTC 24 |
2564577818 ps |
| T1042 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio_smoketest.86369746 |
|
|
Aug 22 09:50:49 AM UTC 24 |
Aug 22 09:54:13 AM UTC 24 |
3289528800 ps |
| T1043 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_rma.490630787 |
|
|
Aug 22 09:52:20 AM UTC 24 |
Aug 22 09:55:12 AM UTC 24 |
3475198425 ps |
| T1044 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_dev.3812232107 |
|
|
Aug 22 09:53:11 AM UTC 24 |
Aug 22 09:55:17 AM UTC 24 |
2665830033 ps |
| T157 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_sensor_ctrl_alert.409627824 |
|
|
Aug 22 09:50:56 AM UTC 24 |
Aug 22 09:56:34 AM UTC 24 |
4182306600 ps |
| T1045 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx1.3819774313 |
|
|
Aug 22 09:50:08 AM UTC 24 |
Aug 22 09:56:34 AM UTC 24 |
3755871620 ps |
| T1046 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_plic_smoketest.383794761 |
|
|
Aug 22 09:54:11 AM UTC 24 |
Aug 22 09:57:09 AM UTC 24 |
2115139480 ps |
| T271 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_data_integrity_escalation.1688194653 |
|
|
Aug 22 09:50:28 AM UTC 24 |
Aug 22 09:57:31 AM UTC 24 |
5460092704 ps |
| T350 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_all_escalation_resets.295056125 |
|
|
Aug 22 09:49:36 AM UTC 24 |
Aug 22 09:57:40 AM UTC 24 |
5510158752 ps |
| T1047 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1394446141 |
|
|
Aug 22 09:52:47 AM UTC 24 |
Aug 22 09:57:52 AM UTC 24 |
3335234599 ps |
| T131 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_rst_inputs.1064407755 |
|
|
Aug 22 09:25:51 AM UTC 24 |
Aug 22 10:03:43 AM UTC 24 |
21716392547 ps |
| T247 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3642846032 |
|
|
Aug 22 10:00:25 AM UTC 24 |
Aug 22 10:04:18 AM UTC 24 |
3204295760 ps |
| T290 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3304873414 |
|
|
Aug 22 06:42:32 AM UTC 24 |
Aug 22 10:07:41 AM UTC 24 |
78460421012 ps |
| T291 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.762698633 |
|
|
Aug 22 10:04:03 AM UTC 24 |
Aug 22 10:08:50 AM UTC 24 |
3927864215 ps |
| T292 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx.4057440740 |
|
|
Aug 22 10:03:41 AM UTC 24 |
Aug 22 10:10:18 AM UTC 24 |
4561829790 ps |
| T293 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2388323018 |
|
|
Aug 22 10:05:25 AM UTC 24 |
Aug 22 10:10:38 AM UTC 24 |
7278234232 ps |
| T294 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_all_escalation_resets.3074877245 |
|
|
Aug 22 10:03:20 AM UTC 24 |
Aug 22 10:10:59 AM UTC 24 |
5463786280 ps |
| T295 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_uart_rand_baudrate.359118186 |
|
|
Aug 22 10:05:39 AM UTC 24 |
Aug 22 10:11:50 AM UTC 24 |
3672636896 ps |
| T296 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx2.1716202677 |
|
|
Aug 22 10:07:56 AM UTC 24 |
Aug 22 10:14:07 AM UTC 24 |
4498886692 ps |
| T297 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3701249783 |
|
|
Aug 22 10:09:30 AM UTC 24 |
Aug 22 10:14:11 AM UTC 24 |
3208656200 ps |
| T298 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx3.1772942899 |
|
|
Aug 22 10:07:19 AM UTC 24 |
Aug 22 10:15:08 AM UTC 24 |
4701444428 ps |
| T1048 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_lc_ctrl_transition.455729891 |
|
|
Aug 22 10:05:45 AM UTC 24 |
Aug 22 10:16:22 AM UTC 24 |
13097184359 ps |
| T119 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_virus.4041151544 |
|
|
Aug 22 10:01:46 AM UTC 24 |
Aug 22 10:17:57 AM UTC 24 |
5403280920 ps |
| T668 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_all_escalation_resets.50740635 |
|
|
Aug 22 10:10:22 AM UTC 24 |
Aug 22 10:18:52 AM UTC 24 |
5858922610 ps |
| T1049 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_prod.3008087515 |
|
|
Aug 22 10:17:58 AM UTC 24 |
Aug 22 10:19:38 AM UTC 24 |
2592106395 ps |
| T1050 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_uart_rand_baudrate.521351332 |
|
|
Aug 22 10:05:59 AM UTC 24 |
Aug 22 10:23:12 AM UTC 24 |
8617782972 ps |
| T627 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1207871879 |
|
|
Aug 22 10:18:35 AM UTC 24 |
Aug 22 10:23:17 AM UTC 24 |
3757488640 ps |
| T1051 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx.660113128 |
|
|
Aug 22 10:17:36 AM UTC 24 |
Aug 22 10:23:49 AM UTC 24 |
3894154564 ps |
| T238 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_all_escalation_resets.4025869414 |
|
|
Aug 22 10:18:13 AM UTC 24 |
Aug 22 10:24:44 AM UTC 24 |
5614013950 ps |
| T1052 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_uart_rand_baudrate.360709045 |
|
|
Aug 22 10:07:34 AM UTC 24 |
Aug 22 10:25:08 AM UTC 24 |
8638252518 ps |
| T1053 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.3656540623 |
|
|
Aug 22 09:41:12 AM UTC 24 |
Aug 22 10:27:37 AM UTC 24 |
14773282460 ps |
| T1054 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_exception_c.1235994160 |
|
|
Aug 22 09:43:15 AM UTC 24 |
Aug 22 10:27:46 AM UTC 24 |
14520885531 ps |
| T1055 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx3.2204331987 |
|
|
Aug 22 10:21:22 AM UTC 24 |
Aug 22 10:29:24 AM UTC 24 |
4578078704 ps |
| T1056 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_uart_rand_baudrate.694838198 |
|
|
Aug 22 10:14:00 AM UTC 24 |
Aug 22 10:30:35 AM UTC 24 |
7955112458 ps |
| T1057 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_uart_rand_baudrate.831352012 |
|
|
Aug 22 10:12:40 AM UTC 24 |
Aug 22 10:30:55 AM UTC 24 |
8732680416 ps |
| T1058 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_lc_ctrl_transition.3243551273 |
|
|
Aug 22 10:25:52 AM UTC 24 |
Aug 22 10:31:43 AM UTC 24 |
6753685851 ps |
| T1059 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_uart_rand_baudrate.3150172158 |
|
|
Aug 22 10:27:55 AM UTC 24 |
Aug 22 10:32:55 AM UTC 24 |
3738434040 ps |
| T648 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2486362219 |
|
|
Aug 22 10:28:23 AM UTC 24 |
Aug 22 10:33:16 AM UTC 24 |
3958794424 ps |
| T1060 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2488363274 |
|
|
Aug 22 10:28:47 AM UTC 24 |
Aug 22 10:33:42 AM UTC 24 |
6336123960 ps |
| T656 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_all_escalation_resets.3532329951 |
|
|
Aug 22 10:27:04 AM UTC 24 |
Aug 22 10:34:02 AM UTC 24 |
5175947552 ps |
| T1061 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_rand_baudrate.3922204425 |
|
|
Aug 22 10:02:46 AM UTC 24 |
Aug 22 10:34:16 AM UTC 24 |
13352967446 ps |
| T705 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1799360366 |
|
|
Aug 22 10:30:52 AM UTC 24 |
Aug 22 10:34:45 AM UTC 24 |
3514736328 ps |
| T630 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_all_escalation_resets.2890708862 |
|
|
Aug 22 10:36:59 AM UTC 24 |
Aug 22 10:43:34 AM UTC 24 |
5037071000 ps |
| T634 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_all_escalation_resets.1626851137 |
|
|
Aug 22 10:37:13 AM UTC 24 |
Aug 22 10:44:53 AM UTC 24 |
4898323416 ps |
| T1062 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_lc_ctrl_transition.1097207681 |
|
|
Aug 22 10:32:53 AM UTC 24 |
Aug 22 10:46:15 AM UTC 24 |
10434989075 ps |
| T1063 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_lc_ctrl_transition.525448799 |
|
|
Aug 22 10:33:55 AM UTC 24 |
Aug 22 10:46:20 AM UTC 24 |
14092994690 ps |
| T1064 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3782982112 |
|
|
Aug 22 10:29:30 AM UTC 24 |
Aug 22 10:46:38 AM UTC 24 |
7975452793 ps |
| T635 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.198356334 |
|
|
Aug 22 10:43:04 AM UTC 24 |
Aug 22 10:47:33 AM UTC 24 |
4026120248 ps |
| T1065 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_smoke.2788515048 |
|
|
Aug 22 09:59:45 AM UTC 24 |
Aug 22 10:47:37 AM UTC 24 |
14988452024 ps |
| T1066 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.395450415 |
|
|
Aug 22 10:43:55 AM UTC 24 |
Aug 22 10:49:34 AM UTC 24 |
4374145628 ps |
| T1067 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_csrng_edn_concurrency.3268017825 |
|
|
Aug 22 10:26:35 AM UTC 24 |
Aug 22 10:51:12 AM UTC 24 |
9561395060 ps |
| T689 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_all_escalation_resets.3573237565 |
|
|
Aug 22 10:45:52 AM UTC 24 |
Aug 22 10:52:08 AM UTC 24 |
4772327160 ps |
| T643 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.918733245 |
|
|
Aug 22 10:47:40 AM UTC 24 |
Aug 22 10:52:23 AM UTC 24 |
3938182670 ps |
| T1068 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.4244162010 |
|
|
Aug 22 10:05:18 AM UTC 24 |
Aug 22 10:52:45 AM UTC 24 |
15089533454 ps |
| T706 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1322198723 |
|
|
Aug 22 10:49:25 AM UTC 24 |
Aug 22 10:53:18 AM UTC 24 |
3119027800 ps |
| T663 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_all_escalation_resets.3420569644 |
|
|
Aug 22 10:45:08 AM UTC 24 |
Aug 22 10:53:46 AM UTC 24 |
6379483192 ps |
| T98 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_all_escalation_resets.1692490521 |
|
|
Aug 22 10:47:18 AM UTC 24 |
Aug 22 10:54:37 AM UTC 24 |
4581257868 ps |
| T104 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_all_escalation_resets.2430781611 |
|
|
Aug 22 10:47:32 AM UTC 24 |
Aug 22 10:54:59 AM UTC 24 |
4186823196 ps |
| T105 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.399188982 |
|
|
Aug 22 10:51:49 AM UTC 24 |
Aug 22 10:56:09 AM UTC 24 |
3491398528 ps |
| T106 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_rand_baudrate.2562488618 |
|
|
Aug 22 10:37:06 AM UTC 24 |
Aug 22 10:57:02 AM UTC 24 |
8853969944 ps |
| T107 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_uart_rand_baudrate.3768518235 |
|
|
Aug 22 10:51:12 AM UTC 24 |
Aug 22 10:57:34 AM UTC 24 |
3962109076 ps |
| T108 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.578015217 |
|
|
Aug 22 08:00:37 AM UTC 24 |
Aug 22 10:58:09 AM UTC 24 |
254559445584 ps |
| T109 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_lc_ctrl_transition.4262664654 |
|
|
Aug 22 10:52:21 AM UTC 24 |
Aug 22 10:59:22 AM UTC 24 |
7212538048 ps |
| T110 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_uart_rand_baudrate.773087855 |
|
|
Aug 22 10:52:28 AM UTC 24 |
Aug 22 10:59:58 AM UTC 24 |
4986477520 ps |
| T111 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_lc_ctrl_transition.149351256 |
|
|
Aug 22 10:53:56 AM UTC 24 |
Aug 22 11:01:02 AM UTC 24 |
5889061524 ps |
| T112 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1775647468 |
|
|
Aug 22 10:57:09 AM UTC 24 |
Aug 22 11:02:05 AM UTC 24 |
3796142600 ps |
| T363 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_uart_rand_baudrate.3518208969 |
|
|
Aug 22 10:31:56 AM UTC 24 |
Aug 22 11:02:17 AM UTC 24 |
13787096034 ps |
| T1069 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_output.3103891996 |
|
|
Aug 22 10:21:39 AM UTC 24 |
Aug 22 11:03:40 AM UTC 24 |
28985065800 ps |
| T1070 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_static_critical.468618193 |
|
|
Aug 22 10:09:15 AM UTC 24 |
Aug 22 11:03:46 AM UTC 24 |
17159382858 ps |
| T1071 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_csrng_edn_concurrency.3071326975 |
|
|
Aug 22 10:21:46 AM UTC 24 |
Aug 22 11:04:07 AM UTC 24 |
13837586150 ps |
| T1072 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_uart_rand_baudrate.3226065946 |
|
|
Aug 22 10:32:45 AM UTC 24 |
Aug 22 11:04:10 AM UTC 24 |
12772176508 ps |
| T692 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.4222217918 |
|
|
Aug 22 11:01:22 AM UTC 24 |
Aug 22 11:05:59 AM UTC 24 |
3443065320 ps |
| T673 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_all_escalation_resets.2423981317 |
|
|
Aug 22 11:02:14 AM UTC 24 |
Aug 22 11:07:49 AM UTC 24 |
4316966936 ps |
| T681 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3673455849 |
|
|
Aug 22 11:03:00 AM UTC 24 |
Aug 22 11:07:55 AM UTC 24 |
4156573668 ps |
| T649 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_all_escalation_resets.670545256 |
|
|
Aug 22 11:01:30 AM UTC 24 |
Aug 22 11:08:28 AM UTC 24 |
5119173370 ps |
| T1073 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_uart_rand_baudrate.2274861035 |
|
|
Aug 22 11:02:38 AM UTC 24 |
Aug 22 11:08:30 AM UTC 24 |
4005919992 ps |
| T1074 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_lc_ctrl_transition.3414381669 |
|
|
Aug 22 10:59:06 AM UTC 24 |
Aug 22 11:08:34 AM UTC 24 |
12545058148 ps |
| T1075 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_csrng_edn_concurrency.42276081 |
|
|
Aug 22 10:24:28 AM UTC 24 |
Aug 22 11:08:52 AM UTC 24 |
14512578604 ps |
| T99 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3123952420 |
|
|
Aug 22 11:04:31 AM UTC 24 |
Aug 22 11:09:20 AM UTC 24 |
4177904920 ps |
| T652 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3472463982 |
|
|
Aug 22 11:05:58 AM UTC 24 |
Aug 22 11:10:09 AM UTC 24 |
4149170170 ps |
| T637 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2978216743 |
|
|
Aug 22 11:07:55 AM UTC 24 |
Aug 22 11:12:49 AM UTC 24 |
3750941000 ps |
| T684 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3606136575 |
|
|
Aug 22 11:08:09 AM UTC 24 |
Aug 22 11:13:11 AM UTC 24 |
4138927144 ps |
| T351 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_all_escalation_resets.1397242994 |
|
|
Aug 22 11:08:17 AM UTC 24 |
Aug 22 11:14:55 AM UTC 24 |
4450719320 ps |
| T602 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.742621053 |
|
|
Aug 22 11:10:53 AM UTC 24 |
Aug 22 11:15:31 AM UTC 24 |
3827066150 ps |
| T1076 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.380059826 |
|
|
Aug 22 10:30:07 AM UTC 24 |
Aug 22 11:17:20 AM UTC 24 |
14708357928 ps |
| T694 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2683190563 |
|
|
Aug 22 11:14:06 AM UTC 24 |
Aug 22 11:18:38 AM UTC 24 |
3666184766 ps |
| T674 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.114100800 |
|
|
Aug 22 11:16:34 AM UTC 24 |
Aug 22 11:21:52 AM UTC 24 |
4237378480 ps |
| T132 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1621963042 |
|
|
Aug 22 06:04:49 AM UTC 24 |
Aug 22 11:22:32 AM UTC 24 |
148524008395 ps |
| T644 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_all_escalation_resets.1454887653 |
|
|
Aug 22 11:18:34 AM UTC 24 |
Aug 22 11:25:09 AM UTC 24 |
5737681620 ps |
| T240 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_all_escalation_resets.1664928696 |
|
|
Aug 22 11:19:34 AM UTC 24 |
Aug 22 11:25:34 AM UTC 24 |
5474257640 ps |
| T701 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2131555436 |
|
|
Aug 22 11:21:22 AM UTC 24 |
Aug 22 11:25:44 AM UTC 24 |
3713486620 ps |
| T100 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.569777927 |
|
|
Aug 22 11:23:02 AM UTC 24 |
Aug 22 11:27:19 AM UTC 24 |
3598556054 ps |
| T1077 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_self_hash.2097581345 |
|
|
Aug 22 10:08:53 AM UTC 24 |
Aug 22 11:30:56 AM UTC 24 |
26702424680 ps |
| T604 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2710133729 |
|
|
Aug 22 11:26:44 AM UTC 24 |
Aug 22 11:31:49 AM UTC 24 |
4104357614 ps |
| T682 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.232277386 |
|
|
Aug 22 11:27:21 AM UTC 24 |
Aug 22 11:32:10 AM UTC 24 |
3787080050 ps |
| T636 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_all_escalation_resets.3708097562 |
|
|
Aug 22 11:25:48 AM UTC 24 |
Aug 22 11:32:20 AM UTC 24 |
5750856700 ps |
| T1078 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_uart_rand_baudrate.2342681979 |
|
|
Aug 22 11:18:04 AM UTC 24 |
Aug 22 11:34:43 AM UTC 24 |
8336117760 ps |
| T625 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_all_escalation_resets.2623824599 |
|
|
Aug 22 11:29:29 AM UTC 24 |
Aug 22 11:35:45 AM UTC 24 |
5865223072 ps |
| T609 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_all_escalation_resets.1063903802 |
|
|
Aug 22 11:28:44 AM UTC 24 |
Aug 22 11:35:51 AM UTC 24 |
4969615416 ps |
| T603 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_all_escalation_resets.352595807 |
|
|
Aug 22 11:29:22 AM UTC 24 |
Aug 22 11:36:31 AM UTC 24 |
5587586746 ps |
| T1079 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_uart_rand_baudrate.849550377 |
|
|
Aug 22 11:18:54 AM UTC 24 |
Aug 22 11:36:52 AM UTC 24 |
9393726174 ps |
| T646 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_all_escalation_resets.725044878 |
|
|
Aug 22 11:29:45 AM UTC 24 |
Aug 22 11:37:16 AM UTC 24 |
5862458380 ps |
| T1080 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_csrng_edn_concurrency.2098059432 |
|
|
Aug 22 10:11:41 AM UTC 24 |
Aug 22 11:37:45 AM UTC 24 |
27237737764 ps |
| T1081 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_uart_rand_baudrate.1433398505 |
|
|
Aug 22 11:20:03 AM UTC 24 |
Aug 22 11:37:49 AM UTC 24 |
8908701584 ps |
| T248 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.4114065252 |
|
|
Aug 22 11:33:40 AM UTC 24 |
Aug 22 11:38:20 AM UTC 24 |
3755070676 ps |
| T631 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2950687022 |
|
|
Aug 22 11:34:47 AM UTC 24 |
Aug 22 11:38:57 AM UTC 24 |
3677405400 ps |
| T662 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1440480362 |
|
|
Aug 22 11:34:55 AM UTC 24 |
Aug 22 11:38:58 AM UTC 24 |
4096238440 ps |
| T659 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_all_escalation_resets.2984798276 |
|
|
Aug 22 11:31:37 AM UTC 24 |
Aug 22 11:40:11 AM UTC 24 |
5468736584 ps |
| T1082 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_all_escalation_resets.3645836730 |
|
|
Aug 22 11:32:09 AM UTC 24 |
Aug 22 11:40:35 AM UTC 24 |
5727946250 ps |
| T610 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3375989992 |
|
|
Aug 22 11:36:12 AM UTC 24 |
Aug 22 11:40:41 AM UTC 24 |
3391418428 ps |
| T650 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_all_escalation_resets.2706743752 |
|
|
Aug 22 11:34:02 AM UTC 24 |
Aug 22 11:40:59 AM UTC 24 |
5915412232 ps |
| T651 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1539385748 |
|
|
Aug 22 11:37:26 AM UTC 24 |
Aug 22 11:41:47 AM UTC 24 |
3709165176 ps |
| T360 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.194864842 |
|
|
Aug 22 11:38:36 AM UTC 24 |
Aug 22 11:43:10 AM UTC 24 |
3990342220 ps |
| T628 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_all_escalation_resets.901271410 |
|
|
Aug 22 11:37:33 AM UTC 24 |
Aug 22 11:44:49 AM UTC 24 |
6383643652 ps |
| T670 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_all_escalation_resets.2795660789 |
|
|
Aug 22 11:37:12 AM UTC 24 |
Aug 22 11:45:17 AM UTC 24 |
4427250300 ps |
| T1083 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2737488889 |
|
|
Aug 22 11:41:23 AM UTC 24 |
Aug 22 11:45:30 AM UTC 24 |
3984782248 ps |
| T693 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3076550157 |
|
|
Aug 22 11:41:59 AM UTC 24 |
Aug 22 11:46:10 AM UTC 24 |
3841947672 ps |
| T1084 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_csrng_edn_concurrency.1246079315 |
|
|
Aug 22 10:52:06 AM UTC 24 |
Aug 22 11:46:15 AM UTC 24 |
17993851968 ps |
| T690 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_all_escalation_resets.2706847493 |
|
|
Aug 22 11:40:00 AM UTC 24 |
Aug 22 11:46:30 AM UTC 24 |
4939640048 ps |
| T675 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2208975196 |
|
|
Aug 22 11:43:18 AM UTC 24 |
Aug 22 11:48:08 AM UTC 24 |
3652828940 ps |
| T638 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_all_escalation_resets.1723143848 |
|
|
Aug 22 11:41:52 AM UTC 24 |
Aug 22 11:48:27 AM UTC 24 |
5047616504 ps |
| T679 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_all_escalation_resets.3580658879 |
|
|
Aug 22 11:42:48 AM UTC 24 |
Aug 22 11:49:46 AM UTC 24 |
5644255640 ps |
| T691 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_all_escalation_resets.4033931073 |
|
|
Aug 22 11:42:07 AM UTC 24 |
Aug 22 11:49:55 AM UTC 24 |
5238018984 ps |
| T680 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.761167494 |
|
|
Aug 22 11:45:39 AM UTC 24 |
Aug 22 11:51:12 AM UTC 24 |
4028993330 ps |
| T1085 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3521495923 |
|
|
Aug 22 11:46:14 AM UTC 24 |
Aug 22 11:51:27 AM UTC 24 |
4044221680 ps |
| T666 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1369081659 |
|
|
Aug 22 11:47:41 AM UTC 24 |
Aug 22 11:51:43 AM UTC 24 |
3108657084 ps |
| T1086 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_all_escalation_resets.667015763 |
|
|
Aug 22 11:46:48 AM UTC 24 |
Aug 22 11:53:44 AM UTC 24 |
5930669620 ps |
| T325 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3000783354 |
|
|
Aug 22 11:50:50 AM UTC 24 |
Aug 22 11:54:26 AM UTC 24 |
3571429900 ps |
| T330 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.721553884 |
|
|
Aug 22 11:53:07 AM UTC 24 |
Aug 22 11:57:10 AM UTC 24 |
3609049772 ps |
| T331 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3911349547 |
|
|
Aug 22 11:52:19 AM UTC 24 |
Aug 22 11:57:31 AM UTC 24 |
4516742898 ps |
| T332 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.985497602 |
|
|
Aug 22 11:54:24 AM UTC 24 |
Aug 22 11:58:22 AM UTC 24 |
3398844216 ps |
| T333 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_all_escalation_resets.2960279941 |
|
|
Aug 22 11:53:35 AM UTC 24 |
Aug 22 12:00:05 PM UTC 24 |
5406128154 ps |
| T334 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_uart_rand_baudrate.92607872 |
|
|
Aug 22 11:30:29 AM UTC 24 |
Aug 22 12:01:04 PM UTC 24 |
13061462904 ps |
| T326 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1749376776 |
|
|
Aug 22 11:57:26 AM UTC 24 |
Aug 22 12:01:28 PM UTC 24 |
3870409368 ps |
| T335 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2599743840 |
|
|
Aug 22 11:59:16 AM UTC 24 |
Aug 22 12:03:20 PM UTC 24 |
3742170848 ps |
| T336 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1005401676 |
|
|
Aug 22 12:01:25 PM UTC 24 |
Aug 22 12:05:32 PM UTC 24 |
3351439728 ps |
| T337 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_all_escalation_resets.3236794594 |
|
|
Aug 22 12:00:05 PM UTC 24 |
Aug 22 12:05:53 PM UTC 24 |
5322750104 ps |
| T654 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_all_escalation_resets.3567794691 |
|
|
Aug 22 11:57:40 AM UTC 24 |
Aug 22 12:06:06 PM UTC 24 |
6218607700 ps |
| T241 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_all_escalation_resets.3732577988 |
|
|
Aug 22 11:59:58 AM UTC 24 |
Aug 22 12:06:18 PM UTC 24 |
5612825812 ps |
| T669 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_all_escalation_resets.1329716961 |
|
|
Aug 22 11:59:51 AM UTC 24 |
Aug 22 12:06:35 PM UTC 24 |
4615705514 ps |
| T616 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_all_escalation_resets.1758074505 |
|
|
Aug 22 12:01:32 PM UTC 24 |
Aug 22 12:08:54 PM UTC 24 |
6340158242 ps |
| T1087 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1755939802 |
|
|
Aug 22 12:04:08 PM UTC 24 |
Aug 22 12:08:56 PM UTC 24 |
3618977408 ps |
| T664 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.29473620 |
|
|
Aug 22 12:04:49 PM UTC 24 |
Aug 22 12:09:24 PM UTC 24 |
3547475290 ps |
| T1088 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_csrng_edn_concurrency.1281961581 |
|
|
Aug 22 10:05:52 AM UTC 24 |
Aug 22 12:10:30 PM UTC 24 |
37906291044 ps |
| T348 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_all_escalation_resets.1098905781 |
|
|
Aug 22 12:03:20 PM UTC 24 |
Aug 22 12:11:23 PM UTC 24 |
5989853224 ps |
| T632 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.4055774703 |
|
|
Aug 22 12:07:29 PM UTC 24 |
Aug 22 12:11:23 PM UTC 24 |
3783813792 ps |
| T687 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2197574652 |
|
|
Aug 22 12:09:04 PM UTC 24 |
Aug 22 12:12:53 PM UTC 24 |
3276103648 ps |
| T647 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3314333196 |
|
|
Aug 22 12:08:58 PM UTC 24 |
Aug 22 12:13:49 PM UTC 24 |
3956223642 ps |
| T640 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.1071592937 |
|
|
Aug 22 12:11:01 PM UTC 24 |
Aug 22 12:14:54 PM UTC 24 |
3670406342 ps |
| T611 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3913715728 |
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|
Aug 22 12:10:34 PM UTC 24 |
Aug 22 12:14:59 PM UTC 24 |
4295511368 ps |
| T671 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3507595203 |
|
|
Aug 22 12:11:34 PM UTC 24 |
Aug 22 12:16:05 PM UTC 24 |
3998662504 ps |
| T249 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2992848219 |
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|
Aug 22 12:13:36 PM UTC 24 |
Aug 22 12:17:11 PM UTC 24 |
3531978046 ps |
| T677 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2741523418 |
|
|
Aug 22 12:12:50 PM UTC 24 |
Aug 22 12:17:27 PM UTC 24 |
3713956268 ps |
| T1089 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_csrng_edn_concurrency.1346814771 |
|
|
Aug 22 10:44:31 AM UTC 24 |
Aug 22 12:18:00 PM UTC 24 |
30981266488 ps |
| T660 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_all_escalation_resets.252146264 |
|
|
Aug 22 12:13:10 PM UTC 24 |
Aug 22 12:19:13 PM UTC 24 |
4953953840 ps |
| T688 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2004293129 |
|
|
Aug 22 12:16:18 PM UTC 24 |
Aug 22 12:19:58 PM UTC 24 |
3692278684 ps |
| T257 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_all_escalation_resets.777251747 |
|
|
Aug 22 12:12:58 PM UTC 24 |
Aug 22 12:20:11 PM UTC 24 |
6292084578 ps |
| T698 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_all_escalation_resets.3907878492 |
|
|
Aug 22 12:12:24 PM UTC 24 |
Aug 22 12:20:12 PM UTC 24 |
5227745038 ps |
| T665 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_all_escalation_resets.1965792096 |
|
|
Aug 22 12:16:24 PM UTC 24 |
Aug 22 12:22:12 PM UTC 24 |
5260691154 ps |
| T667 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_all_escalation_resets.3049721954 |
|
|
Aug 22 12:17:05 PM UTC 24 |
Aug 22 12:22:39 PM UTC 24 |
5144540300 ps |
| T642 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3562911083 |
|
|
Aug 22 12:19:03 PM UTC 24 |
Aug 22 12:22:49 PM UTC 24 |
3133724900 ps |
| T242 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_all_escalation_resets.487956249 |
|
|
Aug 22 12:17:26 PM UTC 24 |
Aug 22 12:23:32 PM UTC 24 |
4299053822 ps |
| T629 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3749016852 |
|
|
Aug 22 12:23:55 PM UTC 24 |
Aug 22 12:28:25 PM UTC 24 |
4604282600 ps |
| T612 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2884063574 |
|
|
Aug 22 12:24:43 PM UTC 24 |
Aug 22 12:28:40 PM UTC 24 |
3934571904 ps |
| T645 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1383038480 |
|
|
Aug 22 12:26:52 PM UTC 24 |
Aug 22 12:31:25 PM UTC 24 |
3592909736 ps |
| T1090 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_all_escalation_resets.1496010349 |
|
|
Aug 22 12:25:10 PM UTC 24 |
Aug 22 12:32:24 PM UTC 24 |
4970429176 ps |
| T361 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_all_escalation_resets.3174712249 |
|
|
Aug 22 12:28:18 PM UTC 24 |
Aug 22 12:34:27 PM UTC 24 |
5845489928 ps |
| T703 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_all_escalation_resets.2523992187 |
|
|
Aug 22 12:30:03 PM UTC 24 |
Aug 22 12:35:19 PM UTC 24 |
3961214520 ps |
| T678 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.525346870 |
|
|
Aug 22 12:32:30 PM UTC 24 |
Aug 22 12:36:40 PM UTC 24 |
3560477056 ps |
| T1091 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_all_escalation_resets.2871623923 |
|
|
Aug 22 12:30:11 PM UTC 24 |
Aug 22 12:36:59 PM UTC 24 |
4667711800 ps |
| T101 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3091025714 |
|
|
Aug 22 12:32:17 PM UTC 24 |
Aug 22 12:37:29 PM UTC 24 |
4017361844 ps |
| T639 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_all_escalation_resets.2522663786 |
|
|
Aug 22 12:31:10 PM UTC 24 |
Aug 22 12:37:42 PM UTC 24 |
5422784214 ps |
| T1092 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.4164620921 |
|
|
Aug 22 12:32:52 PM UTC 24 |
Aug 22 12:38:10 PM UTC 24 |
4173478418 ps |
| T633 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.327325002 |
|
|
Aug 22 12:33:57 PM UTC 24 |
Aug 22 12:38:36 PM UTC 24 |
3298196800 ps |
| T620 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2245864013 |
|
|
Aug 22 12:35:29 PM UTC 24 |
Aug 22 12:40:06 PM UTC 24 |
3247285000 ps |
| T608 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_all_escalation_resets.3641805150 |
|
|
Aug 22 12:33:20 PM UTC 24 |
Aug 22 12:40:43 PM UTC 24 |
5313583928 ps |
| T1093 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_all_escalation_resets.110791749 |
|
|
Aug 22 12:33:51 PM UTC 24 |
Aug 22 12:41:13 PM UTC 24 |
5977566732 ps |
| T614 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3675480172 |
|
|
Aug 22 12:37:36 PM UTC 24 |
Aug 22 12:41:53 PM UTC 24 |
3999282762 ps |
| T622 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1424702993 |
|
|
Aug 22 12:37:21 PM UTC 24 |
Aug 22 12:42:13 PM UTC 24 |
3624474168 ps |
| T1094 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.4153875793 |
|
|
Aug 22 12:38:34 PM UTC 24 |
Aug 22 12:43:15 PM UTC 24 |
3678909228 ps |
| T606 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_all_escalation_resets.839769710 |
|
|
Aug 22 12:37:50 PM UTC 24 |
Aug 22 12:44:42 PM UTC 24 |
5219644408 ps |
| T657 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2786731321 |
|
|
Aug 22 12:41:04 PM UTC 24 |
Aug 22 12:45:31 PM UTC 24 |
4280436360 ps |
| T362 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2043779365 |
|
|
Aug 22 12:41:40 PM UTC 24 |
Aug 22 12:45:39 PM UTC 24 |
3762034048 ps |
| T1095 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_all_escalation_resets.1253063306 |
|
|
Aug 22 12:38:20 PM UTC 24 |
Aug 22 12:45:47 PM UTC 24 |
4946749832 ps |
| T607 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_all_escalation_resets.524223926 |
|
|
Aug 22 12:40:12 PM UTC 24 |
Aug 22 12:46:07 PM UTC 24 |
4482792410 ps |
| T700 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.386988141 |
|
|
Aug 22 12:42:08 PM UTC 24 |
Aug 22 12:46:44 PM UTC 24 |
4350473260 ps |
| T661 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.62824089 |
|
|
Aug 22 12:41:26 PM UTC 24 |
Aug 22 12:46:47 PM UTC 24 |
3981272752 ps |
| T327 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/91.chip_sw_all_escalation_resets.3044385759 |
|
|
Aug 22 12:38:55 PM UTC 24 |
Aug 22 12:46:58 PM UTC 24 |
5390380122 ps |
| T702 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3966771744 |
|
|
Aug 22 12:42:52 PM UTC 24 |
Aug 22 12:47:06 PM UTC 24 |
3674404700 ps |
| T258 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/92.chip_sw_all_escalation_resets.142860893 |
|
|
Aug 22 12:40:04 PM UTC 24 |
Aug 22 12:47:08 PM UTC 24 |
5593697050 ps |
| T328 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1525997232 |
|
|
Aug 22 12:43:25 PM UTC 24 |
Aug 22 12:48:16 PM UTC 24 |
3736535348 ps |
| T683 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3635649944 |
|
|
Aug 22 12:43:48 PM UTC 24 |
Aug 22 12:48:17 PM UTC 24 |
3138315834 ps |
| T699 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/95.chip_sw_all_escalation_resets.1101444139 |
|
|
Aug 22 12:43:11 PM UTC 24 |
Aug 22 12:49:24 PM UTC 24 |
5264708032 ps |
| T102 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.866983258 |
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|
Aug 22 12:44:45 PM UTC 24 |
Aug 22 12:50:05 PM UTC 24 |
3530606750 ps |
| T685 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3528836064 |
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|
Aug 22 12:45:25 PM UTC 24 |
Aug 22 12:50:22 PM UTC 24 |
3628774060 ps |
| T641 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1587455574 |
|
|
Aug 22 12:45:48 PM UTC 24 |
Aug 22 12:50:24 PM UTC 24 |
4336031128 ps |
| T626 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.474522522 |
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|
Aug 22 12:45:17 PM UTC 24 |
Aug 22 12:50:53 PM UTC 24 |
3789610876 ps |
| T655 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/97.chip_sw_all_escalation_resets.2673467187 |
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|
Aug 22 12:43:31 PM UTC 24 |
Aug 22 12:51:42 PM UTC 24 |
6128942856 ps |
| T697 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2472279421 |
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Aug 22 12:48:17 PM UTC 24 |
Aug 22 12:52:37 PM UTC 24 |
3549291200 ps |
| T672 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_all_escalation_resets.1177174213 |
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Aug 22 12:46:35 PM UTC 24 |
Aug 22 12:53:02 PM UTC 24 |
4246383016 ps |
| T613 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_all_escalation_resets.3388577905 |
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Aug 22 12:46:15 PM UTC 24 |
Aug 22 12:53:20 PM UTC 24 |
5738921376 ps |