| T2020 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_zero_delays.3795790446 |
|
|
Aug 21 10:49:54 PM UTC 24 |
Aug 21 10:50:13 PM UTC 24 |
169689519 ps |
| T2021 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device.3798877985 |
|
|
Aug 21 10:48:21 PM UTC 24 |
Aug 21 10:50:24 PM UTC 24 |
2817361980 ps |
| T2022 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all.787568321 |
|
|
Aug 21 10:41:18 PM UTC 24 |
Aug 21 10:50:30 PM UTC 24 |
17244690994 ps |
| T2023 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.2671674517 |
|
|
Aug 21 10:49:26 PM UTC 24 |
Aug 21 10:50:32 PM UTC 24 |
1393313067 ps |
| T2024 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.3454769027 |
|
|
Aug 21 10:48:52 PM UTC 24 |
Aug 21 10:50:32 PM UTC 24 |
6552608011 ps |
| T2025 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_unmapped_addr.1322745408 |
|
|
Aug 21 10:50:11 PM UTC 24 |
Aug 21 10:50:36 PM UTC 24 |
206319235 ps |
| T2026 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all.4027050712 |
|
|
Aug 21 10:49:29 PM UTC 24 |
Aug 21 10:50:44 PM UTC 24 |
2417210446 ps |
| T2027 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_large_delays.987954237 |
|
|
Aug 21 10:48:56 PM UTC 24 |
Aug 21 10:50:46 PM UTC 24 |
8576466005 ps |
| T2028 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.2730827508 |
|
|
Aug 21 10:34:41 PM UTC 24 |
Aug 21 10:50:49 PM UTC 24 |
61201842325 ps |
| T2029 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_random.679299349 |
|
|
Aug 21 10:50:11 PM UTC 24 |
Aug 21 10:50:54 PM UTC 24 |
488306513 ps |
| T2030 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.4027413549 |
|
|
Aug 21 10:49:39 PM UTC 24 |
Aug 21 10:50:56 PM UTC 24 |
4271093819 ps |
| T2031 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_slow_rsp.1568367816 |
|
|
Aug 21 10:37:25 PM UTC 24 |
Aug 21 10:50:59 PM UTC 24 |
46943005834 ps |
| T2032 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_zero_delays.1862992871 |
|
|
Aug 21 10:50:55 PM UTC 24 |
Aug 21 10:51:05 PM UTC 24 |
41196268 ps |
| T2033 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke.1838280521 |
|
|
Aug 21 10:50:55 PM UTC 24 |
Aug 21 10:51:05 PM UTC 24 |
119088701 ps |
| T2034 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_error.1065793318 |
|
|
Aug 21 10:47:41 PM UTC 24 |
Aug 21 10:51:07 PM UTC 24 |
2578632253 ps |
| T2035 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_same_source.1589801047 |
|
|
Aug 21 10:50:12 PM UTC 24 |
Aug 21 10:51:14 PM UTC 24 |
1719786343 ps |
| T2036 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.1928223720 |
|
|
Aug 21 10:50:16 PM UTC 24 |
Aug 21 10:51:19 PM UTC 24 |
1378701502 ps |
| T2037 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.3652707276 |
|
|
Aug 21 10:48:21 PM UTC 24 |
Aug 21 10:51:20 PM UTC 24 |
8641851160 ps |
| T2038 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_large_delays.27834173 |
|
|
Aug 21 10:49:37 PM UTC 24 |
Aug 21 10:51:24 PM UTC 24 |
9497619314 ps |
| T2039 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_zero_delays.3099904533 |
|
|
Aug 21 10:51:06 PM UTC 24 |
Aug 21 10:51:33 PM UTC 24 |
285919098 ps |
| T2040 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random.2292018779 |
|
|
Aug 21 10:51:10 PM UTC 24 |
Aug 21 10:51:34 PM UTC 24 |
179054845 ps |
| T550 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.4051378571 |
|
|
Aug 21 10:42:36 PM UTC 24 |
Aug 21 10:51:46 PM UTC 24 |
13507571530 ps |
| T2041 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_same_source.1204847526 |
|
|
Aug 21 10:51:29 PM UTC 24 |
Aug 21 10:51:48 PM UTC 24 |
399628110 ps |
| T2042 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.3379014465 |
|
|
Aug 21 10:48:37 PM UTC 24 |
Aug 21 10:51:49 PM UTC 24 |
2180799129 ps |
| T2043 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_random.2209414049 |
|
|
Aug 21 10:51:29 PM UTC 24 |
Aug 21 10:51:50 PM UTC 24 |
347581232 ps |
| T2044 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_large_delays.3252363535 |
|
|
Aug 21 10:50:56 PM UTC 24 |
Aug 21 10:51:50 PM UTC 24 |
4583224545 ps |
| T2045 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all.2699319422 |
|
|
Aug 21 10:43:46 PM UTC 24 |
Aug 21 10:51:54 PM UTC 24 |
12032073012 ps |
| T2046 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.1373666143 |
|
|
Aug 21 10:51:01 PM UTC 24 |
Aug 21 10:52:06 PM UTC 24 |
4565621576 ps |
| T2047 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_large_delays.876733224 |
|
|
Aug 21 10:37:24 PM UTC 24 |
Aug 21 10:52:07 PM UTC 24 |
93952973767 ps |
| T2048 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke.2248085640 |
|
|
Aug 21 10:51:55 PM UTC 24 |
Aug 21 10:52:08 PM UTC 24 |
198162108 ps |
| T2049 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_zero_delays.3199022459 |
|
|
Aug 21 10:52:11 PM UTC 24 |
Aug 21 10:52:19 PM UTC 24 |
47421445 ps |
| T2050 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.3217964955 |
|
|
Aug 21 10:50:34 PM UTC 24 |
Aug 21 10:52:20 PM UTC 24 |
316130160 ps |
| T2051 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.4030279842 |
|
|
Aug 21 10:51:36 PM UTC 24 |
Aug 21 10:52:21 PM UTC 24 |
1376812774 ps |
| T2052 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device.707637516 |
|
|
Aug 21 10:51:21 PM UTC 24 |
Aug 21 10:52:22 PM UTC 24 |
1462664289 ps |
| T2053 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_zero_delays.1344285009 |
|
|
Aug 21 10:52:15 PM UTC 24 |
Aug 21 10:52:23 PM UTC 24 |
35356185 ps |
| T2054 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_unmapped_addr.341446883 |
|
|
Aug 21 10:51:32 PM UTC 24 |
Aug 21 10:52:24 PM UTC 24 |
874575369 ps |
| T2055 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device.3012427342 |
|
|
Aug 21 10:50:06 PM UTC 24 |
Aug 21 10:52:33 PM UTC 24 |
3503670610 ps |
| T2056 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random.666987369 |
|
|
Aug 21 10:52:14 PM UTC 24 |
Aug 21 10:52:37 PM UTC 24 |
431829192 ps |
| T2057 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device.833345571 |
|
|
Aug 21 10:52:30 PM UTC 24 |
Aug 21 10:52:41 PM UTC 24 |
221931874 ps |
| T2058 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_error.2992957591 |
|
|
Aug 21 10:51:49 PM UTC 24 |
Aug 21 10:53:13 PM UTC 24 |
2455893896 ps |
| T2059 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.833128661 |
|
|
Aug 21 10:47:46 PM UTC 24 |
Aug 21 10:53:16 PM UTC 24 |
3174350084 ps |
| T2060 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_unmapped_addr.1997260078 |
|
|
Aug 21 10:52:44 PM UTC 24 |
Aug 21 10:53:16 PM UTC 24 |
602132927 ps |
| T2061 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke.2848427857 |
|
|
Aug 21 10:53:05 PM UTC 24 |
Aug 21 10:53:18 PM UTC 24 |
198791171 ps |
| T2062 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.3010135140 |
|
|
Aug 21 10:52:13 PM UTC 24 |
Aug 21 10:53:24 PM UTC 24 |
4215551865 ps |
| T2063 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_same_source.1090183101 |
|
|
Aug 21 10:52:42 PM UTC 24 |
Aug 21 10:53:26 PM UTC 24 |
447375565 ps |
| T2064 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_large_delays.3388657275 |
|
|
Aug 21 10:52:10 PM UTC 24 |
Aug 21 10:53:31 PM UTC 24 |
8197409124 ps |
| T2065 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.2670192707 |
|
|
Aug 21 10:52:46 PM UTC 24 |
Aug 21 10:53:36 PM UTC 24 |
934230871 ps |
| T2066 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_slow_rsp.385935229 |
|
|
Aug 21 10:47:03 PM UTC 24 |
Aug 21 10:53:39 PM UTC 24 |
23071947332 ps |
| T2067 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_error.3309667714 |
|
|
Aug 21 10:50:35 PM UTC 24 |
Aug 21 10:53:44 PM UTC 24 |
4843582269 ps |
| T2068 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_zero_delays.158773299 |
|
|
Aug 21 10:53:38 PM UTC 24 |
Aug 21 10:53:47 PM UTC 24 |
45191071 ps |
| T2069 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_slow_rsp.2397056158 |
|
|
Aug 21 10:38:31 PM UTC 24 |
Aug 21 10:53:50 PM UTC 24 |
53456088989 ps |
| T2070 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_slow_rsp.75396594 |
|
|
Aug 21 10:39:24 PM UTC 24 |
Aug 21 10:53:57 PM UTC 24 |
55096013003 ps |
| T2071 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.1213300114 |
|
|
Aug 21 10:53:00 PM UTC 24 |
Aug 21 10:53:58 PM UTC 24 |
265744246 ps |
| T2072 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_zero_delays.1038413444 |
|
|
Aug 21 10:53:48 PM UTC 24 |
Aug 21 10:53:58 PM UTC 24 |
33537847 ps |
| T2073 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_random.297933176 |
|
|
Aug 21 10:52:43 PM UTC 24 |
Aug 21 10:54:07 PM UTC 24 |
2079691211 ps |
| T2074 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.3125856306 |
|
|
Aug 21 10:51:58 PM UTC 24 |
Aug 21 10:54:13 PM UTC 24 |
365709620 ps |
| T2075 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.2249242788 |
|
|
Aug 21 10:49:09 PM UTC 24 |
Aug 21 10:54:18 PM UTC 24 |
19436805233 ps |
| T2076 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_same_source.2838210352 |
|
|
Aug 21 10:54:07 PM UTC 24 |
Aug 21 10:54:18 PM UTC 24 |
115906192 ps |
| T2077 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.3955887658 |
|
|
Aug 21 10:47:36 PM UTC 24 |
Aug 21 10:54:19 PM UTC 24 |
1445697664 ps |
| T2078 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random.2004570931 |
|
|
Aug 21 10:53:42 PM UTC 24 |
Aug 21 10:54:32 PM UTC 24 |
1506725596 ps |
| T2079 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.3354829207 |
|
|
Aug 21 10:45:13 PM UTC 24 |
Aug 21 10:54:40 PM UTC 24 |
11753811925 ps |
| T2080 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_unmapped_addr.599091287 |
|
|
Aug 21 10:54:13 PM UTC 24 |
Aug 21 10:54:41 PM UTC 24 |
166198763 ps |
| T2081 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.142285377 |
|
|
Aug 21 10:54:21 PM UTC 24 |
Aug 21 10:54:49 PM UTC 24 |
181226793 ps |
| T2082 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke.3453561735 |
|
|
Aug 21 10:54:43 PM UTC 24 |
Aug 21 10:54:52 PM UTC 24 |
47866973 ps |
| T2083 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_zero_delays.2247845087 |
|
|
Aug 21 10:54:43 PM UTC 24 |
Aug 21 10:54:53 PM UTC 24 |
43709634 ps |
| T2084 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_large_delays.1241464386 |
|
|
Aug 21 10:39:21 PM UTC 24 |
Aug 21 10:55:03 PM UTC 24 |
82399147038 ps |
| T2085 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_large_delays.1040911048 |
|
|
Aug 21 10:46:58 PM UTC 24 |
Aug 21 10:55:08 PM UTC 24 |
44606077929 ps |
| T2086 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_large_delays.2413952777 |
|
|
Aug 21 10:48:15 PM UTC 24 |
Aug 21 10:55:08 PM UTC 24 |
42670013405 ps |
| T2087 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_error.1430654402 |
|
|
Aug 21 10:48:27 PM UTC 24 |
Aug 21 10:55:12 PM UTC 24 |
13124737151 ps |
| T2088 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_random.1796586692 |
|
|
Aug 21 10:54:07 PM UTC 24 |
Aug 21 10:55:12 PM UTC 24 |
610133599 ps |
| T2089 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_large_delays.587591394 |
|
|
Aug 21 10:53:40 PM UTC 24 |
Aug 21 10:55:14 PM UTC 24 |
8674378681 ps |
| T2090 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all.4189149925 |
|
|
Aug 21 10:51:44 PM UTC 24 |
Aug 21 10:55:15 PM UTC 24 |
5292125743 ps |
| T2091 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_error.546199939 |
|
|
Aug 21 10:52:57 PM UTC 24 |
Aug 21 10:55:25 PM UTC 24 |
1952240730 ps |
| T2092 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device.1167733119 |
|
|
Aug 21 10:55:18 PM UTC 24 |
Aug 21 10:55:32 PM UTC 24 |
101890413 ps |
| T2093 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.2877667637 |
|
|
Aug 21 10:53:38 PM UTC 24 |
Aug 21 10:55:42 PM UTC 24 |
5451440241 ps |
| T2094 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.3650886000 |
|
|
Aug 21 10:35:43 PM UTC 24 |
Aug 21 10:55:42 PM UTC 24 |
86343545961 ps |
| T2095 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_random.2818177725 |
|
|
Aug 21 10:55:34 PM UTC 24 |
Aug 21 10:55:44 PM UTC 24 |
108236385 ps |
| T2096 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.1053101490 |
|
|
Aug 21 10:46:06 PM UTC 24 |
Aug 21 10:55:47 PM UTC 24 |
8285700627 ps |
| T2097 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_zero_delays.1387704180 |
|
|
Aug 21 10:55:06 PM UTC 24 |
Aug 21 10:55:48 PM UTC 24 |
499926409 ps |
| T800 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.3495361757 |
|
|
Aug 21 10:54:23 PM UTC 24 |
Aug 21 10:55:49 PM UTC 24 |
78737219 ps |
| T2098 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.1604886891 |
|
|
Aug 21 10:55:37 PM UTC 24 |
Aug 21 10:55:53 PM UTC 24 |
221167319 ps |
| T801 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.1655232106 |
|
|
Aug 21 10:49:37 PM UTC 24 |
Aug 21 10:55:56 PM UTC 24 |
4331911694 ps |
| T2099 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_error.4038365514 |
|
|
Aug 21 10:49:30 PM UTC 24 |
Aug 21 10:55:57 PM UTC 24 |
10633628447 ps |
| T2100 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_unmapped_addr.4045684391 |
|
|
Aug 21 10:55:38 PM UTC 24 |
Aug 21 10:55:57 PM UTC 24 |
116527728 ps |
| T2101 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.3073967737 |
|
|
Aug 21 10:48:24 PM UTC 24 |
Aug 21 10:56:03 PM UTC 24 |
9378052571 ps |
| T2102 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_slow_rsp.1823381255 |
|
|
Aug 21 10:43:17 PM UTC 24 |
Aug 21 10:56:11 PM UTC 24 |
55326643745 ps |
| T2103 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device.3026698462 |
|
|
Aug 21 10:54:00 PM UTC 24 |
Aug 21 10:56:15 PM UTC 24 |
3206730059 ps |
| T2104 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke.3431290023 |
|
|
Aug 21 10:56:04 PM UTC 24 |
Aug 21 10:56:15 PM UTC 24 |
213170052 ps |
| T2105 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_large_delays.1985835743 |
|
|
Aug 21 10:49:07 PM UTC 24 |
Aug 21 10:56:15 PM UTC 24 |
44671772139 ps |
| T2106 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_zero_delays.394948124 |
|
|
Aug 21 10:56:06 PM UTC 24 |
Aug 21 10:56:16 PM UTC 24 |
55857847 ps |
| T2107 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random.1706446100 |
|
|
Aug 21 10:55:04 PM UTC 24 |
Aug 21 10:56:20 PM UTC 24 |
1597857017 ps |
| T2108 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_error.3035606775 |
|
|
Aug 21 10:55:50 PM UTC 24 |
Aug 21 10:56:26 PM UTC 24 |
1417256274 ps |
| T2109 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_large_delays.1235350456 |
|
|
Aug 21 10:54:44 PM UTC 24 |
Aug 21 10:56:26 PM UTC 24 |
9323298011 ps |
| T2110 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all.617296794 |
|
|
Aug 21 10:54:23 PM UTC 24 |
Aug 21 10:56:35 PM UTC 24 |
1272037247 ps |
| T2111 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_same_source.2584914380 |
|
|
Aug 21 10:55:33 PM UTC 24 |
Aug 21 10:56:35 PM UTC 24 |
2360174971 ps |
| T2112 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_zero_delays.3221024947 |
|
|
Aug 21 10:56:12 PM UTC 24 |
Aug 21 10:56:37 PM UTC 24 |
297975712 ps |
| T2113 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_error.1928124552 |
|
|
Aug 21 10:54:32 PM UTC 24 |
Aug 21 10:56:39 PM UTC 24 |
3705774237 ps |
| T2114 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_large_delays.807349092 |
|
|
Aug 21 10:41:42 PM UTC 24 |
Aug 21 10:56:42 PM UTC 24 |
78460096147 ps |
| T2115 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.3703306113 |
|
|
Aug 21 10:55:36 PM UTC 24 |
Aug 21 10:56:45 PM UTC 24 |
88981643 ps |
| T2116 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_unmapped_addr.995797721 |
|
|
Aug 21 10:56:37 PM UTC 24 |
Aug 21 10:56:46 PM UTC 24 |
47587645 ps |
| T2117 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.336355085 |
|
|
Aug 21 10:54:58 PM UTC 24 |
Aug 21 10:56:56 PM UTC 24 |
5224705939 ps |
| T2118 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke.537558272 |
|
|
Aug 21 10:56:47 PM UTC 24 |
Aug 21 10:56:57 PM UTC 24 |
48667300 ps |
| T2119 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device.3518338103 |
|
|
Aug 21 10:56:20 PM UTC 24 |
Aug 21 10:57:02 PM UTC 24 |
475063205 ps |
| T2120 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.3004198721 |
|
|
Aug 21 10:16:21 PM UTC 24 |
Aug 21 10:57:03 PM UTC 24 |
163061219627 ps |
| T2121 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_zero_delays.1621970639 |
|
|
Aug 21 10:56:57 PM UTC 24 |
Aug 21 10:57:04 PM UTC 24 |
42923611 ps |
| T2122 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random.2516076590 |
|
|
Aug 21 10:56:57 PM UTC 24 |
Aug 21 10:57:11 PM UTC 24 |
121306802 ps |
| T2123 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_random.2753599386 |
|
|
Aug 21 10:56:32 PM UTC 24 |
Aug 21 10:57:16 PM UTC 24 |
1410988248 ps |
| T2124 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random.2373720642 |
|
|
Aug 21 10:56:13 PM UTC 24 |
Aug 21 10:57:17 PM UTC 24 |
549657751 ps |
| T2125 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.364413562 |
|
|
Aug 21 10:56:11 PM UTC 24 |
Aug 21 10:57:24 PM UTC 24 |
5597809344 ps |
| T2126 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.3720301615 |
|
|
Aug 21 10:56:40 PM UTC 24 |
Aug 21 10:57:26 PM UTC 24 |
942663938 ps |
| T2127 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_large_delays.3175375030 |
|
|
Aug 21 10:56:08 PM UTC 24 |
Aug 21 10:57:34 PM UTC 24 |
9050397291 ps |
| T2128 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all.2269698983 |
|
|
Aug 21 10:52:42 PM UTC 24 |
Aug 21 10:57:36 PM UTC 24 |
8307502248 ps |
| T2129 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.2101919109 |
|
|
Aug 21 10:55:57 PM UTC 24 |
Aug 21 10:57:38 PM UTC 24 |
196752630 ps |
| T2130 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.2963658562 |
|
|
Aug 21 10:57:35 PM UTC 24 |
Aug 21 10:57:45 PM UTC 24 |
78041854 ps |
| T2131 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_same_source.2771323183 |
|
|
Aug 21 10:56:26 PM UTC 24 |
Aug 21 10:57:46 PM UTC 24 |
2493020118 ps |
| T2132 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_large_delays.661993553 |
|
|
Aug 21 10:53:48 PM UTC 24 |
Aug 21 10:57:48 PM UTC 24 |
26310810565 ps |
| T2133 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all.2642224513 |
|
|
Aug 21 10:48:26 PM UTC 24 |
Aug 21 10:57:49 PM UTC 24 |
13988359675 ps |
| T2134 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_unmapped_addr.2482391530 |
|
|
Aug 21 10:57:29 PM UTC 24 |
Aug 21 10:57:52 PM UTC 24 |
188554532 ps |
| T2135 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_zero_delays.3706629206 |
|
|
Aug 21 10:57:05 PM UTC 24 |
Aug 21 10:57:54 PM UTC 24 |
577664066 ps |
| T2136 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all.1746235508 |
|
|
Aug 21 10:50:24 PM UTC 24 |
Aug 21 10:58:05 PM UTC 24 |
11150200317 ps |
| T2137 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_same_source.4040567794 |
|
|
Aug 21 10:57:25 PM UTC 24 |
Aug 21 10:58:06 PM UTC 24 |
1288134879 ps |
| T2138 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.1190312906 |
|
|
Aug 21 10:57:47 PM UTC 24 |
Aug 21 10:58:07 PM UTC 24 |
31995519 ps |
| T2139 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke.1229035283 |
|
|
Aug 21 10:57:58 PM UTC 24 |
Aug 21 10:58:08 PM UTC 24 |
56879433 ps |
| T2140 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_random.151423906 |
|
|
Aug 21 10:57:26 PM UTC 24 |
Aug 21 10:58:10 PM UTC 24 |
855529914 ps |
| T2141 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_zero_delays.3105917365 |
|
|
Aug 21 10:58:02 PM UTC 24 |
Aug 21 10:58:11 PM UTC 24 |
44045601 ps |
| T2142 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.3147892270 |
|
|
Aug 21 10:40:45 PM UTC 24 |
Aug 21 10:58:11 PM UTC 24 |
66105852592 ps |
| T2143 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.3597279976 |
|
|
Aug 21 10:57:00 PM UTC 24 |
Aug 21 10:58:37 PM UTC 24 |
4294509197 ps |
| T2144 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_large_delays.2800722813 |
|
|
Aug 21 10:56:58 PM UTC 24 |
Aug 21 10:58:38 PM UTC 24 |
9022548326 ps |
| T2145 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all.3082368145 |
|
|
Aug 21 10:55:40 PM UTC 24 |
Aug 21 10:58:39 PM UTC 24 |
5673120306 ps |
| T2146 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.922298579 |
|
|
Aug 21 10:54:38 PM UTC 24 |
Aug 21 10:58:41 PM UTC 24 |
807865855 ps |
| T2147 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device.3736801799 |
|
|
Aug 21 10:57:16 PM UTC 24 |
Aug 21 10:58:51 PM UTC 24 |
2553848441 ps |
| T2148 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_large_delays.1332052297 |
|
|
Aug 21 10:44:30 PM UTC 24 |
Aug 21 10:58:59 PM UTC 24 |
82565774778 ps |
| T2149 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_unmapped_addr.403486798 |
|
|
Aug 21 10:58:32 PM UTC 24 |
Aug 21 10:59:01 PM UTC 24 |
269991041 ps |
| T2150 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_zero_delays.3050767102 |
|
|
Aug 21 10:58:14 PM UTC 24 |
Aug 21 10:59:03 PM UTC 24 |
392915491 ps |
| T2151 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random.361541342 |
|
|
Aug 21 10:58:11 PM UTC 24 |
Aug 21 10:59:05 PM UTC 24 |
1298396909 ps |
| T2152 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke.1001256953 |
|
|
Aug 21 10:59:02 PM UTC 24 |
Aug 21 10:59:11 PM UTC 24 |
48686488 ps |
| T2153 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.3928405848 |
|
|
Aug 21 10:58:32 PM UTC 24 |
Aug 21 10:59:15 PM UTC 24 |
753136157 ps |
| T2154 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_zero_delays.2396315607 |
|
|
Aug 21 10:59:05 PM UTC 24 |
Aug 21 10:59:15 PM UTC 24 |
55881038 ps |
| T2155 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_error.2962311731 |
|
|
Aug 21 10:57:47 PM UTC 24 |
Aug 21 10:59:22 PM UTC 24 |
3097206469 ps |
| T2156 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device.1134813483 |
|
|
Aug 21 10:58:17 PM UTC 24 |
Aug 21 10:59:25 PM UTC 24 |
613164596 ps |
| T2157 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.794012239 |
|
|
Aug 21 10:59:03 PM UTC 24 |
Aug 21 10:59:31 PM UTC 24 |
151794184 ps |
| T2158 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_slow_rsp.4007482061 |
|
|
Aug 21 10:52:31 PM UTC 24 |
Aug 21 10:59:37 PM UTC 24 |
25934367996 ps |
| T2159 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_random.307860596 |
|
|
Aug 21 10:58:29 PM UTC 24 |
Aug 21 10:59:41 PM UTC 24 |
2166765811 ps |
| T2160 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random.501094457 |
|
|
Aug 21 10:59:23 PM UTC 24 |
Aug 21 10:59:49 PM UTC 24 |
170405701 ps |
| T2161 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_large_delays.957850955 |
|
|
Aug 21 10:58:03 PM UTC 24 |
Aug 21 10:59:50 PM UTC 24 |
6616886087 ps |
| T2162 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_same_source.4225384121 |
|
|
Aug 21 10:58:30 PM UTC 24 |
Aug 21 10:59:55 PM UTC 24 |
2187868499 ps |
| T2163 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.221021633 |
|
|
Aug 21 10:58:08 PM UTC 24 |
Aug 21 10:59:55 PM UTC 24 |
6166777867 ps |
| T2164 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.3257715538 |
|
|
Aug 21 10:27:50 PM UTC 24 |
Aug 21 11:00:00 PM UTC 24 |
119189233131 ps |
| T2165 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_error.2196970889 |
|
|
Aug 21 10:56:40 PM UTC 24 |
Aug 21 11:00:26 PM UTC 24 |
2618432524 ps |
| T2166 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device.1412411544 |
|
|
Aug 21 10:59:39 PM UTC 24 |
Aug 21 11:00:26 PM UTC 24 |
517334015 ps |
| T2167 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke.3247792922 |
|
|
Aug 21 11:00:20 PM UTC 24 |
Aug 21 11:00:29 PM UTC 24 |
51211003 ps |
| T2168 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_zero_delays.2927491731 |
|
|
Aug 21 10:59:27 PM UTC 24 |
Aug 21 11:00:31 PM UTC 24 |
574226729 ps |
| T2169 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.1225344408 |
|
|
Aug 21 10:51:45 PM UTC 24 |
Aug 21 11:00:31 PM UTC 24 |
3157231530 ps |
| T2170 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_same_source.3854731211 |
|
|
Aug 21 10:59:45 PM UTC 24 |
Aug 21 11:00:32 PM UTC 24 |
562724801 ps |
| T2171 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_random.2869800945 |
|
|
Aug 21 10:59:49 PM UTC 24 |
Aug 21 11:00:35 PM UTC 24 |
1510761589 ps |
| T2172 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_zero_delays.3156226663 |
|
|
Aug 21 11:00:25 PM UTC 24 |
Aug 21 11:00:35 PM UTC 24 |
42451009 ps |
| T812 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.3319036730 |
|
|
Aug 21 10:57:38 PM UTC 24 |
Aug 21 11:00:36 PM UTC 24 |
368284923 ps |
| T2173 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.192071193 |
|
|
Aug 21 10:59:23 PM UTC 24 |
Aug 21 11:00:40 PM UTC 24 |
4547038220 ps |
| T2174 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_unmapped_addr.2569920676 |
|
|
Aug 21 10:59:54 PM UTC 24 |
Aug 21 11:00:44 PM UTC 24 |
940939796 ps |
| T2175 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.2748538104 |
|
|
Aug 21 11:00:02 PM UTC 24 |
Aug 21 11:00:44 PM UTC 24 |
327389459 ps |
| T2176 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random.2566608817 |
|
|
Aug 21 11:00:52 PM UTC 24 |
Aug 21 11:01:04 PM UTC 24 |
68950070 ps |
| T2177 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_zero_delays.2658402144 |
|
|
Aug 21 11:00:56 PM UTC 24 |
Aug 21 11:01:12 PM UTC 24 |
95367498 ps |
| T2178 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_large_delays.1143217247 |
|
|
Aug 21 10:59:11 PM UTC 24 |
Aug 21 11:01:15 PM UTC 24 |
8979137765 ps |
| T2179 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_slow_rsp.3006980198 |
|
|
Aug 21 10:44:35 PM UTC 24 |
Aug 21 11:01:32 PM UTC 24 |
62470346078 ps |
| T2180 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_same_source.1976263258 |
|
|
Aug 21 11:01:00 PM UTC 24 |
Aug 21 11:01:39 PM UTC 24 |
1358716425 ps |
| T2181 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_unmapped_addr.4248584594 |
|
|
Aug 21 11:01:05 PM UTC 24 |
Aug 21 11:01:43 PM UTC 24 |
221207651 ps |
| T2182 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.375131617 |
|
|
Aug 21 11:01:07 PM UTC 24 |
Aug 21 11:01:44 PM UTC 24 |
638778844 ps |
| T2183 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_random.2969550504 |
|
|
Aug 21 11:01:02 PM UTC 24 |
Aug 21 11:01:59 PM UTC 24 |
1359539044 ps |
| T2184 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_slow_rsp.95519611 |
|
|
Aug 21 10:45:43 PM UTC 24 |
Aug 21 11:02:02 PM UTC 24 |
65880415043 ps |
| T2185 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all.1750916912 |
|
|
Aug 21 10:58:35 PM UTC 24 |
Aug 21 11:02:06 PM UTC 24 |
5862256278 ps |
| T2186 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_large_delays.1674202634 |
|
|
Aug 21 11:00:50 PM UTC 24 |
Aug 21 11:02:11 PM UTC 24 |
9325773160 ps |
| T2187 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device.5122759 |
|
|
Aug 21 11:00:59 PM UTC 24 |
Aug 21 11:02:12 PM UTC 24 |
1740162571 ps |
| T2188 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke.1910816644 |
|
|
Aug 21 11:02:03 PM UTC 24 |
Aug 21 11:02:16 PM UTC 24 |
170223158 ps |
| T2189 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_zero_delays.3580362615 |
|
|
Aug 21 11:02:08 PM UTC 24 |
Aug 21 11:02:17 PM UTC 24 |
48539003 ps |
| T2190 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.3601202526 |
|
|
Aug 21 10:52:47 PM UTC 24 |
Aug 21 11:02:18 PM UTC 24 |
8837368171 ps |
| T2191 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all.3675727125 |
|
|
Aug 21 10:57:38 PM UTC 24 |
Aug 21 11:02:21 PM UTC 24 |
8016209493 ps |
| T2192 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_large_delays.1526220129 |
|
|
Aug 21 10:55:14 PM UTC 24 |
Aug 21 11:02:26 PM UTC 24 |
44771395352 ps |
| T2193 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.3950115810 |
|
|
Aug 21 10:50:49 PM UTC 24 |
Aug 21 11:02:39 PM UTC 24 |
7993197813 ps |
| T2194 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.2438889960 |
|
|
Aug 21 11:00:49 PM UTC 24 |
Aug 21 11:02:43 PM UTC 24 |
5457053766 ps |
| T2195 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random.2342719591 |
|
|
Aug 21 11:02:25 PM UTC 24 |
Aug 21 11:02:55 PM UTC 24 |
266033212 ps |
| T2196 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all.3178306610 |
|
|
Aug 21 11:01:29 PM UTC 24 |
Aug 21 11:02:56 PM UTC 24 |
1160540437 ps |
| T2197 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_slow_rsp.2384938182 |
|
|
Aug 21 10:49:06 PM UTC 24 |
Aug 21 11:02:59 PM UTC 24 |
52525493043 ps |
| T2198 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_zero_delays.1530810707 |
|
|
Aug 21 11:02:27 PM UTC 24 |
Aug 21 11:03:02 PM UTC 24 |
293057458 ps |
| T2199 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_large_delays.3515679454 |
|
|
Aug 21 10:56:14 PM UTC 24 |
Aug 21 11:03:06 PM UTC 24 |
42328166742 ps |
| T2200 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_slow_rsp.3342411285 |
|
|
Aug 21 10:51:19 PM UTC 24 |
Aug 21 11:03:06 PM UTC 24 |
43915534485 ps |
| T2201 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_slow_rsp.3792742488 |
|
|
Aug 21 10:55:17 PM UTC 24 |
Aug 21 11:03:12 PM UTC 24 |
33307023362 ps |
| T2202 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_same_source.1985681952 |
|
|
Aug 21 11:02:42 PM UTC 24 |
Aug 21 11:03:28 PM UTC 24 |
511139474 ps |
| T2203 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_random.3241679683 |
|
|
Aug 21 11:02:43 PM UTC 24 |
Aug 21 11:03:31 PM UTC 24 |
1009839835 ps |
| T2204 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_large_delays.2291878445 |
|
|
Aug 21 11:02:06 PM UTC 24 |
Aug 21 11:03:34 PM UTC 24 |
8304912640 ps |
| T2205 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_slow_rsp.1966876789 |
|
|
Aug 21 10:50:06 PM UTC 24 |
Aug 21 11:03:34 PM UTC 24 |
59122744017 ps |
| T2206 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_zero_delays.3964097901 |
|
|
Aug 21 11:03:30 PM UTC 24 |
Aug 21 11:03:36 PM UTC 24 |
34609344 ps |
| T2207 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_unmapped_addr.2351489694 |
|
|
Aug 21 11:02:47 PM UTC 24 |
Aug 21 11:03:40 PM UTC 24 |
1008726152 ps |
| T2208 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all.1142811900 |
|
|
Aug 21 11:00:06 PM UTC 24 |
Aug 21 11:03:40 PM UTC 24 |
6488539615 ps |
| T2209 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke.3090368965 |
|
|
Aug 21 11:03:28 PM UTC 24 |
Aug 21 11:03:42 PM UTC 24 |
216752511 ps |
| T2210 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.952873967 |
|
|
Aug 21 11:03:05 PM UTC 24 |
Aug 21 11:03:44 PM UTC 24 |
747639846 ps |
| T2211 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device.2992668865 |
|
|
Aug 21 11:02:39 PM UTC 24 |
Aug 21 11:03:47 PM UTC 24 |
2011060921 ps |
| T795 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.714814910 |
|
|
Aug 21 10:49:30 PM UTC 24 |
Aug 21 11:03:51 PM UTC 24 |
16302513432 ps |
| T2212 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.3160198170 |
|
|
Aug 21 11:02:23 PM UTC 24 |
Aug 21 11:03:58 PM UTC 24 |
4913669158 ps |
| T2213 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.1248683874 |
|
|
Aug 21 11:00:20 PM UTC 24 |
Aug 21 11:03:58 PM UTC 24 |
1664048741 ps |
| T2214 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.2152691404 |
|
|
Aug 21 11:00:14 PM UTC 24 |
Aug 21 11:04:00 PM UTC 24 |
330623979 ps |
| T2215 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_error.539449689 |
|
|
Aug 21 11:00:15 PM UTC 24 |
Aug 21 11:04:12 PM UTC 24 |
5844558669 ps |
| T2216 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random.624450489 |
|
|
Aug 21 11:03:52 PM UTC 24 |
Aug 21 11:04:22 PM UTC 24 |
304037600 ps |
| T2217 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_large_delays.1885491882 |
|
|
Aug 21 11:03:31 PM UTC 24 |
Aug 21 11:04:26 PM UTC 24 |
6124410052 ps |
| T2218 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_large_delays.3801980382 |
|
|
Aug 21 10:52:12 PM UTC 24 |
Aug 21 11:04:31 PM UTC 24 |
77342090148 ps |
| T2219 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.283920243 |
|
|
Aug 21 11:04:12 PM UTC 24 |
Aug 21 11:04:40 PM UTC 24 |
636203652 ps |
| T2220 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all.3077912096 |
|
|
Aug 21 11:03:03 PM UTC 24 |
Aug 21 11:04:44 PM UTC 24 |
3179269068 ps |
| T2221 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_zero_delays.980784891 |
|
|
Aug 21 11:03:56 PM UTC 24 |
Aug 21 11:04:45 PM UTC 24 |
410191430 ps |
| T2222 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke.1427505732 |
|
|
Aug 21 11:04:33 PM UTC 24 |
Aug 21 11:04:49 PM UTC 24 |
240196651 ps |
| T2223 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_unmapped_addr.22625515 |
|
|
Aug 21 11:04:04 PM UTC 24 |
Aug 21 11:04:52 PM UTC 24 |
859040383 ps |
| T2224 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_zero_delays.2932037219 |
|
|
Aug 21 11:04:45 PM UTC 24 |
Aug 21 11:04:53 PM UTC 24 |
40796535 ps |
| T2225 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_large_delays.1065274484 |
|
|
Aug 21 10:50:01 PM UTC 24 |
Aug 21 11:04:56 PM UTC 24 |
94699351151 ps |
| T813 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.1457757815 |
|
|
Aug 21 10:56:48 PM UTC 24 |
Aug 21 11:05:01 PM UTC 24 |
8701806608 ps |
| T2226 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.3298004444 |
|
|
Aug 21 11:03:37 PM UTC 24 |
Aug 21 11:05:03 PM UTC 24 |
5463876257 ps |
| T2227 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_error.1760016835 |
|
|
Aug 21 10:58:58 PM UTC 24 |
Aug 21 11:05:05 PM UTC 24 |
10571489015 ps |
| T2228 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_random.3974356801 |
|
|
Aug 21 11:04:06 PM UTC 24 |
Aug 21 11:05:08 PM UTC 24 |
1924305851 ps |
| T2229 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_same_source.929208753 |
|
|
Aug 21 11:04:02 PM UTC 24 |
Aug 21 11:05:21 PM UTC 24 |
2548187034 ps |
| T2230 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device.1736888302 |
|
|
Aug 21 11:04:00 PM UTC 24 |
Aug 21 11:05:26 PM UTC 24 |
1159138771 ps |
| T2231 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.4238062756 |
|
|
Aug 21 11:01:38 PM UTC 24 |
Aug 21 11:05:27 PM UTC 24 |
4023406482 ps |
| T2232 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_zero_delays.68345966 |
|
|
Aug 21 11:05:10 PM UTC 24 |
Aug 21 11:05:28 PM UTC 24 |
122497972 ps |
| T2233 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random.3572276776 |
|
|
Aug 21 11:05:04 PM UTC 24 |
Aug 21 11:05:31 PM UTC 24 |
339614114 ps |
| T2234 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_random.1327101281 |
|
|
Aug 21 11:05:24 PM UTC 24 |
Aug 21 11:05:34 PM UTC 24 |
82305851 ps |
| T2235 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_unmapped_addr.2495057657 |
|
|
Aug 21 11:05:26 PM UTC 24 |
Aug 21 11:05:41 PM UTC 24 |
62686442 ps |
| T2236 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_aliasing.2754839919 |
|
|
Aug 21 09:12:11 PM UTC 24 |
Aug 21 11:05:50 PM UTC 24 |
40628083682 ps |
| T2237 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_slow_rsp.463672313 |
|
|
Aug 21 10:57:08 PM UTC 24 |
Aug 21 11:05:51 PM UTC 24 |
34749366600 ps |
| T2238 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_large_delays.3594467187 |
|
|
Aug 21 10:45:48 PM UTC 24 |
Aug 21 11:05:51 PM UTC 24 |
109247804013 ps |
| T2239 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_slow_rsp.1928177148 |
|
|
Aug 21 10:58:16 PM UTC 24 |
Aug 21 11:05:52 PM UTC 24 |
28946038603 ps |
| T2240 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_same_source.2699511869 |
|
|
Aug 21 11:05:21 PM UTC 24 |
Aug 21 11:05:54 PM UTC 24 |
1168549454 ps |
| T2241 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.708676219 |
|
|
Aug 21 10:57:22 PM UTC 24 |
Aug 21 11:05:58 PM UTC 24 |
29633128340 ps |
| T2242 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke.1506307401 |
|
|
Aug 21 11:05:49 PM UTC 24 |
Aug 21 11:06:01 PM UTC 24 |
244604003 ps |
| T2243 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_zero_delays.4274374718 |
|
|
Aug 21 11:05:54 PM UTC 24 |
Aug 21 11:06:01 PM UTC 24 |
48249372 ps |
| T2244 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.3414621329 |
|
|
Aug 21 11:05:30 PM UTC 24 |
Aug 21 11:06:09 PM UTC 24 |
269439547 ps |
| T2245 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_error.4109927660 |
|
|
Aug 21 11:01:40 PM UTC 24 |
Aug 21 11:06:17 PM UTC 24 |
7339275573 ps |
| T2246 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_large_delays.2178032870 |
|
|
Aug 21 11:04:51 PM UTC 24 |
Aug 21 11:06:23 PM UTC 24 |
9011380429 ps |
| T2247 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all.226146915 |
|
|
Aug 21 10:56:34 PM UTC 24 |
Aug 21 11:06:24 PM UTC 24 |
16433911717 ps |
| T2248 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_error.1954724692 |
|
|
Aug 21 11:04:22 PM UTC 24 |
Aug 21 11:06:39 PM UTC 24 |
1767654756 ps |
| T2249 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.1637813275 |
|
|
Aug 21 11:04:52 PM UTC 24 |
Aug 21 11:06:43 PM UTC 24 |
5828487752 ps |
| T2250 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device.457047664 |
|
|
Aug 21 11:05:17 PM UTC 24 |
Aug 21 11:06:51 PM UTC 24 |
2608438091 ps |
| T2251 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_zero_delays.289502276 |
|
|
Aug 21 11:06:13 PM UTC 24 |
Aug 21 11:06:51 PM UTC 24 |
337347963 ps |
| T2252 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device.1695989787 |
|
|
Aug 21 11:06:16 PM UTC 24 |
Aug 21 11:06:57 PM UTC 24 |
407280135 ps |
| T2253 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.221761202 |
|
|
Aug 21 11:06:02 PM UTC 24 |
Aug 21 11:06:58 PM UTC 24 |
3848267537 ps |
| T2254 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_error.1037366166 |
|
|
Aug 21 11:03:19 PM UTC 24 |
Aug 21 11:07:03 PM UTC 24 |
2642736059 ps |
| T2255 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_same_source.4115057849 |
|
|
Aug 21 11:06:25 PM UTC 24 |
Aug 21 11:07:10 PM UTC 24 |
595555875 ps |
| T2256 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_random.1304081950 |
|
|
Aug 21 11:06:21 PM UTC 24 |
Aug 21 11:07:11 PM UTC 24 |
1656927499 ps |
| T2257 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random.2726375593 |
|
|
Aug 21 11:06:13 PM UTC 24 |
Aug 21 11:07:13 PM UTC 24 |
1579296984 ps |
| T2258 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.946067258 |
|
|
Aug 21 11:06:42 PM UTC 24 |
Aug 21 11:07:15 PM UTC 24 |
241762523 ps |
| T2259 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.364171651 |
|
|
Aug 21 11:04:02 PM UTC 24 |
Aug 21 11:07:15 PM UTC 24 |
11899946506 ps |
| T2260 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_unmapped_addr.1701269606 |
|
|
Aug 21 11:06:34 PM UTC 24 |
Aug 21 11:07:19 PM UTC 24 |
845770677 ps |
| T2261 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_zero_delays.1751751264 |
|
|
Aug 21 11:07:13 PM UTC 24 |
Aug 21 11:07:23 PM UTC 24 |
43362919 ps |
| T2262 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke.237363793 |
|
|
Aug 21 11:07:14 PM UTC 24 |
Aug 21 11:07:25 PM UTC 24 |
123033441 ps |
| T2263 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.3465688341 |
|
|
Aug 21 10:58:36 PM UTC 24 |
Aug 21 11:07:33 PM UTC 24 |
4615838312 ps |