| T1780 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.3872173260 |
|
|
Aug 21 10:33:10 PM UTC 24 |
Aug 21 10:34:50 PM UTC 24 |
5138226640 ps |
| T1781 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.1279825365 |
|
|
Aug 21 10:34:52 PM UTC 24 |
Aug 21 10:35:05 PM UTC 24 |
68858298 ps |
| T1782 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_same_source.3088777299 |
|
|
Aug 21 10:34:49 PM UTC 24 |
Aug 21 10:35:08 PM UTC 24 |
409168933 ps |
| T1783 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all.3206311903 |
|
|
Aug 21 10:34:59 PM UTC 24 |
Aug 21 10:35:09 PM UTC 24 |
48440034 ps |
| T1784 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.2833473596 |
|
|
Aug 21 10:17:33 PM UTC 24 |
Aug 21 10:35:11 PM UTC 24 |
68640480184 ps |
| T1785 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_error.518829536 |
|
|
Aug 21 10:34:05 PM UTC 24 |
Aug 21 10:35:11 PM UTC 24 |
800006372 ps |
| T1786 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_unmapped_addr.3409202642 |
|
|
Aug 21 10:34:51 PM UTC 24 |
Aug 21 10:35:15 PM UTC 24 |
181189633 ps |
| T1787 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random.758504606 |
|
|
Aug 21 10:34:28 PM UTC 24 |
Aug 21 10:35:19 PM UTC 24 |
451118988 ps |
| T1788 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_zero_delays.1353342143 |
|
|
Aug 21 10:34:28 PM UTC 24 |
Aug 21 10:35:19 PM UTC 24 |
572095835 ps |
| T1789 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke.1371039643 |
|
|
Aug 21 10:35:12 PM UTC 24 |
Aug 21 10:35:20 PM UTC 24 |
49199554 ps |
| T747 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.2921902358 |
|
|
Aug 21 10:20:55 PM UTC 24 |
Aug 21 10:35:21 PM UTC 24 |
52515521847 ps |
| T1790 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_error.3904279290 |
|
|
Aug 21 10:35:12 PM UTC 24 |
Aug 21 10:35:25 PM UTC 24 |
224307778 ps |
| T1791 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_random.1848784931 |
|
|
Aug 21 10:34:51 PM UTC 24 |
Aug 21 10:35:28 PM UTC 24 |
1068037981 ps |
| T1792 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_error.1086062679 |
|
|
Aug 21 10:32:49 PM UTC 24 |
Aug 21 10:35:37 PM UTC 24 |
2137395163 ps |
| T1793 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_slow_rsp.858243752 |
|
|
Aug 21 10:17:32 PM UTC 24 |
Aug 21 10:35:37 PM UTC 24 |
67767961134 ps |
| T1794 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_zero_delays.868903181 |
|
|
Aug 21 10:35:30 PM UTC 24 |
Aug 21 10:35:39 PM UTC 24 |
36554090 ps |
| T1795 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.2148263810 |
|
|
Aug 21 10:19:53 PM UTC 24 |
Aug 21 10:35:39 PM UTC 24 |
63914933978 ps |
| T1796 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all.2892174734 |
|
|
Aug 21 10:28:05 PM UTC 24 |
Aug 21 10:35:44 PM UTC 24 |
13140455656 ps |
| T1797 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device.3830267988 |
|
|
Aug 21 10:33:29 PM UTC 24 |
Aug 21 10:35:47 PM UTC 24 |
3049367847 ps |
| T1798 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random.4180067082 |
|
|
Aug 21 10:35:35 PM UTC 24 |
Aug 21 10:35:47 PM UTC 24 |
315847342 ps |
| T1799 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_slow_rsp.441351875 |
|
|
Aug 21 10:29:02 PM UTC 24 |
Aug 21 10:35:49 PM UTC 24 |
27505276553 ps |
| T1800 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.4032073531 |
|
|
Aug 21 10:34:22 PM UTC 24 |
Aug 21 10:35:50 PM UTC 24 |
4839964435 ps |
| T1801 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_zero_delays.2498519697 |
|
|
Aug 21 10:35:35 PM UTC 24 |
Aug 21 10:35:56 PM UTC 24 |
191958335 ps |
| T1802 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device.4235601050 |
|
|
Aug 21 10:34:38 PM UTC 24 |
Aug 21 10:35:58 PM UTC 24 |
746357047 ps |
| T1803 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device.3960561428 |
|
|
Aug 21 10:35:44 PM UTC 24 |
Aug 21 10:35:58 PM UTC 24 |
289572475 ps |
| T1804 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_unmapped_addr.1340112362 |
|
|
Aug 21 10:35:50 PM UTC 24 |
Aug 21 10:36:00 PM UTC 24 |
34841904 ps |
| T1805 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.3876957540 |
|
|
Aug 21 10:34:02 PM UTC 24 |
Aug 21 10:36:06 PM UTC 24 |
232263100 ps |
| T1806 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_large_delays.1870992258 |
|
|
Aug 21 10:34:21 PM UTC 24 |
Aug 21 10:36:09 PM UTC 24 |
8726439123 ps |
| T1807 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_zero_delays.2025323654 |
|
|
Aug 21 10:36:07 PM UTC 24 |
Aug 21 10:36:14 PM UTC 24 |
39833975 ps |
| T1808 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke.1435960670 |
|
|
Aug 21 10:36:10 PM UTC 24 |
Aug 21 10:36:18 PM UTC 24 |
50536973 ps |
| T1809 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_random.312316149 |
|
|
Aug 21 10:35:49 PM UTC 24 |
Aug 21 10:36:19 PM UTC 24 |
298911249 ps |
| T1810 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_error.1567846421 |
|
|
Aug 21 10:31:28 PM UTC 24 |
Aug 21 10:36:23 PM UTC 24 |
8408737395 ps |
| T1811 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.1526030864 |
|
|
Aug 21 10:35:58 PM UTC 24 |
Aug 21 10:36:25 PM UTC 24 |
809494403 ps |
| T1812 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.140578889 |
|
|
Aug 21 10:30:48 PM UTC 24 |
Aug 21 10:36:26 PM UTC 24 |
19022127232 ps |
| T1813 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.4175678616 |
|
|
Aug 21 10:35:32 PM UTC 24 |
Aug 21 10:36:30 PM UTC 24 |
3342336560 ps |
| T1814 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_slow_rsp.837847046 |
|
|
Aug 21 10:20:52 PM UTC 24 |
Aug 21 10:36:34 PM UTC 24 |
61566722214 ps |
| T1815 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_large_delays.3172353736 |
|
|
Aug 21 10:25:01 PM UTC 24 |
Aug 21 10:36:40 PM UTC 24 |
69689324206 ps |
| T1816 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.2372257946 |
|
|
Aug 21 10:36:02 PM UTC 24 |
Aug 21 10:36:45 PM UTC 24 |
75677801 ps |
| T1817 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all.2870892631 |
|
|
Aug 21 10:27:09 PM UTC 24 |
Aug 21 10:36:49 PM UTC 24 |
14646636336 ps |
| T1818 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random.3552336671 |
|
|
Aug 21 10:36:16 PM UTC 24 |
Aug 21 10:36:49 PM UTC 24 |
1093598869 ps |
| T1819 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_slow_rsp.2565273259 |
|
|
Aug 21 10:22:25 PM UTC 24 |
Aug 21 10:36:54 PM UTC 24 |
59161893035 ps |
| T1820 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_same_source.3784485200 |
|
|
Aug 21 10:35:45 PM UTC 24 |
Aug 21 10:36:57 PM UTC 24 |
1760887327 ps |
| T1821 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_zero_delays.2813140462 |
|
|
Aug 21 10:36:20 PM UTC 24 |
Aug 21 10:37:01 PM UTC 24 |
428197005 ps |
| T1822 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_large_delays.193698184 |
|
|
Aug 21 10:35:31 PM UTC 24 |
Aug 21 10:37:01 PM UTC 24 |
6187516505 ps |
| T1823 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_large_delays.589789073 |
|
|
Aug 21 10:33:17 PM UTC 24 |
Aug 21 10:37:06 PM UTC 24 |
17603368306 ps |
| T1824 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke.2003817432 |
|
|
Aug 21 10:37:02 PM UTC 24 |
Aug 21 10:37:14 PM UTC 24 |
215963002 ps |
| T1825 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_same_source.972093701 |
|
|
Aug 21 10:36:38 PM UTC 24 |
Aug 21 10:37:15 PM UTC 24 |
340448165 ps |
| T1826 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_zero_delays.364101063 |
|
|
Aug 21 10:37:09 PM UTC 24 |
Aug 21 10:37:18 PM UTC 24 |
42991878 ps |
| T1827 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_large_delays.2397018763 |
|
|
Aug 21 10:23:41 PM UTC 24 |
Aug 21 10:37:18 PM UTC 24 |
83607548318 ps |
| T1828 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_random.75759403 |
|
|
Aug 21 10:36:42 PM UTC 24 |
Aug 21 10:37:26 PM UTC 24 |
1434332772 ps |
| T1829 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_large_delays.4056366055 |
|
|
Aug 21 10:36:05 PM UTC 24 |
Aug 21 10:37:27 PM UTC 24 |
7333400354 ps |
| T1830 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_unmapped_addr.1175974809 |
|
|
Aug 21 10:36:43 PM UTC 24 |
Aug 21 10:37:27 PM UTC 24 |
777777300 ps |
| T1831 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.2618278000 |
|
|
Aug 21 10:36:48 PM UTC 24 |
Aug 21 10:37:28 PM UTC 24 |
988244717 ps |
| T1832 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.482810448 |
|
|
Aug 21 10:36:00 PM UTC 24 |
Aug 21 10:37:29 PM UTC 24 |
908276858 ps |
| T556 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_error.1641251954 |
|
|
Aug 21 10:30:08 PM UTC 24 |
Aug 21 10:37:37 PM UTC 24 |
12715382155 ps |
| T1833 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.496494035 |
|
|
Aug 21 10:36:09 PM UTC 24 |
Aug 21 10:37:39 PM UTC 24 |
5139125029 ps |
| T1834 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.2897226499 |
|
|
Aug 21 10:35:12 PM UTC 24 |
Aug 21 10:37:43 PM UTC 24 |
350889386 ps |
| T1835 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_slow_rsp.2770797530 |
|
|
Aug 21 10:26:47 PM UTC 24 |
Aug 21 10:37:51 PM UTC 24 |
38842102276 ps |
| T1836 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random.2711650660 |
|
|
Aug 21 10:37:18 PM UTC 24 |
Aug 21 10:37:59 PM UTC 24 |
517171127 ps |
| T1837 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_zero_delays.3030663051 |
|
|
Aug 21 10:37:20 PM UTC 24 |
Aug 21 10:38:00 PM UTC 24 |
367009057 ps |
| T784 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.2831554882 |
|
|
Aug 21 10:32:51 PM UTC 24 |
Aug 21 10:38:02 PM UTC 24 |
6057775895 ps |
| T586 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_error.849861305 |
|
|
Aug 21 10:36:04 PM UTC 24 |
Aug 21 10:38:06 PM UTC 24 |
3661962044 ps |
| T1838 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke.3619360850 |
|
|
Aug 21 10:37:58 PM UTC 24 |
Aug 21 10:38:07 PM UTC 24 |
38644220 ps |
| T1839 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_zero_delays.1725323610 |
|
|
Aug 21 10:38:03 PM UTC 24 |
Aug 21 10:38:13 PM UTC 24 |
48188284 ps |
| T1840 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_same_csr_outstanding.72134495 |
|
|
Aug 21 09:46:37 PM UTC 24 |
Aug 21 10:38:17 PM UTC 24 |
26062038272 ps |
| T1841 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.3586741985 |
|
|
Aug 21 10:37:14 PM UTC 24 |
Aug 21 10:38:17 PM UTC 24 |
3852452479 ps |
| T1842 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_unmapped_addr.252501568 |
|
|
Aug 21 10:37:41 PM UTC 24 |
Aug 21 10:38:26 PM UTC 24 |
1129992927 ps |
| T1843 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_same_source.682665511 |
|
|
Aug 21 10:37:35 PM UTC 24 |
Aug 21 10:38:29 PM UTC 24 |
1641491257 ps |
| T1844 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random.1952185398 |
|
|
Aug 21 10:38:24 PM UTC 24 |
Aug 21 10:38:34 PM UTC 24 |
36767971 ps |
| T1845 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_random.2083658266 |
|
|
Aug 21 10:37:43 PM UTC 24 |
Aug 21 10:38:37 PM UTC 24 |
1796951477 ps |
| T1846 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.3308792153 |
|
|
Aug 21 10:37:50 PM UTC 24 |
Aug 21 10:38:40 PM UTC 24 |
1236928695 ps |
| T1847 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_slow_rsp.2893383729 |
|
|
Aug 21 10:35:41 PM UTC 24 |
Aug 21 10:38:44 PM UTC 24 |
11828877548 ps |
| T1848 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all.1720990342 |
|
|
Aug 21 10:37:48 PM UTC 24 |
Aug 21 10:38:51 PM UTC 24 |
2352213934 ps |
| T1849 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_large_delays.1885587526 |
|
|
Aug 21 10:37:13 PM UTC 24 |
Aug 21 10:38:52 PM UTC 24 |
6473898571 ps |
| T1850 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_zero_delays.1175546115 |
|
|
Aug 21 10:38:25 PM UTC 24 |
Aug 21 10:38:52 PM UTC 24 |
271529084 ps |
| T1851 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device.280164286 |
|
|
Aug 21 10:36:28 PM UTC 24 |
Aug 21 10:38:56 PM UTC 24 |
3093884729 ps |
| T1852 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.3412129095 |
|
|
Aug 21 10:38:49 PM UTC 24 |
Aug 21 10:38:58 PM UTC 24 |
37140945 ps |
| T1853 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.1872644802 |
|
|
Aug 21 10:34:06 PM UTC 24 |
Aug 21 10:39:00 PM UTC 24 |
1541489791 ps |
| T1854 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all.228427007 |
|
|
Aug 21 10:36:02 PM UTC 24 |
Aug 21 10:39:00 PM UTC 24 |
2300216194 ps |
| T1855 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.65416959 |
|
|
Aug 21 10:37:49 PM UTC 24 |
Aug 21 10:39:02 PM UTC 24 |
184284033 ps |
| T1856 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_random.1820953787 |
|
|
Aug 21 10:38:42 PM UTC 24 |
Aug 21 10:39:05 PM UTC 24 |
198982193 ps |
| T1857 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device.2232844438 |
|
|
Aug 21 10:37:29 PM UTC 24 |
Aug 21 10:39:06 PM UTC 24 |
2678966634 ps |
| T1858 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_slow_rsp.386981311 |
|
|
Aug 21 10:25:13 PM UTC 24 |
Aug 21 10:39:07 PM UTC 24 |
55647047675 ps |
| T1859 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_same_source.128176437 |
|
|
Aug 21 10:38:41 PM UTC 24 |
Aug 21 10:39:10 PM UTC 24 |
734334425 ps |
| T1860 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_large_delays.2799523732 |
|
|
Aug 21 10:38:08 PM UTC 24 |
Aug 21 10:39:20 PM UTC 24 |
7755883859 ps |
| T1861 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_zero_delays.748990388 |
|
|
Aug 21 10:39:15 PM UTC 24 |
Aug 21 10:39:23 PM UTC 24 |
41186301 ps |
| T1862 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke.2044375063 |
|
|
Aug 21 10:39:13 PM UTC 24 |
Aug 21 10:39:28 PM UTC 24 |
243830642 ps |
| T1863 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.1320692386 |
|
|
Aug 21 10:29:13 PM UTC 24 |
Aug 21 10:39:38 PM UTC 24 |
35597783354 ps |
| T1864 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_zero_delays.1887467602 |
|
|
Aug 21 10:39:20 PM UTC 24 |
Aug 21 10:39:41 PM UTC 24 |
249612627 ps |
| T1865 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.1282338166 |
|
|
Aug 21 10:39:08 PM UTC 24 |
Aug 21 10:39:43 PM UTC 24 |
141844799 ps |
| T1866 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device.1235477226 |
|
|
Aug 21 10:38:31 PM UTC 24 |
Aug 21 10:39:46 PM UTC 24 |
1829764067 ps |
| T1867 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_unmapped_addr.1680659103 |
|
|
Aug 21 10:38:51 PM UTC 24 |
Aug 21 10:39:48 PM UTC 24 |
1393865395 ps |
| T1868 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_same_source.3116061121 |
|
|
Aug 21 10:39:28 PM UTC 24 |
Aug 21 10:39:51 PM UTC 24 |
243514692 ps |
| T1869 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device.3586450119 |
|
|
Aug 21 10:39:27 PM UTC 24 |
Aug 21 10:39:59 PM UTC 24 |
732113393 ps |
| T1870 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_unmapped_addr.3656188770 |
|
|
Aug 21 10:39:45 PM UTC 24 |
Aug 21 10:40:03 PM UTC 24 |
235702583 ps |
| T1871 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.3402557025 |
|
|
Aug 21 10:39:47 PM UTC 24 |
Aug 21 10:40:11 PM UTC 24 |
148741962 ps |
| T1872 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.2360898617 |
|
|
Aug 21 10:36:44 PM UTC 24 |
Aug 21 10:40:13 PM UTC 24 |
4628469662 ps |
| T1873 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random.4291267651 |
|
|
Aug 21 10:39:19 PM UTC 24 |
Aug 21 10:40:16 PM UTC 24 |
2048469407 ps |
| T1874 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke.878233423 |
|
|
Aug 21 10:40:09 PM UTC 24 |
Aug 21 10:40:19 PM UTC 24 |
210992072 ps |
| T1875 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.1054001614 |
|
|
Aug 21 10:38:16 PM UTC 24 |
Aug 21 10:40:19 PM UTC 24 |
5484788337 ps |
| T1876 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_zero_delays.1989800421 |
|
|
Aug 21 10:40:09 PM UTC 24 |
Aug 21 10:40:20 PM UTC 24 |
56100329 ps |
| T1877 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all.3588893422 |
|
|
Aug 21 10:33:55 PM UTC 24 |
Aug 21 10:40:22 PM UTC 24 |
11321970057 ps |
| T1878 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_random.4125099667 |
|
|
Aug 21 10:39:33 PM UTC 24 |
Aug 21 10:40:25 PM UTC 24 |
1588869801 ps |
| T1879 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_error.950220271 |
|
|
Aug 21 10:37:51 PM UTC 24 |
Aug 21 10:40:45 PM UTC 24 |
5684965039 ps |
| T1880 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.1750459463 |
|
|
Aug 21 10:39:16 PM UTC 24 |
Aug 21 10:40:54 PM UTC 24 |
6762431059 ps |
| T1881 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_large_delays.4070253805 |
|
|
Aug 21 10:39:16 PM UTC 24 |
Aug 21 10:40:54 PM UTC 24 |
9566383949 ps |
| T1882 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.4292189824 |
|
|
Aug 21 10:36:57 PM UTC 24 |
Aug 21 10:40:58 PM UTC 24 |
2877956463 ps |
| T1883 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_unmapped_addr.1979478945 |
|
|
Aug 21 10:40:50 PM UTC 24 |
Aug 21 10:41:00 PM UTC 24 |
21555875 ps |
| T1884 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device.4058130071 |
|
|
Aug 21 10:40:40 PM UTC 24 |
Aug 21 10:41:09 PM UTC 24 |
216761619 ps |
| T1885 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_same_source.2386483753 |
|
|
Aug 21 10:40:44 PM UTC 24 |
Aug 21 10:41:09 PM UTC 24 |
239756518 ps |
| T709 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_error.2963417350 |
|
|
Aug 21 10:39:02 PM UTC 24 |
Aug 21 10:41:10 PM UTC 24 |
3766754700 ps |
| T1886 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random.239706612 |
|
|
Aug 21 10:40:28 PM UTC 24 |
Aug 21 10:41:11 PM UTC 24 |
500901658 ps |
| T1887 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_large_delays.2877095647 |
|
|
Aug 21 10:36:19 PM UTC 24 |
Aug 21 10:41:13 PM UTC 24 |
28319102608 ps |
| T1888 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_slow_rsp.1446050486 |
|
|
Aug 21 10:34:32 PM UTC 24 |
Aug 21 10:41:15 PM UTC 24 |
27195183507 ps |
| T1889 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_zero_delays.728989948 |
|
|
Aug 21 10:40:36 PM UTC 24 |
Aug 21 10:41:21 PM UTC 24 |
494284689 ps |
| T1890 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.3700216498 |
|
|
Aug 21 10:41:09 PM UTC 24 |
Aug 21 10:41:28 PM UTC 24 |
100000390 ps |
| T1891 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_random.2622531993 |
|
|
Aug 21 10:40:44 PM UTC 24 |
Aug 21 10:41:36 PM UTC 24 |
1540992282 ps |
| T1892 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_zero_delays.117151203 |
|
|
Aug 21 10:41:32 PM UTC 24 |
Aug 21 10:41:40 PM UTC 24 |
47480331 ps |
| T1893 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_large_delays.1618866564 |
|
|
Aug 21 10:40:15 PM UTC 24 |
Aug 21 10:41:43 PM UTC 24 |
9260034668 ps |
| T1894 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke.4154617832 |
|
|
Aug 21 10:41:29 PM UTC 24 |
Aug 21 10:41:43 PM UTC 24 |
207422146 ps |
| T1895 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.753544141 |
|
|
Aug 21 10:41:19 PM UTC 24 |
Aug 21 10:41:49 PM UTC 24 |
37778424 ps |
| T1896 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random.1695465535 |
|
|
Aug 21 10:41:37 PM UTC 24 |
Aug 21 10:41:59 PM UTC 24 |
235038074 ps |
| T1897 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_error.435833627 |
|
|
Aug 21 10:41:24 PM UTC 24 |
Aug 21 10:42:07 PM UTC 24 |
407566611 ps |
| T1898 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_slow_rsp.3013162231 |
|
|
Aug 21 10:30:42 PM UTC 24 |
Aug 21 10:42:10 PM UTC 24 |
45291273825 ps |
| T1899 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.720617634 |
|
|
Aug 21 10:41:22 PM UTC 24 |
Aug 21 10:42:11 PM UTC 24 |
167850345 ps |
| T1900 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.3911479373 |
|
|
Aug 21 10:40:22 PM UTC 24 |
Aug 21 10:42:13 PM UTC 24 |
5231320685 ps |
| T1901 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.3277833405 |
|
|
Aug 21 10:25:19 PM UTC 24 |
Aug 21 10:42:13 PM UTC 24 |
70665115475 ps |
| T790 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.2276720705 |
|
|
Aug 21 10:37:50 PM UTC 24 |
Aug 21 10:42:13 PM UTC 24 |
1860757546 ps |
| T1902 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_zero_delays.2714021235 |
|
|
Aug 21 10:41:38 PM UTC 24 |
Aug 21 10:42:41 PM UTC 24 |
634362741 ps |
| T1903 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.4129020036 |
|
|
Aug 21 10:39:01 PM UTC 24 |
Aug 21 10:42:41 PM UTC 24 |
4253361112 ps |
| T1904 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke.339250163 |
|
|
Aug 21 10:42:37 PM UTC 24 |
Aug 21 10:42:47 PM UTC 24 |
39595665 ps |
| T1905 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.1143296180 |
|
|
Aug 21 10:35:05 PM UTC 24 |
Aug 21 10:42:49 PM UTC 24 |
4247180896 ps |
| T1906 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_zero_delays.1602227034 |
|
|
Aug 21 10:42:38 PM UTC 24 |
Aug 21 10:42:50 PM UTC 24 |
57110761 ps |
| T1907 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_same_source.3031513057 |
|
|
Aug 21 10:42:07 PM UTC 24 |
Aug 21 10:42:53 PM UTC 24 |
1067015671 ps |
| T1908 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.1161824281 |
|
|
Aug 21 10:42:23 PM UTC 24 |
Aug 21 10:42:53 PM UTC 24 |
294588844 ps |
| T1909 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device.1748401200 |
|
|
Aug 21 10:42:01 PM UTC 24 |
Aug 21 10:42:57 PM UTC 24 |
700446902 ps |
| T1910 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.3599992264 |
|
|
Aug 21 10:41:36 PM UTC 24 |
Aug 21 10:43:00 PM UTC 24 |
4376424181 ps |
| T585 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_error.214765654 |
|
|
Aug 21 10:36:52 PM UTC 24 |
Aug 21 10:43:00 PM UTC 24 |
10606089363 ps |
| T1911 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_error.2927251686 |
|
|
Aug 21 10:42:34 PM UTC 24 |
Aug 21 10:43:06 PM UTC 24 |
484252251 ps |
| T1912 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_large_delays.1892763308 |
|
|
Aug 21 10:41:34 PM UTC 24 |
Aug 21 10:43:08 PM UTC 24 |
6850161613 ps |
| T1913 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all.2111437183 |
|
|
Aug 21 10:36:50 PM UTC 24 |
Aug 21 10:43:21 PM UTC 24 |
4341992207 ps |
| T1914 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_unmapped_addr.931891368 |
|
|
Aug 21 10:42:14 PM UTC 24 |
Aug 21 10:43:25 PM UTC 24 |
1251599570 ps |
| T555 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_random.4098022939 |
|
|
Aug 21 10:42:09 PM UTC 24 |
Aug 21 10:43:25 PM UTC 24 |
2304539743 ps |
| T1915 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random.901403980 |
|
|
Aug 21 10:43:11 PM UTC 24 |
Aug 21 10:43:29 PM UTC 24 |
128437575 ps |
| T1916 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_slow_rsp.1103135136 |
|
|
Aug 21 10:36:24 PM UTC 24 |
Aug 21 10:43:45 PM UTC 24 |
26248510676 ps |
| T1917 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_zero_delays.1775022551 |
|
|
Aug 21 10:43:11 PM UTC 24 |
Aug 21 10:43:45 PM UTC 24 |
340732091 ps |
| T1918 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device.1713872100 |
|
|
Aug 21 10:43:19 PM UTC 24 |
Aug 21 10:43:52 PM UTC 24 |
290891131 ps |
| T1919 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_same_source.4193434322 |
|
|
Aug 21 10:43:21 PM UTC 24 |
Aug 21 10:44:03 PM UTC 24 |
1015484775 ps |
| T1920 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.532073058 |
|
|
Aug 21 10:40:05 PM UTC 24 |
Aug 21 10:44:05 PM UTC 24 |
3756145393 ps |
| T1921 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.2845509135 |
|
|
Aug 21 10:43:33 PM UTC 24 |
Aug 21 10:44:07 PM UTC 24 |
214493810 ps |
| T1922 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.1503486234 |
|
|
Aug 21 10:33:33 PM UTC 24 |
Aug 21 10:44:07 PM UTC 24 |
44844396281 ps |
| T710 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.1432622228 |
|
|
Aug 21 10:11:06 PM UTC 24 |
Aug 21 10:44:10 PM UTC 24 |
138253818326 ps |
| T1923 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_unmapped_addr.1843214583 |
|
|
Aug 21 10:43:28 PM UTC 24 |
Aug 21 10:44:12 PM UTC 24 |
764665040 ps |
| T1924 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_zero_delays.2236215934 |
|
|
Aug 21 10:44:08 PM UTC 24 |
Aug 21 10:44:15 PM UTC 24 |
41159022 ps |
| T1925 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke.321897626 |
|
|
Aug 21 10:44:09 PM UTC 24 |
Aug 21 10:44:18 PM UTC 24 |
46081858 ps |
| T1926 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.3425346782 |
|
|
Aug 21 10:26:48 PM UTC 24 |
Aug 21 10:44:22 PM UTC 24 |
68324097419 ps |
| T1927 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.2369130482 |
|
|
Aug 21 10:43:06 PM UTC 24 |
Aug 21 10:44:22 PM UTC 24 |
3724297916 ps |
| T1928 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.1104471296 |
|
|
Aug 21 10:22:27 PM UTC 24 |
Aug 21 10:44:26 PM UTC 24 |
91591401739 ps |
| T1929 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_large_delays.464476275 |
|
|
Aug 21 10:43:03 PM UTC 24 |
Aug 21 10:44:33 PM UTC 24 |
7873303854 ps |
| T1930 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_zero_delays.3627930595 |
|
|
Aug 21 10:44:30 PM UTC 24 |
Aug 21 10:44:42 PM UTC 24 |
66690930 ps |
| T1931 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_random.2547871365 |
|
|
Aug 21 10:43:25 PM UTC 24 |
Aug 21 10:44:45 PM UTC 24 |
2233834462 ps |
| T1932 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all.1840357740 |
|
|
Aug 21 10:42:29 PM UTC 24 |
Aug 21 10:44:50 PM UTC 24 |
1744146815 ps |
| T1933 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_large_delays.899581321 |
|
|
Aug 21 10:26:42 PM UTC 24 |
Aug 21 10:44:54 PM UTC 24 |
96977301100 ps |
| T1934 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.791319132 |
|
|
Aug 21 10:23:49 PM UTC 24 |
Aug 21 10:45:00 PM UTC 24 |
84155767294 ps |
| T1935 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_large_delays.1949214561 |
|
|
Aug 21 10:44:17 PM UTC 24 |
Aug 21 10:45:07 PM UTC 24 |
4771146164 ps |
| T1936 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_unmapped_addr.1098145143 |
|
|
Aug 21 10:44:46 PM UTC 24 |
Aug 21 10:45:13 PM UTC 24 |
537261347 ps |
| T1937 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all.3174980681 |
|
|
Aug 21 10:38:56 PM UTC 24 |
Aug 21 10:45:19 PM UTC 24 |
10473031949 ps |
| T1938 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_large_delays.3671650435 |
|
|
Aug 21 10:35:38 PM UTC 24 |
Aug 21 10:45:21 PM UTC 24 |
61368893875 ps |
| T1939 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random.1378350003 |
|
|
Aug 21 10:44:31 PM UTC 24 |
Aug 21 10:45:23 PM UTC 24 |
1458610824 ps |
| T1940 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_random.2797502734 |
|
|
Aug 21 10:44:46 PM UTC 24 |
Aug 21 10:45:23 PM UTC 24 |
416359156 ps |
| T1941 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_same_source.2817308636 |
|
|
Aug 21 10:44:42 PM UTC 24 |
Aug 21 10:45:24 PM UTC 24 |
505535337 ps |
| T1942 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_large_delays.772696137 |
|
|
Aug 21 10:38:28 PM UTC 24 |
Aug 21 10:45:32 PM UTC 24 |
41214021326 ps |
| T1943 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke.2759571412 |
|
|
Aug 21 10:45:19 PM UTC 24 |
Aug 21 10:45:33 PM UTC 24 |
226485889 ps |
| T1944 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_zero_delays.1915842134 |
|
|
Aug 21 10:45:24 PM UTC 24 |
Aug 21 10:45:33 PM UTC 24 |
38339026 ps |
| T1945 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device.3236209192 |
|
|
Aug 21 10:44:36 PM UTC 24 |
Aug 21 10:45:34 PM UTC 24 |
731107843 ps |
| T1946 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.1345216269 |
|
|
Aug 21 10:44:28 PM UTC 24 |
Aug 21 10:45:39 PM UTC 24 |
3097492354 ps |
| T1947 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.2175214491 |
|
|
Aug 21 10:42:03 PM UTC 24 |
Aug 21 10:45:40 PM UTC 24 |
13119627452 ps |
| T1948 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.218660546 |
|
|
Aug 21 10:37:34 PM UTC 24 |
Aug 21 10:45:42 PM UTC 24 |
29622391674 ps |
| T1949 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.3959137771 |
|
|
Aug 21 10:44:52 PM UTC 24 |
Aug 21 10:45:46 PM UTC 24 |
1150816055 ps |
| T1950 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.1944427866 |
|
|
Aug 21 10:43:51 PM UTC 24 |
Aug 21 10:46:01 PM UTC 24 |
256560304 ps |
| T1951 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_zero_delays.1502930453 |
|
|
Aug 21 10:45:46 PM UTC 24 |
Aug 21 10:46:24 PM UTC 24 |
344838802 ps |
| T1952 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.1398821108 |
|
|
Aug 21 10:15:11 PM UTC 24 |
Aug 21 10:46:26 PM UTC 24 |
128183067867 ps |
| T1953 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.3439345182 |
|
|
Aug 21 10:12:18 PM UTC 24 |
Aug 21 10:46:27 PM UTC 24 |
141195396147 ps |
| T1954 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.335814114 |
|
|
Aug 21 10:45:06 PM UTC 24 |
Aug 21 10:46:32 PM UTC 24 |
254441207 ps |
| T1955 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random.3289810711 |
|
|
Aug 21 10:45:44 PM UTC 24 |
Aug 21 10:46:33 PM UTC 24 |
1037692653 ps |
| T1956 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_same_source.2083266180 |
|
|
Aug 21 10:45:59 PM UTC 24 |
Aug 21 10:46:33 PM UTC 24 |
311365530 ps |
| T1957 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_error.597963813 |
|
|
Aug 21 10:43:50 PM UTC 24 |
Aug 21 10:46:34 PM UTC 24 |
5502320051 ps |
| T1958 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_slow_rsp.3502560523 |
|
|
Aug 21 10:32:08 PM UTC 24 |
Aug 21 10:46:41 PM UTC 24 |
53541087427 ps |
| T1959 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_random.3120476660 |
|
|
Aug 21 10:45:53 PM UTC 24 |
Aug 21 10:46:47 PM UTC 24 |
625279520 ps |
| T1960 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_unmapped_addr.3557706222 |
|
|
Aug 21 10:45:58 PM UTC 24 |
Aug 21 10:46:48 PM UTC 24 |
1461151746 ps |
| T1961 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke.1409550475 |
|
|
Aug 21 10:46:49 PM UTC 24 |
Aug 21 10:46:58 PM UTC 24 |
42757812 ps |
| T1962 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.3783806033 |
|
|
Aug 21 10:46:01 PM UTC 24 |
Aug 21 10:46:59 PM UTC 24 |
1212490221 ps |
| T1963 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_zero_delays.4292183668 |
|
|
Aug 21 10:46:50 PM UTC 24 |
Aug 21 10:47:01 PM UTC 24 |
53651865 ps |
| T1964 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.2901031487 |
|
|
Aug 21 10:32:17 PM UTC 24 |
Aug 21 10:47:04 PM UTC 24 |
60455843356 ps |
| T1965 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_large_delays.37485726 |
|
|
Aug 21 10:45:31 PM UTC 24 |
Aug 21 10:47:12 PM UTC 24 |
10511860110 ps |
| T1966 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random.3402806866 |
|
|
Aug 21 10:46:58 PM UTC 24 |
Aug 21 10:47:13 PM UTC 24 |
102577681 ps |
| T1967 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.3231352472 |
|
|
Aug 21 10:39:29 PM UTC 24 |
Aug 21 10:47:18 PM UTC 24 |
26985676983 ps |
| T1968 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.2894916071 |
|
|
Aug 21 10:38:38 PM UTC 24 |
Aug 21 10:47:22 PM UTC 24 |
33711003432 ps |
| T1969 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_large_delays.3200112480 |
|
|
Aug 21 10:40:37 PM UTC 24 |
Aug 21 10:47:25 PM UTC 24 |
36836444225 ps |
| T1970 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device.2381590205 |
|
|
Aug 21 10:45:46 PM UTC 24 |
Aug 21 10:47:26 PM UTC 24 |
800120099 ps |
| T1971 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.915471506 |
|
|
Aug 21 10:40:03 PM UTC 24 |
Aug 21 10:47:28 PM UTC 24 |
8025145876 ps |
| T1972 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.853493111 |
|
|
Aug 21 10:46:27 PM UTC 24 |
Aug 21 10:47:30 PM UTC 24 |
1022481713 ps |
| T1973 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_large_delays.2570586114 |
|
|
Aug 21 10:31:59 PM UTC 24 |
Aug 21 10:47:40 PM UTC 24 |
94611834674 ps |
| T1974 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_unmapped_addr.814617692 |
|
|
Aug 21 10:47:23 PM UTC 24 |
Aug 21 10:47:42 PM UTC 24 |
342350531 ps |
| T1975 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.1429481239 |
|
|
Aug 21 10:45:38 PM UTC 24 |
Aug 21 10:47:50 PM UTC 24 |
5943249003 ps |
| T1976 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_zero_delays.3532522553 |
|
|
Aug 21 10:46:56 PM UTC 24 |
Aug 21 10:47:52 PM UTC 24 |
547547338 ps |
| T1977 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_slow_rsp.3170059702 |
|
|
Aug 21 10:40:41 PM UTC 24 |
Aug 21 10:47:56 PM UTC 24 |
31670093000 ps |
| T1978 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke.627664280 |
|
|
Aug 21 10:47:47 PM UTC 24 |
Aug 21 10:47:57 PM UTC 24 |
40566310 ps |
| T1979 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_zero_delays.851703043 |
|
|
Aug 21 10:47:50 PM UTC 24 |
Aug 21 10:47:58 PM UTC 24 |
58900139 ps |
| T1980 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.3906073167 |
|
|
Aug 21 10:47:29 PM UTC 24 |
Aug 21 10:47:58 PM UTC 24 |
203944093 ps |
| T1981 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_random.2575430919 |
|
|
Aug 21 10:47:24 PM UTC 24 |
Aug 21 10:47:58 PM UTC 24 |
313031036 ps |
| T1982 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device.2984304997 |
|
|
Aug 21 10:47:11 PM UTC 24 |
Aug 21 10:48:00 PM UTC 24 |
827266699 ps |
| T1983 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all.3268917781 |
|
|
Aug 21 10:47:34 PM UTC 24 |
Aug 21 10:48:00 PM UTC 24 |
436428285 ps |
| T1984 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all.1431954711 |
|
|
Aug 21 10:44:58 PM UTC 24 |
Aug 21 10:48:02 PM UTC 24 |
5429259635 ps |
| T1985 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_same_source.2155921604 |
|
|
Aug 21 10:47:23 PM UTC 24 |
Aug 21 10:48:03 PM UTC 24 |
1173562815 ps |
| T1986 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_large_delays.743018111 |
|
|
Aug 21 10:46:52 PM UTC 24 |
Aug 21 10:48:16 PM UTC 24 |
8094692797 ps |
| T1987 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.1128575190 |
|
|
Aug 21 10:43:55 PM UTC 24 |
Aug 21 10:48:28 PM UTC 24 |
773489505 ps |
| T1988 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random.3085486410 |
|
|
Aug 21 10:48:05 PM UTC 24 |
Aug 21 10:48:30 PM UTC 24 |
239857208 ps |
| T1989 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.477128009 |
|
|
Aug 21 10:47:13 PM UTC 24 |
Aug 21 10:48:32 PM UTC 24 |
4062784244 ps |
| T1990 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all.1611178232 |
|
|
Aug 21 10:46:01 PM UTC 24 |
Aug 21 10:48:33 PM UTC 24 |
4582489722 ps |
| T1991 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_error.1147017918 |
|
|
Aug 21 10:40:07 PM UTC 24 |
Aug 21 10:48:36 PM UTC 24 |
15259633868 ps |
| T1992 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all.1148860396 |
|
|
Aug 21 10:39:53 PM UTC 24 |
Aug 21 10:48:36 PM UTC 24 |
13635116720 ps |
| T1993 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.777819522 |
|
|
Aug 21 10:46:58 PM UTC 24 |
Aug 21 10:48:43 PM UTC 24 |
5670928221 ps |
| T1994 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_same_source.3676615173 |
|
|
Aug 21 10:48:23 PM UTC 24 |
Aug 21 10:48:43 PM UTC 24 |
673496232 ps |
| T1995 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_zero_delays.3625846794 |
|
|
Aug 21 10:48:08 PM UTC 24 |
Aug 21 10:48:44 PM UTC 24 |
431938050 ps |
| T1996 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.1983941192 |
|
|
Aug 21 10:42:34 PM UTC 24 |
Aug 21 10:48:44 PM UTC 24 |
2201337619 ps |
| T1997 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.286477474 |
|
|
Aug 21 10:36:34 PM UTC 24 |
Aug 21 10:48:52 PM UTC 24 |
45148100818 ps |
| T1998 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.796562253 |
|
|
Aug 21 10:47:54 PM UTC 24 |
Aug 21 10:48:53 PM UTC 24 |
3851933185 ps |
| T1999 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_zero_delays.2707615120 |
|
|
Aug 21 10:48:51 PM UTC 24 |
Aug 21 10:49:01 PM UTC 24 |
52821602 ps |
| T2000 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke.3742044550 |
|
|
Aug 21 10:48:52 PM UTC 24 |
Aug 21 10:49:02 PM UTC 24 |
246915980 ps |
| T2001 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_large_delays.3694520191 |
|
|
Aug 21 10:34:29 PM UTC 24 |
Aug 21 10:49:04 PM UTC 24 |
102488509586 ps |
| T2002 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_random.199016515 |
|
|
Aug 21 10:48:23 PM UTC 24 |
Aug 21 10:49:08 PM UTC 24 |
435135223 ps |
| T2003 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random.3807816397 |
|
|
Aug 21 10:49:01 PM UTC 24 |
Aug 21 10:49:08 PM UTC 24 |
119358866 ps |
| T2004 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.2270934109 |
|
|
Aug 21 10:48:23 PM UTC 24 |
Aug 21 10:49:12 PM UTC 24 |
1045487428 ps |
| T2005 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_slow_rsp.3894412529 |
|
|
Aug 21 10:41:52 PM UTC 24 |
Aug 21 10:49:12 PM UTC 24 |
29387907632 ps |
| T554 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_error.1002436105 |
|
|
Aug 21 10:45:10 PM UTC 24 |
Aug 21 10:49:14 PM UTC 24 |
7285477618 ps |
| T2006 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_large_delays.1555678113 |
|
|
Aug 21 10:30:43 PM UTC 24 |
Aug 21 10:49:15 PM UTC 24 |
101600644348 ps |
| T2007 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_unmapped_addr.1377988632 |
|
|
Aug 21 10:48:23 PM UTC 24 |
Aug 21 10:49:16 PM UTC 24 |
1328180897 ps |
| T2008 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_same_source.2736189212 |
|
|
Aug 21 10:49:15 PM UTC 24 |
Aug 21 10:49:27 PM UTC 24 |
87824742 ps |
| T2009 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_zero_delays.1542895444 |
|
|
Aug 21 10:49:00 PM UTC 24 |
Aug 21 10:49:32 PM UTC 24 |
246548775 ps |
| T2010 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_large_delays.1866041343 |
|
|
Aug 21 10:43:14 PM UTC 24 |
Aug 21 10:49:36 PM UTC 24 |
38734063261 ps |
| T2011 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_error.3475724766 |
|
|
Aug 21 10:46:11 PM UTC 24 |
Aug 21 10:49:41 PM UTC 24 |
6172857285 ps |
| T2012 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device.2215084347 |
|
|
Aug 21 10:49:09 PM UTC 24 |
Aug 21 10:49:41 PM UTC 24 |
719091094 ps |
| T2013 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_unmapped_addr.1895061851 |
|
|
Aug 21 10:49:22 PM UTC 24 |
Aug 21 10:49:43 PM UTC 24 |
132924659 ps |
| T2014 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke.3996228021 |
|
|
Aug 21 10:49:35 PM UTC 24 |
Aug 21 10:49:48 PM UTC 24 |
155203692 ps |
| T2015 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_zero_delays.432227531 |
|
|
Aug 21 10:49:39 PM UTC 24 |
Aug 21 10:49:50 PM UTC 24 |
56434229 ps |
| T2016 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_slow_rsp.2099541821 |
|
|
Aug 21 10:48:17 PM UTC 24 |
Aug 21 10:49:51 PM UTC 24 |
6199366710 ps |
| T2017 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_large_delays.4251124556 |
|
|
Aug 21 10:47:50 PM UTC 24 |
Aug 21 10:49:52 PM UTC 24 |
9600346051 ps |
| T2018 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_random.3859733406 |
|
|
Aug 21 10:49:15 PM UTC 24 |
Aug 21 10:50:02 PM UTC 24 |
1341825903 ps |
| T2019 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random.980198325 |
|
|
Aug 21 10:49:51 PM UTC 24 |
Aug 21 10:50:09 PM UTC 24 |
383850886 ps |