| T1554 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.3486637647 |
|
|
Aug 21 10:14:29 PM UTC 24 |
Aug 21 10:16:41 PM UTC 24 |
428345683 ps |
| T1555 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_same_csr_outstanding.3094856654 |
|
|
Aug 21 09:41:17 PM UTC 24 |
Aug 21 10:16:44 PM UTC 24 |
16317061277 ps |
| T1556 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.3743083672 |
|
|
Aug 21 10:16:28 PM UTC 24 |
Aug 21 10:16:45 PM UTC 24 |
93406155 ps |
| T1557 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_unmapped_addr.1402631059 |
|
|
Aug 21 10:16:23 PM UTC 24 |
Aug 21 10:16:47 PM UTC 24 |
128892705 ps |
| T1558 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_random.2314897344 |
|
|
Aug 21 10:16:22 PM UTC 24 |
Aug 21 10:17:03 PM UTC 24 |
356044985 ps |
| T584 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.3168948806 |
|
|
Aug 21 10:11:39 PM UTC 24 |
Aug 21 10:17:06 PM UTC 24 |
1634467289 ps |
| T1559 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.1964595703 |
|
|
Aug 21 10:14:29 PM UTC 24 |
Aug 21 10:17:07 PM UTC 24 |
594614774 ps |
| T1560 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device.2933817219 |
|
|
Aug 21 10:15:07 PM UTC 24 |
Aug 21 10:17:08 PM UTC 24 |
2776627660 ps |
| T1561 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.1933459352 |
|
|
Aug 21 10:16:53 PM UTC 24 |
Aug 21 10:17:09 PM UTC 24 |
35926972 ps |
| T1562 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_large_delays.651437375 |
|
|
Aug 21 10:15:44 PM UTC 24 |
Aug 21 10:17:11 PM UTC 24 |
8833732485 ps |
| T1563 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_zero_delays.552574730 |
|
|
Aug 21 10:17:05 PM UTC 24 |
Aug 21 10:17:16 PM UTC 24 |
48152567 ps |
| T1564 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke.908410701 |
|
|
Aug 21 10:17:03 PM UTC 24 |
Aug 21 10:17:17 PM UTC 24 |
197233846 ps |
| T453 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_same_source.239009600 |
|
|
Aug 21 10:16:23 PM UTC 24 |
Aug 21 10:17:19 PM UTC 24 |
530768226 ps |
| T1565 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all.3821060096 |
|
|
Aug 21 10:16:36 PM UTC 24 |
Aug 21 10:17:19 PM UTC 24 |
378801840 ps |
| T1566 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random.524336181 |
|
|
Aug 21 10:17:12 PM UTC 24 |
Aug 21 10:17:23 PM UTC 24 |
178808765 ps |
| T1567 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_error.3926481341 |
|
|
Aug 21 10:14:29 PM UTC 24 |
Aug 21 10:17:27 PM UTC 24 |
5652796237 ps |
| T728 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.761524502 |
|
|
Aug 21 09:52:16 PM UTC 24 |
Aug 21 10:17:27 PM UTC 24 |
108548469575 ps |
| T1568 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.3338030715 |
|
|
Aug 21 10:15:42 PM UTC 24 |
Aug 21 10:17:29 PM UTC 24 |
6570461898 ps |
| T1569 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device.3677930363 |
|
|
Aug 21 10:16:16 PM UTC 24 |
Aug 21 10:17:35 PM UTC 24 |
824949777 ps |
| T1570 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_zero_delays.557822907 |
|
|
Aug 21 10:17:25 PM UTC 24 |
Aug 21 10:17:43 PM UTC 24 |
195839803 ps |
| T803 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.569870026 |
|
|
Aug 21 10:15:26 PM UTC 24 |
Aug 21 10:17:46 PM UTC 24 |
417132173 ps |
| T1571 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_unmapped_addr.251382314 |
|
|
Aug 21 10:17:42 PM UTC 24 |
Aug 21 10:17:56 PM UTC 24 |
145345666 ps |
| T1572 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke.2502537438 |
|
|
Aug 21 10:17:54 PM UTC 24 |
Aug 21 10:18:06 PM UTC 24 |
173185537 ps |
| T1573 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_random.3154163838 |
|
|
Aug 21 10:17:39 PM UTC 24 |
Aug 21 10:18:06 PM UTC 24 |
314020911 ps |
| T1574 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_error.1503696828 |
|
|
Aug 21 10:16:42 PM UTC 24 |
Aug 21 10:18:07 PM UTC 24 |
2396594118 ps |
| T1575 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_zero_delays.1365842458 |
|
|
Aug 21 10:18:00 PM UTC 24 |
Aug 21 10:18:08 PM UTC 24 |
42789689 ps |
| T1576 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_same_source.124882918 |
|
|
Aug 21 10:17:35 PM UTC 24 |
Aug 21 10:18:16 PM UTC 24 |
387752289 ps |
| T1577 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.1810895801 |
|
|
Aug 21 10:13:19 PM UTC 24 |
Aug 21 10:18:17 PM UTC 24 |
519379960 ps |
| T1578 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_large_delays.1427276363 |
|
|
Aug 21 10:17:09 PM UTC 24 |
Aug 21 10:18:20 PM UTC 24 |
7788919420 ps |
| T1579 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.3735626143 |
|
|
Aug 21 10:17:44 PM UTC 24 |
Aug 21 10:18:23 PM UTC 24 |
321339829 ps |
| T1580 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.3126411774 |
|
|
Aug 21 10:17:09 PM UTC 24 |
Aug 21 10:18:25 PM UTC 24 |
4490356968 ps |
| T1581 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device.811470620 |
|
|
Aug 21 10:17:31 PM UTC 24 |
Aug 21 10:19:00 PM UTC 24 |
2059317149 ps |
| T1582 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_unmapped_addr.1616622138 |
|
|
Aug 21 10:18:48 PM UTC 24 |
Aug 21 10:19:06 PM UTC 24 |
86007729 ps |
| T1583 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random.3349340022 |
|
|
Aug 21 10:18:17 PM UTC 24 |
Aug 21 10:19:06 PM UTC 24 |
433548167 ps |
| T1584 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_large_delays.2618299677 |
|
|
Aug 21 10:12:12 PM UTC 24 |
Aug 21 10:19:09 PM UTC 24 |
38391056467 ps |
| T1585 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_large_delays.180808585 |
|
|
Aug 21 10:18:29 PM UTC 24 |
Aug 21 10:19:10 PM UTC 24 |
2517478237 ps |
| T1586 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.2617782088 |
|
|
Aug 21 10:07:56 PM UTC 24 |
Aug 21 10:19:13 PM UTC 24 |
43731225423 ps |
| T1587 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_large_delays.1805151339 |
|
|
Aug 21 10:07:46 PM UTC 24 |
Aug 21 10:19:14 PM UTC 24 |
68346747940 ps |
| T1588 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_same_source.1420444388 |
|
|
Aug 21 10:18:39 PM UTC 24 |
Aug 21 10:19:17 PM UTC 24 |
513448155 ps |
| T382 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_same_csr_outstanding.3888833361 |
|
|
Aug 21 09:49:11 PM UTC 24 |
Aug 21 10:19:21 PM UTC 24 |
16518298646 ps |
| T1589 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_slow_rsp.4161734320 |
|
|
Aug 21 10:13:08 PM UTC 24 |
Aug 21 10:19:23 PM UTC 24 |
23531519041 ps |
| T1590 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.1111937369 |
|
|
Aug 21 10:18:46 PM UTC 24 |
Aug 21 10:19:24 PM UTC 24 |
718396422 ps |
| T1591 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_zero_delays.550056878 |
|
|
Aug 21 10:18:27 PM UTC 24 |
Aug 21 10:19:25 PM UTC 24 |
602500173 ps |
| T1592 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all.810217091 |
|
|
Aug 21 10:11:22 PM UTC 24 |
Aug 21 10:19:28 PM UTC 24 |
13045810964 ps |
| T1593 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_large_delays.2755345234 |
|
|
Aug 21 10:18:08 PM UTC 24 |
Aug 21 10:19:29 PM UTC 24 |
8410466949 ps |
| T1594 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_error.1749073247 |
|
|
Aug 21 10:17:48 PM UTC 24 |
Aug 21 10:19:30 PM UTC 24 |
2681357907 ps |
| T1595 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device.4251118700 |
|
|
Aug 21 10:18:30 PM UTC 24 |
Aug 21 10:19:43 PM UTC 24 |
765611288 ps |
| T721 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_error.362977125 |
|
|
Aug 21 10:13:18 PM UTC 24 |
Aug 21 10:19:46 PM UTC 24 |
9704725946 ps |
| T1596 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_zero_delays.4150319378 |
|
|
Aug 21 10:19:36 PM UTC 24 |
Aug 21 10:19:46 PM UTC 24 |
55381519 ps |
| T1597 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke.684645028 |
|
|
Aug 21 10:19:34 PM UTC 24 |
Aug 21 10:19:47 PM UTC 24 |
172252762 ps |
| T786 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.2284786454 |
|
|
Aug 21 10:09:25 PM UTC 24 |
Aug 21 10:19:49 PM UTC 24 |
16909492784 ps |
| T1598 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.2926488382 |
|
|
Aug 21 10:03:18 PM UTC 24 |
Aug 21 10:19:50 PM UTC 24 |
62116653485 ps |
| T1599 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.2350764054 |
|
|
Aug 21 10:18:09 PM UTC 24 |
Aug 21 10:19:54 PM UTC 24 |
5536465127 ps |
| T742 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.1421787701 |
|
|
Aug 21 10:10:07 PM UTC 24 |
Aug 21 10:19:59 PM UTC 24 |
37256781640 ps |
| T1600 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all.1551514737 |
|
|
Aug 21 10:14:19 PM UTC 24 |
Aug 21 10:20:05 PM UTC 24 |
8560131493 ps |
| T1601 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_random.1130618452 |
|
|
Aug 21 10:18:44 PM UTC 24 |
Aug 21 10:20:17 PM UTC 24 |
2487993755 ps |
| T1602 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.3282234889 |
|
|
Aug 21 10:20:08 PM UTC 24 |
Aug 21 10:20:18 PM UTC 24 |
71550445 ps |
| T1603 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_large_delays.2413471172 |
|
|
Aug 21 10:10:01 PM UTC 24 |
Aug 21 10:20:20 PM UTC 24 |
55414272230 ps |
| T1604 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random.5088228 |
|
|
Aug 21 10:19:44 PM UTC 24 |
Aug 21 10:20:21 PM UTC 24 |
885650450 ps |
| T1605 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device.1931156743 |
|
|
Aug 21 10:19:51 PM UTC 24 |
Aug 21 10:20:25 PM UTC 24 |
850799098 ps |
| T1606 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_random.3893984004 |
|
|
Aug 21 10:20:05 PM UTC 24 |
Aug 21 10:20:28 PM UTC 24 |
369939984 ps |
| T1607 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke.2207322802 |
|
|
Aug 21 10:20:22 PM UTC 24 |
Aug 21 10:20:32 PM UTC 24 |
44524567 ps |
| T1608 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_zero_delays.194018792 |
|
|
Aug 21 10:20:29 PM UTC 24 |
Aug 21 10:20:39 PM UTC 24 |
51938514 ps |
| T1609 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_unmapped_addr.2056299253 |
|
|
Aug 21 10:20:07 PM UTC 24 |
Aug 21 10:20:49 PM UTC 24 |
302322690 ps |
| T1610 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.1350996108 |
|
|
Aug 21 10:20:18 PM UTC 24 |
Aug 21 10:21:05 PM UTC 24 |
123885173 ps |
| T1611 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_same_source.175094467 |
|
|
Aug 21 10:19:54 PM UTC 24 |
Aug 21 10:21:08 PM UTC 24 |
2411851443 ps |
| T1612 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all.2273141924 |
|
|
Aug 21 10:17:43 PM UTC 24 |
Aug 21 10:21:18 PM UTC 24 |
5113350172 ps |
| T1613 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_zero_delays.2089963116 |
|
|
Aug 21 10:20:44 PM UTC 24 |
Aug 21 10:21:18 PM UTC 24 |
253726804 ps |
| T1614 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random.2287039780 |
|
|
Aug 21 10:20:44 PM UTC 24 |
Aug 21 10:21:23 PM UTC 24 |
766997137 ps |
| T1615 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_same_source.835409209 |
|
|
Aug 21 10:21:03 PM UTC 24 |
Aug 21 10:21:27 PM UTC 24 |
210765188 ps |
| T1616 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.2788128651 |
|
|
Aug 21 10:19:41 PM UTC 24 |
Aug 21 10:21:29 PM UTC 24 |
5872620249 ps |
| T1617 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_same_csr_outstanding.3775215308 |
|
|
Aug 21 09:25:15 PM UTC 24 |
Aug 21 10:21:32 PM UTC 24 |
28462708726 ps |
| T1618 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all.2093446584 |
|
|
Aug 21 10:20:06 PM UTC 24 |
Aug 21 10:21:41 PM UTC 24 |
2668089790 ps |
| T1619 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_unmapped_addr.257874806 |
|
|
Aug 21 10:21:29 PM UTC 24 |
Aug 21 10:21:48 PM UTC 24 |
89456434 ps |
| T1620 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.905731753 |
|
|
Aug 21 10:20:40 PM UTC 24 |
Aug 21 10:21:55 PM UTC 24 |
5344138599 ps |
| T1621 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_slow_rsp.287305776 |
|
|
Aug 21 10:15:00 PM UTC 24 |
Aug 21 10:22:00 PM UTC 24 |
27562474985 ps |
| T1622 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.4026752818 |
|
|
Aug 21 10:21:33 PM UTC 24 |
Aug 21 10:22:01 PM UTC 24 |
473203049 ps |
| T1623 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_error.994133412 |
|
|
Aug 21 10:15:23 PM UTC 24 |
Aug 21 10:22:02 PM UTC 24 |
11181075435 ps |
| T481 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.1765957616 |
|
|
Aug 21 10:10:27 PM UTC 24 |
Aug 21 10:22:02 PM UTC 24 |
11125537429 ps |
| T1624 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_random.1196705076 |
|
|
Aug 21 10:21:14 PM UTC 24 |
Aug 21 10:22:02 PM UTC 24 |
572593959 ps |
| T1625 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke.3825676526 |
|
|
Aug 21 10:21:51 PM UTC 24 |
Aug 21 10:22:03 PM UTC 24 |
200812588 ps |
| T1626 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_zero_delays.178569425 |
|
|
Aug 21 10:21:56 PM UTC 24 |
Aug 21 10:22:06 PM UTC 24 |
45855088 ps |
| T1627 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_slow_rsp.3392844778 |
|
|
Aug 21 10:14:04 PM UTC 24 |
Aug 21 10:22:06 PM UTC 24 |
33784093037 ps |
| T1628 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_large_delays.2778075119 |
|
|
Aug 21 10:19:36 PM UTC 24 |
Aug 21 10:22:07 PM UTC 24 |
9630506245 ps |
| T1629 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device.3862212586 |
|
|
Aug 21 10:20:53 PM UTC 24 |
Aug 21 10:22:18 PM UTC 24 |
1952536671 ps |
| T1630 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_large_delays.2373261853 |
|
|
Aug 21 10:06:25 PM UTC 24 |
Aug 21 10:22:29 PM UTC 24 |
85570820507 ps |
| T1631 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_large_delays.693186841 |
|
|
Aug 21 10:20:39 PM UTC 24 |
Aug 21 10:22:37 PM UTC 24 |
9289080171 ps |
| T1632 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.2753992815 |
|
|
Aug 21 10:17:47 PM UTC 24 |
Aug 21 10:22:37 PM UTC 24 |
591447137 ps |
| T751 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_error.2356163939 |
|
|
Aug 21 10:20:13 PM UTC 24 |
Aug 21 10:22:42 PM UTC 24 |
4328856933 ps |
| T1633 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_random.1870388053 |
|
|
Aug 21 10:22:29 PM UTC 24 |
Aug 21 10:22:50 PM UTC 24 |
275080790 ps |
| T454 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.2373274065 |
|
|
Aug 21 10:15:22 PM UTC 24 |
Aug 21 10:22:53 PM UTC 24 |
12628211583 ps |
| T1634 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.4288702189 |
|
|
Aug 21 10:22:30 PM UTC 24 |
Aug 21 10:22:54 PM UTC 24 |
364951602 ps |
| T1635 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_same_source.4020643206 |
|
|
Aug 21 10:22:24 PM UTC 24 |
Aug 21 10:23:02 PM UTC 24 |
343042738 ps |
| T1636 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke.1116327624 |
|
|
Aug 21 10:23:08 PM UTC 24 |
Aug 21 10:23:17 PM UTC 24 |
44250422 ps |
| T1637 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_zero_delays.3408312800 |
|
|
Aug 21 10:22:24 PM UTC 24 |
Aug 21 10:23:17 PM UTC 24 |
441030324 ps |
| T1638 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_large_delays.2490509364 |
|
|
Aug 21 10:22:05 PM UTC 24 |
Aug 21 10:23:20 PM UTC 24 |
7780131336 ps |
| T1639 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_slow_rsp.4008157391 |
|
|
Aug 21 10:10:03 PM UTC 24 |
Aug 21 10:23:25 PM UTC 24 |
49752625512 ps |
| T1640 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_zero_delays.2133548922 |
|
|
Aug 21 10:23:16 PM UTC 24 |
Aug 21 10:23:26 PM UTC 24 |
47279693 ps |
| T1641 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random.108890336 |
|
|
Aug 21 10:22:18 PM UTC 24 |
Aug 21 10:23:31 PM UTC 24 |
2365197454 ps |
| T1642 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_unmapped_addr.989759309 |
|
|
Aug 21 10:22:30 PM UTC 24 |
Aug 21 10:23:40 PM UTC 24 |
1209322816 ps |
| T1643 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all.2292437398 |
|
|
Aug 21 10:19:23 PM UTC 24 |
Aug 21 10:23:41 PM UTC 24 |
7167880508 ps |
| T1644 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.48918008 |
|
|
Aug 21 10:22:11 PM UTC 24 |
Aug 21 10:23:43 PM UTC 24 |
4633415493 ps |
| T1645 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_zero_delays.172167357 |
|
|
Aug 21 10:23:41 PM UTC 24 |
Aug 21 10:24:01 PM UTC 24 |
232708614 ps |
| T1646 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random.582626848 |
|
|
Aug 21 10:23:27 PM UTC 24 |
Aug 21 10:24:05 PM UTC 24 |
311090445 ps |
| T1647 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_large_delays.3751206469 |
|
|
Aug 21 10:14:55 PM UTC 24 |
Aug 21 10:24:10 PM UTC 24 |
55020512420 ps |
| T1648 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all.3530246879 |
|
|
Aug 21 10:21:43 PM UTC 24 |
Aug 21 10:24:14 PM UTC 24 |
1667099552 ps |
| T1649 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_unmapped_addr.3207686188 |
|
|
Aug 21 10:24:05 PM UTC 24 |
Aug 21 10:24:24 PM UTC 24 |
252087057 ps |
| T1650 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_random.1126103990 |
|
|
Aug 21 10:24:04 PM UTC 24 |
Aug 21 10:24:26 PM UTC 24 |
149400121 ps |
| T1651 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_same_source.4068294649 |
|
|
Aug 21 10:23:55 PM UTC 24 |
Aug 21 10:24:29 PM UTC 24 |
800665406 ps |
| T1652 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_large_delays.462956327 |
|
|
Aug 21 10:22:22 PM UTC 24 |
Aug 21 10:24:36 PM UTC 24 |
11234107293 ps |
| T1653 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device.3620604908 |
|
|
Aug 21 10:23:48 PM UTC 24 |
Aug 21 10:24:38 PM UTC 24 |
1211490987 ps |
| T1654 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_error.161523388 |
|
|
Aug 21 10:21:48 PM UTC 24 |
Aug 21 10:24:39 PM UTC 24 |
2180024229 ps |
| T1655 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device.1069675222 |
|
|
Aug 21 10:22:28 PM UTC 24 |
Aug 21 10:24:39 PM UTC 24 |
3128661566 ps |
| T1656 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_slow_rsp.1461060283 |
|
|
Aug 21 10:23:45 PM UTC 24 |
Aug 21 10:24:50 PM UTC 24 |
4622577822 ps |
| T597 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.2033178924 |
|
|
Aug 21 09:11:12 PM UTC 24 |
Aug 21 10:24:52 PM UTC 24 |
45646034870 ps |
| T1657 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.798272660 |
|
|
Aug 21 10:23:20 PM UTC 24 |
Aug 21 10:24:54 PM UTC 24 |
5505405166 ps |
| T1658 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke.1406596457 |
|
|
Aug 21 10:24:47 PM UTC 24 |
Aug 21 10:24:56 PM UTC 24 |
46253078 ps |
| T1659 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_zero_delays.1625829987 |
|
|
Aug 21 10:24:48 PM UTC 24 |
Aug 21 10:24:58 PM UTC 24 |
46821542 ps |
| T1660 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.1572336267 |
|
|
Aug 21 10:24:07 PM UTC 24 |
Aug 21 10:25:03 PM UTC 24 |
1270005321 ps |
| T789 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.2923834393 |
|
|
Aug 21 10:24:38 PM UTC 24 |
Aug 21 10:25:29 PM UTC 24 |
152816214 ps |
| T1661 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_zero_delays.3847253361 |
|
|
Aug 21 10:25:04 PM UTC 24 |
Aug 21 10:25:34 PM UTC 24 |
426357027 ps |
| T1662 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.3072522682 |
|
|
Aug 21 10:19:32 PM UTC 24 |
Aug 21 10:25:34 PM UTC 24 |
2716397483 ps |
| T1663 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_large_delays.1889880546 |
|
|
Aug 21 10:23:18 PM UTC 24 |
Aug 21 10:25:36 PM UTC 24 |
8244767058 ps |
| T746 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.2671746386 |
|
|
Aug 21 09:56:47 PM UTC 24 |
Aug 21 10:25:37 PM UTC 24 |
113418360726 ps |
| T1664 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_unmapped_addr.425383964 |
|
|
Aug 21 10:25:27 PM UTC 24 |
Aug 21 10:25:38 PM UTC 24 |
38861543 ps |
| T1665 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.699125263 |
|
|
Aug 21 10:20:12 PM UTC 24 |
Aug 21 10:25:41 PM UTC 24 |
547717040 ps |
| T1666 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_random.4279077821 |
|
|
Aug 21 10:25:22 PM UTC 24 |
Aug 21 10:25:50 PM UTC 24 |
240096080 ps |
| T1667 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_slow_rsp.2497612422 |
|
|
Aug 21 10:16:13 PM UTC 24 |
Aug 21 10:25:51 PM UTC 24 |
32256707061 ps |
| T1668 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random.2330666337 |
|
|
Aug 21 10:25:02 PM UTC 24 |
Aug 21 10:25:54 PM UTC 24 |
431727055 ps |
| T1669 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke.503192615 |
|
|
Aug 21 10:26:04 PM UTC 24 |
Aug 21 10:26:15 PM UTC 24 |
156494115 ps |
| T1670 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_zero_delays.4161879260 |
|
|
Aug 21 10:26:06 PM UTC 24 |
Aug 21 10:26:16 PM UTC 24 |
44541767 ps |
| T1671 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_same_csr_outstanding.3718020355 |
|
|
Aug 21 09:51:24 PM UTC 24 |
Aug 21 10:26:22 PM UTC 24 |
15850101903 ps |
| T1672 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.3051133435 |
|
|
Aug 21 10:24:59 PM UTC 24 |
Aug 21 10:26:24 PM UTC 24 |
5160345942 ps |
| T1673 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_same_source.1944906907 |
|
|
Aug 21 10:25:19 PM UTC 24 |
Aug 21 10:26:26 PM UTC 24 |
1635832519 ps |
| T1674 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all.3425264527 |
|
|
Aug 21 10:24:22 PM UTC 24 |
Aug 21 10:26:28 PM UTC 24 |
1182648689 ps |
| T1675 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.3178731019 |
|
|
Aug 21 10:26:00 PM UTC 24 |
Aug 21 10:26:30 PM UTC 24 |
9626475 ps |
| T1676 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_large_delays.43578412 |
|
|
Aug 21 10:24:52 PM UTC 24 |
Aug 21 10:26:37 PM UTC 24 |
10267809334 ps |
| T1677 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_large_delays.1445223520 |
|
|
Aug 21 10:10:54 PM UTC 24 |
Aug 21 10:26:40 PM UTC 24 |
88355670221 ps |
| T1678 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device.4231527119 |
|
|
Aug 21 10:25:17 PM UTC 24 |
Aug 21 10:26:44 PM UTC 24 |
2166468707 ps |
| T1679 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_large_delays.525112259 |
|
|
Aug 21 10:20:49 PM UTC 24 |
Aug 21 10:26:46 PM UTC 24 |
35344413148 ps |
| T1680 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.986064617 |
|
|
Aug 21 10:25:54 PM UTC 24 |
Aug 21 10:26:59 PM UTC 24 |
1149513405 ps |
| T1681 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_random.370380582 |
|
|
Aug 21 10:26:52 PM UTC 24 |
Aug 21 10:27:01 PM UTC 24 |
140865520 ps |
| T1682 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_error.1226588420 |
|
|
Aug 21 10:23:02 PM UTC 24 |
Aug 21 10:27:08 PM UTC 24 |
7158708803 ps |
| T1683 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_zero_delays.196418 |
|
|
Aug 21 10:26:39 PM UTC 24 |
Aug 21 10:27:09 PM UTC 24 |
232839252 ps |
| T1684 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random.3485288414 |
|
|
Aug 21 10:26:20 PM UTC 24 |
Aug 21 10:27:13 PM UTC 24 |
478538969 ps |
| T1685 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.2533980750 |
|
|
Aug 21 10:21:43 PM UTC 24 |
Aug 21 10:27:16 PM UTC 24 |
3542872416 ps |
| T1686 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device.3929692758 |
|
|
Aug 21 10:26:48 PM UTC 24 |
Aug 21 10:27:17 PM UTC 24 |
298780992 ps |
| T1687 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_large_delays.2788106227 |
|
|
Aug 21 10:15:57 PM UTC 24 |
Aug 21 10:27:16 PM UTC 24 |
76109045690 ps |
| T1688 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_large_delays.2567197313 |
|
|
Aug 21 10:17:30 PM UTC 24 |
Aug 21 10:27:24 PM UTC 24 |
61524713158 ps |
| T1689 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_unmapped_addr.151694533 |
|
|
Aug 21 10:26:58 PM UTC 24 |
Aug 21 10:27:26 PM UTC 24 |
444405611 ps |
| T1690 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.195760928 |
|
|
Aug 21 10:21:52 PM UTC 24 |
Aug 21 10:27:28 PM UTC 24 |
7321319228 ps |
| T1691 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_slow_rsp.3287659361 |
|
|
Aug 21 10:18:29 PM UTC 24 |
Aug 21 10:27:28 PM UTC 24 |
31926143833 ps |
| T762 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_error.2029295286 |
|
|
Aug 21 10:24:35 PM UTC 24 |
Aug 21 10:27:31 PM UTC 24 |
5614707249 ps |
| T1692 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_same_source.1031842583 |
|
|
Aug 21 10:26:51 PM UTC 24 |
Aug 21 10:27:34 PM UTC 24 |
374067198 ps |
| T1693 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.3505716690 |
|
|
Aug 21 10:26:15 PM UTC 24 |
Aug 21 10:27:35 PM UTC 24 |
5394818088 ps |
| T1694 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.2945138812 |
|
|
Aug 21 10:27:06 PM UTC 24 |
Aug 21 10:27:40 PM UTC 24 |
291424463 ps |
| T1695 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_zero_delays.2815742376 |
|
|
Aug 21 10:27:33 PM UTC 24 |
Aug 21 10:27:43 PM UTC 24 |
39786082 ps |
| T1696 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke.1072991310 |
|
|
Aug 21 10:27:32 PM UTC 24 |
Aug 21 10:27:46 PM UTC 24 |
201391039 ps |
| T783 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.3835791470 |
|
|
Aug 21 10:26:03 PM UTC 24 |
Aug 21 10:27:55 PM UTC 24 |
179418961 ps |
| T1697 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_zero_delays.2772039874 |
|
|
Aug 21 10:27:37 PM UTC 24 |
Aug 21 10:27:57 PM UTC 24 |
135343702 ps |
| T798 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.1175435501 |
|
|
Aug 21 10:16:37 PM UTC 24 |
Aug 21 10:28:08 PM UTC 24 |
4478421233 ps |
| T1698 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_unmapped_addr.918164917 |
|
|
Aug 21 10:27:59 PM UTC 24 |
Aug 21 10:28:13 PM UTC 24 |
330525473 ps |
| T1699 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_large_delays.2300272096 |
|
|
Aug 21 10:26:15 PM UTC 24 |
Aug 21 10:28:14 PM UTC 24 |
7387248778 ps |
| T1700 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.2989003997 |
|
|
Aug 21 10:28:03 PM UTC 24 |
Aug 21 10:28:20 PM UTC 24 |
115831096 ps |
| T1701 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_random.3786327533 |
|
|
Aug 21 10:27:57 PM UTC 24 |
Aug 21 10:28:25 PM UTC 24 |
690235185 ps |
| T781 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.163991663 |
|
|
Aug 21 10:23:03 PM UTC 24 |
Aug 21 10:28:30 PM UTC 24 |
1834287228 ps |
| T1702 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device.1352917876 |
|
|
Aug 21 10:27:51 PM UTC 24 |
Aug 21 10:28:33 PM UTC 24 |
547701747 ps |
| T1703 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random.1424662202 |
|
|
Aug 21 10:27:38 PM UTC 24 |
Aug 21 10:28:37 PM UTC 24 |
1969559953 ps |
| T1704 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all.1139473250 |
|
|
Aug 21 10:25:58 PM UTC 24 |
Aug 21 10:28:46 PM UTC 24 |
4593639948 ps |
| T1705 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke.3899413768 |
|
|
Aug 21 10:28:33 PM UTC 24 |
Aug 21 10:28:48 PM UTC 24 |
229936107 ps |
| T1706 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_zero_delays.3259807521 |
|
|
Aug 21 10:28:38 PM UTC 24 |
Aug 21 10:28:49 PM UTC 24 |
52673481 ps |
| T1707 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_large_delays.2751305676 |
|
|
Aug 21 10:27:36 PM UTC 24 |
Aug 21 10:29:13 PM UTC 24 |
7190195558 ps |
| T1708 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_same_source.3779089222 |
|
|
Aug 21 10:27:54 PM UTC 24 |
Aug 21 10:29:15 PM UTC 24 |
2125514628 ps |
| T1709 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_large_delays.2850010043 |
|
|
Aug 21 10:19:46 PM UTC 24 |
Aug 21 10:29:19 PM UTC 24 |
44950466983 ps |
| T1710 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.1104497880 |
|
|
Aug 21 10:22:54 PM UTC 24 |
Aug 21 10:29:24 PM UTC 24 |
5521141248 ps |
| T1711 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.2888941245 |
|
|
Aug 21 10:27:38 PM UTC 24 |
Aug 21 10:29:35 PM UTC 24 |
5867095646 ps |
| T1712 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_zero_delays.996895175 |
|
|
Aug 21 10:28:56 PM UTC 24 |
Aug 21 10:29:43 PM UTC 24 |
402532887 ps |
| T1713 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_slow_rsp.2439678686 |
|
|
Aug 21 10:27:48 PM UTC 24 |
Aug 21 10:29:44 PM UTC 24 |
7733590577 ps |
| T1714 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.3502436924 |
|
|
Aug 21 10:28:07 PM UTC 24 |
Aug 21 10:29:49 PM UTC 24 |
401290932 ps |
| T1715 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all.3005432979 |
|
|
Aug 21 10:22:42 PM UTC 24 |
Aug 21 10:29:51 PM UTC 24 |
10367223050 ps |
| T1716 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random.2667440047 |
|
|
Aug 21 10:28:48 PM UTC 24 |
Aug 21 10:29:56 PM UTC 24 |
589392800 ps |
| T1717 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.1955600984 |
|
|
Aug 21 10:29:42 PM UTC 24 |
Aug 21 10:29:58 PM UTC 24 |
212394424 ps |
| T1718 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_random.2603440233 |
|
|
Aug 21 10:29:38 PM UTC 24 |
Aug 21 10:30:01 PM UTC 24 |
683682045 ps |
| T1719 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.2437331442 |
|
|
Aug 21 10:28:42 PM UTC 24 |
Aug 21 10:30:15 PM UTC 24 |
4404117380 ps |
| T1720 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.4058884817 |
|
|
Aug 21 10:27:27 PM UTC 24 |
Aug 21 10:30:18 PM UTC 24 |
2655145437 ps |
| T1721 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke.2517245338 |
|
|
Aug 21 10:30:13 PM UTC 24 |
Aug 21 10:30:22 PM UTC 24 |
141880569 ps |
| T1722 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_same_source.3263606084 |
|
|
Aug 21 10:29:13 PM UTC 24 |
Aug 21 10:30:23 PM UTC 24 |
1935229292 ps |
| T1723 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_zero_delays.2907535340 |
|
|
Aug 21 10:30:16 PM UTC 24 |
Aug 21 10:30:24 PM UTC 24 |
40341734 ps |
| T806 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.3607391794 |
|
|
Aug 21 10:19:27 PM UTC 24 |
Aug 21 10:30:33 PM UTC 24 |
5035972746 ps |
| T1724 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_unmapped_addr.1702321342 |
|
|
Aug 21 10:29:39 PM UTC 24 |
Aug 21 10:30:47 PM UTC 24 |
1186973014 ps |
| T1725 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_large_delays.1829803390 |
|
|
Aug 21 10:14:04 PM UTC 24 |
Aug 21 10:30:48 PM UTC 24 |
100204246845 ps |
| T759 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.1267353827 |
|
|
Aug 21 10:18:39 PM UTC 24 |
Aug 21 10:30:52 PM UTC 24 |
42223197639 ps |
| T1726 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_large_delays.2748148785 |
|
|
Aug 21 10:28:38 PM UTC 24 |
Aug 21 10:30:54 PM UTC 24 |
8703800881 ps |
| T1727 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device.1030969031 |
|
|
Aug 21 10:29:11 PM UTC 24 |
Aug 21 10:30:58 PM UTC 24 |
1955531000 ps |
| T1728 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_error.1688020960 |
|
|
Aug 21 10:19:31 PM UTC 24 |
Aug 21 10:31:05 PM UTC 24 |
19866634278 ps |
| T1729 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device.481870864 |
|
|
Aug 21 10:30:47 PM UTC 24 |
Aug 21 10:31:09 PM UTC 24 |
123503658 ps |
| T1730 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_zero_delays.3795250391 |
|
|
Aug 21 10:30:40 PM UTC 24 |
Aug 21 10:31:13 PM UTC 24 |
279866758 ps |
| T1731 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_large_delays.261447334 |
|
|
Aug 21 10:28:56 PM UTC 24 |
Aug 21 10:31:17 PM UTC 24 |
12794827628 ps |
| T1732 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random.1981423099 |
|
|
Aug 21 10:30:26 PM UTC 24 |
Aug 21 10:31:17 PM UTC 24 |
472475016 ps |
| T1733 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_large_delays.1824229059 |
|
|
Aug 21 10:13:02 PM UTC 24 |
Aug 21 10:31:24 PM UTC 24 |
107855248073 ps |
| T1734 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_unmapped_addr.3940918921 |
|
|
Aug 21 10:31:12 PM UTC 24 |
Aug 21 10:31:29 PM UTC 24 |
287295638 ps |
| T1735 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all.1206462149 |
|
|
Aug 21 10:31:18 PM UTC 24 |
Aug 21 10:31:29 PM UTC 24 |
55093350 ps |
| T1736 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.2305704940 |
|
|
Aug 21 10:30:22 PM UTC 24 |
Aug 21 10:31:36 PM UTC 24 |
5240070519 ps |
| T1737 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_zero_delays.3555961980 |
|
|
Aug 21 10:31:37 PM UTC 24 |
Aug 21 10:31:44 PM UTC 24 |
44696208 ps |
| T1738 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke.3902886288 |
|
|
Aug 21 10:31:37 PM UTC 24 |
Aug 21 10:31:44 PM UTC 24 |
43479323 ps |
| T1739 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_random.1707221567 |
|
|
Aug 21 10:31:12 PM UTC 24 |
Aug 21 10:31:52 PM UTC 24 |
462597184 ps |
| T763 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.4144851497 |
|
|
Aug 21 10:13:09 PM UTC 24 |
Aug 21 10:31:58 PM UTC 24 |
71332449258 ps |
| T1740 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_same_source.1214273564 |
|
|
Aug 21 10:30:54 PM UTC 24 |
Aug 21 10:32:00 PM UTC 24 |
1859370403 ps |
| T1741 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.1630795815 |
|
|
Aug 21 10:31:16 PM UTC 24 |
Aug 21 10:32:02 PM UTC 24 |
874039164 ps |
| T1742 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.1456252864 |
|
|
Aug 21 10:24:30 PM UTC 24 |
Aug 21 10:32:08 PM UTC 24 |
5813659700 ps |
| T811 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.151585898 |
|
|
Aug 21 10:27:09 PM UTC 24 |
Aug 21 10:32:15 PM UTC 24 |
702317955 ps |
| T1743 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_zero_delays.2863274854 |
|
|
Aug 21 10:31:52 PM UTC 24 |
Aug 21 10:32:23 PM UTC 24 |
359618288 ps |
| T1744 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_large_delays.1904608324 |
|
|
Aug 21 10:30:21 PM UTC 24 |
Aug 21 10:32:24 PM UTC 24 |
8150241727 ps |
| T1745 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_error.1646468896 |
|
|
Aug 21 10:28:20 PM UTC 24 |
Aug 21 10:32:28 PM UTC 24 |
7359943207 ps |
| T1746 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random.2064286447 |
|
|
Aug 21 10:31:54 PM UTC 24 |
Aug 21 10:32:34 PM UTC 24 |
802123850 ps |
| T1747 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_random.2612141014 |
|
|
Aug 21 10:32:23 PM UTC 24 |
Aug 21 10:32:38 PM UTC 24 |
179679085 ps |
| T1748 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device.3591876204 |
|
|
Aug 21 10:32:10 PM UTC 24 |
Aug 21 10:32:44 PM UTC 24 |
387778391 ps |
| T1749 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.637417967 |
|
|
Aug 21 10:31:46 PM UTC 24 |
Aug 21 10:32:45 PM UTC 24 |
3653321152 ps |
| T1750 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.1715989816 |
|
|
Aug 21 10:32:33 PM UTC 24 |
Aug 21 10:32:47 PM UTC 24 |
73319164 ps |
| T1751 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_same_source.3190313536 |
|
|
Aug 21 10:32:19 PM UTC 24 |
Aug 21 10:32:47 PM UTC 24 |
709851845 ps |
| T1752 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_unmapped_addr.3018942055 |
|
|
Aug 21 10:32:26 PM UTC 24 |
Aug 21 10:32:52 PM UTC 24 |
155370536 ps |
| T1753 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_error.250028051 |
|
|
Aug 21 10:27:20 PM UTC 24 |
Aug 21 10:32:57 PM UTC 24 |
10450324045 ps |
| T1754 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_error.2007112331 |
|
|
Aug 21 10:26:01 PM UTC 24 |
Aug 21 10:33:06 PM UTC 24 |
12747040282 ps |
| T1755 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke.2329407718 |
|
|
Aug 21 10:32:58 PM UTC 24 |
Aug 21 10:33:08 PM UTC 24 |
46179799 ps |
| T1756 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_zero_delays.783760707 |
|
|
Aug 21 10:33:02 PM UTC 24 |
Aug 21 10:33:11 PM UTC 24 |
42281752 ps |
| T1757 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.1282922247 |
|
|
Aug 21 10:14:08 PM UTC 24 |
Aug 21 10:33:12 PM UTC 24 |
74759634646 ps |
| T1758 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_large_delays.2026454509 |
|
|
Aug 21 10:31:40 PM UTC 24 |
Aug 21 10:33:17 PM UTC 24 |
8657002777 ps |
| T807 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.2262173833 |
|
|
Aug 21 10:31:21 PM UTC 24 |
Aug 21 10:33:29 PM UTC 24 |
475688588 ps |
| T1759 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_same_csr_outstanding.2202178192 |
|
|
Aug 21 09:37:02 PM UTC 24 |
Aug 21 10:33:30 PM UTC 24 |
28584843239 ps |
| T1760 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_slow_rsp.2451207343 |
|
|
Aug 21 10:19:49 PM UTC 24 |
Aug 21 10:33:38 PM UTC 24 |
44227453727 ps |
| T1761 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.3770630198 |
|
|
Aug 21 10:17:51 PM UTC 24 |
Aug 21 10:33:42 PM UTC 24 |
24305174368 ps |
| T1762 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_large_delays.317553069 |
|
|
Aug 21 10:27:47 PM UTC 24 |
Aug 21 10:33:44 PM UTC 24 |
32233801552 ps |
| T1763 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.3592009235 |
|
|
Aug 21 10:05:25 PM UTC 24 |
Aug 21 10:33:50 PM UTC 24 |
102598026741 ps |
| T1764 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.3004263594 |
|
|
Aug 21 10:32:48 PM UTC 24 |
Aug 21 10:33:54 PM UTC 24 |
222893988 ps |
| T1765 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random.3593708174 |
|
|
Aug 21 10:33:11 PM UTC 24 |
Aug 21 10:33:57 PM UTC 24 |
549094274 ps |
| T1766 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_same_source.896742172 |
|
|
Aug 21 10:33:34 PM UTC 24 |
Aug 21 10:33:59 PM UTC 24 |
498466673 ps |
| T1767 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_unmapped_addr.234268167 |
|
|
Aug 21 10:33:41 PM UTC 24 |
Aug 21 10:34:03 PM UTC 24 |
150108254 ps |
| T1768 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all.1042316829 |
|
|
Aug 21 10:29:50 PM UTC 24 |
Aug 21 10:34:06 PM UTC 24 |
3527211521 ps |
| T1769 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.563343528 |
|
|
Aug 21 10:33:54 PM UTC 24 |
Aug 21 10:34:08 PM UTC 24 |
71794548 ps |
| T1770 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_zero_delays.2055784606 |
|
|
Aug 21 10:33:12 PM UTC 24 |
Aug 21 10:34:08 PM UTC 24 |
507662702 ps |
| T1771 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all.179100355 |
|
|
Aug 21 10:32:39 PM UTC 24 |
Aug 21 10:34:14 PM UTC 24 |
1177358767 ps |
| T1772 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_slow_rsp.1443087698 |
|
|
Aug 21 10:33:22 PM UTC 24 |
Aug 21 10:34:18 PM UTC 24 |
3778037219 ps |
| T1773 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.1807952889 |
|
|
Aug 21 10:30:00 PM UTC 24 |
Aug 21 10:34:25 PM UTC 24 |
443617635 ps |
| T1774 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke.1822027159 |
|
|
Aug 21 10:34:14 PM UTC 24 |
Aug 21 10:34:26 PM UTC 24 |
187136947 ps |
| T1775 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_zero_delays.4177570888 |
|
|
Aug 21 10:34:16 PM UTC 24 |
Aug 21 10:34:27 PM UTC 24 |
49081332 ps |
| T1776 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_random.1553325028 |
|
|
Aug 21 10:33:36 PM UTC 24 |
Aug 21 10:34:28 PM UTC 24 |
586552660 ps |
| T1777 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.650535373 |
|
|
Aug 21 10:31:30 PM UTC 24 |
Aug 21 10:34:37 PM UTC 24 |
439570148 ps |
| T1778 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.1929157963 |
|
|
Aug 21 10:30:09 PM UTC 24 |
Aug 21 10:34:40 PM UTC 24 |
4393270140 ps |
| T805 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.2615365188 |
|
|
Aug 21 10:28:23 PM UTC 24 |
Aug 21 10:34:47 PM UTC 24 |
5633828747 ps |
| T1779 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_large_delays.1185079305 |
|
|
Aug 21 10:33:09 PM UTC 24 |
Aug 21 10:34:48 PM UTC 24 |
8842007122 ps |