| T1172 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2528479106 |
|
|
Aug 21 09:34:07 PM UTC 24 |
Aug 21 09:34:14 PM UTC 24 |
46884814 ps |
| T714 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.3341736857 |
|
|
Aug 21 09:22:23 PM UTC 24 |
Aug 21 09:34:15 PM UTC 24 |
50960011360 ps |
| T1173 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke.1171054642 |
|
|
Aug 21 09:34:04 PM UTC 24 |
Aug 21 09:34:17 PM UTC 24 |
202303388 ps |
| T1174 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_rw.1333952936 |
|
|
Aug 21 09:26:50 PM UTC 24 |
Aug 21 09:34:36 PM UTC 24 |
6389792792 ps |
| T1175 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_large_delays.1801561899 |
|
|
Aug 21 09:34:09 PM UTC 24 |
Aug 21 09:35:23 PM UTC 24 |
6932232428 ps |
| T1176 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.3866308471 |
|
|
Aug 21 09:29:56 PM UTC 24 |
Aug 21 09:35:25 PM UTC 24 |
28177403734 ps |
| T1177 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_zero_delays.3032993947 |
|
|
Aug 21 09:34:38 PM UTC 24 |
Aug 21 09:35:26 PM UTC 24 |
355451711 ps |
| T563 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random.2448478906 |
|
|
Aug 21 09:34:21 PM UTC 24 |
Aug 21 09:35:58 PM UTC 24 |
2187922094 ps |
| T1178 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.884769347 |
|
|
Aug 21 09:34:13 PM UTC 24 |
Aug 21 09:35:59 PM UTC 24 |
4854827332 ps |
| T1179 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.170432476 |
|
|
Aug 21 09:26:50 PM UTC 24 |
Aug 21 09:36:06 PM UTC 24 |
6272120922 ps |
| T1180 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_random.821270697 |
|
|
Aug 21 09:35:50 PM UTC 24 |
Aug 21 09:36:12 PM UTC 24 |
278879468 ps |
| T529 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_slow_rsp.2404515642 |
|
|
Aug 21 09:21:40 PM UTC 24 |
Aug 21 09:36:30 PM UTC 24 |
59688011270 ps |
| T1181 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_rw.107362372 |
|
|
Aug 21 09:25:01 PM UTC 24 |
Aug 21 09:36:30 PM UTC 24 |
6187861936 ps |
| T1182 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.2558059055 |
|
|
Aug 21 09:35:49 PM UTC 24 |
Aug 21 09:36:31 PM UTC 24 |
1198311200 ps |
| T1183 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1288556941 |
|
|
Aug 21 09:36:23 PM UTC 24 |
Aug 21 09:36:42 PM UTC 24 |
429143156 ps |
| T1184 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all.1860963231 |
|
|
Aug 21 09:36:31 PM UTC 24 |
Aug 21 09:36:42 PM UTC 24 |
56465014 ps |
| T522 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.2555293507 |
|
|
Aug 21 09:31:22 PM UTC 24 |
Aug 21 09:36:50 PM UTC 24 |
4899264412 ps |
| T1185 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.4270524960 |
|
|
Aug 21 09:31:09 PM UTC 24 |
Aug 21 09:36:53 PM UTC 24 |
4580297095 ps |
| T423 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device.3950162333 |
|
|
Aug 21 09:35:01 PM UTC 24 |
Aug 21 09:37:02 PM UTC 24 |
1180473004 ps |
| T1186 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_unmapped_addr.3069703239 |
|
|
Aug 21 09:36:22 PM UTC 24 |
Aug 21 09:37:08 PM UTC 24 |
905868804 ps |
| T1187 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.59091023 |
|
|
Aug 21 09:25:06 PM UTC 24 |
Aug 21 09:37:15 PM UTC 24 |
12232451938 ps |
| T1188 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_large_delays.2816044716 |
|
|
Aug 21 09:24:05 PM UTC 24 |
Aug 21 09:37:24 PM UTC 24 |
82594876742 ps |
| T792 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1091248250 |
|
|
Aug 21 09:36:56 PM UTC 24 |
Aug 21 09:37:25 PM UTC 24 |
142580482 ps |
| T1189 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke.2860224523 |
|
|
Aug 21 09:37:16 PM UTC 24 |
Aug 21 09:37:29 PM UTC 24 |
196392355 ps |
| T426 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3038031236 |
|
|
Aug 21 09:30:55 PM UTC 24 |
Aug 21 09:37:30 PM UTC 24 |
4015527299 ps |
| T1190 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_zero_delays.2555531935 |
|
|
Aug 21 09:37:26 PM UTC 24 |
Aug 21 09:37:34 PM UTC 24 |
47188042 ps |
| T730 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1890008632 |
|
|
Aug 21 09:30:57 PM UTC 24 |
Aug 21 09:37:38 PM UTC 24 |
6920474689 ps |
| T365 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.4026839855 |
|
|
Aug 21 09:09:53 PM UTC 24 |
Aug 21 09:37:43 PM UTC 24 |
14485878530 ps |
| T1191 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_error.2250899565 |
|
|
Aug 21 09:33:11 PM UTC 24 |
Aug 21 09:38:00 PM UTC 24 |
10603745545 ps |
| T526 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.1112874846 |
|
|
Aug 21 09:33:55 PM UTC 24 |
Aug 21 09:38:05 PM UTC 24 |
3821026153 ps |
| T1192 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.4147458968 |
|
|
Aug 21 09:37:58 PM UTC 24 |
Aug 21 09:38:05 PM UTC 24 |
15030819 ps |
| T1193 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.2754286620 |
|
|
Aug 21 09:23:37 PM UTC 24 |
Aug 21 09:38:06 PM UTC 24 |
12491294948 ps |
| T1194 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.3053498502 |
|
|
Aug 21 09:31:17 PM UTC 24 |
Aug 21 09:38:09 PM UTC 24 |
7073974232 ps |
| T1195 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.2529021302 |
|
|
Aug 21 09:37:39 PM UTC 24 |
Aug 21 09:38:16 PM UTC 24 |
2848533060 ps |
| T1196 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_same_source.2451452681 |
|
|
Aug 21 09:38:08 PM UTC 24 |
Aug 21 09:38:22 PM UTC 24 |
146881958 ps |
| T1197 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.3902727704 |
|
|
Aug 21 09:28:59 PM UTC 24 |
Aug 21 09:38:30 PM UTC 24 |
7531565720 ps |
| T715 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3694702686 |
|
|
Aug 21 09:32:21 PM UTC 24 |
Aug 21 09:38:37 PM UTC 24 |
26403217510 ps |
| T1198 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_zero_delays.1695645286 |
|
|
Aug 21 09:37:49 PM UTC 24 |
Aug 21 09:38:38 PM UTC 24 |
393501059 ps |
| T1199 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.346914888 |
|
|
Aug 21 09:38:26 PM UTC 24 |
Aug 21 09:38:41 PM UTC 24 |
66176771 ps |
| T1200 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random.2701632016 |
|
|
Aug 21 09:37:42 PM UTC 24 |
Aug 21 09:38:41 PM UTC 24 |
1633799303 ps |
| T431 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.3094048956 |
|
|
Aug 21 09:32:56 PM UTC 24 |
Aug 21 09:38:55 PM UTC 24 |
11143241271 ps |
| T1201 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_unmapped_addr.436220590 |
|
|
Aug 21 09:38:24 PM UTC 24 |
Aug 21 09:38:58 PM UTC 24 |
287219060 ps |
| T1202 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_large_delays.539629167 |
|
|
Aug 21 09:37:31 PM UTC 24 |
Aug 21 09:39:00 PM UTC 24 |
8889751229 ps |
| T1203 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_large_delays.3147934021 |
|
|
Aug 21 09:34:39 PM UTC 24 |
Aug 21 09:39:15 PM UTC 24 |
17642808723 ps |
| T1204 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke.307743543 |
|
|
Aug 21 09:39:05 PM UTC 24 |
Aug 21 09:39:17 PM UTC 24 |
131724794 ps |
| T1205 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_rw.512342973 |
|
|
Aug 21 09:29:01 PM UTC 24 |
Aug 21 09:39:17 PM UTC 24 |
6404689110 ps |
| T1206 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_error.430473739 |
|
|
Aug 21 09:36:55 PM UTC 24 |
Aug 21 09:39:26 PM UTC 24 |
1682299354 ps |
| T1207 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.3820885011 |
|
|
Aug 21 09:33:46 PM UTC 24 |
Aug 21 09:39:29 PM UTC 24 |
3651874964 ps |
| T1208 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_zero_delays.2070074031 |
|
|
Aug 21 09:39:19 PM UTC 24 |
Aug 21 09:39:30 PM UTC 24 |
49272439 ps |
| T482 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all.190077784 |
|
|
Aug 21 09:38:29 PM UTC 24 |
Aug 21 09:39:42 PM UTC 24 |
999505420 ps |
| T735 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1731226731 |
|
|
Aug 21 09:38:47 PM UTC 24 |
Aug 21 09:39:54 PM UTC 24 |
312582158 ps |
| T466 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.836174220 |
|
|
Aug 21 09:32:59 PM UTC 24 |
Aug 21 09:40:00 PM UTC 24 |
2905590527 ps |
| T456 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_zero_delays.1441984156 |
|
|
Aug 21 09:39:40 PM UTC 24 |
Aug 21 09:40:08 PM UTC 24 |
229164637 ps |
| T458 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random.2833929136 |
|
|
Aug 21 09:39:40 PM UTC 24 |
Aug 21 09:40:08 PM UTC 24 |
300062336 ps |
| T1209 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_slow_rsp.3609261586 |
|
|
Aug 21 09:25:44 PM UTC 24 |
Aug 21 09:40:09 PM UTC 24 |
52403699913 ps |
| T1210 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_random.2308608631 |
|
|
Aug 21 09:38:21 PM UTC 24 |
Aug 21 09:40:15 PM UTC 24 |
2388943699 ps |
| T726 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_error.4128538999 |
|
|
Aug 21 09:38:41 PM UTC 24 |
Aug 21 09:40:22 PM UTC 24 |
1454345335 ps |
| T1211 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_same_source.4148805831 |
|
|
Aug 21 09:40:07 PM UTC 24 |
Aug 21 09:40:27 PM UTC 24 |
160854234 ps |
| T1212 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.3799645931 |
|
|
Aug 21 09:39:25 PM UTC 24 |
Aug 21 09:40:38 PM UTC 24 |
5224182419 ps |
| T1213 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_unmapped_addr.2412476699 |
|
|
Aug 21 09:40:25 PM UTC 24 |
Aug 21 09:40:52 PM UTC 24 |
155036388 ps |
| T1214 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_random.2239412675 |
|
|
Aug 21 09:40:18 PM UTC 24 |
Aug 21 09:41:07 PM UTC 24 |
1002982445 ps |
| T731 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.3426600266 |
|
|
Aug 21 09:28:55 PM UTC 24 |
Aug 21 09:41:23 PM UTC 24 |
14597530246 ps |
| T1215 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_large_delays.2801279985 |
|
|
Aug 21 09:32:09 PM UTC 24 |
Aug 21 09:41:26 PM UTC 24 |
48465787869 ps |
| T1216 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3574381333 |
|
|
Aug 21 09:40:33 PM UTC 24 |
Aug 21 09:41:32 PM UTC 24 |
1412420751 ps |
| T1217 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_large_delays.3397956190 |
|
|
Aug 21 09:39:23 PM UTC 24 |
Aug 21 09:41:33 PM UTC 24 |
8614635716 ps |
| T732 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device.2183520377 |
|
|
Aug 21 09:39:52 PM UTC 24 |
Aug 21 09:41:35 PM UTC 24 |
1960381856 ps |
| T535 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.4203094864 |
|
|
Aug 21 09:37:15 PM UTC 24 |
Aug 21 09:41:38 PM UTC 24 |
3991380772 ps |
| T545 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_tl_errors.3211487743 |
|
|
Aug 21 09:39:06 PM UTC 24 |
Aug 21 09:41:46 PM UTC 24 |
3198013100 ps |
| T1218 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_zero_delays.650440983 |
|
|
Aug 21 09:41:51 PM UTC 24 |
Aug 21 09:41:59 PM UTC 24 |
42449561 ps |
| T484 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_large_delays.1545256459 |
|
|
Aug 21 09:21:35 PM UTC 24 |
Aug 21 09:41:59 PM UTC 24 |
105351788505 ps |
| T1219 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke.1332249653 |
|
|
Aug 21 09:41:47 PM UTC 24 |
Aug 21 09:42:02 PM UTC 24 |
246042868 ps |
| T1220 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.967835290 |
|
|
Aug 21 09:29:55 PM UTC 24 |
Aug 21 09:42:08 PM UTC 24 |
51041478283 ps |
| T754 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all.4156411623 |
|
|
Aug 21 09:40:33 PM UTC 24 |
Aug 21 09:42:17 PM UTC 24 |
1132810240 ps |
| T1221 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_rw.4165704737 |
|
|
Aug 21 09:36:55 PM UTC 24 |
Aug 21 09:42:28 PM UTC 24 |
3694471464 ps |
| T1222 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_zero_delays.2418369461 |
|
|
Aug 21 09:42:02 PM UTC 24 |
Aug 21 09:42:32 PM UTC 24 |
237880459 ps |
| T782 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.1797819940 |
|
|
Aug 21 09:40:33 PM UTC 24 |
Aug 21 09:42:41 PM UTC 24 |
248963251 ps |
| T475 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random.2821065105 |
|
|
Aug 21 09:41:59 PM UTC 24 |
Aug 21 09:42:52 PM UTC 24 |
462293352 ps |
| T1223 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_large_delays.3908741446 |
|
|
Aug 21 09:41:57 PM UTC 24 |
Aug 21 09:42:56 PM UTC 24 |
5734032345 ps |
| T718 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1918682006 |
|
|
Aug 21 09:30:26 PM UTC 24 |
Aug 21 09:43:02 PM UTC 24 |
48975296703 ps |
| T1224 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_same_source.1022617875 |
|
|
Aug 21 09:42:33 PM UTC 24 |
Aug 21 09:43:06 PM UTC 24 |
319464535 ps |
| T1225 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_large_delays.3620545244 |
|
|
Aug 21 09:39:42 PM UTC 24 |
Aug 21 09:43:13 PM UTC 24 |
23851797116 ps |
| T421 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device.795079432 |
|
|
Aug 21 09:42:24 PM UTC 24 |
Aug 21 09:43:16 PM UTC 24 |
627107536 ps |
| T1226 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_random.529708055 |
|
|
Aug 21 09:42:41 PM UTC 24 |
Aug 21 09:43:16 PM UTC 24 |
787996145 ps |
| T1227 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_unmapped_addr.4094377360 |
|
|
Aug 21 09:42:52 PM UTC 24 |
Aug 21 09:43:38 PM UTC 24 |
1209755841 ps |
| T1228 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.2990824415 |
|
|
Aug 21 09:41:57 PM UTC 24 |
Aug 21 09:43:41 PM UTC 24 |
4582003654 ps |
| T1229 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.3743552930 |
|
|
Aug 21 09:42:56 PM UTC 24 |
Aug 21 09:43:43 PM UTC 24 |
799472750 ps |
| T1230 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke.998952852 |
|
|
Aug 21 09:43:40 PM UTC 24 |
Aug 21 09:43:50 PM UTC 24 |
44864837 ps |
| T1231 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_zero_delays.4236839612 |
|
|
Aug 21 09:44:02 PM UTC 24 |
Aug 21 09:44:10 PM UTC 24 |
32163273 ps |
| T464 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.579959745 |
|
|
Aug 21 09:38:33 PM UTC 24 |
Aug 21 09:44:18 PM UTC 24 |
1128419269 ps |
| T707 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.1727785836 |
|
|
Aug 21 09:19:30 PM UTC 24 |
Aug 21 09:44:40 PM UTC 24 |
104501192983 ps |
| T446 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random.3465446469 |
|
|
Aug 21 09:44:15 PM UTC 24 |
Aug 21 09:44:51 PM UTC 24 |
730948554 ps |
| T1232 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_same_csr_outstanding.1191949861 |
|
|
Aug 21 09:12:14 PM UTC 24 |
Aug 21 09:44:52 PM UTC 24 |
16489509690 ps |
| T1233 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_rw.715763195 |
|
|
Aug 21 09:38:53 PM UTC 24 |
Aug 21 09:44:54 PM UTC 24 |
4331086194 ps |
| T472 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_large_delays.2926123064 |
|
|
Aug 21 09:25:42 PM UTC 24 |
Aug 21 09:44:59 PM UTC 24 |
94732990330 ps |
| T1234 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_large_delays.1491821950 |
|
|
Aug 21 09:44:06 PM UTC 24 |
Aug 21 09:45:26 PM UTC 24 |
4910926362 ps |
| T473 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_zero_delays.487234643 |
|
|
Aug 21 09:44:35 PM UTC 24 |
Aug 21 09:45:27 PM UTC 24 |
551550172 ps |
| T1235 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.2877648275 |
|
|
Aug 21 09:44:08 PM UTC 24 |
Aug 21 09:45:41 PM UTC 24 |
4328624049 ps |
| T538 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_tl_errors.3657061229 |
|
|
Aug 21 09:43:41 PM UTC 24 |
Aug 21 09:45:45 PM UTC 24 |
3568147055 ps |
| T366 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_same_csr_outstanding.3770117171 |
|
|
Aug 21 09:20:57 PM UTC 24 |
Aug 21 09:45:51 PM UTC 24 |
14586981227 ps |
| T1236 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_same_source.4037231143 |
|
|
Aug 21 09:45:19 PM UTC 24 |
Aug 21 09:45:52 PM UTC 24 |
376817778 ps |
| T722 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_error.372444587 |
|
|
Aug 21 09:43:17 PM UTC 24 |
Aug 21 09:45:57 PM UTC 24 |
4353595368 ps |
| T1237 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_unmapped_addr.3849036531 |
|
|
Aug 21 09:45:50 PM UTC 24 |
Aug 21 09:46:01 PM UTC 24 |
49512327 ps |
| T723 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2881382872 |
|
|
Aug 21 09:12:37 PM UTC 24 |
Aug 21 09:46:12 PM UTC 24 |
135561193225 ps |
| T1238 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.2960754038 |
|
|
Aug 21 09:45:51 PM UTC 24 |
Aug 21 09:46:29 PM UTC 24 |
225683935 ps |
| T1239 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_random.3412026538 |
|
|
Aug 21 09:45:23 PM UTC 24 |
Aug 21 09:46:29 PM UTC 24 |
1329666504 ps |
| T536 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_tl_errors.1536675360 |
|
|
Aug 21 09:41:32 PM UTC 24 |
Aug 21 09:46:45 PM UTC 24 |
3493546750 ps |
| T1240 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_rw.3910179665 |
|
|
Aug 21 09:43:22 PM UTC 24 |
Aug 21 09:46:52 PM UTC 24 |
3775102990 ps |
| T1241 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke.3662214868 |
|
|
Aug 21 09:46:52 PM UTC 24 |
Aug 21 09:47:00 PM UTC 24 |
53865683 ps |
| T1242 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_rw.2785501965 |
|
|
Aug 21 09:40:52 PM UTC 24 |
Aug 21 09:47:10 PM UTC 24 |
3728611404 ps |
| T367 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_same_csr_outstanding.3479235283 |
|
|
Aug 21 09:13:37 PM UTC 24 |
Aug 21 09:47:13 PM UTC 24 |
15723316459 ps |
| T1243 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_zero_delays.2657486982 |
|
|
Aug 21 09:47:09 PM UTC 24 |
Aug 21 09:47:19 PM UTC 24 |
42135674 ps |
| T1244 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_large_delays.4285738212 |
|
|
Aug 21 09:37:50 PM UTC 24 |
Aug 21 09:47:27 PM UTC 24 |
52675212642 ps |
| T368 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_same_csr_outstanding.851513927 |
|
|
Aug 21 09:18:08 PM UTC 24 |
Aug 21 09:47:28 PM UTC 24 |
16033071080 ps |
| T724 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device.942606730 |
|
|
Aug 21 09:45:16 PM UTC 24 |
Aug 21 09:47:30 PM UTC 24 |
2339114014 ps |
| T737 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1020451132 |
|
|
Aug 21 09:38:02 PM UTC 24 |
Aug 21 09:47:36 PM UTC 24 |
33297081096 ps |
| T780 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.1799287757 |
|
|
Aug 21 09:43:09 PM UTC 24 |
Aug 21 09:47:37 PM UTC 24 |
1190581176 ps |
| T1245 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.871075278 |
|
|
Aug 21 09:37:05 PM UTC 24 |
Aug 21 09:48:11 PM UTC 24 |
6616951067 ps |
| T581 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.1759051641 |
|
|
Aug 21 09:43:20 PM UTC 24 |
Aug 21 09:48:13 PM UTC 24 |
2117946854 ps |
| T443 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_zero_delays.4263867245 |
|
|
Aug 21 09:47:37 PM UTC 24 |
Aug 21 09:48:17 PM UTC 24 |
332358463 ps |
| T1246 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_random.3653316015 |
|
|
Aug 21 09:48:02 PM UTC 24 |
Aug 21 09:48:18 PM UTC 24 |
88619375 ps |
| T729 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_error.20946273 |
|
|
Aug 21 09:40:39 PM UTC 24 |
Aug 21 09:48:35 PM UTC 24 |
13790860710 ps |
| T1247 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_slow_rsp.804566418 |
|
|
Aug 21 09:39:51 PM UTC 24 |
Aug 21 09:48:40 PM UTC 24 |
38084614492 ps |
| T1248 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.2951292633 |
|
|
Aug 21 09:48:38 PM UTC 24 |
Aug 21 09:48:44 PM UTC 24 |
22993513 ps |
| T439 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_same_source.4034463211 |
|
|
Aug 21 09:48:01 PM UTC 24 |
Aug 21 09:48:46 PM UTC 24 |
485902400 ps |
| T1249 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.1363496962 |
|
|
Aug 21 09:47:24 PM UTC 24 |
Aug 21 09:48:46 PM UTC 24 |
6104210149 ps |
| T756 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_error.2687946610 |
|
|
Aug 21 09:46:15 PM UTC 24 |
Aug 21 09:48:48 PM UTC 24 |
1808248686 ps |
| T1250 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random.1422080672 |
|
|
Aug 21 09:47:33 PM UTC 24 |
Aug 21 09:48:49 PM UTC 24 |
1652098013 ps |
| T799 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.419562746 |
|
|
Aug 21 09:40:45 PM UTC 24 |
Aug 21 09:48:59 PM UTC 24 |
3001321390 ps |
| T1251 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_large_delays.2206576131 |
|
|
Aug 21 09:47:17 PM UTC 24 |
Aug 21 09:49:10 PM UTC 24 |
7787759187 ps |
| T1252 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all.349999995 |
|
|
Aug 21 09:48:41 PM UTC 24 |
Aug 21 09:49:11 PM UTC 24 |
338218120 ps |
| T1253 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke.617167553 |
|
|
Aug 21 09:49:13 PM UTC 24 |
Aug 21 09:49:20 PM UTC 24 |
50867413 ps |
| T1254 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_unmapped_addr.1644471633 |
|
|
Aug 21 09:48:37 PM UTC 24 |
Aug 21 09:49:27 PM UTC 24 |
1081634970 ps |
| T440 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3027987808 |
|
|
Aug 21 09:36:36 PM UTC 24 |
Aug 21 09:49:30 PM UTC 24 |
6061854153 ps |
| T1255 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_zero_delays.1558723020 |
|
|
Aug 21 09:49:24 PM UTC 24 |
Aug 21 09:49:34 PM UTC 24 |
44800970 ps |
| T1256 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_large_delays.633992341 |
|
|
Aug 21 09:44:42 PM UTC 24 |
Aug 21 09:49:34 PM UTC 24 |
26418659757 ps |
| T1257 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.3783217087 |
|
|
Aug 21 09:39:01 PM UTC 24 |
Aug 21 09:49:34 PM UTC 24 |
7887804346 ps |
| T480 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device.895198921 |
|
|
Aug 21 09:47:49 PM UTC 24 |
Aug 21 09:49:54 PM UTC 24 |
2676166596 ps |
| T557 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_tl_errors.2175555745 |
|
|
Aug 21 09:46:51 PM UTC 24 |
Aug 21 09:49:56 PM UTC 24 |
3982992503 ps |
| T1258 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_slow_rsp.4139080458 |
|
|
Aug 21 09:37:53 PM UTC 24 |
Aug 21 09:50:01 PM UTC 24 |
44298701114 ps |
| T1259 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random.2048642399 |
|
|
Aug 21 09:49:45 PM UTC 24 |
Aug 21 09:50:02 PM UTC 24 |
205748893 ps |
| T1260 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_slow_rsp.4264970273 |
|
|
Aug 21 09:34:36 PM UTC 24 |
Aug 21 09:50:08 PM UTC 24 |
63507456855 ps |
| T553 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_slow_rsp.2667837531 |
|
|
Aug 21 09:47:50 PM UTC 24 |
Aug 21 09:50:20 PM UTC 24 |
6678450170 ps |
| T1261 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.3927633926 |
|
|
Aug 21 09:33:50 PM UTC 24 |
Aug 21 09:50:23 PM UTC 24 |
11165821625 ps |
| T489 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_zero_delays.1498688833 |
|
|
Aug 21 09:49:51 PM UTC 24 |
Aug 21 09:50:31 PM UTC 24 |
470931771 ps |
| T369 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_same_csr_outstanding.112533834 |
|
|
Aug 21 09:23:36 PM UTC 24 |
Aug 21 09:50:40 PM UTC 24 |
15817663264 ps |
| T444 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all.2323529496 |
|
|
Aug 21 09:43:05 PM UTC 24 |
Aug 21 09:50:52 PM UTC 24 |
10843753886 ps |
| T1262 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.2460600455 |
|
|
Aug 21 09:50:26 PM UTC 24 |
Aug 21 09:50:59 PM UTC 24 |
602501607 ps |
| T1263 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_same_source.3362852950 |
|
|
Aug 21 09:50:17 PM UTC 24 |
Aug 21 09:51:09 PM UTC 24 |
1212303970 ps |
| T1264 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_random.2492514033 |
|
|
Aug 21 09:50:18 PM UTC 24 |
Aug 21 09:51:12 PM UTC 24 |
1547653738 ps |
| T785 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.3644871207 |
|
|
Aug 21 09:46:06 PM UTC 24 |
Aug 21 09:51:19 PM UTC 24 |
979226742 ps |
| T1265 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_unmapped_addr.1423864260 |
|
|
Aug 21 09:50:24 PM UTC 24 |
Aug 21 09:51:22 PM UTC 24 |
1440053094 ps |
| T1266 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.980981818 |
|
|
Aug 21 09:49:36 PM UTC 24 |
Aug 21 09:51:22 PM UTC 24 |
6809130917 ps |
| T736 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2811807403 |
|
|
Aug 21 09:35:49 PM UTC 24 |
Aug 21 09:51:28 PM UTC 24 |
53102025226 ps |
| T448 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device.1897802177 |
|
|
Aug 21 09:49:58 PM UTC 24 |
Aug 21 09:51:37 PM UTC 24 |
2500290441 ps |
| T1267 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_error.4139213473 |
|
|
Aug 21 09:50:45 PM UTC 24 |
Aug 21 09:51:37 PM UTC 24 |
1406438216 ps |
| T772 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.4020752478 |
|
|
Aug 21 09:46:14 PM UTC 24 |
Aug 21 09:51:49 PM UTC 24 |
2179982847 ps |
| T1268 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_zero_delays.2986972573 |
|
|
Aug 21 09:51:42 PM UTC 24 |
Aug 21 09:51:49 PM UTC 24 |
52589648 ps |
| T1269 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke.2649226677 |
|
|
Aug 21 09:51:36 PM UTC 24 |
Aug 21 09:51:51 PM UTC 24 |
214310531 ps |
| T1270 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_large_delays.2997362344 |
|
|
Aug 21 09:49:35 PM UTC 24 |
Aug 21 09:52:07 PM UTC 24 |
9234654894 ps |
| T1271 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_error.479749987 |
|
|
Aug 21 09:48:59 PM UTC 24 |
Aug 21 09:52:30 PM UTC 24 |
5402240326 ps |
| T1272 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random.218269675 |
|
|
Aug 21 09:51:51 PM UTC 24 |
Aug 21 09:52:56 PM UTC 24 |
1874994959 ps |
| T802 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.546665405 |
|
|
Aug 21 09:49:02 PM UTC 24 |
Aug 21 09:53:06 PM UTC 24 |
882163739 ps |
| T1273 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_zero_delays.2104913518 |
|
|
Aug 21 09:52:02 PM UTC 24 |
Aug 21 09:53:08 PM UTC 24 |
648125084 ps |
| T1274 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_same_source.3115852116 |
|
|
Aug 21 09:52:32 PM UTC 24 |
Aug 21 09:53:11 PM UTC 24 |
327432297 ps |
| T449 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all.3601801396 |
|
|
Aug 21 09:46:04 PM UTC 24 |
Aug 21 09:53:12 PM UTC 24 |
13432602345 ps |
| T1275 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.3477332990 |
|
|
Aug 21 09:43:31 PM UTC 24 |
Aug 21 09:53:23 PM UTC 24 |
6215299615 ps |
| T558 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_tl_errors.4077475918 |
|
|
Aug 21 09:49:13 PM UTC 24 |
Aug 21 09:53:29 PM UTC 24 |
3635082140 ps |
| T733 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.859259527 |
|
|
Aug 21 09:17:21 PM UTC 24 |
Aug 21 09:53:37 PM UTC 24 |
133372509338 ps |
| T1276 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_unmapped_addr.4212314501 |
|
|
Aug 21 09:53:21 PM UTC 24 |
Aug 21 09:53:47 PM UTC 24 |
425498245 ps |
| T1277 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_random.711500898 |
|
|
Aug 21 09:52:55 PM UTC 24 |
Aug 21 09:53:48 PM UTC 24 |
1331501510 ps |
| T1278 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke.3523733161 |
|
|
Aug 21 09:54:11 PM UTC 24 |
Aug 21 09:54:22 PM UTC 24 |
52621343 ps |
| T769 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device.221190068 |
|
|
Aug 21 09:52:15 PM UTC 24 |
Aug 21 09:53:52 PM UTC 24 |
2427238272 ps |
| T1279 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.789671672 |
|
|
Aug 21 09:51:44 PM UTC 24 |
Aug 21 09:54:03 PM UTC 24 |
5775759091 ps |
| T1280 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_large_delays.3481041666 |
|
|
Aug 21 09:51:46 PM UTC 24 |
Aug 21 09:54:04 PM UTC 24 |
9860036083 ps |
| T1281 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.1972080042 |
|
|
Aug 21 09:53:44 PM UTC 24 |
Aug 21 09:54:15 PM UTC 24 |
12440371 ps |
| T1282 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_zero_delays.496951644 |
|
|
Aug 21 09:54:12 PM UTC 24 |
Aug 21 09:54:20 PM UTC 24 |
52986024 ps |
| T1283 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.1332169212 |
|
|
Aug 21 09:53:31 PM UTC 24 |
Aug 21 09:54:26 PM UTC 24 |
1374831258 ps |
| T485 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_zero_delays.225189699 |
|
|
Aug 21 09:54:27 PM UTC 24 |
Aug 21 09:54:40 PM UTC 24 |
63373215 ps |
| T809 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.3824617945 |
|
|
Aug 21 09:50:40 PM UTC 24 |
Aug 21 09:55:07 PM UTC 24 |
653701149 ps |
| T755 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.2836979149 |
|
|
Aug 21 09:25:53 PM UTC 24 |
Aug 21 09:55:09 PM UTC 24 |
110669697747 ps |
| T1284 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random.1514681036 |
|
|
Aug 21 09:54:27 PM UTC 24 |
Aug 21 09:55:19 PM UTC 24 |
615792182 ps |
| T1285 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_large_delays.3585334416 |
|
|
Aug 21 09:54:13 PM UTC 24 |
Aug 21 09:55:37 PM UTC 24 |
8549545050 ps |
| T1286 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.1138330992 |
|
|
Aug 21 09:41:03 PM UTC 24 |
Aug 21 09:55:38 PM UTC 24 |
7871338136 ps |
| T461 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.4161544958 |
|
|
Aug 21 09:48:43 PM UTC 24 |
Aug 21 09:55:40 PM UTC 24 |
2769334095 ps |
| T740 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.1343773905 |
|
|
Aug 21 09:27:46 PM UTC 24 |
Aug 21 09:55:49 PM UTC 24 |
97717443585 ps |
| T1287 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_unmapped_addr.305463319 |
|
|
Aug 21 09:55:33 PM UTC 24 |
Aug 21 09:55:49 PM UTC 24 |
74540743 ps |
| T1288 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.328881973 |
|
|
Aug 21 09:54:15 PM UTC 24 |
Aug 21 09:55:52 PM UTC 24 |
5439163783 ps |
| T1289 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.3849013529 |
|
|
Aug 21 09:55:45 PM UTC 24 |
Aug 21 09:55:53 PM UTC 24 |
56859997 ps |
| T765 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device.2056307611 |
|
|
Aug 21 09:54:47 PM UTC 24 |
Aug 21 09:55:59 PM UTC 24 |
639972932 ps |
| T1290 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_large_delays.2132584021 |
|
|
Aug 21 09:54:39 PM UTC 24 |
Aug 21 09:56:14 PM UTC 24 |
6615213633 ps |
| T589 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_tl_errors.937581092 |
|
|
Aug 21 09:51:34 PM UTC 24 |
Aug 21 09:56:15 PM UTC 24 |
4113316192 ps |
| T1291 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all.975038690 |
|
|
Aug 21 09:53:32 PM UTC 24 |
Aug 21 09:56:15 PM UTC 24 |
1592206372 ps |
| T1292 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_same_csr_outstanding.1058871995 |
|
|
Aug 21 09:27:08 PM UTC 24 |
Aug 21 09:56:17 PM UTC 24 |
14584467522 ps |
| T1293 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke.2316404902 |
|
|
Aug 21 09:56:11 PM UTC 24 |
Aug 21 09:56:21 PM UTC 24 |
184873245 ps |
| T1294 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_zero_delays.1637883325 |
|
|
Aug 21 09:56:15 PM UTC 24 |
Aug 21 09:56:23 PM UTC 24 |
38206154 ps |
| T1295 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_same_source.4229407190 |
|
|
Aug 21 09:55:04 PM UTC 24 |
Aug 21 09:56:24 PM UTC 24 |
1942835574 ps |
| T1296 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_random.3663316428 |
|
|
Aug 21 09:55:32 PM UTC 24 |
Aug 21 09:56:27 PM UTC 24 |
1605301043 ps |
| T1297 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.183219743 |
|
|
Aug 21 09:49:10 PM UTC 24 |
Aug 21 09:56:30 PM UTC 24 |
6604925472 ps |
| T401 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_rw.2910182743 |
|
|
Aug 21 09:46:19 PM UTC 24 |
Aug 21 09:56:47 PM UTC 24 |
5976780040 ps |
| T1298 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random.3803718875 |
|
|
Aug 21 09:56:39 PM UTC 24 |
Aug 21 09:56:56 PM UTC 24 |
99005693 ps |
| T1299 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_unmapped_addr.657581303 |
|
|
Aug 21 09:56:53 PM UTC 24 |
Aug 21 09:57:16 PM UTC 24 |
173866118 ps |
| T1300 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_large_delays.3110356189 |
|
|
Aug 21 09:56:15 PM UTC 24 |
Aug 21 09:57:20 PM UTC 24 |
6976520595 ps |
| T571 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.chip_tl_errors.3568035915 |
|
|
Aug 21 09:54:00 PM UTC 24 |
Aug 21 09:57:25 PM UTC 24 |
3498945986 ps |
| T1301 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_error.4155046833 |
|
|
Aug 21 09:56:00 PM UTC 24 |
Aug 21 09:57:29 PM UTC 24 |
1286021933 ps |
| T1302 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_zero_delays.679681388 |
|
|
Aug 21 09:56:38 PM UTC 24 |
Aug 21 09:57:39 PM UTC 24 |
566853613 ps |
| T1303 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_slow_rsp.482963047 |
|
|
Aug 21 09:45:04 PM UTC 24 |
Aug 21 09:57:40 PM UTC 24 |
47972593396 ps |
| T441 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_same_source.795990961 |
|
|
Aug 21 09:56:48 PM UTC 24 |
Aug 21 09:57:47 PM UTC 24 |
1395865677 ps |
| T1304 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.2449164490 |
|
|
Aug 21 09:57:11 PM UTC 24 |
Aug 21 09:57:52 PM UTC 24 |
268609602 ps |
| T1305 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all.4036373743 |
|
|
Aug 21 09:50:33 PM UTC 24 |
Aug 21 09:57:56 PM UTC 24 |
13820209467 ps |
| T1306 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_zero_delays.636294316 |
|
|
Aug 21 09:58:02 PM UTC 24 |
Aug 21 09:58:11 PM UTC 24 |
39789735 ps |
| T474 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke.3616280291 |
|
|
Aug 21 09:58:03 PM UTC 24 |
Aug 21 09:58:13 PM UTC 24 |
46327602 ps |
| T1307 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.4219094661 |
|
|
Aug 21 09:56:22 PM UTC 24 |
Aug 21 09:58:13 PM UTC 24 |
5910524578 ps |
| T757 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device.758227276 |
|
|
Aug 21 09:56:44 PM UTC 24 |
Aug 21 09:58:14 PM UTC 24 |
785642367 ps |
| T1308 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_random.1811023955 |
|
|
Aug 21 09:56:50 PM UTC 24 |
Aug 21 09:58:19 PM UTC 24 |
1759511005 ps |
| T1309 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_unmapped_addr.485449213 |
|
|
Aug 21 10:00:38 PM UTC 24 |
Aug 21 10:01:33 PM UTC 24 |
899426232 ps |
| T1310 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.1540332131 |
|
|
Aug 21 09:51:16 PM UTC 24 |
Aug 21 09:58:21 PM UTC 24 |
7039997799 ps |
| T483 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all.226432598 |
|
|
Aug 21 09:55:49 PM UTC 24 |
Aug 21 09:58:22 PM UTC 24 |
2140519916 ps |
| T1311 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_slow_rsp.773092993 |
|
|
Aug 21 09:42:24 PM UTC 24 |
Aug 21 09:58:25 PM UTC 24 |
72084086543 ps |
| T1312 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_large_delays.2605428621 |
|
|
Aug 21 09:42:11 PM UTC 24 |
Aug 21 09:58:49 PM UTC 24 |
90706149665 ps |
| T1313 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_rw.2409606850 |
|
|
Aug 21 09:49:08 PM UTC 24 |
Aug 21 09:58:49 PM UTC 24 |
5865504160 ps |
| T1314 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_zero_delays.2595371977 |
|
|
Aug 21 09:58:36 PM UTC 24 |
Aug 21 09:59:09 PM UTC 24 |
380132311 ps |
| T766 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_error.1181253971 |
|
|
Aug 21 09:53:34 PM UTC 24 |
Aug 21 09:59:11 PM UTC 24 |
9611428356 ps |
| T1315 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_random.1202339698 |
|
|
Aug 21 09:58:45 PM UTC 24 |
Aug 21 09:59:22 PM UTC 24 |
934841016 ps |
| T1316 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.4251735399 |
|
|
Aug 21 09:59:12 PM UTC 24 |
Aug 21 09:59:23 PM UTC 24 |
33136670 ps |
| T1317 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device.1913597520 |
|
|
Aug 21 09:58:38 PM UTC 24 |
Aug 21 09:59:28 PM UTC 24 |
508801367 ps |
| T1318 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_unmapped_addr.445852078 |
|
|
Aug 21 09:58:49 PM UTC 24 |
Aug 21 09:59:36 PM UTC 24 |
262781156 ps |
| T1319 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_same_source.1960184015 |
|
|
Aug 21 09:58:46 PM UTC 24 |
Aug 21 09:59:37 PM UTC 24 |
557354959 ps |
| T1320 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_same_csr_outstanding.3549567668 |
|
|
Aug 21 09:33:50 PM UTC 24 |
Aug 21 09:59:37 PM UTC 24 |
14797950382 ps |
| T804 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.3919786902 |
|
|
Aug 21 09:57:50 PM UTC 24 |
Aug 21 09:59:56 PM UTC 24 |
298362948 ps |
| T490 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all.2288077670 |
|
|
Aug 21 09:57:21 PM UTC 24 |
Aug 21 09:59:56 PM UTC 24 |
2069960855 ps |
| T1321 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.3453591992 |
|
|
Aug 21 09:58:16 PM UTC 24 |
Aug 21 09:59:56 PM UTC 24 |
6044245778 ps |
| T1322 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_large_delays.3507263875 |
|
|
Aug 21 09:58:12 PM UTC 24 |
Aug 21 09:59:57 PM UTC 24 |
7746852195 ps |
| T1323 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_rw.557738938 |
|
|
Aug 21 09:53:49 PM UTC 24 |
Aug 21 09:59:57 PM UTC 24 |
4444013976 ps |
| T1324 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_slow_rsp.3852452908 |
|
|
Aug 21 09:52:13 PM UTC 24 |
Aug 21 10:00:04 PM UTC 24 |
26339356829 ps |
| T1325 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke.3018964150 |
|
|
Aug 21 09:59:52 PM UTC 24 |
Aug 21 10:00:06 PM UTC 24 |
214582056 ps |
| T486 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random.295877710 |
|
|
Aug 21 09:58:21 PM UTC 24 |
Aug 21 10:00:11 PM UTC 24 |
2354507467 ps |
| T1326 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_zero_delays.194113198 |
|
|
Aug 21 10:00:00 PM UTC 24 |
Aug 21 10:00:14 PM UTC 24 |
47822826 ps |
| T1327 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_zero_delays.3459370571 |
|
|
Aug 21 10:00:20 PM UTC 24 |
Aug 21 10:00:30 PM UTC 24 |
31851598 ps |
| T1328 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_rw.523366265 |
|
|
Aug 21 09:51:06 PM UTC 24 |
Aug 21 10:00:39 PM UTC 24 |
5721201284 ps |
| T1329 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_same_source.669583762 |
|
|
Aug 21 10:00:31 PM UTC 24 |
Aug 21 10:00:49 PM UTC 24 |
303420834 ps |
| T1330 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_random.2663755249 |
|
|
Aug 21 10:00:34 PM UTC 24 |
Aug 21 10:00:50 PM UTC 24 |
107748722 ps |
| T442 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_large_delays.3245973791 |
|
|
Aug 21 09:47:43 PM UTC 24 |
Aug 21 10:00:51 PM UTC 24 |
76983375891 ps |
| T1331 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random.1200328305 |
|
|
Aug 21 10:00:19 PM UTC 24 |
Aug 21 10:00:55 PM UTC 24 |
1177025745 ps |
| T1332 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_large_delays.334761823 |
|
|
Aug 21 09:56:37 PM UTC 24 |
Aug 21 10:01:02 PM UTC 24 |
19444222921 ps |
| T1333 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.902998544 |
|
|
Aug 21 10:00:01 PM UTC 24 |
Aug 21 10:01:14 PM UTC 24 |
4054234152 ps |
| T1334 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.360423215 |
|
|
Aug 21 09:54:51 PM UTC 24 |
Aug 21 10:01:14 PM UTC 24 |
24049518625 ps |
| T468 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.775838424 |
|
|
Aug 21 09:56:01 PM UTC 24 |
Aug 21 10:01:15 PM UTC 24 |
6813238792 ps |
| T1335 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_large_delays.2348990150 |
|
|
Aug 21 09:58:37 PM UTC 24 |
Aug 21 10:01:18 PM UTC 24 |
11709884683 ps |
| T1336 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.815206088 |
|
|
Aug 21 09:56:00 PM UTC 24 |
Aug 21 10:01:25 PM UTC 24 |
2985987213 ps |
| T1337 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.2589431298 |
|
|
Aug 21 10:00:54 PM UTC 24 |
Aug 21 10:01:29 PM UTC 24 |
699640261 ps |