| T1338 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device.1625632545 |
|
|
Aug 21 10:00:21 PM UTC 24 |
Aug 21 10:01:36 PM UTC 24 |
919734295 ps |
| T1339 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_error.3379420328 |
|
|
Aug 21 10:01:15 PM UTC 24 |
Aug 21 10:01:37 PM UTC 24 |
393970138 ps |
| T749 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.1363059878 |
|
|
Aug 21 09:58:43 PM UTC 24 |
Aug 21 10:01:39 PM UTC 24 |
10419775278 ps |
| T787 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.689614418 |
|
|
Aug 21 09:57:41 PM UTC 24 |
Aug 21 10:01:41 PM UTC 24 |
684549921 ps |
| T1340 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke.903712815 |
|
|
Aug 21 10:01:26 PM UTC 24 |
Aug 21 10:01:41 PM UTC 24 |
266956123 ps |
| T1341 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_zero_delays.3303342433 |
|
|
Aug 21 10:01:37 PM UTC 24 |
Aug 21 10:01:47 PM UTC 24 |
40252087 ps |
| T1342 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.2646664720 |
|
|
Aug 21 09:53:52 PM UTC 24 |
Aug 21 10:01:58 PM UTC 24 |
6558291592 ps |
| T1343 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_large_delays.1661788487 |
|
|
Aug 21 10:00:01 PM UTC 24 |
Aug 21 10:02:00 PM UTC 24 |
9390705350 ps |
| T727 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.461108553 |
|
|
Aug 21 09:39:55 PM UTC 24 |
Aug 21 10:02:04 PM UTC 24 |
86890697017 ps |
| T708 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.799644448 |
|
|
Aug 21 09:53:34 PM UTC 24 |
Aug 21 10:02:05 PM UTC 24 |
11081218930 ps |
| T1344 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_error.3432217293 |
|
|
Aug 21 09:57:44 PM UTC 24 |
Aug 21 10:02:17 PM UTC 24 |
7489027758 ps |
| T1345 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random.1740544245 |
|
|
Aug 21 10:01:42 PM UTC 24 |
Aug 21 10:02:22 PM UTC 24 |
942698024 ps |
| T1346 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_error.624900223 |
|
|
Aug 21 09:59:35 PM UTC 24 |
Aug 21 10:02:33 PM UTC 24 |
2286650368 ps |
| T590 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.chip_tl_errors.155509694 |
|
|
Aug 21 09:57:53 PM UTC 24 |
Aug 21 10:02:34 PM UTC 24 |
3775719420 ps |
| T1347 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.1140767503 |
|
|
Aug 21 09:59:47 PM UTC 24 |
Aug 21 10:02:41 PM UTC 24 |
1160301813 ps |
| T469 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_large_delays.3878328918 |
|
|
Aug 21 10:01:37 PM UTC 24 |
Aug 21 10:02:42 PM UTC 24 |
6574829019 ps |
| T1348 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_unmapped_addr.3155975445 |
|
|
Aug 21 10:02:07 PM UTC 24 |
Aug 21 10:02:50 PM UTC 24 |
630670051 ps |
| T1349 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device.3815465808 |
|
|
Aug 21 10:02:01 PM UTC 24 |
Aug 21 10:02:49 PM UTC 24 |
857592469 ps |
| T380 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.3535465417 |
|
|
Aug 21 09:31:20 PM UTC 24 |
Aug 21 10:02:53 PM UTC 24 |
16261539007 ps |
| T1350 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.1901725580 |
|
|
Aug 21 09:46:24 PM UTC 24 |
Aug 21 10:02:54 PM UTC 24 |
11282818864 ps |
| T1351 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_zero_delays.3925382591 |
|
|
Aug 21 10:01:50 PM UTC 24 |
Aug 21 10:02:55 PM UTC 24 |
555574019 ps |
| T1352 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.2073529835 |
|
|
Aug 21 10:02:11 PM UTC 24 |
Aug 21 10:02:55 PM UTC 24 |
1093367888 ps |
| T1353 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke.2748658011 |
|
|
Aug 21 10:02:45 PM UTC 24 |
Aug 21 10:02:56 PM UTC 24 |
50877475 ps |
| T1354 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.1132841162 |
|
|
Aug 21 09:50:52 PM UTC 24 |
Aug 21 10:02:58 PM UTC 24 |
14704671971 ps |
| T1355 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_slow_rsp.51676166 |
|
|
Aug 21 10:00:19 PM UTC 24 |
Aug 21 10:03:03 PM UTC 24 |
8272945919 ps |
| T1356 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_random.2923701616 |
|
|
Aug 21 10:02:06 PM UTC 24 |
Aug 21 10:03:04 PM UTC 24 |
1548461278 ps |
| T1357 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_large_delays.3202415138 |
|
|
Aug 21 09:49:55 PM UTC 24 |
Aug 21 10:03:04 PM UTC 24 |
70708486116 ps |
| T1358 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_zero_delays.3980163816 |
|
|
Aug 21 10:02:57 PM UTC 24 |
Aug 21 10:03:06 PM UTC 24 |
43129738 ps |
| T1359 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_same_source.2170626101 |
|
|
Aug 21 10:02:04 PM UTC 24 |
Aug 21 10:03:14 PM UTC 24 |
1757751804 ps |
| T1360 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random.702054119 |
|
|
Aug 21 10:03:05 PM UTC 24 |
Aug 21 10:03:16 PM UTC 24 |
112838455 ps |
| T1361 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_zero_delays.1783444452 |
|
|
Aug 21 10:03:10 PM UTC 24 |
Aug 21 10:03:20 PM UTC 24 |
31608203 ps |
| T1362 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.3836616634 |
|
|
Aug 21 09:49:57 PM UTC 24 |
Aug 21 10:03:24 PM UTC 24 |
53697566387 ps |
| T1363 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.32037494 |
|
|
Aug 21 10:01:40 PM UTC 24 |
Aug 21 10:03:25 PM UTC 24 |
5155650235 ps |
| T1364 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.2740376521 |
|
|
Aug 21 10:01:16 PM UTC 24 |
Aug 21 10:03:26 PM UTC 24 |
434706821 ps |
| T1365 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_unmapped_addr.1169088784 |
|
|
Aug 21 10:03:18 PM UTC 24 |
Aug 21 10:03:29 PM UTC 24 |
146525097 ps |
| T725 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.3767587889 |
|
|
Aug 21 09:42:26 PM UTC 24 |
Aug 21 10:03:33 PM UTC 24 |
79841190790 ps |
| T1366 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_large_delays.2369585151 |
|
|
Aug 21 09:52:02 PM UTC 24 |
Aug 21 10:03:43 PM UTC 24 |
70625265939 ps |
| T1367 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.3899183018 |
|
|
Aug 21 10:01:14 PM UTC 24 |
Aug 21 10:03:50 PM UTC 24 |
618394985 ps |
| T1368 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke.1817152821 |
|
|
Aug 21 10:03:42 PM UTC 24 |
Aug 21 10:03:51 PM UTC 24 |
51313095 ps |
| T1369 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.227174263 |
|
|
Aug 21 10:03:27 PM UTC 24 |
Aug 21 10:03:56 PM UTC 24 |
171227293 ps |
| T1370 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_zero_delays.2313358965 |
|
|
Aug 21 10:03:49 PM UTC 24 |
Aug 21 10:03:59 PM UTC 24 |
48079067 ps |
| T487 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_same_source.1010706720 |
|
|
Aug 21 10:03:19 PM UTC 24 |
Aug 21 10:04:02 PM UTC 24 |
1613189116 ps |
| T1371 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all.1886595261 |
|
|
Aug 21 10:02:21 PM UTC 24 |
Aug 21 10:04:02 PM UTC 24 |
1009061884 ps |
| T1372 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random.2202421552 |
|
|
Aug 21 10:03:53 PM UTC 24 |
Aug 21 10:04:07 PM UTC 24 |
75086526 ps |
| T1373 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.2403124850 |
|
|
Aug 21 10:03:04 PM UTC 24 |
Aug 21 10:04:19 PM UTC 24 |
4528976772 ps |
| T1374 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all.1806467884 |
|
|
Aug 21 10:01:04 PM UTC 24 |
Aug 21 10:04:22 PM UTC 24 |
2176747399 ps |
| T1375 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_zero_delays.3029658924 |
|
|
Aug 21 10:03:55 PM UTC 24 |
Aug 21 10:04:22 PM UTC 24 |
193629677 ps |
| T1376 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_slow_rsp.1317774063 |
|
|
Aug 21 10:03:14 PM UTC 24 |
Aug 21 10:04:23 PM UTC 24 |
4340909485 ps |
| T1377 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_large_delays.3347335872 |
|
|
Aug 21 10:02:58 PM UTC 24 |
Aug 21 10:04:26 PM UTC 24 |
8622593782 ps |
| T1378 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device.2215060619 |
|
|
Aug 21 10:04:15 PM UTC 24 |
Aug 21 10:04:27 PM UTC 24 |
73671416 ps |
| T402 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.678211871 |
|
|
Aug 21 09:29:05 PM UTC 24 |
Aug 21 10:04:30 PM UTC 24 |
16127353733 ps |
| T1379 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_random.3031952381 |
|
|
Aug 21 10:03:19 PM UTC 24 |
Aug 21 10:04:30 PM UTC 24 |
1933643900 ps |
| T775 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device.1314500129 |
|
|
Aug 21 10:03:18 PM UTC 24 |
Aug 21 10:04:34 PM UTC 24 |
1770357142 ps |
| T1380 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.4050084367 |
|
|
Aug 21 10:02:18 PM UTC 24 |
Aug 21 10:04:52 PM UTC 24 |
500681132 ps |
| T1381 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_unmapped_addr.1267599408 |
|
|
Aug 21 10:04:25 PM UTC 24 |
Aug 21 10:04:56 PM UTC 24 |
205925259 ps |
| T1382 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.3789437301 |
|
|
Aug 21 09:59:32 PM UTC 24 |
Aug 21 10:04:58 PM UTC 24 |
1548215616 ps |
| T797 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.811131785 |
|
|
Aug 21 10:03:28 PM UTC 24 |
Aug 21 10:05:02 PM UTC 24 |
199791610 ps |
| T1383 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_large_delays.677094371 |
|
|
Aug 21 10:03:14 PM UTC 24 |
Aug 21 10:05:02 PM UTC 24 |
12368691977 ps |
| T1384 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.1596475845 |
|
|
Aug 21 10:04:29 PM UTC 24 |
Aug 21 10:05:02 PM UTC 24 |
273645522 ps |
| T1385 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_zero_delays.1262934934 |
|
|
Aug 21 10:04:54 PM UTC 24 |
Aug 21 10:05:04 PM UTC 24 |
47459724 ps |
| T1386 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke.3614555662 |
|
|
Aug 21 10:04:51 PM UTC 24 |
Aug 21 10:05:04 PM UTC 24 |
156627361 ps |
| T1387 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_same_source.3846411940 |
|
|
Aug 21 10:04:24 PM UTC 24 |
Aug 21 10:05:04 PM UTC 24 |
389099109 ps |
| T1388 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.chip_tl_errors.2557856332 |
|
|
Aug 21 09:56:13 PM UTC 24 |
Aug 21 10:05:05 PM UTC 24 |
5312870431 ps |
| T1389 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_random.2553373443 |
|
|
Aug 21 10:04:27 PM UTC 24 |
Aug 21 10:05:15 PM UTC 24 |
636565456 ps |
| T1390 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.190667487 |
|
|
Aug 21 10:03:46 PM UTC 24 |
Aug 21 10:05:35 PM UTC 24 |
5997554016 ps |
| T1391 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.1933199321 |
|
|
Aug 21 10:04:47 PM UTC 24 |
Aug 21 10:05:39 PM UTC 24 |
67077984 ps |
| T1392 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_slow_rsp.1736421501 |
|
|
Aug 21 09:54:43 PM UTC 24 |
Aug 21 10:05:41 PM UTC 24 |
45119253316 ps |
| T1393 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_same_csr_outstanding.2415062838 |
|
|
Aug 21 09:15:47 PM UTC 24 |
Aug 21 10:05:42 PM UTC 24 |
31024270457 ps |
| T1394 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_unmapped_addr.1051765740 |
|
|
Aug 21 10:05:25 PM UTC 24 |
Aug 21 10:05:49 PM UTC 24 |
152320624 ps |
| T1395 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_slow_rsp.598808129 |
|
|
Aug 21 09:49:53 PM UTC 24 |
Aug 21 10:05:51 PM UTC 24 |
64864799906 ps |
| T591 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.chip_tl_errors.1221142937 |
|
|
Aug 21 09:59:48 PM UTC 24 |
Aug 21 10:05:53 PM UTC 24 |
5274548550 ps |
| T1396 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_same_source.2512911494 |
|
|
Aug 21 10:05:25 PM UTC 24 |
Aug 21 10:05:58 PM UTC 24 |
621084864 ps |
| T1397 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_zero_delays.3897639676 |
|
|
Aug 21 10:05:18 PM UTC 24 |
Aug 21 10:06:01 PM UTC 24 |
399599469 ps |
| T1398 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device.1918297141 |
|
|
Aug 21 10:05:24 PM UTC 24 |
Aug 21 10:06:02 PM UTC 24 |
410706879 ps |
| T1399 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_large_delays.3021456541 |
|
|
Aug 21 10:04:55 PM UTC 24 |
Aug 21 10:06:11 PM UTC 24 |
7000726358 ps |
| T1400 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.1427486519 |
|
|
Aug 21 10:05:27 PM UTC 24 |
Aug 21 10:06:14 PM UTC 24 |
1221280143 ps |
| T1401 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_large_delays.2116418748 |
|
|
Aug 21 10:03:51 PM UTC 24 |
Aug 21 10:06:14 PM UTC 24 |
10127128113 ps |
| T1402 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke.3374377704 |
|
|
Aug 21 10:06:05 PM UTC 24 |
Aug 21 10:06:16 PM UTC 24 |
150909056 ps |
| T1403 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all.3500599598 |
|
|
Aug 21 09:59:11 PM UTC 24 |
Aug 21 10:06:17 PM UTC 24 |
10710162069 ps |
| T1404 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.2433097453 |
|
|
Aug 21 10:02:29 PM UTC 24 |
Aug 21 10:06:20 PM UTC 24 |
727817665 ps |
| T1405 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_zero_delays.741220870 |
|
|
Aug 21 10:06:12 PM UTC 24 |
Aug 21 10:06:22 PM UTC 24 |
51587925 ps |
| T1406 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random.3774926578 |
|
|
Aug 21 10:05:16 PM UTC 24 |
Aug 21 10:06:27 PM UTC 24 |
1759680521 ps |
| T1407 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_random.1507394692 |
|
|
Aug 21 10:05:24 PM UTC 24 |
Aug 21 10:06:43 PM UTC 24 |
2214863374 ps |
| T1408 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.2559199914 |
|
|
Aug 21 10:05:00 PM UTC 24 |
Aug 21 10:06:50 PM UTC 24 |
5746198190 ps |
| T1409 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_zero_delays.34166713 |
|
|
Aug 21 10:06:24 PM UTC 24 |
Aug 21 10:06:53 PM UTC 24 |
265852538 ps |
| T1410 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_random.2753808571 |
|
|
Aug 21 10:06:41 PM UTC 24 |
Aug 21 10:06:54 PM UTC 24 |
208182571 ps |
| T1411 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random.4181077194 |
|
|
Aug 21 10:06:21 PM UTC 24 |
Aug 21 10:06:56 PM UTC 24 |
281489164 ps |
| T1412 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_large_delays.1881537194 |
|
|
Aug 21 10:05:19 PM UTC 24 |
Aug 21 10:07:09 PM UTC 24 |
7525940244 ps |
| T592 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.chip_tl_errors.3255152648 |
|
|
Aug 21 10:03:36 PM UTC 24 |
Aug 21 10:07:16 PM UTC 24 |
3878344020 ps |
| T1413 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_large_delays.2868789635 |
|
|
Aug 21 10:06:12 PM UTC 24 |
Aug 21 10:07:17 PM UTC 24 |
6167607873 ps |
| T1414 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.3848245422 |
|
|
Aug 21 10:06:41 PM UTC 24 |
Aug 21 10:07:19 PM UTC 24 |
896817904 ps |
| T447 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_unmapped_addr.3027657271 |
|
|
Aug 21 10:06:43 PM UTC 24 |
Aug 21 10:07:21 PM UTC 24 |
610940460 ps |
| T1415 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.873734833 |
|
|
Aug 21 10:06:15 PM UTC 24 |
Aug 21 10:07:25 PM UTC 24 |
3480864894 ps |
| T1416 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_large_delays.1372718779 |
|
|
Aug 21 10:00:21 PM UTC 24 |
Aug 21 10:07:26 PM UTC 24 |
37525894365 ps |
| T1417 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke.2641934579 |
|
|
Aug 21 10:07:16 PM UTC 24 |
Aug 21 10:07:29 PM UTC 24 |
192187367 ps |
| T1418 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.chip_tl_errors.694950895 |
|
|
Aug 21 10:02:42 PM UTC 24 |
Aug 21 10:07:35 PM UTC 24 |
4046322655 ps |
| T1419 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.chip_tl_errors.3719184557 |
|
|
Aug 21 10:04:51 PM UTC 24 |
Aug 21 10:07:41 PM UTC 24 |
3296743548 ps |
| T1420 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.chip_tl_errors.1578274824 |
|
|
Aug 21 10:01:19 PM UTC 24 |
Aug 21 10:07:41 PM UTC 24 |
4434591842 ps |
| T1421 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_zero_delays.1910460247 |
|
|
Aug 21 10:07:31 PM UTC 24 |
Aug 21 10:07:41 PM UTC 24 |
54166891 ps |
| T459 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_same_source.1383305645 |
|
|
Aug 21 10:06:38 PM UTC 24 |
Aug 21 10:07:47 PM UTC 24 |
1941532639 ps |
| T1422 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_error.455360669 |
|
|
Aug 21 10:03:28 PM UTC 24 |
Aug 21 10:07:51 PM UTC 24 |
3061394933 ps |
| T1423 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.chip_tl_errors.4212181620 |
|
|
Aug 21 10:06:05 PM UTC 24 |
Aug 21 10:08:01 PM UTC 24 |
3415823500 ps |
| T1424 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device.1458658438 |
|
|
Aug 21 10:06:37 PM UTC 24 |
Aug 21 10:08:06 PM UTC 24 |
2201912935 ps |
| T1425 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.3447068171 |
|
|
Aug 21 10:06:04 PM UTC 24 |
Aug 21 10:08:08 PM UTC 24 |
220362185 ps |
| T1426 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.2432675258 |
|
|
Aug 21 10:04:21 PM UTC 24 |
Aug 21 10:08:09 PM UTC 24 |
13697768264 ps |
| T1427 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_zero_delays.73766289 |
|
|
Aug 21 10:07:42 PM UTC 24 |
Aug 21 10:08:10 PM UTC 24 |
249469811 ps |
| T1428 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.2989863807 |
|
|
Aug 21 10:08:08 PM UTC 24 |
Aug 21 10:08:32 PM UTC 24 |
316537289 ps |
| T1429 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_random.3963026024 |
|
|
Aug 21 10:08:05 PM UTC 24 |
Aug 21 10:08:32 PM UTC 24 |
218955925 ps |
| T1430 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_error.1690537983 |
|
|
Aug 21 10:07:13 PM UTC 24 |
Aug 21 10:08:36 PM UTC 24 |
2426359609 ps |
| T1431 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device.1220156588 |
|
|
Aug 21 10:07:51 PM UTC 24 |
Aug 21 10:08:36 PM UTC 24 |
571527259 ps |
| T1432 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all.1998350732 |
|
|
Aug 21 10:05:25 PM UTC 24 |
Aug 21 10:08:40 PM UTC 24 |
2459426230 ps |
| T1433 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_unmapped_addr.3158996107 |
|
|
Aug 21 10:08:04 PM UTC 24 |
Aug 21 10:08:42 PM UTC 24 |
303294046 ps |
| T1434 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke.2259496631 |
|
|
Aug 21 10:08:34 PM UTC 24 |
Aug 21 10:08:43 PM UTC 24 |
53636617 ps |
| T1435 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_zero_delays.291742378 |
|
|
Aug 21 10:08:35 PM UTC 24 |
Aug 21 10:08:44 PM UTC 24 |
42302015 ps |
| T381 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_same_csr_outstanding.3701920611 |
|
|
Aug 21 09:39:03 PM UTC 24 |
Aug 21 10:08:44 PM UTC 24 |
16408596862 ps |
| T1436 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_slow_rsp.2346525439 |
|
|
Aug 21 09:58:37 PM UTC 24 |
Aug 21 10:08:52 PM UTC 24 |
40250423239 ps |
| T1437 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_slow_rsp.388174080 |
|
|
Aug 21 10:07:49 PM UTC 24 |
Aug 21 10:08:54 PM UTC 24 |
3850595947 ps |
| T1438 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_same_source.3932532523 |
|
|
Aug 21 10:08:05 PM UTC 24 |
Aug 21 10:08:56 PM UTC 24 |
527673646 ps |
| T452 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all.3787466185 |
|
|
Aug 21 10:03:27 PM UTC 24 |
Aug 21 10:08:56 PM UTC 24 |
8611957601 ps |
| T1439 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random.560571926 |
|
|
Aug 21 10:07:40 PM UTC 24 |
Aug 21 10:08:57 PM UTC 24 |
1995031281 ps |
| T743 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device.105109671 |
|
|
Aug 21 10:10:05 PM UTC 24 |
Aug 21 10:11:09 PM UTC 24 |
891410932 ps |
| T1440 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.1171105863 |
|
|
Aug 21 10:08:25 PM UTC 24 |
Aug 21 10:09:00 PM UTC 24 |
93992192 ps |
| T583 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_error.1464521365 |
|
|
Aug 21 10:02:27 PM UTC 24 |
Aug 21 10:09:02 PM UTC 24 |
5831692408 ps |
| T1441 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_error.3770778281 |
|
|
Aug 21 10:04:47 PM UTC 24 |
Aug 21 10:09:04 PM UTC 24 |
3203395853 ps |
| T1442 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all.3728671453 |
|
|
Aug 21 10:04:41 PM UTC 24 |
Aug 21 10:09:09 PM UTC 24 |
2970591118 ps |
| T1443 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.1293093451 |
|
|
Aug 21 10:09:21 PM UTC 24 |
Aug 21 10:09:27 PM UTC 24 |
6974600 ps |
| T1444 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke.2518582262 |
|
|
Aug 21 10:09:25 PM UTC 24 |
Aug 21 10:09:36 PM UTC 24 |
50632271 ps |
| T1445 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_large_delays.99606474 |
|
|
Aug 21 10:07:37 PM UTC 24 |
Aug 21 10:09:37 PM UTC 24 |
9909163174 ps |
| T1446 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_unmapped_addr.698716187 |
|
|
Aug 21 10:09:15 PM UTC 24 |
Aug 21 10:09:37 PM UTC 24 |
286506157 ps |
| T720 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.304180631 |
|
|
Aug 21 09:47:55 PM UTC 24 |
Aug 21 10:09:39 PM UTC 24 |
80748864602 ps |
| T1447 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.1052412811 |
|
|
Aug 21 10:07:36 PM UTC 24 |
Aug 21 10:09:39 PM UTC 24 |
6524183707 ps |
| T1448 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.3777856197 |
|
|
Aug 21 10:09:13 PM UTC 24 |
Aug 21 10:09:40 PM UTC 24 |
473667581 ps |
| T1449 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_zero_delays.3344915640 |
|
|
Aug 21 10:09:31 PM UTC 24 |
Aug 21 10:09:41 PM UTC 24 |
46761150 ps |
| T1450 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all.1059840408 |
|
|
Aug 21 10:09:18 PM UTC 24 |
Aug 21 10:09:42 PM UTC 24 |
340726527 ps |
| T1451 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random.451832620 |
|
|
Aug 21 10:08:57 PM UTC 24 |
Aug 21 10:09:43 PM UTC 24 |
553786559 ps |
| T1452 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_same_source.3539654822 |
|
|
Aug 21 10:09:06 PM UTC 24 |
Aug 21 10:09:51 PM UTC 24 |
572471208 ps |
| T1453 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.3282723609 |
|
|
Aug 21 10:09:05 PM UTC 24 |
Aug 21 10:09:53 PM UTC 24 |
2808208751 ps |
| T1454 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_zero_delays.2454720753 |
|
|
Aug 21 10:09:01 PM UTC 24 |
Aug 21 10:09:57 PM UTC 24 |
611413260 ps |
| T1455 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_slow_rsp.870379061 |
|
|
Aug 21 10:09:04 PM UTC 24 |
Aug 21 10:10:03 PM UTC 24 |
3278685678 ps |
| T1456 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_random.550025097 |
|
|
Aug 21 10:09:16 PM UTC 24 |
Aug 21 10:10:08 PM UTC 24 |
519433567 ps |
| T1457 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_slow_rsp.2256004516 |
|
|
Aug 21 10:04:10 PM UTC 24 |
Aug 21 10:10:14 PM UTC 24 |
27939359151 ps |
| T1458 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_slow_rsp.3023610470 |
|
|
Aug 21 10:06:33 PM UTC 24 |
Aug 21 10:10:18 PM UTC 24 |
17372074672 ps |
| T403 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.514406623 |
|
|
Aug 21 09:11:17 PM UTC 24 |
Aug 21 10:10:22 PM UTC 24 |
28713576748 ps |
| T1459 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_zero_delays.357752932 |
|
|
Aug 21 10:10:01 PM UTC 24 |
Aug 21 10:10:27 PM UTC 24 |
176313378 ps |
| T1460 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_random.546464020 |
|
|
Aug 21 10:10:08 PM UTC 24 |
Aug 21 10:10:28 PM UTC 24 |
491725994 ps |
| T1461 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.3333466592 |
|
|
Aug 21 10:06:34 PM UTC 24 |
Aug 21 10:10:29 PM UTC 24 |
15366803514 ps |
| T1462 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_large_delays.3861570500 |
|
|
Aug 21 10:08:55 PM UTC 24 |
Aug 21 10:10:30 PM UTC 24 |
9221460846 ps |
| T1463 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.650242387 |
|
|
Aug 21 10:00:30 PM UTC 24 |
Aug 21 10:10:32 PM UTC 24 |
41693225951 ps |
| T1464 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_large_delays.165560293 |
|
|
Aug 21 10:01:54 PM UTC 24 |
Aug 21 10:10:33 PM UTC 24 |
49746051045 ps |
| T1465 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_same_source.2907609623 |
|
|
Aug 21 10:10:06 PM UTC 24 |
Aug 21 10:10:42 PM UTC 24 |
496692563 ps |
| T1466 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_unmapped_addr.1774423151 |
|
|
Aug 21 10:10:15 PM UTC 24 |
Aug 21 10:10:45 PM UTC 24 |
242523998 ps |
| T1467 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.3228500343 |
|
|
Aug 21 10:08:56 PM UTC 24 |
Aug 21 10:10:50 PM UTC 24 |
5948650367 ps |
| T1468 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke.1744953146 |
|
|
Aug 21 10:10:38 PM UTC 24 |
Aug 21 10:10:52 PM UTC 24 |
206346976 ps |
| T1469 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_zero_delays.4065213553 |
|
|
Aug 21 10:10:43 PM UTC 24 |
Aug 21 10:10:53 PM UTC 24 |
51036743 ps |
| T1470 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_large_delays.288879635 |
|
|
Aug 21 10:09:50 PM UTC 24 |
Aug 21 10:11:02 PM UTC 24 |
6298001382 ps |
| T1471 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.2904631134 |
|
|
Aug 21 10:10:17 PM UTC 24 |
Aug 21 10:11:02 PM UTC 24 |
1106029827 ps |
| T1472 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random.994521408 |
|
|
Aug 21 10:10:02 PM UTC 24 |
Aug 21 10:11:12 PM UTC 24 |
2156122704 ps |
| T1473 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_zero_delays.259100152 |
|
|
Aug 21 10:10:54 PM UTC 24 |
Aug 21 10:11:14 PM UTC 24 |
162529966 ps |
| T1474 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.3916078133 |
|
|
Aug 21 10:10:36 PM UTC 24 |
Aug 21 10:11:21 PM UTC 24 |
29811179 ps |
| T1475 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_same_source.1486658111 |
|
|
Aug 21 10:11:12 PM UTC 24 |
Aug 21 10:11:22 PM UTC 24 |
49052470 ps |
| T1476 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.2964203669 |
|
|
Aug 21 10:11:25 PM UTC 24 |
Aug 21 10:11:34 PM UTC 24 |
56516780 ps |
| T793 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.1434882707 |
|
|
Aug 21 10:05:37 PM UTC 24 |
Aug 21 10:11:41 PM UTC 24 |
4266369795 ps |
| T1477 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_unmapped_addr.208792453 |
|
|
Aug 21 10:11:16 PM UTC 24 |
Aug 21 10:11:45 PM UTC 24 |
154702699 ps |
| T1478 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.3882386305 |
|
|
Aug 21 10:10:00 PM UTC 24 |
Aug 21 10:11:46 PM UTC 24 |
5678451485 ps |
| T1479 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device.1954765789 |
|
|
Aug 21 10:09:08 PM UTC 24 |
Aug 21 10:11:47 PM UTC 24 |
3379110161 ps |
| T1480 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.1096148304 |
|
|
Aug 21 10:07:07 PM UTC 24 |
Aug 21 10:11:54 PM UTC 24 |
523100816 ps |
| T1481 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke.4045806960 |
|
|
Aug 21 10:11:44 PM UTC 24 |
Aug 21 10:11:54 PM UTC 24 |
40435876 ps |
| T1482 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_random.3109684396 |
|
|
Aug 21 10:11:14 PM UTC 24 |
Aug 21 10:11:55 PM UTC 24 |
378750724 ps |
| T1483 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_zero_delays.3245201257 |
|
|
Aug 21 10:11:46 PM UTC 24 |
Aug 21 10:11:56 PM UTC 24 |
51097846 ps |
| T1484 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_slow_rsp.2876542920 |
|
|
Aug 21 10:01:57 PM UTC 24 |
Aug 21 10:12:01 PM UTC 24 |
39141958865 ps |
| T741 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.1086977510 |
|
|
Aug 21 09:45:08 PM UTC 24 |
Aug 21 10:12:02 PM UTC 24 |
91282668455 ps |
| T1485 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_error.2025412609 |
|
|
Aug 21 10:08:31 PM UTC 24 |
Aug 21 10:12:04 PM UTC 24 |
2910311685 ps |
| T1486 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_slow_rsp.2565382600 |
|
|
Aug 21 10:05:22 PM UTC 24 |
Aug 21 10:12:05 PM UTC 24 |
27845167092 ps |
| T1487 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_large_delays.4095613645 |
|
|
Aug 21 10:10:51 PM UTC 24 |
Aug 21 10:12:06 PM UTC 24 |
6742755165 ps |
| T744 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device.2267831352 |
|
|
Aug 21 10:11:05 PM UTC 24 |
Aug 21 10:12:15 PM UTC 24 |
1088267188 ps |
| T1488 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.3631981652 |
|
|
Aug 21 10:08:33 PM UTC 24 |
Aug 21 10:12:15 PM UTC 24 |
2920807080 ps |
| T1489 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.244072495 |
|
|
Aug 21 10:10:50 PM UTC 24 |
Aug 21 10:12:16 PM UTC 24 |
5928381663 ps |
| T1490 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random.4143856881 |
|
|
Aug 21 10:10:49 PM UTC 24 |
Aug 21 10:12:22 PM UTC 24 |
1935726666 ps |
| T1491 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_same_csr_outstanding.2752166988 |
|
|
Aug 21 09:43:37 PM UTC 24 |
Aug 21 10:12:23 PM UTC 24 |
13745952874 ps |
| T1492 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_slow_rsp.3372899976 |
|
|
Aug 21 10:10:52 PM UTC 24 |
Aug 21 10:12:24 PM UTC 24 |
5407779019 ps |
| T1493 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all.1788979863 |
|
|
Aug 21 10:08:15 PM UTC 24 |
Aug 21 10:12:30 PM UTC 24 |
6637889571 ps |
| T1494 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_unmapped_addr.2115500676 |
|
|
Aug 21 10:12:22 PM UTC 24 |
Aug 21 10:12:39 PM UTC 24 |
118695566 ps |
| T476 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_large_delays.3544939081 |
|
|
Aug 21 10:04:06 PM UTC 24 |
Aug 21 10:12:40 PM UTC 24 |
56499703602 ps |
| T1495 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_random.90002762 |
|
|
Aug 21 10:12:25 PM UTC 24 |
Aug 21 10:12:43 PM UTC 24 |
125065389 ps |
| T1496 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.1965643077 |
|
|
Aug 21 10:03:36 PM UTC 24 |
Aug 21 10:12:43 PM UTC 24 |
6407050797 ps |
| T1497 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_slow_rsp.2059839530 |
|
|
Aug 21 09:56:40 PM UTC 24 |
Aug 21 10:12:46 PM UTC 24 |
63096076571 ps |
| T1498 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.3970782002 |
|
|
Aug 21 10:12:26 PM UTC 24 |
Aug 21 10:12:51 PM UTC 24 |
163832486 ps |
| T1499 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke.3879126602 |
|
|
Aug 21 10:12:39 PM UTC 24 |
Aug 21 10:12:53 PM UTC 24 |
232359230 ps |
| T1500 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_error.3290390038 |
|
|
Aug 21 10:05:59 PM UTC 24 |
Aug 21 10:12:53 PM UTC 24 |
13755612435 ps |
| T1501 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_error.3343995967 |
|
|
Aug 21 10:09:20 PM UTC 24 |
Aug 21 10:12:54 PM UTC 24 |
2659261424 ps |
| T1502 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random.802078493 |
|
|
Aug 21 10:12:08 PM UTC 24 |
Aug 21 10:12:54 PM UTC 24 |
914092857 ps |
| T1503 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_zero_delays.3282606537 |
|
|
Aug 21 10:12:45 PM UTC 24 |
Aug 21 10:12:56 PM UTC 24 |
55400032 ps |
| T1504 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all.1408253584 |
|
|
Aug 21 10:12:29 PM UTC 24 |
Aug 21 10:12:57 PM UTC 24 |
297359080 ps |
| T1505 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_zero_delays.3861227101 |
|
|
Aug 21 10:12:11 PM UTC 24 |
Aug 21 10:12:58 PM UTC 24 |
486396173 ps |
| T1506 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_same_source.398899575 |
|
|
Aug 21 10:12:19 PM UTC 24 |
Aug 21 10:12:59 PM UTC 24 |
395464793 ps |
| T1507 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.2603260426 |
|
|
Aug 21 10:07:14 PM UTC 24 |
Aug 21 10:13:09 PM UTC 24 |
3353556772 ps |
| T808 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.2643362633 |
|
|
Aug 21 10:04:48 PM UTC 24 |
Aug 21 10:13:12 PM UTC 24 |
11086506904 ps |
| T1508 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke.3545100211 |
|
|
Aug 21 10:13:22 PM UTC 24 |
Aug 21 10:13:33 PM UTC 24 |
51853452 ps |
| T1509 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.chip_tl_errors.3516275504 |
|
|
Aug 21 10:07:14 PM UTC 24 |
Aug 21 10:13:37 PM UTC 24 |
4296015816 ps |
| T1510 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_large_delays.1106152274 |
|
|
Aug 21 10:11:57 PM UTC 24 |
Aug 21 10:13:37 PM UTC 24 |
8963176191 ps |
| T1511 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.4042072018 |
|
|
Aug 21 10:12:05 PM UTC 24 |
Aug 21 10:13:41 PM UTC 24 |
5508020171 ps |
| T1512 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_zero_delays.3141726473 |
|
|
Aug 21 10:13:34 PM UTC 24 |
Aug 21 10:13:42 PM UTC 24 |
41231432 ps |
| T1513 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_unmapped_addr.1974505121 |
|
|
Aug 21 10:13:16 PM UTC 24 |
Aug 21 10:13:43 PM UTC 24 |
141713619 ps |
| T1514 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_large_delays.2924671336 |
|
|
Aug 21 10:09:01 PM UTC 24 |
Aug 21 10:13:44 PM UTC 24 |
28400597893 ps |
| T1515 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.3323039720 |
|
|
Aug 21 10:13:18 PM UTC 24 |
Aug 21 10:13:44 PM UTC 24 |
240138147 ps |
| T1516 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_zero_delays.2501876910 |
|
|
Aug 21 10:13:01 PM UTC 24 |
Aug 21 10:13:52 PM UTC 24 |
444101861 ps |
| T1517 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random.332001562 |
|
|
Aug 21 10:12:51 PM UTC 24 |
Aug 21 10:13:52 PM UTC 24 |
1443487342 ps |
| T1518 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all.1878764031 |
|
|
Aug 21 10:10:21 PM UTC 24 |
Aug 21 10:13:54 PM UTC 24 |
5834668458 ps |
| T460 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all.566037933 |
|
|
Aug 21 10:06:48 PM UTC 24 |
Aug 21 10:13:57 PM UTC 24 |
11509979492 ps |
| T1519 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_same_source.3336036299 |
|
|
Aug 21 10:13:15 PM UTC 24 |
Aug 21 10:14:05 PM UTC 24 |
483011147 ps |
| T1520 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_random.378973464 |
|
|
Aug 21 10:13:13 PM UTC 24 |
Aug 21 10:14:05 PM UTC 24 |
1502087322 ps |
| T1521 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_large_delays.3482671887 |
|
|
Aug 21 10:12:44 PM UTC 24 |
Aug 21 10:14:05 PM UTC 24 |
7642936472 ps |
| T1522 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random.3536642878 |
|
|
Aug 21 10:13:59 PM UTC 24 |
Aug 21 10:14:14 PM UTC 24 |
115550172 ps |
| T1523 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_error.4053849584 |
|
|
Aug 21 10:10:30 PM UTC 24 |
Aug 21 10:14:19 PM UTC 24 |
3115269602 ps |
| T745 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device.586884274 |
|
|
Aug 21 10:12:16 PM UTC 24 |
Aug 21 10:14:19 PM UTC 24 |
3124880529 ps |
| T1524 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_same_source.2542964547 |
|
|
Aug 21 10:14:07 PM UTC 24 |
Aug 21 10:14:22 PM UTC 24 |
107669809 ps |
| T1525 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_slow_rsp.1640576071 |
|
|
Aug 21 10:12:18 PM UTC 24 |
Aug 21 10:14:26 PM UTC 24 |
6075269409 ps |
| T1526 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.4188212402 |
|
|
Aug 21 10:14:14 PM UTC 24 |
Aug 21 10:14:28 PM UTC 24 |
109656154 ps |
| T491 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device.163625048 |
|
|
Aug 21 10:13:09 PM UTC 24 |
Aug 21 10:14:30 PM UTC 24 |
1498873232 ps |
| T1527 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.2058045584 |
|
|
Aug 21 10:12:45 PM UTC 24 |
Aug 21 10:14:36 PM UTC 24 |
5771339213 ps |
| T1528 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.311545056 |
|
|
Aug 21 10:02:02 PM UTC 24 |
Aug 21 10:14:42 PM UTC 24 |
48042358140 ps |
| T1529 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_unmapped_addr.1039534299 |
|
|
Aug 21 10:14:14 PM UTC 24 |
Aug 21 10:14:47 PM UTC 24 |
827218836 ps |
| T1530 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke.2932234814 |
|
|
Aug 21 10:14:37 PM UTC 24 |
Aug 21 10:14:50 PM UTC 24 |
233443873 ps |
| T1531 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_random.527039909 |
|
|
Aug 21 10:14:15 PM UTC 24 |
Aug 21 10:14:51 PM UTC 24 |
1033062488 ps |
| T788 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.1406868038 |
|
|
Aug 21 10:12:37 PM UTC 24 |
Aug 21 10:14:51 PM UTC 24 |
710662782 ps |
| T1532 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_zero_delays.2916765982 |
|
|
Aug 21 10:14:43 PM UTC 24 |
Aug 21 10:14:55 PM UTC 24 |
58819683 ps |
| T471 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_zero_delays.433762834 |
|
|
Aug 21 10:13:58 PM UTC 24 |
Aug 21 10:14:57 PM UTC 24 |
626293456 ps |
| T1533 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.1011193522 |
|
|
Aug 21 10:13:17 PM UTC 24 |
Aug 21 10:14:58 PM UTC 24 |
228462335 ps |
| T1534 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.1383318361 |
|
|
Aug 21 10:11:32 PM UTC 24 |
Aug 21 10:14:59 PM UTC 24 |
459504724 ps |
| T1535 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.4071403653 |
|
|
Aug 21 10:13:54 PM UTC 24 |
Aug 21 10:15:01 PM UTC 24 |
3871642165 ps |
| T1536 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.3271112198 |
|
|
Aug 21 10:12:29 PM UTC 24 |
Aug 21 10:15:13 PM UTC 24 |
334496153 ps |
| T1537 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_zero_delays.159320963 |
|
|
Aug 21 10:14:52 PM UTC 24 |
Aug 21 10:15:18 PM UTC 24 |
225032196 ps |
| T1538 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_zero_delays.416042689 |
|
|
Aug 21 10:19:46 PM UTC 24 |
Aug 21 10:20:28 PM UTC 24 |
466736116 ps |
| T1539 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_large_delays.30564421 |
|
|
Aug 21 10:13:36 PM UTC 24 |
Aug 21 10:15:18 PM UTC 24 |
9928093149 ps |
| T761 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device.3757991355 |
|
|
Aug 21 10:14:04 PM UTC 24 |
Aug 21 10:15:20 PM UTC 24 |
1555378708 ps |
| T758 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all.3701451516 |
|
|
Aug 21 10:13:17 PM UTC 24 |
Aug 21 10:15:27 PM UTC 24 |
3875578800 ps |
| T1540 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.4294739793 |
|
|
Aug 21 10:15:17 PM UTC 24 |
Aug 21 10:15:31 PM UTC 24 |
72948117 ps |
| T1541 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_same_source.3227856927 |
|
|
Aug 21 10:15:14 PM UTC 24 |
Aug 21 10:15:33 PM UTC 24 |
344030638 ps |
| T1542 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_zero_delays.1964988180 |
|
|
Aug 21 10:15:41 PM UTC 24 |
Aug 21 10:15:50 PM UTC 24 |
37594045 ps |
| T1543 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke.147396887 |
|
|
Aug 21 10:15:38 PM UTC 24 |
Aug 21 10:15:53 PM UTC 24 |
228965179 ps |
| T1544 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_random.1759391422 |
|
|
Aug 21 10:15:14 PM UTC 24 |
Aug 21 10:15:57 PM UTC 24 |
608698880 ps |
| T1545 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random.2465319116 |
|
|
Aug 21 10:14:48 PM UTC 24 |
Aug 21 10:15:58 PM UTC 24 |
1625607845 ps |
| T1546 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.3574455481 |
|
|
Aug 21 10:14:47 PM UTC 24 |
Aug 21 10:15:59 PM UTC 24 |
4991032119 ps |
| T1547 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_error.350083287 |
|
|
Aug 21 10:11:36 PM UTC 24 |
Aug 21 10:16:00 PM UTC 24 |
3211597695 ps |
| T1548 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random.1445797970 |
|
|
Aug 21 10:15:50 PM UTC 24 |
Aug 21 10:16:05 PM UTC 24 |
178544671 ps |
| T1549 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_unmapped_addr.57072396 |
|
|
Aug 21 10:15:14 PM UTC 24 |
Aug 21 10:16:14 PM UTC 24 |
1413053020 ps |
| T1550 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all.1101872381 |
|
|
Aug 21 10:15:19 PM UTC 24 |
Aug 21 10:16:15 PM UTC 24 |
1338367686 ps |
| T1551 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_zero_delays.779177703 |
|
|
Aug 21 10:15:54 PM UTC 24 |
Aug 21 10:16:18 PM UTC 24 |
154312788 ps |
| T1552 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_large_delays.3842502203 |
|
|
Aug 21 10:14:41 PM UTC 24 |
Aug 21 10:16:28 PM UTC 24 |
8623171386 ps |
| T1553 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_error.2405180539 |
|
|
Aug 21 10:12:38 PM UTC 24 |
Aug 21 10:16:38 PM UTC 24 |
2875832920 ps |