| T686 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3553625618 |
|
|
Aug 22 12:49:31 PM UTC 24 |
Aug 22 12:53:39 PM UTC 24 |
3380424900 ps |
| T605 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2732207118 |
|
|
Aug 22 12:49:38 PM UTC 24 |
Aug 22 12:54:06 PM UTC 24 |
3520888922 ps |
| T1096 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/98.chip_sw_all_escalation_resets.3873907542 |
|
|
Aug 22 12:47:23 PM UTC 24 |
Aug 22 12:54:27 PM UTC 24 |
5769620852 ps |
| T615 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3158527534 |
|
|
Aug 22 12:50:53 PM UTC 24 |
Aug 22 12:55:08 PM UTC 24 |
3862016900 ps |
| T623 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/94.chip_sw_all_escalation_resets.1605373756 |
|
|
Aug 22 12:48:37 PM UTC 24 |
Aug 22 12:55:34 PM UTC 24 |
4597422456 ps |
| T704 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_all_escalation_resets.2744470686 |
|
|
Aug 22 12:50:14 PM UTC 24 |
Aug 22 12:55:46 PM UTC 24 |
4435322512 ps |
| T103 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2842877241 |
|
|
Aug 22 12:51:09 PM UTC 24 |
Aug 22 12:55:53 PM UTC 24 |
4192521074 ps |
| T624 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3413393704 |
|
|
Aug 22 12:51:00 PM UTC 24 |
Aug 22 12:56:02 PM UTC 24 |
3895312214 ps |
| T676 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.4000336387 |
|
|
Aug 22 12:53:01 PM UTC 24 |
Aug 22 12:56:37 PM UTC 24 |
3433379160 ps |
| T1097 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_all_escalation_resets.602259930 |
|
|
Aug 22 12:52:20 PM UTC 24 |
Aug 22 12:58:27 PM UTC 24 |
5905302200 ps |
| T259 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/99.chip_sw_all_escalation_resets.1934228077 |
|
|
Aug 22 12:52:41 PM UTC 24 |
Aug 22 12:58:36 PM UTC 24 |
5308367968 ps |
| T658 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/93.chip_sw_all_escalation_resets.960023341 |
|
|
Aug 22 12:51:44 PM UTC 24 |
Aug 22 12:58:38 PM UTC 24 |
5709952500 ps |
| T695 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_all_escalation_resets.519121817 |
|
|
Aug 22 12:52:07 PM UTC 24 |
Aug 22 12:59:04 PM UTC 24 |
5434011130 ps |
| T621 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/90.chip_sw_all_escalation_resets.2359875566 |
|
|
Aug 22 12:52:35 PM UTC 24 |
Aug 22 12:59:59 PM UTC 24 |
5736969412 ps |
| T696 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/96.chip_sw_all_escalation_resets.1169286007 |
|
|
Aug 22 12:53:08 PM UTC 24 |
Aug 22 01:00:06 PM UTC 24 |
5011627888 ps |
| T329 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_all_escalation_resets.2169840622 |
|
|
Aug 22 12:53:37 PM UTC 24 |
Aug 22 01:00:27 PM UTC 24 |
6377320264 ps |
| T567 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.607106330 |
|
|
Aug 22 09:06:32 AM UTC 24 |
Aug 22 01:49:55 PM UTC 24 |
139403918500 ps |
| T85 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.2130416716 |
|
|
Aug 21 09:10:02 PM UTC 24 |
Aug 21 09:10:14 PM UTC 24 |
154849001 ps |
| T86 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.516818834 |
|
|
Aug 21 09:10:06 PM UTC 24 |
Aug 21 09:10:16 PM UTC 24 |
40630043 ps |
| T87 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.1194290155 |
|
|
Aug 21 09:10:23 PM UTC 24 |
Aug 21 09:10:35 PM UTC 24 |
66623833 ps |
| T90 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.2904752570 |
|
|
Aug 21 09:10:38 PM UTC 24 |
Aug 21 09:10:46 PM UTC 24 |
31437971 ps |
| T89 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.2972113652 |
|
|
Aug 21 09:10:15 PM UTC 24 |
Aug 21 09:10:47 PM UTC 24 |
290243551 ps |
| T91 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.367894270 |
|
|
Aug 21 09:10:42 PM UTC 24 |
Aug 21 09:11:08 PM UTC 24 |
832274164 ps |
| T250 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.1386770131 |
|
|
Aug 21 09:10:41 PM UTC 24 |
Aug 21 09:11:24 PM UTC 24 |
865149243 ps |
| T417 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2049723067 |
|
|
Aug 21 09:10:14 PM UTC 24 |
Aug 21 09:11:32 PM UTC 24 |
5312407805 ps |
| T413 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.3514692535 |
|
|
Aug 21 09:10:37 PM UTC 24 |
Aug 21 09:11:34 PM UTC 24 |
2060351025 ps |
| T507 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.2194940895 |
|
|
Aug 21 09:11:29 PM UTC 24 |
Aug 21 09:11:39 PM UTC 24 |
47175833 ps |
| T776 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2073894530 |
|
|
Aug 21 09:10:24 PM UTC 24 |
Aug 21 09:11:40 PM UTC 24 |
4353046386 ps |
| T509 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.814472792 |
|
|
Aug 21 09:11:34 PM UTC 24 |
Aug 21 09:11:42 PM UTC 24 |
43212217 ps |
| T498 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.1476273256 |
|
|
Aug 21 09:10:07 PM UTC 24 |
Aug 21 09:11:44 PM UTC 24 |
6689989324 ps |
| T414 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.867834312 |
|
|
Aug 21 09:10:30 PM UTC 24 |
Aug 21 09:11:47 PM UTC 24 |
946837430 ps |
| T500 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.1731922489 |
|
|
Aug 21 09:11:52 PM UTC 24 |
Aug 21 09:12:07 PM UTC 24 |
104186516 ps |
| T479 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.3896319165 |
|
|
Aug 21 09:11:43 PM UTC 24 |
Aug 21 09:12:08 PM UTC 24 |
204115733 ps |
| T412 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.3127630732 |
|
|
Aug 21 09:11:43 PM UTC 24 |
Aug 21 09:12:10 PM UTC 24 |
300126300 ps |
| T619 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.2453554546 |
|
|
Aug 21 09:11:48 PM UTC 24 |
Aug 21 09:12:10 PM UTC 24 |
319693044 ps |
| T494 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.4173675946 |
|
|
Aug 21 09:11:47 PM UTC 24 |
Aug 21 09:12:13 PM UTC 24 |
878040761 ps |
| T411 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1125855231 |
|
|
Aug 21 09:11:54 PM UTC 24 |
Aug 21 09:12:20 PM UTC 24 |
208648616 ps |
| T467 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.1404875182 |
|
|
Aug 21 09:10:21 PM UTC 24 |
Aug 21 09:12:21 PM UTC 24 |
11180707866 ps |
| T511 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke.2986486515 |
|
|
Aug 21 09:12:19 PM UTC 24 |
Aug 21 09:12:28 PM UTC 24 |
207865895 ps |
| T504 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.351436127 |
|
|
Aug 21 09:11:12 PM UTC 24 |
Aug 21 09:12:33 PM UTC 24 |
387322602 ps |
| T497 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_zero_delays.1191633360 |
|
|
Aug 21 09:12:23 PM UTC 24 |
Aug 21 09:12:33 PM UTC 24 |
58327165 ps |
| T501 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.1836546269 |
|
|
Aug 21 09:11:52 PM UTC 24 |
Aug 21 09:12:49 PM UTC 24 |
1775677954 ps |
| T435 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random.672968094 |
|
|
Aug 21 09:12:29 PM UTC 24 |
Aug 21 09:12:57 PM UTC 24 |
790453311 ps |
| T513 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.4360625 |
|
|
Aug 21 09:11:41 PM UTC 24 |
Aug 21 09:13:03 PM UTC 24 |
4901369724 ps |
| T510 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.2132512026 |
|
|
Aug 21 09:12:40 PM UTC 24 |
Aug 21 09:13:09 PM UTC 24 |
455549779 ps |
| T499 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device.2888506801 |
|
|
Aug 21 09:12:36 PM UTC 24 |
Aug 21 09:13:12 PM UTC 24 |
793794252 ps |
| T432 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_same_source.468436293 |
|
|
Aug 21 09:12:38 PM UTC 24 |
Aug 21 09:13:13 PM UTC 24 |
770079050 ps |
| T398 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_zero_delays.879026468 |
|
|
Aug 21 09:12:32 PM UTC 24 |
Aug 21 09:13:19 PM UTC 24 |
484401825 ps |
| T506 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.1826488322 |
|
|
Aug 21 09:11:37 PM UTC 24 |
Aug 21 09:13:32 PM UTC 24 |
10257220673 ps |
| T503 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_random.1054528804 |
|
|
Aug 21 09:12:43 PM UTC 24 |
Aug 21 09:13:38 PM UTC 24 |
1776938288 ps |
| T424 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_unmapped_addr.3863658366 |
|
|
Aug 21 09:12:41 PM UTC 24 |
Aug 21 09:13:47 PM UTC 24 |
1375324182 ps |
| T495 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.4014801249 |
|
|
Aug 21 09:11:02 PM UTC 24 |
Aug 21 09:13:52 PM UTC 24 |
2772227591 ps |
| T514 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke.338399901 |
|
|
Aug 21 09:13:40 PM UTC 24 |
Aug 21 09:13:53 PM UTC 24 |
174004954 ps |
| T502 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.610648086 |
|
|
Aug 21 09:11:57 PM UTC 24 |
Aug 21 09:13:54 PM UTC 24 |
2666049840 ps |
| T399 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.792417779 |
|
|
Aug 21 09:10:58 PM UTC 24 |
Aug 21 09:13:57 PM UTC 24 |
2113313119 ps |
| T777 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.3822351870 |
|
|
Aug 21 09:12:27 PM UTC 24 |
Aug 21 09:14:05 PM UTC 24 |
6704675545 ps |
| T512 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_zero_delays.158712253 |
|
|
Aug 21 09:13:57 PM UTC 24 |
Aug 21 09:14:06 PM UTC 24 |
52495159 ps |
| T508 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.108664396 |
|
|
Aug 21 09:13:02 PM UTC 24 |
Aug 21 09:14:08 PM UTC 24 |
505975608 ps |
| T580 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_large_delays.3623167428 |
|
|
Aug 21 09:12:23 PM UTC 24 |
Aug 21 09:14:09 PM UTC 24 |
8880479538 ps |
| T96 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.3328376781 |
|
|
Aug 21 09:11:11 PM UTC 24 |
Aug 21 09:14:18 PM UTC 24 |
4540497228 ps |
| T505 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.2119815980 |
|
|
Aug 21 09:11:10 PM UTC 24 |
Aug 21 09:14:33 PM UTC 24 |
2560185666 ps |
| T427 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_zero_delays.670581270 |
|
|
Aug 21 09:14:17 PM UTC 24 |
Aug 21 09:14:38 PM UTC 24 |
157636741 ps |
| T379 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.1314615565 |
|
|
Aug 21 09:11:17 PM UTC 24 |
Aug 21 09:14:57 PM UTC 24 |
3805825984 ps |
| T752 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device.2267393589 |
|
|
Aug 21 09:14:28 PM UTC 24 |
Aug 21 09:14:58 PM UTC 24 |
490861095 ps |
| T1098 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_random.2003313507 |
|
|
Aug 21 09:14:34 PM UTC 24 |
Aug 21 09:15:02 PM UTC 24 |
227691776 ps |
| T465 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random.3802046477 |
|
|
Aug 21 09:14:17 PM UTC 24 |
Aug 21 09:15:03 PM UTC 24 |
1236938172 ps |
| T519 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.556022313 |
|
|
Aug 21 09:09:56 PM UTC 24 |
Aug 21 09:15:05 PM UTC 24 |
3453358100 ps |
| T564 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_unmapped_addr.2382834779 |
|
|
Aug 21 09:14:41 PM UTC 24 |
Aug 21 09:15:09 PM UTC 24 |
393305294 ps |
| T1099 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.1193241978 |
|
|
Aug 21 09:14:57 PM UTC 24 |
Aug 21 09:15:19 PM UTC 24 |
348613196 ps |
| T400 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.3118383550 |
|
|
Aug 21 09:11:57 PM UTC 24 |
Aug 21 09:15:24 PM UTC 24 |
2547052022 ps |
| T768 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.3954173256 |
|
|
Aug 21 09:14:12 PM UTC 24 |
Aug 21 09:15:38 PM UTC 24 |
3834351764 ps |
| T1100 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_large_delays.1099705767 |
|
|
Aug 21 09:14:00 PM UTC 24 |
Aug 21 09:15:43 PM UTC 24 |
8472608539 ps |
| T496 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_same_source.4217871466 |
|
|
Aug 21 09:14:33 PM UTC 24 |
Aug 21 09:15:57 PM UTC 24 |
2163413783 ps |
| T1101 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.227296180 |
|
|
Aug 21 09:09:57 PM UTC 24 |
Aug 21 09:15:58 PM UTC 24 |
11522545861 ps |
| T153 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.680670679 |
|
|
Aug 21 09:13:14 PM UTC 24 |
Aug 21 09:16:06 PM UTC 24 |
3606834684 ps |
| T428 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.3402776846 |
|
|
Aug 21 09:12:53 PM UTC 24 |
Aug 21 09:16:06 PM UTC 24 |
1891679823 ps |
| T569 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.3084815215 |
|
|
Aug 21 09:11:57 PM UTC 24 |
Aug 21 09:16:08 PM UTC 24 |
2333107928 ps |
| T1102 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke.1560472894 |
|
|
Aug 21 09:16:06 PM UTC 24 |
Aug 21 09:16:17 PM UTC 24 |
125902637 ps |
| T1103 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_zero_delays.3203608780 |
|
|
Aug 21 09:16:21 PM UTC 24 |
Aug 21 09:16:32 PM UTC 24 |
44133779 ps |
| T1104 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random.2302363877 |
|
|
Aug 21 09:16:29 PM UTC 24 |
Aug 21 09:16:46 PM UTC 24 |
269216530 ps |
| T540 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.2606261425 |
|
|
Aug 21 09:11:44 PM UTC 24 |
Aug 21 09:16:56 PM UTC 24 |
18761629855 ps |
| T1105 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_prim_tl_access.1518919224 |
|
|
Aug 21 09:12:15 PM UTC 24 |
Aug 21 09:16:58 PM UTC 24 |
8317542620 ps |
| T159 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.3660571131 |
|
|
Aug 21 09:12:01 PM UTC 24 |
Aug 21 09:16:59 PM UTC 24 |
4464673492 ps |
| T549 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_zero_delays.3728729541 |
|
|
Aug 21 09:16:32 PM UTC 24 |
Aug 21 09:17:01 PM UTC 24 |
219915315 ps |
| T371 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.1407535712 |
|
|
Aug 21 09:11:13 PM UTC 24 |
Aug 21 09:17:02 PM UTC 24 |
3794170770 ps |
| T1106 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_bit_bash.4140541419 |
|
|
Aug 21 09:12:10 PM UTC 24 |
Aug 21 09:17:03 PM UTC 24 |
4573879522 ps |
| T716 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_error.1122489347 |
|
|
Aug 21 09:15:19 PM UTC 24 |
Aug 21 09:17:07 PM UTC 24 |
2455443781 ps |
| T774 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device.67234591 |
|
|
Aug 21 09:17:10 PM UTC 24 |
Aug 21 09:17:27 PM UTC 24 |
273046249 ps |
| T455 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all.1191943916 |
|
|
Aug 21 09:12:53 PM UTC 24 |
Aug 21 09:17:29 PM UTC 24 |
2950850452 ps |
| T1107 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.2939533030 |
|
|
Aug 21 09:11:17 PM UTC 24 |
Aug 21 09:17:33 PM UTC 24 |
9432898000 ps |
| T520 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_tl_errors.331336878 |
|
|
Aug 21 09:13:38 PM UTC 24 |
Aug 21 09:17:39 PM UTC 24 |
4059486605 ps |
| T547 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_large_delays.114600110 |
|
|
Aug 21 09:16:23 PM UTC 24 |
Aug 21 09:17:40 PM UTC 24 |
6401444444 ps |
| T527 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.3576318983 |
|
|
Aug 21 09:16:28 PM UTC 24 |
Aug 21 09:17:47 PM UTC 24 |
5038833059 ps |
| T601 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_error.1490560610 |
|
|
Aug 21 09:12:57 PM UTC 24 |
Aug 21 09:17:56 PM UTC 24 |
9189172885 ps |
| T546 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_same_source.2032968119 |
|
|
Aug 21 09:17:23 PM UTC 24 |
Aug 21 09:18:12 PM UTC 24 |
1124413279 ps |
| T383 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.302272507 |
|
|
Aug 21 09:12:07 PM UTC 24 |
Aug 21 09:18:16 PM UTC 24 |
5817579560 ps |
| T1108 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.681853556 |
|
|
Aug 21 09:17:25 PM UTC 24 |
Aug 21 09:18:19 PM UTC 24 |
984696139 ps |
| T530 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_unmapped_addr.3522803454 |
|
|
Aug 21 09:17:24 PM UTC 24 |
Aug 21 09:18:23 PM UTC 24 |
1032048823 ps |
| T419 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all.712300694 |
|
|
Aug 21 09:15:03 PM UTC 24 |
Aug 21 09:18:33 PM UTC 24 |
2543061618 ps |
| T429 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all.239628750 |
|
|
Aug 21 09:17:28 PM UTC 24 |
Aug 21 09:18:41 PM UTC 24 |
603602886 ps |
| T561 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke.395616461 |
|
|
Aug 21 09:18:36 PM UTC 24 |
Aug 21 09:18:48 PM UTC 24 |
46236412 ps |
| T532 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_zero_delays.1607301466 |
|
|
Aug 21 09:18:41 PM UTC 24 |
Aug 21 09:18:52 PM UTC 24 |
47669878 ps |
| T748 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_random.1484285344 |
|
|
Aug 21 09:17:23 PM UTC 24 |
Aug 21 09:19:06 PM UTC 24 |
2379763434 ps |
| T1109 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_zero_delays.3721575508 |
|
|
Aug 21 09:19:06 PM UTC 24 |
Aug 21 09:19:15 PM UTC 24 |
35763968 ps |
| T541 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_slow_rsp.450981158 |
|
|
Aug 21 09:16:56 PM UTC 24 |
Aug 21 09:19:18 PM UTC 24 |
10683246645 ps |
| T450 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3373286340 |
|
|
Aug 21 09:11:54 PM UTC 24 |
Aug 21 09:19:30 PM UTC 24 |
5417117494 ps |
| T523 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.868675544 |
|
|
Aug 21 09:11:44 PM UTC 24 |
Aug 21 09:19:42 PM UTC 24 |
38793691042 ps |
| T773 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device.3027574044 |
|
|
Aug 21 09:19:15 PM UTC 24 |
Aug 21 09:19:47 PM UTC 24 |
553712782 ps |
| T1110 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_same_source.1763164443 |
|
|
Aug 21 09:19:41 PM UTC 24 |
Aug 21 09:19:57 PM UTC 24 |
107437154 ps |
| T492 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random.3352788363 |
|
|
Aug 21 09:18:58 PM UTC 24 |
Aug 21 09:20:15 PM UTC 24 |
1690149114 ps |
| T154 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_hw_reset.1434159003 |
|
|
Aug 21 09:15:27 PM UTC 24 |
Aug 21 09:20:18 PM UTC 24 |
4256843785 ps |
| T1111 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_random.361679336 |
|
|
Aug 21 09:19:43 PM UTC 24 |
Aug 21 09:20:26 PM UTC 24 |
513185062 ps |
| T539 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_unmapped_addr.2427186647 |
|
|
Aug 21 09:19:55 PM UTC 24 |
Aug 21 09:20:31 PM UTC 24 |
220153945 ps |
| T1112 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.2276145021 |
|
|
Aug 21 09:18:47 PM UTC 24 |
Aug 21 09:20:32 PM UTC 24 |
5921294917 ps |
| T451 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_large_delays.2844578758 |
|
|
Aug 21 09:18:44 PM UTC 24 |
Aug 21 09:20:35 PM UTC 24 |
9743540886 ps |
| T374 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.3694214509 |
|
|
Aug 21 09:12:03 PM UTC 24 |
Aug 21 09:20:37 PM UTC 24 |
5935316932 ps |
| T515 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_tl_errors.2567329497 |
|
|
Aug 21 09:12:13 PM UTC 24 |
Aug 21 09:20:40 PM UTC 24 |
5799774375 ps |
| T1113 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.2233364227 |
|
|
Aug 21 09:09:59 PM UTC 24 |
Aug 21 09:20:50 PM UTC 24 |
14662218823 ps |
| T437 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.89886304 |
|
|
Aug 21 09:14:31 PM UTC 24 |
Aug 21 09:21:05 PM UTC 24 |
23700101034 ps |
| T1114 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.3284834821 |
|
|
Aug 21 09:20:07 PM UTC 24 |
Aug 21 09:21:07 PM UTC 24 |
1099575298 ps |
| T1115 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_zero_delays.2898989280 |
|
|
Aug 21 09:21:04 PM UTC 24 |
Aug 21 09:21:11 PM UTC 24 |
44647683 ps |
| T560 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.3700297477 |
|
|
Aug 21 09:10:23 PM UTC 24 |
Aug 21 09:21:12 PM UTC 24 |
48083100320 ps |
| T1116 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke.1859312312 |
|
|
Aug 21 09:21:02 PM UTC 24 |
Aug 21 09:21:15 PM UTC 24 |
212674418 ps |
| T764 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.1824156724 |
|
|
Aug 21 09:20:42 PM UTC 24 |
Aug 21 09:21:58 PM UTC 24 |
121595923 ps |
| T375 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.462911525 |
|
|
Aug 21 09:15:33 PM UTC 24 |
Aug 21 09:21:59 PM UTC 24 |
5543426288 ps |
| T1117 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random.604338675 |
|
|
Aug 21 09:21:32 PM UTC 24 |
Aug 21 09:22:03 PM UTC 24 |
668248421 ps |
| T516 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_tl_errors.1456955136 |
|
|
Aug 21 09:16:04 PM UTC 24 |
Aug 21 09:22:03 PM UTC 24 |
4312846409 ps |
| T518 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_tl_errors.3075525330 |
|
|
Aug 21 09:18:21 PM UTC 24 |
Aug 21 09:22:04 PM UTC 24 |
3215230796 ps |
| T1118 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_tl_errors.3623129768 |
|
|
Aug 21 09:20:59 PM UTC 24 |
Aug 21 09:22:24 PM UTC 24 |
2896068427 ps |
| T711 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.3529591818 |
|
|
Aug 21 09:15:27 PM UTC 24 |
Aug 21 09:22:33 PM UTC 24 |
5538725551 ps |
| T462 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_zero_delays.3439289370 |
|
|
Aug 21 09:21:35 PM UTC 24 |
Aug 21 09:22:43 PM UTC 24 |
631991800 ps |
| T1119 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_same_source.3144415898 |
|
|
Aug 21 09:22:28 PM UTC 24 |
Aug 21 09:22:45 PM UTC 24 |
110280839 ps |
| T1120 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_error.2339055940 |
|
|
Aug 21 09:20:41 PM UTC 24 |
Aug 21 09:22:48 PM UTC 24 |
2032079916 ps |
| T1121 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_unmapped_addr.4001729292 |
|
|
Aug 21 09:22:28 PM UTC 24 |
Aug 21 09:23:07 PM UTC 24 |
539833214 ps |
| T384 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_bit_bash.1297719808 |
|
|
Aug 21 09:15:43 PM UTC 24 |
Aug 21 09:23:12 PM UTC 24 |
5231235155 ps |
| T570 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_error.2638659578 |
|
|
Aug 21 09:17:48 PM UTC 24 |
Aug 21 09:23:13 PM UTC 24 |
9262238464 ps |
| T1122 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_random.3707905953 |
|
|
Aug 21 09:22:28 PM UTC 24 |
Aug 21 09:23:17 PM UTC 24 |
1150255996 ps |
| T155 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_hw_reset.4127808709 |
|
|
Aug 21 09:17:57 PM UTC 24 |
Aug 21 09:23:17 PM UTC 24 |
6677145180 ps |
| T719 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.3146664232 |
|
|
Aug 21 09:17:53 PM UTC 24 |
Aug 21 09:23:19 PM UTC 24 |
3885488364 ps |
| T778 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.1479536808 |
|
|
Aug 21 09:21:29 PM UTC 24 |
Aug 21 09:23:21 PM UTC 24 |
5802842649 ps |
| T390 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.150060984 |
|
|
Aug 21 09:18:01 PM UTC 24 |
Aug 21 09:23:29 PM UTC 24 |
6941399959 ps |
| T493 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_large_delays.1639740899 |
|
|
Aug 21 09:14:19 PM UTC 24 |
Aug 21 09:23:30 PM UTC 24 |
48279363968 ps |
| T771 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.140744327 |
|
|
Aug 21 09:20:22 PM UTC 24 |
Aug 21 09:23:37 PM UTC 24 |
585173900 ps |
| T391 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.2312401759 |
|
|
Aug 21 09:11:14 PM UTC 24 |
Aug 21 09:23:42 PM UTC 24 |
11371431180 ps |
| T810 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.2631396865 |
|
|
Aug 21 09:23:07 PM UTC 24 |
Aug 21 09:23:43 PM UTC 24 |
106523243 ps |
| T1123 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke.3749307709 |
|
|
Aug 21 09:23:39 PM UTC 24 |
Aug 21 09:23:50 PM UTC 24 |
54975522 ps |
| T738 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device.3150235184 |
|
|
Aug 21 09:22:22 PM UTC 24 |
Aug 21 09:23:51 PM UTC 24 |
1984476133 ps |
| T739 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.3936793848 |
|
|
Aug 21 09:22:47 PM UTC 24 |
Aug 21 09:23:55 PM UTC 24 |
1258819784 ps |
| T1124 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_zero_delays.1036801635 |
|
|
Aug 21 09:23:45 PM UTC 24 |
Aug 21 09:23:57 PM UTC 24 |
61105575 ps |
| T392 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_rw.3965363047 |
|
|
Aug 21 09:13:22 PM UTC 24 |
Aug 21 09:24:17 PM UTC 24 |
5978079292 ps |
| T488 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.1592162544 |
|
|
Aug 21 09:15:22 PM UTC 24 |
Aug 21 09:24:18 PM UTC 24 |
6521108439 ps |
| T1125 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_large_delays.1310157295 |
|
|
Aug 21 09:21:15 PM UTC 24 |
Aug 21 09:24:18 PM UTC 24 |
9808101544 ps |
| T572 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_error.3092259119 |
|
|
Aug 21 09:23:09 PM UTC 24 |
Aug 21 09:24:22 PM UTC 24 |
1021333551 ps |
| T559 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_zero_delays.1923730180 |
|
|
Aug 21 09:24:01 PM UTC 24 |
Aug 21 09:24:25 PM UTC 24 |
236340162 ps |
| T216 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.1686632564 |
|
|
Aug 21 09:09:49 PM UTC 24 |
Aug 21 09:24:25 PM UTC 24 |
7932828724 ps |
| T1126 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1172516435 |
|
|
Aug 21 09:11:26 PM UTC 24 |
Aug 21 09:24:40 PM UTC 24 |
16731598826 ps |
| T1127 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.1120576396 |
|
|
Aug 21 09:24:41 PM UTC 24 |
Aug 21 09:24:50 PM UTC 24 |
168228106 ps |
| T436 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random.3587356243 |
|
|
Aug 21 09:23:55 PM UTC 24 |
Aug 21 09:24:55 PM UTC 24 |
649146696 ps |
| T573 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_random.613831367 |
|
|
Aug 21 09:24:19 PM UTC 24 |
Aug 21 09:25:00 PM UTC 24 |
1212900797 ps |
| T551 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_large_delays.4043580439 |
|
|
Aug 21 09:19:12 PM UTC 24 |
Aug 21 09:25:04 PM UTC 24 |
35200996215 ps |
| T1128 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.3194730046 |
|
|
Aug 21 09:12:13 PM UTC 24 |
Aug 21 09:25:07 PM UTC 24 |
14451262651 ps |
| T1129 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_large_delays.279607829 |
|
|
Aug 21 09:23:46 PM UTC 24 |
Aug 21 09:25:08 PM UTC 24 |
7479659511 ps |
| T445 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all.982000013 |
|
|
Aug 21 09:20:11 PM UTC 24 |
Aug 21 09:25:10 PM UTC 24 |
8143260658 ps |
| T712 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device.3153026514 |
|
|
Aug 21 09:24:14 PM UTC 24 |
Aug 21 09:25:15 PM UTC 24 |
1342159081 ps |
| T393 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_rw.3787338007 |
|
|
Aug 21 09:15:26 PM UTC 24 |
Aug 21 09:25:17 PM UTC 24 |
5723544444 ps |
| T422 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_unmapped_addr.1880672125 |
|
|
Aug 21 09:24:38 PM UTC 24 |
Aug 21 09:25:20 PM UTC 24 |
1023746020 ps |
| T377 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_bit_bash.526008329 |
|
|
Aug 21 09:13:27 PM UTC 24 |
Aug 21 09:25:27 PM UTC 24 |
7328724931 ps |
| T1130 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.725028220 |
|
|
Aug 21 09:23:54 PM UTC 24 |
Aug 21 09:25:29 PM UTC 24 |
5185260895 ps |
| T1131 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke.627801068 |
|
|
Aug 21 09:25:22 PM UTC 24 |
Aug 21 09:25:35 PM UTC 24 |
211382056 ps |
| T1132 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_zero_delays.3290505026 |
|
|
Aug 21 09:25:29 PM UTC 24 |
Aug 21 09:25:38 PM UTC 24 |
45157770 ps |
| T477 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all.2578047200 |
|
|
Aug 21 09:22:57 PM UTC 24 |
Aug 21 09:25:41 PM UTC 24 |
4345367427 ps |
| T430 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_same_source.1858819545 |
|
|
Aug 21 09:24:17 PM UTC 24 |
Aug 21 09:25:52 PM UTC 24 |
2556038802 ps |
| T1133 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_error.3492035158 |
|
|
Aug 21 09:24:44 PM UTC 24 |
Aug 21 09:25:59 PM UTC 24 |
1668661789 ps |
| T753 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.3421359594 |
|
|
Aug 21 09:23:12 PM UTC 24 |
Aug 21 09:26:02 PM UTC 24 |
4000411618 ps |
| T463 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.1823927904 |
|
|
Aug 21 09:17:32 PM UTC 24 |
Aug 21 09:26:15 PM UTC 24 |
3817117527 ps |
| T760 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_random.1861583091 |
|
|
Aug 21 09:26:03 PM UTC 24 |
Aug 21 09:26:25 PM UTC 24 |
569034729 ps |
| T533 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random.862491043 |
|
|
Aug 21 09:25:32 PM UTC 24 |
Aug 21 09:26:25 PM UTC 24 |
531086916 ps |
| T433 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_same_source.1846192299 |
|
|
Aug 21 09:26:00 PM UTC 24 |
Aug 21 09:26:45 PM UTC 24 |
1695080864 ps |
| T767 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.1291127580 |
|
|
Aug 21 09:24:12 PM UTC 24 |
Aug 21 09:26:47 PM UTC 24 |
8882851046 ps |
| T457 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_zero_delays.3712265712 |
|
|
Aug 21 09:25:38 PM UTC 24 |
Aug 21 09:26:53 PM UTC 24 |
608261087 ps |
| T394 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_rw.2798870509 |
|
|
Aug 21 09:18:00 PM UTC 24 |
Aug 21 09:26:54 PM UTC 24 |
6629870410 ps |
| T1134 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_large_delays.3788500844 |
|
|
Aug 21 09:25:31 PM UTC 24 |
Aug 21 09:26:59 PM UTC 24 |
6579178088 ps |
| T524 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_unmapped_addr.978515435 |
|
|
Aug 21 09:26:05 PM UTC 24 |
Aug 21 09:27:02 PM UTC 24 |
1139531759 ps |
| T794 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.851683215 |
|
|
Aug 21 09:26:40 PM UTC 24 |
Aug 21 09:27:03 PM UTC 24 |
160103580 ps |
| T1135 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.1248646881 |
|
|
Aug 21 09:26:06 PM UTC 24 |
Aug 21 09:27:04 PM UTC 24 |
1216773858 ps |
| T1136 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.2288489173 |
|
|
Aug 21 09:25:32 PM UTC 24 |
Aug 21 09:27:08 PM UTC 24 |
5303556845 ps |
| T548 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all.2236163274 |
|
|
Aug 21 09:26:15 PM UTC 24 |
Aug 21 09:27:15 PM UTC 24 |
1673116051 ps |
| T717 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.247759319 |
|
|
Aug 21 09:24:47 PM UTC 24 |
Aug 21 09:27:19 PM UTC 24 |
380798070 ps |
| T1137 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_zero_delays.984412134 |
|
|
Aug 21 09:27:14 PM UTC 24 |
Aug 21 09:27:24 PM UTC 24 |
45632559 ps |
| T1138 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke.3933643484 |
|
|
Aug 21 09:27:15 PM UTC 24 |
Aug 21 09:27:25 PM UTC 24 |
49866142 ps |
| T418 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.2552892247 |
|
|
Aug 21 09:20:56 PM UTC 24 |
Aug 21 09:27:30 PM UTC 24 |
6697689889 ps |
| T1139 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random.1915197120 |
|
|
Aug 21 09:27:27 PM UTC 24 |
Aug 21 09:27:37 PM UTC 24 |
73625507 ps |
| T517 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_tl_errors.280763621 |
|
|
Aug 21 09:25:19 PM UTC 24 |
Aug 21 09:27:46 PM UTC 24 |
3426934137 ps |
| T531 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_zero_delays.1174741075 |
|
|
Aug 21 09:27:26 PM UTC 24 |
Aug 21 09:28:16 PM UTC 24 |
505204167 ps |
| T534 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_large_delays.72872309 |
|
|
Aug 21 09:12:29 PM UTC 24 |
Aug 21 09:28:18 PM UTC 24 |
91578937150 ps |
| T425 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_slow_rsp.4074965195 |
|
|
Aug 21 09:12:30 PM UTC 24 |
Aug 21 09:28:21 PM UTC 24 |
56407137056 ps |
| T1140 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.2882764854 |
|
|
Aug 21 09:28:11 PM UTC 24 |
Aug 21 09:28:30 PM UTC 24 |
121164923 ps |
| T385 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.2047396795 |
|
|
Aug 21 09:13:26 PM UTC 24 |
Aug 21 09:28:37 PM UTC 24 |
11838040008 ps |
| T1141 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.3621672546 |
|
|
Aug 21 09:27:26 PM UTC 24 |
Aug 21 09:28:39 PM UTC 24 |
5084101944 ps |
| T598 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device.3150070740 |
|
|
Aug 21 09:25:52 PM UTC 24 |
Aug 21 09:28:40 PM UTC 24 |
3430446842 ps |
| T1142 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_large_delays.94587468 |
|
|
Aug 21 09:27:20 PM UTC 24 |
Aug 21 09:28:42 PM UTC 24 |
6917794405 ps |
| T1143 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_unmapped_addr.793913037 |
|
|
Aug 21 09:28:01 PM UTC 24 |
Aug 21 09:28:50 PM UTC 24 |
807225553 ps |
| T1144 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_random.760479732 |
|
|
Aug 21 09:27:54 PM UTC 24 |
Aug 21 09:28:58 PM UTC 24 |
594519773 ps |
| T438 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all.2990877712 |
|
|
Aug 21 09:24:43 PM UTC 24 |
Aug 21 09:28:58 PM UTC 24 |
6707303718 ps |
| T1145 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_same_source.3081274769 |
|
|
Aug 21 09:27:48 PM UTC 24 |
Aug 21 09:29:00 PM UTC 24 |
1811708955 ps |
| T543 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_large_delays.271888529 |
|
|
Aug 21 09:27:32 PM UTC 24 |
Aug 21 09:29:29 PM UTC 24 |
9612610277 ps |
| T770 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.75398117 |
|
|
Aug 21 09:29:15 PM UTC 24 |
Aug 21 09:29:30 PM UTC 24 |
222693536 ps |
| T1146 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1939967953 |
|
|
Aug 21 09:29:21 PM UTC 24 |
Aug 21 09:29:31 PM UTC 24 |
47098394 ps |
| T525 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_tl_errors.1006048436 |
|
|
Aug 21 09:27:11 PM UTC 24 |
Aug 21 09:29:31 PM UTC 24 |
3270594893 ps |
| T1147 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all.1991860674 |
|
|
Aug 21 09:28:41 PM UTC 24 |
Aug 21 09:29:34 PM UTC 24 |
1408883681 ps |
| T537 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2140133638 |
|
|
Aug 21 09:11:47 PM UTC 24 |
Aug 21 09:30:02 PM UTC 24 |
78147494889 ps |
| T562 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_large_delays.3485539085 |
|
|
Aug 21 09:16:42 PM UTC 24 |
Aug 21 09:30:05 PM UTC 24 |
80431110502 ps |
| T713 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device.3773136946 |
|
|
Aug 21 09:27:44 PM UTC 24 |
Aug 21 09:30:06 PM UTC 24 |
3043187450 ps |
| T1148 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.4203780465 |
|
|
Aug 21 09:29:58 PM UTC 24 |
Aug 21 09:30:11 PM UTC 24 |
83940121 ps |
| T420 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.3403368754 |
|
|
Aug 21 09:26:24 PM UTC 24 |
Aug 21 09:30:13 PM UTC 24 |
1945935671 ps |
| T1149 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.2438844909 |
|
|
Aug 21 09:29:53 PM UTC 24 |
Aug 21 09:30:17 PM UTC 24 |
419197642 ps |
| T544 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_slow_rsp.2766553807 |
|
|
Aug 21 09:14:23 PM UTC 24 |
Aug 21 09:30:32 PM UTC 24 |
66374869292 ps |
| T750 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_error.3623374567 |
|
|
Aug 21 09:26:26 PM UTC 24 |
Aug 21 09:30:32 PM UTC 24 |
3138783744 ps |
| T1150 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_slow_rsp.2630162961 |
|
|
Aug 21 09:24:09 PM UTC 24 |
Aug 21 09:30:32 PM UTC 24 |
26136946700 ps |
| T470 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.1708601975 |
|
|
Aug 21 09:29:56 PM UTC 24 |
Aug 21 09:30:44 PM UTC 24 |
367376122 ps |
| T1151 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.238414410 |
|
|
Aug 21 09:30:36 PM UTC 24 |
Aug 21 09:30:52 PM UTC 24 |
203459011 ps |
| T734 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_error.2414431152 |
|
|
Aug 21 09:28:46 PM UTC 24 |
Aug 21 09:30:55 PM UTC 24 |
4159007549 ps |
| T1152 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2409819008 |
|
|
Aug 21 09:29:24 PM UTC 24 |
Aug 21 09:30:58 PM UTC 24 |
3366614224 ps |
| T1153 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.167136004 |
|
|
Aug 21 09:29:22 PM UTC 24 |
Aug 21 09:31:24 PM UTC 24 |
9276542751 ps |
| T542 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.4054363393 |
|
|
Aug 21 09:30:41 PM UTC 24 |
Aug 21 09:31:26 PM UTC 24 |
393112830 ps |
| T1154 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.456300215 |
|
|
Aug 21 09:30:37 PM UTC 24 |
Aug 21 09:31:26 PM UTC 24 |
1106516088 ps |
| T175 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_rw.3054275574 |
|
|
Aug 21 09:23:32 PM UTC 24 |
Aug 21 09:31:28 PM UTC 24 |
5264622684 ps |
| T1155 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_rw.1211832731 |
|
|
Aug 21 09:20:50 PM UTC 24 |
Aug 21 09:31:33 PM UTC 24 |
6647624580 ps |
| T1156 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.1416257244 |
|
|
Aug 21 09:30:29 PM UTC 24 |
Aug 21 09:31:36 PM UTC 24 |
1893553315 ps |
| T478 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.3474504600 |
|
|
Aug 21 09:24:47 PM UTC 24 |
Aug 21 09:31:45 PM UTC 24 |
5936337716 ps |
| T1157 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke.3894730871 |
|
|
Aug 21 09:31:46 PM UTC 24 |
Aug 21 09:31:57 PM UTC 24 |
52343749 ps |
| T1158 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.4245407076 |
|
|
Aug 21 09:30:31 PM UTC 24 |
Aug 21 09:31:57 PM UTC 24 |
2351513683 ps |
| T1159 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.1590185168 |
|
|
Aug 21 09:30:54 PM UTC 24 |
Aug 21 09:31:57 PM UTC 24 |
681731682 ps |
| T1160 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_zero_delays.4194483590 |
|
|
Aug 21 09:31:49 PM UTC 24 |
Aug 21 09:32:00 PM UTC 24 |
51932075 ps |
| T521 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_tl_errors.2388465847 |
|
|
Aug 21 09:23:42 PM UTC 24 |
Aug 21 09:32:07 PM UTC 24 |
5309274176 ps |
| T1161 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_zero_delays.101911767 |
|
|
Aug 21 09:32:00 PM UTC 24 |
Aug 21 09:32:14 PM UTC 24 |
78667092 ps |
| T1162 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random.177919739 |
|
|
Aug 21 09:31:55 PM UTC 24 |
Aug 21 09:32:19 PM UTC 24 |
175817838 ps |
| T779 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.1584766370 |
|
|
Aug 21 09:32:21 PM UTC 24 |
Aug 21 09:32:33 PM UTC 24 |
100206575 ps |
| T528 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.3071884594 |
|
|
Aug 21 09:29:06 PM UTC 24 |
Aug 21 09:32:34 PM UTC 24 |
3117675308 ps |
| T434 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_slow_rsp.225813420 |
|
|
Aug 21 09:19:17 PM UTC 24 |
Aug 21 09:32:46 PM UTC 24 |
52197476757 ps |
| T791 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.4043568751 |
|
|
Aug 21 09:28:41 PM UTC 24 |
Aug 21 09:32:53 PM UTC 24 |
622104508 ps |
| T1163 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2882258941 |
|
|
Aug 21 09:32:41 PM UTC 24 |
Aug 21 09:33:24 PM UTC 24 |
1091733019 ps |
| T1164 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.4113760785 |
|
|
Aug 21 09:31:48 PM UTC 24 |
Aug 21 09:33:25 PM UTC 24 |
5140677709 ps |
| T1165 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_slow_rsp.364349137 |
|
|
Aug 21 09:27:38 PM UTC 24 |
Aug 21 09:33:26 PM UTC 24 |
22574211665 ps |
| T1166 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_same_source.1376878750 |
|
|
Aug 21 09:32:22 PM UTC 24 |
Aug 21 09:33:31 PM UTC 24 |
1725484752 ps |
| T1167 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_slow_rsp.3793999520 |
|
|
Aug 21 09:32:20 PM UTC 24 |
Aug 21 09:33:40 PM UTC 24 |
5424947811 ps |
| T1168 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_random.1201924808 |
|
|
Aug 21 09:32:31 PM UTC 24 |
Aug 21 09:33:42 PM UTC 24 |
1716903919 ps |
| T1169 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_unmapped_addr.1390077746 |
|
|
Aug 21 09:32:40 PM UTC 24 |
Aug 21 09:33:43 PM UTC 24 |
1153970358 ps |
| T1170 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.3719173715 |
|
|
Aug 21 09:33:16 PM UTC 24 |
Aug 21 09:33:49 PM UTC 24 |
34185007 ps |
| T1171 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_large_delays.1653504801 |
|
|
Aug 21 09:31:50 PM UTC 24 |
Aug 21 09:33:57 PM UTC 24 |
8178298705 ps |