| T2264 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_large_delays.2523436717 |
|
|
Aug 21 11:05:59 PM UTC 24 |
Aug 21 11:07:35 PM UTC 24 |
8046813672 ps |
| T2265 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.973078753 |
|
|
Aug 21 11:07:08 PM UTC 24 |
Aug 21 11:07:45 PM UTC 24 |
102797564 ps |
| T2266 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_zero_delays.1318922025 |
|
|
Aug 21 11:07:32 PM UTC 24 |
Aug 21 11:08:01 PM UTC 24 |
256699664 ps |
| T2267 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.3645257290 |
|
|
Aug 21 10:43:22 PM UTC 24 |
Aug 21 11:08:05 PM UTC 24 |
94985336074 ps |
| T2268 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_unmapped_addr.3724933752 |
|
|
Aug 21 11:07:47 PM UTC 24 |
Aug 21 11:08:21 PM UTC 24 |
201326869 ps |
| T2269 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.741579627 |
|
|
Aug 21 11:07:57 PM UTC 24 |
Aug 21 11:08:36 PM UTC 24 |
1130576457 ps |
| T2270 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.3652933421 |
|
|
Aug 21 10:54:01 PM UTC 24 |
Aug 21 11:08:44 PM UTC 24 |
59144796745 ps |
| T2271 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.3203845301 |
|
|
Aug 21 11:06:49 PM UTC 24 |
Aug 21 11:08:58 PM UTC 24 |
201974701 ps |
| T2272 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.4211812552 |
|
|
Aug 21 11:08:10 PM UTC 24 |
Aug 21 11:08:59 PM UTC 24 |
111182691 ps |
| T2273 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke.346558679 |
|
|
Aug 21 11:08:45 PM UTC 24 |
Aug 21 11:09:00 PM UTC 24 |
249999520 ps |
| T2274 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.655656744 |
|
|
Aug 21 11:07:22 PM UTC 24 |
Aug 21 11:09:01 PM UTC 24 |
5175726462 ps |
| T2275 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_same_source.1690337644 |
|
|
Aug 21 11:07:39 PM UTC 24 |
Aug 21 11:09:03 PM UTC 24 |
2394213211 ps |
| T2276 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_zero_delays.864972015 |
|
|
Aug 21 11:09:02 PM UTC 24 |
Aug 21 11:09:11 PM UTC 24 |
47127615 ps |
| T2277 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random.4111580679 |
|
|
Aug 21 11:07:28 PM UTC 24 |
Aug 21 11:09:16 PM UTC 24 |
2519349817 ps |
| T2278 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_random.428373160 |
|
|
Aug 21 11:07:47 PM UTC 24 |
Aug 21 11:09:18 PM UTC 24 |
2701177557 ps |
| T2279 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.4135031680 |
|
|
Aug 21 11:08:30 PM UTC 24 |
Aug 21 11:09:28 PM UTC 24 |
309301383 ps |
| T2280 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_large_delays.516542079 |
|
|
Aug 21 11:00:56 PM UTC 24 |
Aug 21 11:09:28 PM UTC 24 |
49349028949 ps |
| T2281 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.2236526091 |
|
|
Aug 21 11:05:51 PM UTC 24 |
Aug 21 11:09:28 PM UTC 24 |
547945509 ps |
| T2282 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all.1627280660 |
|
|
Aug 21 11:06:48 PM UTC 24 |
Aug 21 11:09:35 PM UTC 24 |
4962795632 ps |
| T2283 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device.3880507857 |
|
|
Aug 21 11:07:38 PM UTC 24 |
Aug 21 11:09:38 PM UTC 24 |
2738636588 ps |
| T2284 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random.4203182975 |
|
|
Aug 21 11:09:25 PM UTC 24 |
Aug 21 11:09:41 PM UTC 24 |
86889745 ps |
| T2285 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_large_delays.2605279360 |
|
|
Aug 21 10:51:11 PM UTC 24 |
Aug 21 11:09:46 PM UTC 24 |
106731781069 ps |
| T2286 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.3778560147 |
|
|
Aug 21 10:56:40 PM UTC 24 |
Aug 21 11:09:48 PM UTC 24 |
13942283568 ps |
| T2287 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all.941816120 |
|
|
Aug 21 11:07:57 PM UTC 24 |
Aug 21 11:09:56 PM UTC 24 |
4456650392 ps |
| T2288 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device.1255599363 |
|
|
Aug 21 11:09:36 PM UTC 24 |
Aug 21 11:09:58 PM UTC 24 |
584310493 ps |
| T2289 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_unmapped_addr.2599065253 |
|
|
Aug 21 11:09:50 PM UTC 24 |
Aug 21 11:10:03 PM UTC 24 |
133762397 ps |
| T2290 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_large_delays.1828132625 |
|
|
Aug 21 11:07:18 PM UTC 24 |
Aug 21 11:10:06 PM UTC 24 |
10487900081 ps |
| T2291 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_random.184265790 |
|
|
Aug 21 11:09:52 PM UTC 24 |
Aug 21 11:10:20 PM UTC 24 |
939765798 ps |
| T2292 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke.1052317952 |
|
|
Aug 21 11:10:09 PM UTC 24 |
Aug 21 11:10:21 PM UTC 24 |
197984327 ps |
| T2293 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_zero_delays.3301301781 |
|
|
Aug 21 11:09:22 PM UTC 24 |
Aug 21 11:10:22 PM UTC 24 |
515069477 ps |
| T2294 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.4103749574 |
|
|
Aug 21 11:09:51 PM UTC 24 |
Aug 21 11:10:22 PM UTC 24 |
806671026 ps |
| T2295 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.729239180 |
|
|
Aug 21 10:44:41 PM UTC 24 |
Aug 21 11:10:23 PM UTC 24 |
102328474489 ps |
| T2296 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_zero_delays.1214942249 |
|
|
Aug 21 11:10:20 PM UTC 24 |
Aug 21 11:10:27 PM UTC 24 |
48835341 ps |
| T2297 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_error.671135274 |
|
|
Aug 21 11:10:04 PM UTC 24 |
Aug 21 11:10:29 PM UTC 24 |
253708045 ps |
| T2298 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_slow_rsp.3517638889 |
|
|
Aug 21 11:00:56 PM UTC 24 |
Aug 21 11:10:30 PM UTC 24 |
38977239889 ps |
| T2299 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all.2212542756 |
|
|
Aug 21 11:04:15 PM UTC 24 |
Aug 21 11:10:33 PM UTC 24 |
10005141309 ps |
| T2300 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.3828526845 |
|
|
Aug 21 11:09:22 PM UTC 24 |
Aug 21 11:10:33 PM UTC 24 |
5286727111 ps |
| T2301 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.1387418161 |
|
|
Aug 21 11:05:45 PM UTC 24 |
Aug 21 11:10:35 PM UTC 24 |
504054880 ps |
| T2302 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_large_delays.3501200040 |
|
|
Aug 21 11:09:09 PM UTC 24 |
Aug 21 11:10:40 PM UTC 24 |
9404653886 ps |
| T2303 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_large_delays.3039365848 |
|
|
Aug 21 10:58:13 PM UTC 24 |
Aug 21 11:10:40 PM UTC 24 |
83013557224 ps |
| T2304 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_same_source.3444905412 |
|
|
Aug 21 11:09:40 PM UTC 24 |
Aug 21 11:10:44 PM UTC 24 |
2396068998 ps |
| T2305 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_large_delays.1232580455 |
|
|
Aug 21 10:57:09 PM UTC 24 |
Aug 21 11:10:51 PM UTC 24 |
77342739149 ps |
| T2306 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_error.1932147585 |
|
|
Aug 21 11:05:47 PM UTC 24 |
Aug 21 11:10:52 PM UTC 24 |
9500727032 ps |
| T2307 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.2245418983 |
|
|
Aug 21 11:05:18 PM UTC 24 |
Aug 21 11:10:58 PM UTC 24 |
24098568476 ps |
| T2308 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_slow_rsp.2597477570 |
|
|
Aug 21 10:56:20 PM UTC 24 |
Aug 21 11:11:02 PM UTC 24 |
54376804244 ps |
| T2309 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_slow_rsp.4147882347 |
|
|
Aug 21 10:53:53 PM UTC 24 |
Aug 21 11:11:04 PM UTC 24 |
64904022543 ps |
| T2310 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.3966233966 |
|
|
Aug 21 11:03:24 PM UTC 24 |
Aug 21 11:11:06 PM UTC 24 |
2905203233 ps |
| T2311 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke.3683616430 |
|
|
Aug 21 11:11:05 PM UTC 24 |
Aug 21 11:11:16 PM UTC 24 |
176800493 ps |
| T2312 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_same_source.915850043 |
|
|
Aug 21 11:10:51 PM UTC 24 |
Aug 21 11:11:16 PM UTC 24 |
686231030 ps |
| T2313 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_zero_delays.1662626355 |
|
|
Aug 21 11:11:14 PM UTC 24 |
Aug 21 11:11:23 PM UTC 24 |
51696360 ps |
| T2314 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.617300561 |
|
|
Aug 21 11:10:57 PM UTC 24 |
Aug 21 11:11:23 PM UTC 24 |
156181385 ps |
| T2315 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_error.1632826056 |
|
|
Aug 21 11:11:03 PM UTC 24 |
Aug 21 11:11:23 PM UTC 24 |
648631042 ps |
| T2316 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_error.996859573 |
|
|
Aug 21 11:08:25 PM UTC 24 |
Aug 21 11:11:23 PM UTC 24 |
2724907345 ps |
| T2317 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_large_delays.4140096114 |
|
|
Aug 21 11:10:21 PM UTC 24 |
Aug 21 11:11:25 PM UTC 24 |
6973295237 ps |
| T796 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.954047500 |
|
|
Aug 21 11:03:18 PM UTC 24 |
Aug 21 11:11:29 PM UTC 24 |
7064332410 ps |
| T2318 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.2449378556 |
|
|
Aug 21 10:51:23 PM UTC 24 |
Aug 21 11:11:37 PM UTC 24 |
89553566287 ps |
| T2319 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.392676277 |
|
|
Aug 21 11:04:21 PM UTC 24 |
Aug 21 11:11:39 PM UTC 24 |
8457829519 ps |
| T2320 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_random.4119673498 |
|
|
Aug 21 11:10:52 PM UTC 24 |
Aug 21 11:11:40 PM UTC 24 |
1297760401 ps |
| T2321 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_zero_delays.2588126290 |
|
|
Aug 21 11:11:25 PM UTC 24 |
Aug 21 11:11:41 PM UTC 24 |
106957939 ps |
| T2322 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_unmapped_addr.2826088237 |
|
|
Aug 21 11:10:52 PM UTC 24 |
Aug 21 11:11:42 PM UTC 24 |
1015319522 ps |
| T2323 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.4008015346 |
|
|
Aug 21 11:10:24 PM UTC 24 |
Aug 21 11:11:43 PM UTC 24 |
5725220617 ps |
| T2324 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_zero_delays.1709634903 |
|
|
Aug 21 11:10:45 PM UTC 24 |
Aug 21 11:11:46 PM UTC 24 |
652466556 ps |
| T2325 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.3090830552 |
|
|
Aug 21 10:56:21 PM UTC 24 |
Aug 21 11:11:51 PM UTC 24 |
48117461004 ps |
| T2326 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random.270901232 |
|
|
Aug 21 11:10:31 PM UTC 24 |
Aug 21 11:11:55 PM UTC 24 |
2570417396 ps |
| T2327 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random.1705019600 |
|
|
Aug 21 11:11:23 PM UTC 24 |
Aug 21 11:11:57 PM UTC 24 |
260578248 ps |
| T2328 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.2407886230 |
|
|
Aug 21 11:11:47 PM UTC 24 |
Aug 21 11:12:07 PM UTC 24 |
287201473 ps |
| T2329 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke.3540190242 |
|
|
Aug 21 11:11:59 PM UTC 24 |
Aug 21 11:12:10 PM UTC 24 |
157412614 ps |
| T2330 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_unmapped_addr.3575151476 |
|
|
Aug 21 11:11:46 PM UTC 24 |
Aug 21 11:12:11 PM UTC 24 |
139490475 ps |
| T2331 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_zero_delays.16355641 |
|
|
Aug 21 11:12:03 PM UTC 24 |
Aug 21 11:12:13 PM UTC 24 |
43545516 ps |
| T2332 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.3177286067 |
|
|
Aug 21 11:04:24 PM UTC 24 |
Aug 21 11:12:14 PM UTC 24 |
7937257611 ps |
| T2333 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.3787067048 |
|
|
Aug 21 11:10:08 PM UTC 24 |
Aug 21 11:12:22 PM UTC 24 |
527137422 ps |
| T2334 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random.3519300669 |
|
|
Aug 21 11:12:06 PM UTC 24 |
Aug 21 11:12:25 PM UTC 24 |
311202457 ps |
| T2335 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_slow_rsp.1107254999 |
|
|
Aug 21 11:03:57 PM UTC 24 |
Aug 21 11:12:25 PM UTC 24 |
34974276298 ps |
| T2336 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_large_delays.1249576381 |
|
|
Aug 21 11:11:12 PM UTC 24 |
Aug 21 11:12:25 PM UTC 24 |
8154884507 ps |
| T2337 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_same_source.1850065002 |
|
|
Aug 21 11:11:44 PM UTC 24 |
Aug 21 11:12:29 PM UTC 24 |
491347176 ps |
| T2338 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_zero_delays.4285909727 |
|
|
Aug 21 11:12:16 PM UTC 24 |
Aug 21 11:12:34 PM UTC 24 |
177812282 ps |
| T2339 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device.2542727115 |
|
|
Aug 21 11:10:45 PM UTC 24 |
Aug 21 11:12:44 PM UTC 24 |
3151299690 ps |
| T2340 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all.1348154398 |
|
|
Aug 21 11:09:57 PM UTC 24 |
Aug 21 11:12:55 PM UTC 24 |
2011377065 ps |
| T2341 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_random.4120862259 |
|
|
Aug 21 11:12:38 PM UTC 24 |
Aug 21 11:12:59 PM UTC 24 |
478252599 ps |
| T2342 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.2790439926 |
|
|
Aug 21 11:11:59 PM UTC 24 |
Aug 21 11:12:59 PM UTC 24 |
118719387 ps |
| T2343 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.502082121 |
|
|
Aug 21 11:12:50 PM UTC 24 |
Aug 21 11:13:02 PM UTC 24 |
56711786 ps |
| T2344 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_same_source.1271127845 |
|
|
Aug 21 11:12:36 PM UTC 24 |
Aug 21 11:13:05 PM UTC 24 |
361556008 ps |
| T2345 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.2450700778 |
|
|
Aug 21 11:11:18 PM UTC 24 |
Aug 21 11:13:12 PM UTC 24 |
5432894535 ps |
| T2346 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke.3923926243 |
|
|
Aug 21 11:13:08 PM UTC 24 |
Aug 21 11:13:16 PM UTC 24 |
189047735 ps |
| T2347 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all.1104600006 |
|
|
Aug 21 11:11:49 PM UTC 24 |
Aug 21 11:13:27 PM UTC 24 |
2015111212 ps |
| T2348 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_random.2354276638 |
|
|
Aug 21 11:11:45 PM UTC 24 |
Aug 21 11:13:27 PM UTC 24 |
2502676031 ps |
| T2349 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_zero_delays.225115821 |
|
|
Aug 21 11:13:19 PM UTC 24 |
Aug 21 11:13:28 PM UTC 24 |
49799974 ps |
| T2350 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.2223465223 |
|
|
Aug 21 11:12:49 PM UTC 24 |
Aug 21 11:13:31 PM UTC 24 |
77049143 ps |
| T2351 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_error.3007524307 |
|
|
Aug 21 11:12:02 PM UTC 24 |
Aug 21 11:13:45 PM UTC 24 |
1602264760 ps |
| T2352 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_unmapped_addr.913248880 |
|
|
Aug 21 11:12:46 PM UTC 24 |
Aug 21 11:13:47 PM UTC 24 |
1076059741 ps |
| T2353 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random.3892656331 |
|
|
Aug 21 11:13:26 PM UTC 24 |
Aug 21 11:13:50 PM UTC 24 |
174525081 ps |
| T2354 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_large_delays.570009498 |
|
|
Aug 21 11:12:03 PM UTC 24 |
Aug 21 11:13:50 PM UTC 24 |
7136182390 ps |
| T2355 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device.3567545788 |
|
|
Aug 21 11:11:38 PM UTC 24 |
Aug 21 11:13:50 PM UTC 24 |
3304626104 ps |
| T2356 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.730279211 |
|
|
Aug 21 11:12:08 PM UTC 24 |
Aug 21 11:13:53 PM UTC 24 |
5806128049 ps |
| T2357 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_slow_rsp.2268246990 |
|
|
Aug 21 11:02:35 PM UTC 24 |
Aug 21 11:14:12 PM UTC 24 |
46579868905 ps |
| T2358 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_error.221702795 |
|
|
Aug 21 11:07:05 PM UTC 24 |
Aug 21 11:14:16 PM UTC 24 |
11397853694 ps |
| T2359 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_zero_delays.198781666 |
|
|
Aug 21 11:13:29 PM UTC 24 |
Aug 21 11:14:21 PM UTC 24 |
524393844 ps |
| T2360 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_random.2717712721 |
|
|
Aug 21 11:13:56 PM UTC 24 |
Aug 21 11:14:27 PM UTC 24 |
356191258 ps |
| T2361 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.3492852770 |
|
|
Aug 21 10:45:56 PM UTC 24 |
Aug 21 11:14:32 PM UTC 24 |
114549399148 ps |
| T2362 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_slow_rsp.1088825143 |
|
|
Aug 21 10:59:36 PM UTC 24 |
Aug 21 11:14:34 PM UTC 24 |
60902417576 ps |
| T2363 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_same_source.396633443 |
|
|
Aug 21 11:13:53 PM UTC 24 |
Aug 21 11:14:36 PM UTC 24 |
1085470663 ps |
| T2364 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device.2461443403 |
|
|
Aug 21 11:13:52 PM UTC 24 |
Aug 21 11:14:36 PM UTC 24 |
797079984 ps |
| T2365 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_unmapped_addr.3148653795 |
|
|
Aug 21 11:14:10 PM UTC 24 |
Aug 21 11:14:44 PM UTC 24 |
202055359 ps |
| T2366 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke.587457708 |
|
|
Aug 21 11:14:36 PM UTC 24 |
Aug 21 11:14:47 PM UTC 24 |
45245903 ps |
| T2367 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.3873338040 |
|
|
Aug 21 11:13:24 PM UTC 24 |
Aug 21 11:14:47 PM UTC 24 |
4932126336 ps |
| T2368 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_zero_delays.3138676890 |
|
|
Aug 21 11:14:41 PM UTC 24 |
Aug 21 11:14:51 PM UTC 24 |
48103315 ps |
| T2369 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device.3883836411 |
|
|
Aug 21 11:12:31 PM UTC 24 |
Aug 21 11:14:52 PM UTC 24 |
3619400294 ps |
| T2370 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.2564410225 |
|
|
Aug 21 11:14:13 PM UTC 24 |
Aug 21 11:14:56 PM UTC 24 |
763680097 ps |
| T2371 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all.1800082291 |
|
|
Aug 21 11:12:49 PM UTC 24 |
Aug 21 11:15:05 PM UTC 24 |
1902511748 ps |
| T2372 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_error.3427425956 |
|
|
Aug 21 11:12:54 PM UTC 24 |
Aug 21 11:15:06 PM UTC 24 |
1964141752 ps |
| T2373 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_large_delays.4242814819 |
|
|
Aug 21 11:10:44 PM UTC 24 |
Aug 21 11:15:15 PM UTC 24 |
25867704089 ps |
| T2374 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random.4203350157 |
|
|
Aug 21 11:14:58 PM UTC 24 |
Aug 21 11:15:16 PM UTC 24 |
147579820 ps |
| T2375 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.3431045941 |
|
|
Aug 21 11:01:57 PM UTC 24 |
Aug 21 11:15:27 PM UTC 24 |
8346035525 ps |
| T2376 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.1317724043 |
|
|
Aug 21 10:50:08 PM UTC 24 |
Aug 21 11:15:28 PM UTC 24 |
106419272197 ps |
| T2377 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_large_delays.682630586 |
|
|
Aug 21 11:13:24 PM UTC 24 |
Aug 21 11:15:34 PM UTC 24 |
9058551406 ps |
| T2378 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_slow_rsp.2886043712 |
|
|
Aug 21 11:05:13 PM UTC 24 |
Aug 21 11:15:37 PM UTC 24 |
32561934332 ps |
| T2379 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all.2091995377 |
|
|
Aug 21 11:05:31 PM UTC 24 |
Aug 21 11:15:38 PM UTC 24 |
15514655145 ps |
| T2380 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_unmapped_addr.1028954499 |
|
|
Aug 21 11:15:17 PM UTC 24 |
Aug 21 11:15:45 PM UTC 24 |
229515321 ps |
| T2381 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_slow_rsp.4064998940 |
|
|
Aug 21 11:07:36 PM UTC 24 |
Aug 21 11:15:52 PM UTC 24 |
29323561890 ps |
| T2382 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_zero_delays.2358765224 |
|
|
Aug 21 11:14:59 PM UTC 24 |
Aug 21 11:15:54 PM UTC 24 |
440572394 ps |
| T2383 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_random.215833901 |
|
|
Aug 21 11:15:15 PM UTC 24 |
Aug 21 11:15:56 PM UTC 24 |
578993412 ps |
| T2384 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.3652407418 |
|
|
Aug 21 11:10:59 PM UTC 24 |
Aug 21 11:15:57 PM UTC 24 |
7086993337 ps |
| T2385 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_zero_delays.2158733350 |
|
|
Aug 21 11:15:49 PM UTC 24 |
Aug 21 11:15:58 PM UTC 24 |
42378984 ps |
| T2386 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke.2738102211 |
|
|
Aug 21 11:15:52 PM UTC 24 |
Aug 21 11:16:02 PM UTC 24 |
60091631 ps |
| T2387 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.3756070411 |
|
|
Aug 21 11:15:19 PM UTC 24 |
Aug 21 11:16:16 PM UTC 24 |
1059433172 ps |
| T2388 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_large_delays.1101905372 |
|
|
Aug 21 11:14:46 PM UTC 24 |
Aug 21 11:16:20 PM UTC 24 |
9290366589 ps |
| T2389 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_large_delays.3053670233 |
|
|
Aug 21 11:02:36 PM UTC 24 |
Aug 21 11:16:30 PM UTC 24 |
67670182240 ps |
| T2390 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_slow_rsp.2396407320 |
|
|
Aug 21 11:13:41 PM UTC 24 |
Aug 21 11:16:37 PM UTC 24 |
12191399098 ps |
| T2391 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random.1287792602 |
|
|
Aug 21 11:16:03 PM UTC 24 |
Aug 21 11:16:40 PM UTC 24 |
294603191 ps |
| T2392 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_zero_delays.212231241 |
|
|
Aug 21 11:16:07 PM UTC 24 |
Aug 21 11:16:43 PM UTC 24 |
288229200 ps |
| T2393 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.1705646798 |
|
|
Aug 21 11:14:52 PM UTC 24 |
Aug 21 11:16:43 PM UTC 24 |
5780276624 ps |
| T2394 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all.2782551955 |
|
|
Aug 21 11:14:15 PM UTC 24 |
Aug 21 11:16:46 PM UTC 24 |
3190808553 ps |
| T2395 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device.789355885 |
|
|
Aug 21 11:16:19 PM UTC 24 |
Aug 21 11:16:49 PM UTC 24 |
589400513 ps |
| T2396 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_same_source.3951465186 |
|
|
Aug 21 11:15:11 PM UTC 24 |
Aug 21 11:16:50 PM UTC 24 |
2498905656 ps |
| T2397 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_error.3614297590 |
|
|
Aug 21 11:14:15 PM UTC 24 |
Aug 21 11:16:52 PM UTC 24 |
1660423224 ps |
| T2398 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_unmapped_addr.813095909 |
|
|
Aug 21 11:16:39 PM UTC 24 |
Aug 21 11:16:54 PM UTC 24 |
69842920 ps |
| T2399 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_random.863965142 |
|
|
Aug 21 11:16:25 PM UTC 24 |
Aug 21 11:16:57 PM UTC 24 |
420703448 ps |
| T2400 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all.931900209 |
|
|
Aug 21 11:10:58 PM UTC 24 |
Aug 21 11:16:58 PM UTC 24 |
10205300683 ps |
| T2401 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_same_source.1411115979 |
|
|
Aug 21 11:16:22 PM UTC 24 |
Aug 21 11:17:04 PM UTC 24 |
1129355720 ps |
| T2402 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke.2415210820 |
|
|
Aug 21 11:17:06 PM UTC 24 |
Aug 21 11:17:14 PM UTC 24 |
52745245 ps |
| T2403 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_large_delays.2280576498 |
|
|
Aug 21 11:06:12 PM UTC 24 |
Aug 21 11:17:16 PM UTC 24 |
65084195594 ps |
| T2404 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_zero_delays.2641188223 |
|
|
Aug 21 11:17:10 PM UTC 24 |
Aug 21 11:17:19 PM UTC 24 |
43219277 ps |
| T2405 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.2787764234 |
|
|
Aug 21 11:16:44 PM UTC 24 |
Aug 21 11:17:24 PM UTC 24 |
737219831 ps |
| T2406 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device.308042096 |
|
|
Aug 21 11:15:08 PM UTC 24 |
Aug 21 11:17:26 PM UTC 24 |
2972250314 ps |
| T2407 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_large_delays.2322292176 |
|
|
Aug 21 11:15:55 PM UTC 24 |
Aug 21 11:17:35 PM UTC 24 |
6221930698 ps |
| T2408 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device.4077727004 |
|
|
Aug 21 11:17:24 PM UTC 24 |
Aug 21 11:17:51 PM UTC 24 |
370014145 ps |
| T2409 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_large_delays.2476043728 |
|
|
Aug 21 10:59:30 PM UTC 24 |
Aug 21 11:17:52 PM UTC 24 |
93121604535 ps |
| T2410 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.2912623898 |
|
|
Aug 21 11:17:48 PM UTC 24 |
Aug 21 11:17:56 PM UTC 24 |
16587596 ps |
| T2411 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_slow_rsp.2330429570 |
|
|
Aug 21 11:09:27 PM UTC 24 |
Aug 21 11:17:59 PM UTC 24 |
31360080428 ps |
| T2412 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_large_delays.642215628 |
|
|
Aug 21 11:15:01 PM UTC 24 |
Aug 21 11:18:00 PM UTC 24 |
14559350741 ps |
| T2413 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_zero_delays.1249067898 |
|
|
Aug 21 11:17:16 PM UTC 24 |
Aug 21 11:18:00 PM UTC 24 |
363923078 ps |
| T2414 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_slow_rsp.4160357764 |
|
|
Aug 21 11:15:02 PM UTC 24 |
Aug 21 11:18:02 PM UTC 24 |
12298467887 ps |
| T2415 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_unmapped_addr.4114010542 |
|
|
Aug 21 11:17:48 PM UTC 24 |
Aug 21 11:18:02 PM UTC 24 |
152489883 ps |
| T2416 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.3351371229 |
|
|
Aug 21 11:16:01 PM UTC 24 |
Aug 21 11:18:05 PM UTC 24 |
5426873598 ps |
| T2417 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.2957014831 |
|
|
Aug 21 11:15:41 PM UTC 24 |
Aug 21 11:18:06 PM UTC 24 |
497674386 ps |
| T2418 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_slow_rsp.2163644375 |
|
|
Aug 21 11:12:30 PM UTC 24 |
Aug 21 11:18:06 PM UTC 24 |
20921334685 ps |
| T2419 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.3005962683 |
|
|
Aug 21 11:17:02 PM UTC 24 |
Aug 21 11:18:16 PM UTC 24 |
135193045 ps |
| T2420 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_random.2420055618 |
|
|
Aug 21 11:17:41 PM UTC 24 |
Aug 21 11:18:25 PM UTC 24 |
1227532692 ps |
| T2421 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_slow_rsp.701266785 |
|
|
Aug 21 11:10:43 PM UTC 24 |
Aug 21 11:18:33 PM UTC 24 |
27395646745 ps |
| T2422 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_zero_delays.1161143432 |
|
|
Aug 21 11:18:24 PM UTC 24 |
Aug 21 11:18:34 PM UTC 24 |
52541371 ps |
| T2423 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke.10537459 |
|
|
Aug 21 11:18:21 PM UTC 24 |
Aug 21 11:18:34 PM UTC 24 |
219277247 ps |
| T2424 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.3379718170 |
|
|
Aug 21 11:14:15 PM UTC 24 |
Aug 21 11:18:46 PM UTC 24 |
692789053 ps |
| T2425 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_error.400262616 |
|
|
Aug 21 11:17:05 PM UTC 24 |
Aug 21 11:18:47 PM UTC 24 |
1118513660 ps |
| T2426 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device.442891229 |
|
|
Aug 21 11:18:37 PM UTC 24 |
Aug 21 11:18:53 PM UTC 24 |
274696218 ps |
| T2427 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_same_source.3660646401 |
|
|
Aug 21 11:17:39 PM UTC 24 |
Aug 21 11:18:56 PM UTC 24 |
1878057113 ps |
| T2428 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_large_delays.609822575 |
|
|
Aug 21 11:17:11 PM UTC 24 |
Aug 21 11:18:56 PM UTC 24 |
8564636290 ps |
| T2429 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.3478916709 |
|
|
Aug 21 11:17:13 PM UTC 24 |
Aug 21 11:19:00 PM UTC 24 |
6710416125 ps |
| T2430 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_zero_delays.379025613 |
|
|
Aug 21 11:18:27 PM UTC 24 |
Aug 21 11:19:04 PM UTC 24 |
387469774 ps |
| T2431 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_random.3554864919 |
|
|
Aug 21 11:18:59 PM UTC 24 |
Aug 21 11:19:08 PM UTC 24 |
31098233 ps |
| T2432 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random.3132386076 |
|
|
Aug 21 11:17:13 PM UTC 24 |
Aug 21 11:19:12 PM UTC 24 |
2438026957 ps |
| T2433 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.3910368292 |
|
|
Aug 21 11:11:59 PM UTC 24 |
Aug 21 11:19:12 PM UTC 24 |
3624004057 ps |
| T2434 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all.2863637975 |
|
|
Aug 21 11:15:28 PM UTC 24 |
Aug 21 11:19:15 PM UTC 24 |
3374322725 ps |
| T2435 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_unmapped_addr.3684230943 |
|
|
Aug 21 11:18:58 PM UTC 24 |
Aug 21 11:19:19 PM UTC 24 |
404299035 ps |
| T2436 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random.1951320628 |
|
|
Aug 21 11:18:27 PM UTC 24 |
Aug 21 11:19:25 PM UTC 24 |
1194763856 ps |
| T2437 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_slow_rsp.527481512 |
|
|
Aug 21 11:16:15 PM UTC 24 |
Aug 21 11:19:27 PM UTC 24 |
11004514811 ps |
| T2438 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke.737738533 |
|
|
Aug 21 11:19:22 PM UTC 24 |
Aug 21 11:19:30 PM UTC 24 |
41591815 ps |
| T2439 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_zero_delays.865548808 |
|
|
Aug 21 11:19:27 PM UTC 24 |
Aug 21 11:19:37 PM UTC 24 |
48256882 ps |
| T2440 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.1467971826 |
|
|
Aug 21 11:18:15 PM UTC 24 |
Aug 21 11:19:42 PM UTC 24 |
79007562 ps |
| T2441 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.4191080525 |
|
|
Aug 21 11:19:07 PM UTC 24 |
Aug 21 11:19:45 PM UTC 24 |
964403261 ps |
| T2442 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.838684694 |
|
|
Aug 21 11:18:24 PM UTC 24 |
Aug 21 11:19:55 PM UTC 24 |
6306696513 ps |
| T2443 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random.2052474449 |
|
|
Aug 21 11:19:36 PM UTC 24 |
Aug 21 11:20:03 PM UTC 24 |
279386955 ps |
| T2444 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_large_delays.232379673 |
|
|
Aug 21 11:18:22 PM UTC 24 |
Aug 21 11:20:08 PM UTC 24 |
8665538425 ps |
| T2445 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device.1357865753 |
|
|
Aug 21 11:19:50 PM UTC 24 |
Aug 21 11:20:15 PM UTC 24 |
251918811 ps |
| T2446 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.2220226876 |
|
|
Aug 21 11:12:59 PM UTC 24 |
Aug 21 11:20:16 PM UTC 24 |
7461520472 ps |
| T2447 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_zero_delays.210403174 |
|
|
Aug 21 11:19:39 PM UTC 24 |
Aug 21 11:20:19 PM UTC 24 |
367396037 ps |
| T2448 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_large_delays.1080104954 |
|
|
Aug 21 11:07:29 PM UTC 24 |
Aug 21 11:20:21 PM UTC 24 |
87323241926 ps |
| T2449 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_same_source.2075685263 |
|
|
Aug 21 11:18:58 PM UTC 24 |
Aug 21 11:20:29 PM UTC 24 |
2566983961 ps |
| T2450 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_random.901573946 |
|
|
Aug 21 11:20:07 PM UTC 24 |
Aug 21 11:20:33 PM UTC 24 |
216003742 ps |
| T2451 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_same_source.1583947349 |
|
|
Aug 21 11:20:02 PM UTC 24 |
Aug 21 11:20:51 PM UTC 24 |
1183436463 ps |
| T2452 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_unmapped_addr.1446451684 |
|
|
Aug 21 11:20:09 PM UTC 24 |
Aug 21 11:20:54 PM UTC 24 |
311563547 ps |
| T2453 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_zero_delays.233887405 |
|
|
Aug 21 11:20:45 PM UTC 24 |
Aug 21 11:20:56 PM UTC 24 |
50362517 ps |
| T2454 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_large_delays.3694467598 |
|
|
Aug 21 11:12:16 PM UTC 24 |
Aug 21 11:20:57 PM UTC 24 |
45639000657 ps |
| T2455 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke.3897775423 |
|
|
Aug 21 11:20:43 PM UTC 24 |
Aug 21 11:20:57 PM UTC 24 |
208404462 ps |
| T2456 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.4222185763 |
|
|
Aug 21 11:19:33 PM UTC 24 |
Aug 21 11:21:01 PM UTC 24 |
6287784280 ps |
| T2457 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_slow_rsp.50875721 |
|
|
Aug 21 11:17:19 PM UTC 24 |
Aug 21 11:21:03 PM UTC 24 |
13871373785 ps |
| T2458 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_error.1435746360 |
|
|
Aug 21 11:19:21 PM UTC 24 |
Aug 21 11:21:10 PM UTC 24 |
2922415521 ps |
| T2459 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.1346565022 |
|
|
Aug 21 11:20:20 PM UTC 24 |
Aug 21 11:21:11 PM UTC 24 |
934365989 ps |
| T2460 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.3318786007 |
|
|
Aug 21 11:20:41 PM UTC 24 |
Aug 21 11:21:22 PM UTC 24 |
185329438 ps |
| T2461 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_large_delays.169531223 |
|
|
Aug 21 11:19:32 PM UTC 24 |
Aug 21 11:21:29 PM UTC 24 |
8906968768 ps |
| T2462 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.29095940 |
|
|
Aug 21 10:59:40 PM UTC 24 |
Aug 21 11:21:32 PM UTC 24 |
95808335441 ps |
| T2463 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_zero_delays.3404582954 |
|
|
Aug 21 11:21:16 PM UTC 24 |
Aug 21 11:21:39 PM UTC 24 |
174062230 ps |
| T2464 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_large_delays.3327082809 |
|
|
Aug 21 11:11:29 PM UTC 24 |
Aug 21 11:21:42 PM UTC 24 |
60906575654 ps |
| T2465 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_random.3269164237 |
|
|
Aug 21 11:21:36 PM UTC 24 |
Aug 21 11:21:59 PM UTC 24 |
395488242 ps |
| T2466 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_same_source.1676724965 |
|
|
Aug 21 11:21:29 PM UTC 24 |
Aug 21 11:22:05 PM UTC 24 |
335699965 ps |
| T2467 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random.3539404666 |
|
|
Aug 21 11:21:16 PM UTC 24 |
Aug 21 11:22:06 PM UTC 24 |
1827218475 ps |
| T2468 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_large_delays.956454828 |
|
|
Aug 21 11:05:10 PM UTC 24 |
Aug 21 11:22:11 PM UTC 24 |
92953836096 ps |
| T2469 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_large_delays.3520853710 |
|
|
Aug 21 11:20:55 PM UTC 24 |
Aug 21 11:22:15 PM UTC 24 |
8123437047 ps |
| T2470 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.2312966507 |
|
|
Aug 21 11:18:19 PM UTC 24 |
Aug 21 11:22:18 PM UTC 24 |
2267167058 ps |
| T2471 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.1117467341 |
|
|
Aug 21 11:20:58 PM UTC 24 |
Aug 21 11:22:20 PM UTC 24 |
4827424442 ps |
| T2472 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.585998078 |
|
|
Aug 21 11:14:18 PM UTC 24 |
Aug 21 11:22:23 PM UTC 24 |
5730888111 ps |
| T2473 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device.923355720 |
|
|
Aug 21 11:21:21 PM UTC 24 |
Aug 21 11:22:30 PM UTC 24 |
614514462 ps |
| T2474 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_zero_delays.3692104899 |
|
|
Aug 21 11:22:24 PM UTC 24 |
Aug 21 11:22:34 PM UTC 24 |
47450886 ps |
| T2475 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke.3124449912 |
|
|
Aug 21 11:22:24 PM UTC 24 |
Aug 21 11:22:35 PM UTC 24 |
156730601 ps |
| T2476 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.723087418 |
|
|
Aug 21 11:21:47 PM UTC 24 |
Aug 21 11:22:36 PM UTC 24 |
1025364864 ps |
| T2477 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.563665827 |
|
|
Aug 21 11:19:51 PM UTC 24 |
Aug 21 11:22:37 PM UTC 24 |
12764678331 ps |
| T2478 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all.3898194048 |
|
|
Aug 21 11:18:01 PM UTC 24 |
Aug 21 11:22:38 PM UTC 24 |
8540953744 ps |
| T2479 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.1842558786 |
|
|
Aug 21 11:10:00 PM UTC 24 |
Aug 21 11:22:38 PM UTC 24 |
15478452984 ps |
| T2480 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_unmapped_addr.3609958899 |
|
|
Aug 21 11:21:35 PM UTC 24 |
Aug 21 11:22:40 PM UTC 24 |
1079200047 ps |
| T2481 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all.3485310296 |
|
|
Aug 21 11:19:11 PM UTC 24 |
Aug 21 11:22:45 PM UTC 24 |
2266624196 ps |
| T2482 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_zero_delays.573845123 |
|
|
Aug 21 11:22:43 PM UTC 24 |
Aug 21 11:23:00 PM UTC 24 |
99943960 ps |
| T2483 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.1905906669 |
|
|
Aug 21 10:55:28 PM UTC 24 |
Aug 21 11:23:07 PM UTC 24 |
121373044844 ps |
| T2484 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.1138675438 |
|
|
Aug 21 11:23:00 PM UTC 24 |
Aug 21 11:23:15 PM UTC 24 |
181501130 ps |
| T2485 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_same_source.726955955 |
|
|
Aug 21 11:22:58 PM UTC 24 |
Aug 21 11:23:18 PM UTC 24 |
175500447 ps |
| T2486 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random.3732010365 |
|
|
Aug 21 11:22:38 PM UTC 24 |
Aug 21 11:23:18 PM UTC 24 |
780814765 ps |
| T2487 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.1401802451 |
|
|
Aug 21 10:58:28 PM UTC 24 |
Aug 21 11:23:20 PM UTC 24 |
98275430878 ps |
| T2488 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_slow_rsp.2621373307 |
|
|
Aug 21 11:06:13 PM UTC 24 |
Aug 21 11:23:27 PM UTC 24 |
61634901343 ps |
| T2489 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.426898860 |
|
|
Aug 21 11:23:21 PM UTC 24 |
Aug 21 11:23:32 PM UTC 24 |
7477686 ps |
| T2490 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_unmapped_addr.3565024175 |
|
|
Aug 21 11:23:02 PM UTC 24 |
Aug 21 11:23:33 PM UTC 24 |
456826707 ps |
| T2491 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke.3887975855 |
|
|
Aug 21 11:23:25 PM UTC 24 |
Aug 21 11:23:35 PM UTC 24 |
43015843 ps |
| T2492 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_random.739628927 |
|
|
Aug 21 11:22:58 PM UTC 24 |
Aug 21 11:23:35 PM UTC 24 |
808069239 ps |
| T2493 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all.1914538704 |
|
|
Aug 21 11:16:55 PM UTC 24 |
Aug 21 11:23:36 PM UTC 24 |
11705664434 ps |
| T2494 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.3011589540 |
|
|
Aug 21 11:00:59 PM UTC 24 |
Aug 21 11:23:37 PM UTC 24 |
87002135630 ps |
| T2495 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.2663216664 |
|
|
Aug 21 11:22:33 PM UTC 24 |
Aug 21 11:23:39 PM UTC 24 |
3885342533 ps |
| T2496 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_large_delays.2226644768 |
|
|
Aug 21 11:03:58 PM UTC 24 |
Aug 21 11:23:43 PM UTC 24 |
109983142756 ps |
| T2497 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_zero_delays.1418983374 |
|
|
Aug 21 11:23:40 PM UTC 24 |
Aug 21 11:23:47 PM UTC 24 |
44466324 ps |
| T2498 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device.383615323 |
|
|
Aug 21 11:22:54 PM UTC 24 |
Aug 21 11:23:53 PM UTC 24 |
1725270328 ps |
| T2499 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_slow_rsp.1620126396 |
|
|
Aug 21 11:21:21 PM UTC 24 |
Aug 21 11:24:01 PM UTC 24 |
9591835755 ps |
| T2500 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_slow_rsp.1962818934 |
|
|
Aug 21 11:11:36 PM UTC 24 |
Aug 21 11:24:01 PM UTC 24 |
43231187244 ps |
| T2501 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.285554122 |
|
|
Aug 21 11:19:21 PM UTC 24 |
Aug 21 11:24:06 PM UTC 24 |
948668289 ps |
| T2502 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_large_delays.2454533228 |
|
|
Aug 21 11:19:44 PM UTC 24 |
Aug 21 11:24:15 PM UTC 24 |
23773564578 ps |
| T2503 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_same_source.4256700721 |
|
|
Aug 21 11:23:59 PM UTC 24 |
Aug 21 11:24:16 PM UTC 24 |
307692314 ps |
| T2504 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_zero_delays.1119694172 |
|
|
Aug 21 11:23:52 PM UTC 24 |
Aug 21 11:24:17 PM UTC 24 |
179033959 ps |
| T2505 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_unmapped_addr.2497497154 |
|
|
Aug 21 11:24:04 PM UTC 24 |
Aug 21 11:24:29 PM UTC 24 |
178338574 ps |
| T2506 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random.232621556 |
|
|
Aug 21 11:23:42 PM UTC 24 |
Aug 21 11:24:30 PM UTC 24 |
619246191 ps |
| T2507 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_large_delays.2714772559 |
|
|
Aug 21 11:22:31 PM UTC 24 |
Aug 21 11:24:35 PM UTC 24 |
8880246293 ps |
| T2508 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.1960414775 |
|
|
Aug 21 11:24:26 PM UTC 24 |
Aug 21 11:24:39 PM UTC 24 |
33913106 ps |
| T2509 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke.3290809110 |
|
|
Aug 21 11:24:29 PM UTC 24 |
Aug 21 11:24:43 PM UTC 24 |
197980413 ps |
| T2510 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_random.976050374 |
|
|
Aug 21 11:24:03 PM UTC 24 |
Aug 21 11:24:45 PM UTC 24 |
1114317970 ps |
| T2511 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device.1197073116 |
|
|
Aug 21 11:23:59 PM UTC 24 |
Aug 21 11:24:45 PM UTC 24 |
538147638 ps |
| T2512 |
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all.1503542457 |
|
|
Aug 21 11:24:11 PM UTC 24 |
Aug 21 11:24:48 PM UTC 24 |
384019738 ps |